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STYLE_DIGITAL + + + FullPathName + EMIO_0_tri_t_7 + EMIO_0_tri_t_7 + HEXRADIX + true + STYLE_DIGITAL + + + FullPathName + EMIO_0_tri_t_8 + EMIO_0_tri_t_8 + HEXRADIX + true + STYLE_DIGITAL + + + FullPathName + EMIO_0_tri_t_9 + EMIO_0_tri_t_9 + HEXRADIX + true + STYLE_DIGITAL + + + FullPathName + EMIO_0_tri_t_10 + EMIO_0_tri_t_10 + HEXRADIX + true + STYLE_DIGITAL + + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.hw/webtalk/.xsim_webtallk.info b/2.FW/NewExtInst_Debug/NewExtInst_Debug.hw/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..167c7c6 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.hw/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1768374503 +0 +2 +0 +a8afe58f-132c-49c9-917f-ca0fff35ca74 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/README.txt b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/README.txt new file mode 100644 index 0000000..9015e04 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/sim/NewExtInst_TOP_SPI_Con_0_0.v b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/sim/NewExtInst_TOP_SPI_Con_0_0.v new file mode 100644 index 0000000..70fca58 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/sim/NewExtInst_TOP_SPI_Con_0_0.v @@ -0,0 +1,165 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:user:SPI_Con:1.0 +// IP Revision: 3 + +`timescale 1ns/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module NewExtInst_TOP_SPI_Con_0_0 ( + i_miso, + o_sclk, + o_cs, + o_mosi, + s00_axi_aclk, + s00_axi_aresetn, + s00_axi_awaddr, + s00_axi_awprot, + s00_axi_awvalid, + s00_axi_awready, + s00_axi_wdata, + s00_axi_wstrb, + s00_axi_wvalid, + s00_axi_wready, + s00_axi_bresp, + s00_axi_bvalid, + s00_axi_bready, + s00_axi_araddr, + s00_axi_arprot, + s00_axi_arvalid, + s00_axi_arready, + s00_axi_rdata, + s00_axi_rresp, + s00_axi_rvalid, + s00_axi_rready +); + +input wire i_miso; +output wire o_sclk; +output wire o_cs; +output wire o_mosi; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK" *) +input wire s00_axi_aclk; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S00_AXI_RST RST" *) +input wire s00_axi_aresetn; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *) +input wire [6 : 0] s00_axi_awaddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *) +input wire [2 : 0] s00_axi_awprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *) +input wire s00_axi_awvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *) +output wire s00_axi_awready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *) +input wire [31 : 0] s00_axi_wdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *) +input wire [3 : 0] s00_axi_wstrb; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *) +input wire s00_axi_wvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *) +output wire s00_axi_wready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *) +output wire [1 : 0] s00_axi_bresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *) +output wire s00_axi_bvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *) +input wire s00_axi_bready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *) +input wire [6 : 0] s00_axi_araddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *) +input wire [2 : 0] s00_axi_arprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *) +input wire s00_axi_arvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *) +output wire s00_axi_arready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *) +output wire [31 : 0] s00_axi_rdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *) +output wire [1 : 0] s00_axi_rresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *) +output wire s00_axi_rvalid; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 32, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 7, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM\ +_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) +input wire s00_axi_rready; + + SPI_Con_v1_0 #( + .C_S00_AXI_DATA_WIDTH(32), // Width of S_AXI data bus + .C_S00_AXI_ADDR_WIDTH(7) // Width of S_AXI address bus + ) inst ( + .i_miso(i_miso), + .o_sclk(o_sclk), + .o_cs(o_cs), + .o_mosi(o_mosi), + .s00_axi_aclk(s00_axi_aclk), + .s00_axi_aresetn(s00_axi_aresetn), + .s00_axi_awaddr(s00_axi_awaddr), + .s00_axi_awprot(s00_axi_awprot), + .s00_axi_awvalid(s00_axi_awvalid), + .s00_axi_awready(s00_axi_awready), + .s00_axi_wdata(s00_axi_wdata), + .s00_axi_wstrb(s00_axi_wstrb), + .s00_axi_wvalid(s00_axi_wvalid), + .s00_axi_wready(s00_axi_wready), + .s00_axi_bresp(s00_axi_bresp), + .s00_axi_bvalid(s00_axi_bvalid), + .s00_axi_bready(s00_axi_bready), + .s00_axi_araddr(s00_axi_araddr), + .s00_axi_arprot(s00_axi_arprot), + .s00_axi_arvalid(s00_axi_arvalid), + .s00_axi_arready(s00_axi_arready), + .s00_axi_rdata(s00_axi_rdata), + .s00_axi_rresp(s00_axi_rresp), + .s00_axi_rvalid(s00_axi_rvalid), + .s00_axi_rready(s00_axi_rready) + ); +endmodule diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/sim/NewExtInst_TOP_SPI_Con_0_1.v b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/sim/NewExtInst_TOP_SPI_Con_0_1.v new file mode 100644 index 0000000..1ce11be --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/sim/NewExtInst_TOP_SPI_Con_0_1.v @@ -0,0 +1,165 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:user:SPI_Con:1.0 +// IP Revision: 3 + +`timescale 1ns/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module NewExtInst_TOP_SPI_Con_0_1 ( + i_miso, + o_sclk, + o_cs, + o_mosi, + s00_axi_aclk, + s00_axi_aresetn, + s00_axi_awaddr, + s00_axi_awprot, + s00_axi_awvalid, + s00_axi_awready, + s00_axi_wdata, + s00_axi_wstrb, + s00_axi_wvalid, + s00_axi_wready, + s00_axi_bresp, + s00_axi_bvalid, + s00_axi_bready, + s00_axi_araddr, + s00_axi_arprot, + s00_axi_arvalid, + s00_axi_arready, + s00_axi_rdata, + s00_axi_rresp, + s00_axi_rvalid, + s00_axi_rready +); + +input wire i_miso; +output wire o_sclk; +output wire o_cs; +output wire o_mosi; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK" *) +input wire s00_axi_aclk; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S00_AXI_RST RST" *) +input wire s00_axi_aresetn; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *) +input wire [6 : 0] s00_axi_awaddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *) +input wire [2 : 0] s00_axi_awprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *) +input wire s00_axi_awvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *) +output wire s00_axi_awready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *) +input wire [31 : 0] s00_axi_wdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *) +input wire [3 : 0] s00_axi_wstrb; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *) +input wire s00_axi_wvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *) +output wire s00_axi_wready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *) +output wire [1 : 0] s00_axi_bresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *) +output wire s00_axi_bvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *) +input wire s00_axi_bready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *) +input wire [6 : 0] s00_axi_araddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *) +input wire [2 : 0] s00_axi_arprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *) +input wire s00_axi_arvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *) +output wire s00_axi_arready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *) +output wire [31 : 0] s00_axi_rdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *) +output wire [1 : 0] s00_axi_rresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *) +output wire s00_axi_rvalid; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 32, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 7, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM\ +_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) +input wire s00_axi_rready; + + SPI_Con_v1_0 #( + .C_S00_AXI_DATA_WIDTH(32), // Width of S_AXI data bus + .C_S00_AXI_ADDR_WIDTH(7) // Width of S_AXI address bus + ) inst ( + .i_miso(i_miso), + .o_sclk(o_sclk), + .o_cs(o_cs), + .o_mosi(o_mosi), + .s00_axi_aclk(s00_axi_aclk), + .s00_axi_aresetn(s00_axi_aresetn), + .s00_axi_awaddr(s00_axi_awaddr), + .s00_axi_awprot(s00_axi_awprot), + .s00_axi_awvalid(s00_axi_awvalid), + .s00_axi_awready(s00_axi_awready), + .s00_axi_wdata(s00_axi_wdata), + .s00_axi_wstrb(s00_axi_wstrb), + .s00_axi_wvalid(s00_axi_wvalid), + .s00_axi_wready(s00_axi_wready), + .s00_axi_bresp(s00_axi_bresp), + .s00_axi_bvalid(s00_axi_bvalid), + .s00_axi_bready(s00_axi_bready), + .s00_axi_araddr(s00_axi_araddr), + .s00_axi_arprot(s00_axi_arprot), + .s00_axi_arvalid(s00_axi_arvalid), + .s00_axi_arready(s00_axi_arready), + .s00_axi_rdata(s00_axi_rdata), + .s00_axi_rresp(s00_axi_rresp), + .s00_axi_rvalid(s00_axi_rvalid), + .s00_axi_rready(s00_axi_rready) + ); +endmodule diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/sim/NewExtInst_TOP_SPI_Con_0_2.v b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/sim/NewExtInst_TOP_SPI_Con_0_2.v new file mode 100644 index 0000000..7332c4c --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/sim/NewExtInst_TOP_SPI_Con_0_2.v @@ -0,0 +1,165 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:user:SPI_Con:1.0 +// IP Revision: 3 + +`timescale 1ns/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module NewExtInst_TOP_SPI_Con_0_2 ( + i_miso, + o_sclk, + o_cs, + o_mosi, + s00_axi_aclk, + s00_axi_aresetn, + s00_axi_awaddr, + s00_axi_awprot, + s00_axi_awvalid, + s00_axi_awready, + s00_axi_wdata, + s00_axi_wstrb, + s00_axi_wvalid, + s00_axi_wready, + s00_axi_bresp, + s00_axi_bvalid, + s00_axi_bready, + s00_axi_araddr, + s00_axi_arprot, + s00_axi_arvalid, + s00_axi_arready, + s00_axi_rdata, + s00_axi_rresp, + s00_axi_rvalid, + s00_axi_rready +); + +input wire i_miso; +output wire o_sclk; +output wire o_cs; +output wire o_mosi; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK" *) +input wire s00_axi_aclk; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S00_AXI_RST RST" *) +input wire s00_axi_aresetn; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *) +input wire [6 : 0] s00_axi_awaddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *) +input wire [2 : 0] s00_axi_awprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *) +input wire s00_axi_awvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *) +output wire s00_axi_awready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *) +input wire [31 : 0] s00_axi_wdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *) +input wire [3 : 0] s00_axi_wstrb; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *) +input wire s00_axi_wvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *) +output wire s00_axi_wready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *) +output wire [1 : 0] s00_axi_bresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *) +output wire s00_axi_bvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *) +input wire s00_axi_bready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *) +input wire [6 : 0] s00_axi_araddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *) +input wire [2 : 0] s00_axi_arprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *) +input wire s00_axi_arvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *) +output wire s00_axi_arready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *) +output wire [31 : 0] s00_axi_rdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *) +output wire [1 : 0] s00_axi_rresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *) +output wire s00_axi_rvalid; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 32, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 7, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM\ +_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) +input wire s00_axi_rready; + + SPI_Con_v1_0 #( + .C_S00_AXI_DATA_WIDTH(32), // Width of S_AXI data bus + .C_S00_AXI_ADDR_WIDTH(7) // Width of S_AXI address bus + ) inst ( + .i_miso(i_miso), + .o_sclk(o_sclk), + .o_cs(o_cs), + .o_mosi(o_mosi), + .s00_axi_aclk(s00_axi_aclk), + .s00_axi_aresetn(s00_axi_aresetn), + .s00_axi_awaddr(s00_axi_awaddr), + .s00_axi_awprot(s00_axi_awprot), + .s00_axi_awvalid(s00_axi_awvalid), + .s00_axi_awready(s00_axi_awready), + .s00_axi_wdata(s00_axi_wdata), + .s00_axi_wstrb(s00_axi_wstrb), + .s00_axi_wvalid(s00_axi_wvalid), + .s00_axi_wready(s00_axi_wready), + .s00_axi_bresp(s00_axi_bresp), + .s00_axi_bvalid(s00_axi_bvalid), + .s00_axi_bready(s00_axi_bready), + .s00_axi_araddr(s00_axi_araddr), + .s00_axi_arprot(s00_axi_arprot), + .s00_axi_arvalid(s00_axi_arvalid), + .s00_axi_arready(s00_axi_arready), + .s00_axi_rdata(s00_axi_rdata), + .s00_axi_rresp(s00_axi_rresp), + .s00_axi_rvalid(s00_axi_rvalid), + .s00_axi_rready(s00_axi_rready) + ); +endmodule diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_auto_pc_0/NewExtInst_TOP_auto_pc_0_sim_netlist.v b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_auto_pc_0/NewExtInst_TOP_auto_pc_0_sim_netlist.v new file mode 100644 index 0000000..36f9fe9 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_auto_pc_0/NewExtInst_TOP_auto_pc_0_sim_netlist.v @@ -0,0 +1,12770 @@ +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +// Date : Fri May 15 15:27:03 2026 +// Host : mkb running 64-bit unknown +// Command : write_verilog -force -mode funcsim -rename_top NewExtInst_TOP_auto_pc_0 -prefix +// NewExtInst_TOP_auto_pc_0_ NewExtInst_TOP_auto_pc_0_sim_netlist.v +// Design : NewExtInst_TOP_auto_pc_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z035ffg676-2 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "NewExtInst_TOP_auto_pc_0,axi_protocol_converter_v2_1_29_axi_protocol_converter,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_protocol_converter_v2_1_29_axi_protocol_converter,Vivado 2023.2" *) +(* NotValidForBitStream *) +module NewExtInst_TOP_auto_pc_0 + (aclk, + aresetn, + s_axi_awid, + s_axi_awaddr, + s_axi_awlen, + s_axi_awsize, + s_axi_awburst, + s_axi_awlock, + s_axi_awcache, + s_axi_awprot, + s_axi_awqos, + s_axi_awvalid, + s_axi_awready, + s_axi_wid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wlast, + s_axi_wvalid, + s_axi_wready, + s_axi_bid, + s_axi_bresp, + s_axi_bvalid, + s_axi_bready, + s_axi_arid, + s_axi_araddr, + s_axi_arlen, + s_axi_arsize, + s_axi_arburst, + s_axi_arlock, + s_axi_arcache, + s_axi_arprot, + s_axi_arqos, + s_axi_arvalid, + s_axi_arready, + s_axi_rid, + s_axi_rdata, + s_axi_rresp, + s_axi_rlast, + s_axi_rvalid, + s_axi_rready, + m_axi_awaddr, + m_axi_awprot, + m_axi_awvalid, + m_axi_awready, + m_axi_wdata, + m_axi_wstrb, + m_axi_wvalid, + m_axi_wready, + m_axi_bresp, + m_axi_bvalid, + m_axi_bready, + m_axi_araddr, + m_axi_arprot, + m_axi_arvalid, + m_axi_arready, + m_axi_rdata, + m_axi_rresp, + m_axi_rvalid, + m_axi_rready); + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *) input aclk; + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *) input aresetn; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input [11:0]s_axi_awid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [31:0]s_axi_awaddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [3:0]s_axi_awlen; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input [1:0]s_axi_awlock; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *) input [3:0]s_axi_awqos; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *) input [11:0]s_axi_wid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) output [11:0]s_axi_bid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) input [11:0]s_axi_arid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [31:0]s_axi_araddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [3:0]s_axi_arlen; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input [1:0]s_axi_arlock; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) input [3:0]s_axi_arqos; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) output [11:0]s_axi_rid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input s_axi_rready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output [31:0]m_axi_awaddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output [2:0]m_axi_awprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output m_axi_awvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input m_axi_awready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output [31:0]m_axi_wdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output [3:0]m_axi_wstrb; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output m_axi_wvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input m_axi_wready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input [1:0]m_axi_bresp; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input m_axi_bvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output m_axi_bready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output [31:0]m_axi_araddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output [2:0]m_axi_arprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output m_axi_arvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input m_axi_arready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input [31:0]m_axi_rdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]m_axi_rresp; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input m_axi_rvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output m_axi_rready; + + wire aclk; + wire aresetn; + wire [31:0]m_axi_araddr; + wire [2:0]m_axi_arprot; + wire m_axi_arready; + wire m_axi_arvalid; + wire [31:0]m_axi_awaddr; + wire [2:0]m_axi_awprot; + wire m_axi_awready; + wire m_axi_awvalid; + wire m_axi_bready; + wire [1:0]m_axi_bresp; + wire m_axi_bvalid; + wire [31:0]m_axi_rdata; + wire m_axi_rready; + wire [1:0]m_axi_rresp; + wire m_axi_rvalid; + wire [31:0]m_axi_wdata; + wire m_axi_wready; + wire [3:0]m_axi_wstrb; + wire m_axi_wvalid; + wire [31:0]s_axi_araddr; + wire [1:0]s_axi_arburst; + wire [11:0]s_axi_arid; + wire [3:0]s_axi_arlen; + wire [2:0]s_axi_arprot; + wire s_axi_arready; + wire [2:0]s_axi_arsize; + wire s_axi_arvalid; + wire [31:0]s_axi_awaddr; + wire [1:0]s_axi_awburst; + wire [11:0]s_axi_awid; + wire [3:0]s_axi_awlen; + wire [2:0]s_axi_awprot; + wire s_axi_awready; + wire [2:0]s_axi_awsize; + wire s_axi_awvalid; + wire [11:0]s_axi_bid; + wire s_axi_bready; + wire [1:0]s_axi_bresp; + wire s_axi_bvalid; + wire [31:0]s_axi_rdata; + wire [11:0]s_axi_rid; + wire s_axi_rlast; + wire s_axi_rready; + wire [1:0]s_axi_rresp; + wire s_axi_rvalid; + wire [31:0]s_axi_wdata; + wire s_axi_wready; + wire [3:0]s_axi_wstrb; + wire s_axi_wvalid; + wire NLW_inst_m_axi_wlast_UNCONNECTED; + wire [1:0]NLW_inst_m_axi_arburst_UNCONNECTED; + wire [3:0]NLW_inst_m_axi_arcache_UNCONNECTED; + wire [11:0]NLW_inst_m_axi_arid_UNCONNECTED; + wire [7:0]NLW_inst_m_axi_arlen_UNCONNECTED; + wire [0:0]NLW_inst_m_axi_arlock_UNCONNECTED; + wire [3:0]NLW_inst_m_axi_arqos_UNCONNECTED; + wire [3:0]NLW_inst_m_axi_arregion_UNCONNECTED; + wire [2:0]NLW_inst_m_axi_arsize_UNCONNECTED; + wire [0:0]NLW_inst_m_axi_aruser_UNCONNECTED; + wire [1:0]NLW_inst_m_axi_awburst_UNCONNECTED; + wire [3:0]NLW_inst_m_axi_awcache_UNCONNECTED; + wire [11:0]NLW_inst_m_axi_awid_UNCONNECTED; + wire [7:0]NLW_inst_m_axi_awlen_UNCONNECTED; + wire [0:0]NLW_inst_m_axi_awlock_UNCONNECTED; + wire [3:0]NLW_inst_m_axi_awqos_UNCONNECTED; + wire [3:0]NLW_inst_m_axi_awregion_UNCONNECTED; + wire [2:0]NLW_inst_m_axi_awsize_UNCONNECTED; + wire [0:0]NLW_inst_m_axi_awuser_UNCONNECTED; + wire [11:0]NLW_inst_m_axi_wid_UNCONNECTED; + wire [0:0]NLW_inst_m_axi_wuser_UNCONNECTED; + wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED; + wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED; + + (* C_AXI_ADDR_WIDTH = "32" *) + (* C_AXI_ARUSER_WIDTH = "1" *) + (* C_AXI_AWUSER_WIDTH = "1" *) + (* C_AXI_BUSER_WIDTH = "1" *) + (* C_AXI_DATA_WIDTH = "32" *) + (* C_AXI_ID_WIDTH = "12" *) + (* C_AXI_RUSER_WIDTH = "1" *) + (* C_AXI_SUPPORTS_READ = "1" *) + (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *) + (* C_AXI_SUPPORTS_WRITE = "1" *) + (* C_AXI_WUSER_WIDTH = "1" *) + (* C_FAMILY = "zynq" *) + (* C_IGNORE_ID = "0" *) + (* C_M_AXI_PROTOCOL = "2" *) + (* C_S_AXI_PROTOCOL = "1" *) + (* C_TRANSLATION_MODE = "2" *) + (* DowngradeIPIdentifiedWarnings = "yes" *) + (* P_AXI3 = "1" *) + (* P_AXI4 = "0" *) + (* P_AXILITE = "2" *) + (* P_AXILITE_SIZE = "3'b010" *) + (* P_CONVERSION = "2" *) + (* P_DECERR = "2'b11" *) + (* P_INCR = "2'b01" *) + (* P_PROTECTION = "1" *) + (* P_SLVERR = "2'b10" *) + NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter inst + (.aclk(aclk), + .aresetn(aresetn), + .m_axi_araddr(m_axi_araddr), + .m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[1:0]), + .m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[3:0]), + .m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[11:0]), + .m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[7:0]), + .m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[0]), + .m_axi_arprot(m_axi_arprot), + .m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[3:0]), + .m_axi_arready(m_axi_arready), + .m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[3:0]), + .m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[2:0]), + .m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[0]), + .m_axi_arvalid(m_axi_arvalid), + .m_axi_awaddr(m_axi_awaddr), + .m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[1:0]), + .m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[3:0]), + .m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[11:0]), + .m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[7:0]), + .m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[0]), + .m_axi_awprot(m_axi_awprot), + .m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[3:0]), + .m_axi_awready(m_axi_awready), + .m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[3:0]), + .m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[2:0]), + .m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[0]), + .m_axi_awvalid(m_axi_awvalid), + .m_axi_bid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .m_axi_bready(m_axi_bready), + .m_axi_bresp(m_axi_bresp), + .m_axi_buser(1'b0), + .m_axi_bvalid(m_axi_bvalid), + .m_axi_rdata(m_axi_rdata), + .m_axi_rid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .m_axi_rlast(1'b1), + .m_axi_rready(m_axi_rready), + .m_axi_rresp(m_axi_rresp), + .m_axi_ruser(1'b0), + .m_axi_rvalid(m_axi_rvalid), + .m_axi_wdata(m_axi_wdata), + .m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[11:0]), + .m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED), + .m_axi_wready(m_axi_wready), + .m_axi_wstrb(m_axi_wstrb), + .m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[0]), + .m_axi_wvalid(m_axi_wvalid), + .s_axi_araddr(s_axi_araddr), + .s_axi_arburst(s_axi_arburst), + .s_axi_arcache({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arid(s_axi_arid), + .s_axi_arlen(s_axi_arlen), + .s_axi_arlock({1'b0,1'b0}), + .s_axi_arprot(s_axi_arprot), + .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arready(s_axi_arready), + .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arsize({1'b0,s_axi_arsize[1:0]}), + .s_axi_aruser(1'b0), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awburst(s_axi_awburst), + .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awid(s_axi_awid), + .s_axi_awlen(s_axi_awlen), + .s_axi_awlock({1'b0,1'b0}), + .s_axi_awprot(s_axi_awprot), + .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awready(s_axi_awready), + .s_axi_awregion({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awsize({1'b0,s_axi_awsize[1:0]}), + .s_axi_awuser(1'b0), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_bid(s_axi_bid), + .s_axi_bready(s_axi_bready), + .s_axi_bresp(s_axi_bresp), + .s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_rdata(s_axi_rdata), + .s_axi_rid(s_axi_rid), + .s_axi_rlast(s_axi_rlast), + .s_axi_rready(s_axi_rready), + .s_axi_rresp(s_axi_rresp), + .s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_wdata(s_axi_wdata), + .s_axi_wid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_wlast(1'b0), + .s_axi_wready(s_axi_wready), + .s_axi_wstrb(s_axi_wstrb), + .s_axi_wuser(1'b0), + .s_axi_wvalid(s_axi_wvalid)); +endmodule + +(* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) +(* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "32" *) (* C_AXI_ID_WIDTH = "12" *) +(* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_READ = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *) +(* C_AXI_SUPPORTS_WRITE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_FAMILY = "zynq" *) +(* C_IGNORE_ID = "0" *) (* C_M_AXI_PROTOCOL = "2" *) (* C_S_AXI_PROTOCOL = "1" *) +(* C_TRANSLATION_MODE = "2" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* P_AXI3 = "1" *) +(* P_AXI4 = "0" *) (* P_AXILITE = "2" *) (* P_AXILITE_SIZE = "3'b010" *) +(* P_CONVERSION = "2" *) (* P_DECERR = "2'b11" *) (* P_INCR = "2'b01" *) +(* P_PROTECTION = "1" *) (* P_SLVERR = "2'b10" *) +module NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter + (aclk, + aresetn, + s_axi_awid, + s_axi_awaddr, + s_axi_awlen, + s_axi_awsize, + s_axi_awburst, + s_axi_awlock, + s_axi_awcache, + s_axi_awprot, + s_axi_awregion, + s_axi_awqos, + s_axi_awuser, + s_axi_awvalid, + s_axi_awready, + s_axi_wid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wlast, + s_axi_wuser, + s_axi_wvalid, + s_axi_wready, + s_axi_bid, + s_axi_bresp, + s_axi_buser, + s_axi_bvalid, + s_axi_bready, + s_axi_arid, + s_axi_araddr, + s_axi_arlen, + s_axi_arsize, + s_axi_arburst, + s_axi_arlock, + s_axi_arcache, + s_axi_arprot, + s_axi_arregion, + s_axi_arqos, + s_axi_aruser, + s_axi_arvalid, + s_axi_arready, + s_axi_rid, + s_axi_rdata, + s_axi_rresp, + s_axi_rlast, + s_axi_ruser, + s_axi_rvalid, + s_axi_rready, + m_axi_awid, + m_axi_awaddr, + m_axi_awlen, + m_axi_awsize, + m_axi_awburst, + m_axi_awlock, + m_axi_awcache, + m_axi_awprot, + m_axi_awregion, + m_axi_awqos, + m_axi_awuser, + m_axi_awvalid, + m_axi_awready, + m_axi_wid, + m_axi_wdata, + m_axi_wstrb, + m_axi_wlast, + m_axi_wuser, + m_axi_wvalid, + m_axi_wready, + m_axi_bid, + m_axi_bresp, + m_axi_buser, + m_axi_bvalid, + m_axi_bready, + m_axi_arid, + m_axi_araddr, + m_axi_arlen, + m_axi_arsize, + m_axi_arburst, + m_axi_arlock, + m_axi_arcache, + m_axi_arprot, + m_axi_arregion, + m_axi_arqos, + m_axi_aruser, + m_axi_arvalid, + m_axi_arready, + m_axi_rid, + m_axi_rdata, + m_axi_rresp, + m_axi_rlast, + m_axi_ruser, + m_axi_rvalid, + m_axi_rready); + input aclk; + input aresetn; + input [11:0]s_axi_awid; + input [31:0]s_axi_awaddr; + input [3:0]s_axi_awlen; + input [2:0]s_axi_awsize; + input [1:0]s_axi_awburst; + input [1:0]s_axi_awlock; + input [3:0]s_axi_awcache; + input [2:0]s_axi_awprot; + input [3:0]s_axi_awregion; + input [3:0]s_axi_awqos; + input [0:0]s_axi_awuser; + input s_axi_awvalid; + output s_axi_awready; + input [11:0]s_axi_wid; + input [31:0]s_axi_wdata; + input [3:0]s_axi_wstrb; + input s_axi_wlast; + input [0:0]s_axi_wuser; + input s_axi_wvalid; + output s_axi_wready; + output [11:0]s_axi_bid; + output [1:0]s_axi_bresp; + output [0:0]s_axi_buser; + output s_axi_bvalid; + input s_axi_bready; + input [11:0]s_axi_arid; + input [31:0]s_axi_araddr; + input [3:0]s_axi_arlen; + input [2:0]s_axi_arsize; + input [1:0]s_axi_arburst; + input [1:0]s_axi_arlock; + input [3:0]s_axi_arcache; + input [2:0]s_axi_arprot; + input [3:0]s_axi_arregion; + input [3:0]s_axi_arqos; + input [0:0]s_axi_aruser; + input s_axi_arvalid; + output s_axi_arready; + output [11:0]s_axi_rid; + output [31:0]s_axi_rdata; + output [1:0]s_axi_rresp; + output s_axi_rlast; + output [0:0]s_axi_ruser; + output s_axi_rvalid; + input s_axi_rready; + output [11:0]m_axi_awid; + output [31:0]m_axi_awaddr; + output [7:0]m_axi_awlen; + output [2:0]m_axi_awsize; + output [1:0]m_axi_awburst; + output [0:0]m_axi_awlock; + output [3:0]m_axi_awcache; + output [2:0]m_axi_awprot; + output [3:0]m_axi_awregion; + output [3:0]m_axi_awqos; + output [0:0]m_axi_awuser; + output m_axi_awvalid; + input m_axi_awready; + output [11:0]m_axi_wid; + output [31:0]m_axi_wdata; + output [3:0]m_axi_wstrb; + output m_axi_wlast; + output [0:0]m_axi_wuser; + output m_axi_wvalid; + input m_axi_wready; + input [11:0]m_axi_bid; + input [1:0]m_axi_bresp; + input [0:0]m_axi_buser; + input m_axi_bvalid; + output m_axi_bready; + output [11:0]m_axi_arid; + output [31:0]m_axi_araddr; + output [7:0]m_axi_arlen; + output [2:0]m_axi_arsize; + output [1:0]m_axi_arburst; + output [0:0]m_axi_arlock; + output [3:0]m_axi_arcache; + output [2:0]m_axi_arprot; + output [3:0]m_axi_arregion; + output [3:0]m_axi_arqos; + output [0:0]m_axi_aruser; + output m_axi_arvalid; + input m_axi_arready; + input [11:0]m_axi_rid; + input [31:0]m_axi_rdata; + input [1:0]m_axi_rresp; + input m_axi_rlast; + input [0:0]m_axi_ruser; + input m_axi_rvalid; + output m_axi_rready; + + wire \ ; + wire aclk; + wire aresetn; + wire [31:0]m_axi_araddr; + wire [2:0]m_axi_arprot; + wire m_axi_arready; + wire m_axi_arvalid; + wire [31:0]m_axi_awaddr; + wire [2:0]m_axi_awprot; + wire m_axi_awready; + wire m_axi_awvalid; + wire m_axi_bready; + wire [1:0]m_axi_bresp; + wire m_axi_bvalid; + wire [31:0]m_axi_rdata; + wire m_axi_rready; + wire [1:0]m_axi_rresp; + wire m_axi_rvalid; + wire m_axi_wready; + wire [31:0]s_axi_araddr; + wire [1:0]s_axi_arburst; + wire [11:0]s_axi_arid; + wire [3:0]s_axi_arlen; + wire [2:0]s_axi_arprot; + wire s_axi_arready; + wire [2:0]s_axi_arsize; + wire s_axi_arvalid; + wire [31:0]s_axi_awaddr; + wire [1:0]s_axi_awburst; + wire [11:0]s_axi_awid; + wire [3:0]s_axi_awlen; + wire [2:0]s_axi_awprot; + wire s_axi_awready; + wire [2:0]s_axi_awsize; + wire s_axi_awvalid; + wire [11:0]s_axi_bid; + wire s_axi_bready; + wire [1:0]s_axi_bresp; + wire s_axi_bvalid; + wire [31:0]s_axi_rdata; + wire [11:0]s_axi_rid; + wire s_axi_rlast; + wire s_axi_rready; + wire [1:0]s_axi_rresp; + wire s_axi_rvalid; + wire [31:0]s_axi_wdata; + wire [3:0]s_axi_wstrb; + wire s_axi_wvalid; + + assign m_axi_arburst[1] = \ ; + assign m_axi_arburst[0] = \ ; + assign m_axi_arcache[3] = \ ; + assign m_axi_arcache[2] = \ ; + assign m_axi_arcache[1] = \ ; + assign m_axi_arcache[0] = \ ; + assign m_axi_arid[11] = \ ; + assign m_axi_arid[10] = \ ; + assign m_axi_arid[9] = \ ; + assign m_axi_arid[8] = \ ; + assign m_axi_arid[7] = \ ; + assign m_axi_arid[6] = \ ; + assign m_axi_arid[5] = \ ; + assign m_axi_arid[4] = \ ; + assign m_axi_arid[3] = \ ; + assign m_axi_arid[2] = \ ; + assign m_axi_arid[1] = \ ; + assign m_axi_arid[0] = \ ; + assign m_axi_arlen[7] = \ ; + assign m_axi_arlen[6] = \ ; + assign m_axi_arlen[5] = \ ; + assign m_axi_arlen[4] = \ ; + assign m_axi_arlen[3] = \ ; + assign m_axi_arlen[2] = \ ; + assign m_axi_arlen[1] = \ ; + assign m_axi_arlen[0] = \ ; + assign m_axi_arlock[0] = \ ; + assign m_axi_arqos[3] = \ ; + assign m_axi_arqos[2] = \ ; + assign m_axi_arqos[1] = \ ; + assign m_axi_arqos[0] = \ ; + assign m_axi_arregion[3] = \ ; + assign m_axi_arregion[2] = \ ; + assign m_axi_arregion[1] = \ ; + assign m_axi_arregion[0] = \ ; + assign m_axi_arsize[2] = \ ; + assign m_axi_arsize[1] = \ ; + assign m_axi_arsize[0] = \ ; + assign m_axi_aruser[0] = \ ; + assign m_axi_awburst[1] = \ ; + assign m_axi_awburst[0] = \ ; + assign m_axi_awcache[3] = \ ; + assign m_axi_awcache[2] = \ ; + assign m_axi_awcache[1] = \ ; + assign m_axi_awcache[0] = \ ; + assign m_axi_awid[11] = \ ; + assign m_axi_awid[10] = \ ; + assign m_axi_awid[9] = \ ; + assign m_axi_awid[8] = \ ; + assign m_axi_awid[7] = \ ; + assign m_axi_awid[6] = \ ; + assign m_axi_awid[5] = \ ; + assign m_axi_awid[4] = \ ; + assign m_axi_awid[3] = \ ; + assign m_axi_awid[2] = \ ; + assign m_axi_awid[1] = \ ; + assign m_axi_awid[0] = \ ; + assign m_axi_awlen[7] = \ ; + assign m_axi_awlen[6] = \ ; + assign m_axi_awlen[5] = \ ; + assign m_axi_awlen[4] = \ ; + assign m_axi_awlen[3] = \ ; + assign m_axi_awlen[2] = \ ; + assign m_axi_awlen[1] = \ ; + assign m_axi_awlen[0] = \ ; + assign m_axi_awlock[0] = \ ; + assign m_axi_awqos[3] = \ ; + assign m_axi_awqos[2] = \ ; + assign m_axi_awqos[1] = \ ; + assign m_axi_awqos[0] = \ ; + assign m_axi_awregion[3] = \ ; + assign m_axi_awregion[2] = \ ; + assign m_axi_awregion[1] = \ ; + assign m_axi_awregion[0] = \ ; + assign m_axi_awsize[2] = \ ; + assign m_axi_awsize[1] = \ ; + assign m_axi_awsize[0] = \ ; + assign m_axi_awuser[0] = \ ; + assign m_axi_wdata[31:0] = s_axi_wdata; + assign m_axi_wid[11] = \ ; + assign m_axi_wid[10] = \ ; + assign m_axi_wid[9] = \ ; + assign m_axi_wid[8] = \ ; + assign m_axi_wid[7] = \ ; + assign m_axi_wid[6] = \ ; + assign m_axi_wid[5] = \ ; + assign m_axi_wid[4] = \ ; + assign m_axi_wid[3] = \ ; + assign m_axi_wid[2] = \ ; + assign m_axi_wid[1] = \ ; + assign m_axi_wid[0] = \ ; + assign m_axi_wlast = \ ; + assign m_axi_wstrb[3:0] = s_axi_wstrb; + assign m_axi_wuser[0] = \ ; + assign m_axi_wvalid = s_axi_wvalid; + assign s_axi_buser[0] = \ ; + assign s_axi_ruser[0] = \ ; + assign s_axi_wready = m_axi_wready; + GND GND + (.G(\ )); + NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s \gen_axilite.gen_b2s_conv.axilite_b2s + (.Q({m_axi_awprot,m_axi_awaddr[31:12]}), + .aclk(aclk), + .aresetn(aresetn), + .in({m_axi_rresp,m_axi_rdata}), + .m_axi_araddr(m_axi_araddr[11:0]), + .m_axi_arready(m_axi_arready), + .m_axi_arvalid(m_axi_arvalid), + .m_axi_awaddr(m_axi_awaddr[11:0]), + .m_axi_awready(m_axi_awready), + .m_axi_awvalid(m_axi_awvalid), + .m_axi_bready(m_axi_bready), + .m_axi_bresp(m_axi_bresp), + .m_axi_bvalid(m_axi_bvalid), + .m_axi_rready(m_axi_rready), + .m_axi_rvalid(m_axi_rvalid), + .\m_payload_i_reg[13] ({s_axi_bid,s_axi_bresp}), + .\m_payload_i_reg[34] ({m_axi_arprot,m_axi_araddr[31:12]}), + .\m_payload_i_reg[46] ({s_axi_rid,s_axi_rlast,s_axi_rresp,s_axi_rdata}), + .s_axi_araddr(s_axi_araddr), + .s_axi_arburst(s_axi_arburst), + .s_axi_arid(s_axi_arid), + .s_axi_arlen(s_axi_arlen), + .s_axi_arprot(s_axi_arprot), + .s_axi_arready(s_axi_arready), + .s_axi_arsize(s_axi_arsize[1:0]), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awburst(s_axi_awburst), + .s_axi_awid(s_axi_awid), + .s_axi_awlen(s_axi_awlen), + .s_axi_awprot(s_axi_awprot), + .s_axi_awready(s_axi_awready), + .s_axi_awsize(s_axi_awsize[1:0]), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_bready(s_axi_bready), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_rready(s_axi_rready), + .s_axi_rvalid(s_axi_rvalid)); +endmodule + +module NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s + (s_axi_rvalid, + s_axi_awready, + Q, + s_axi_arready, + \m_payload_i_reg[34] , + s_axi_bvalid, + \m_payload_i_reg[13] , + \m_payload_i_reg[46] , + m_axi_awvalid, + m_axi_bready, + m_axi_arvalid, + m_axi_rready, + m_axi_awaddr, + m_axi_araddr, + m_axi_arready, + s_axi_rready, + s_axi_awvalid, + aclk, + in, + s_axi_awid, + s_axi_awlen, + s_axi_awburst, + s_axi_awsize, + s_axi_awprot, + s_axi_awaddr, + m_axi_bresp, + s_axi_arid, + s_axi_arlen, + s_axi_arburst, + s_axi_arsize, + s_axi_arprot, + s_axi_araddr, + m_axi_awready, + m_axi_bvalid, + m_axi_rvalid, + s_axi_bready, + s_axi_arvalid, + aresetn); + output s_axi_rvalid; + output s_axi_awready; + output [22:0]Q; + output s_axi_arready; + output [22:0]\m_payload_i_reg[34] ; + output s_axi_bvalid; + output [13:0]\m_payload_i_reg[13] ; + output [46:0]\m_payload_i_reg[46] ; + output m_axi_awvalid; + output m_axi_bready; + output m_axi_arvalid; + output m_axi_rready; + output [11:0]m_axi_awaddr; + output [11:0]m_axi_araddr; + input m_axi_arready; + input s_axi_rready; + input s_axi_awvalid; + input aclk; + input [33:0]in; + input [11:0]s_axi_awid; + input [3:0]s_axi_awlen; + input [1:0]s_axi_awburst; + input [1:0]s_axi_awsize; + input [2:0]s_axi_awprot; + input [31:0]s_axi_awaddr; + input [1:0]m_axi_bresp; + input [11:0]s_axi_arid; + input [3:0]s_axi_arlen; + input [1:0]s_axi_arburst; + input [1:0]s_axi_arsize; + input [2:0]s_axi_arprot; + input [31:0]s_axi_araddr; + input m_axi_awready; + input m_axi_bvalid; + input m_axi_rvalid; + input s_axi_bready; + input s_axi_arvalid; + input aresetn; + + wire [22:0]Q; + wire \RD.ar_channel_0_n_1 ; + wire \RD.ar_channel_0_n_10 ; + wire \RD.ar_channel_0_n_11 ; + wire \RD.ar_channel_0_n_12 ; + wire \RD.ar_channel_0_n_13 ; + wire \RD.ar_channel_0_n_14 ; + wire \RD.ar_channel_0_n_15 ; + wire \RD.ar_channel_0_n_16 ; + wire \RD.ar_channel_0_n_17 ; + wire \RD.ar_channel_0_n_18 ; + wire \RD.ar_channel_0_n_19 ; + wire \RD.ar_channel_0_n_20 ; + wire \RD.ar_channel_0_n_21 ; + wire \RD.ar_channel_0_n_22 ; + wire \RD.ar_channel_0_n_23 ; + wire \RD.ar_channel_0_n_24 ; + wire \RD.ar_channel_0_n_25 ; + wire \RD.ar_channel_0_n_26 ; + wire \RD.ar_channel_0_n_27 ; + wire \RD.ar_channel_0_n_28 ; + wire \RD.ar_channel_0_n_4 ; + wire \RD.ar_channel_0_n_47 ; + wire \RD.ar_channel_0_n_48 ; + wire \RD.ar_channel_0_n_49 ; + wire \RD.ar_channel_0_n_5 ; + wire \RD.ar_channel_0_n_50 ; + wire \RD.ar_channel_0_n_6 ; + wire \RD.ar_channel_0_n_7 ; + wire \RD.ar_channel_0_n_8 ; + wire \RD.ar_channel_0_n_9 ; + wire \RD.r_channel_0_n_0 ; + wire \RD.r_channel_0_n_1 ; + wire SI_REG_n_10; + wire SI_REG_n_11; + wire SI_REG_n_128; + wire SI_REG_n_129; + wire SI_REG_n_130; + wire SI_REG_n_131; + wire SI_REG_n_144; + wire SI_REG_n_145; + wire SI_REG_n_146; + wire SI_REG_n_147; + wire SI_REG_n_148; + wire SI_REG_n_149; + wire SI_REG_n_150; + wire SI_REG_n_151; + wire SI_REG_n_152; + wire SI_REG_n_153; + wire SI_REG_n_154; + wire SI_REG_n_155; + wire SI_REG_n_156; + wire SI_REG_n_157; + wire SI_REG_n_158; + wire SI_REG_n_160; + wire SI_REG_n_161; + wire SI_REG_n_162; + wire SI_REG_n_163; + wire SI_REG_n_164; + wire SI_REG_n_165; + wire SI_REG_n_166; + wire SI_REG_n_167; + wire SI_REG_n_168; + wire SI_REG_n_169; + wire SI_REG_n_170; + wire SI_REG_n_171; + wire SI_REG_n_172; + wire SI_REG_n_173; + wire SI_REG_n_174; + wire SI_REG_n_175; + wire SI_REG_n_176; + wire SI_REG_n_177; + wire SI_REG_n_178; + wire SI_REG_n_179; + wire SI_REG_n_180; + wire SI_REG_n_181; + wire SI_REG_n_182; + wire SI_REG_n_183; + wire SI_REG_n_184; + wire SI_REG_n_185; + wire SI_REG_n_186; + wire SI_REG_n_187; + wire SI_REG_n_188; + wire SI_REG_n_66; + wire SI_REG_n_67; + wire SI_REG_n_68; + wire SI_REG_n_69; + wire SI_REG_n_70; + wire SI_REG_n_71; + wire SI_REG_n_72; + wire SI_REG_n_73; + wire SI_REG_n_8; + wire SI_REG_n_9; + wire SI_REG_n_91; + wire SI_REG_n_92; + wire \WR.aw_channel_0_n_19 ; + wire \WR.aw_channel_0_n_20 ; + wire \WR.aw_channel_0_n_21 ; + wire \WR.aw_channel_0_n_22 ; + wire \WR.aw_channel_0_n_23 ; + wire \WR.aw_channel_0_n_24 ; + wire \WR.aw_channel_0_n_25 ; + wire \WR.aw_channel_0_n_26 ; + wire \WR.aw_channel_0_n_27 ; + wire \WR.aw_channel_0_n_28 ; + wire \WR.aw_channel_0_n_29 ; + wire \WR.aw_channel_0_n_30 ; + wire \WR.aw_channel_0_n_4 ; + wire \WR.aw_channel_0_n_48 ; + wire \WR.aw_channel_0_n_49 ; + wire \WR.aw_channel_0_n_5 ; + wire \WR.aw_channel_0_n_50 ; + wire \WR.aw_channel_0_n_51 ; + wire aclk; + wire \ar.ar_pipe/m_valid_i0 ; + wire \ar.ar_pipe/p_1_in ; + wire \ar.ar_pipe/s_ready_i0 ; + wire [1:0]\ar_cmd_fsm_0/state ; + wire areset_d1; + wire areset_d1_i_1_n_0; + wire aresetn; + wire [1:0]\aw_cmd_fsm_0/state ; + wire [11:0]axaddr_incr; + wire [11:0]axaddr_wrap; + wire [1:0]axsize; + wire [11:0]b_awid; + wire [3:0]b_awlen; + wire b_push; + wire [1:0]\bid_fifo_0/cnt_read ; + wire \cmd_translator_0/incr_cmd_0/sel_first ; + wire \cmd_translator_0/incr_cmd_0/sel_first_0 ; + wire [33:0]in; + wire [11:0]m_axi_araddr; + wire m_axi_arready; + wire m_axi_arvalid; + wire [11:0]m_axi_awaddr; + wire m_axi_awready; + wire m_axi_awvalid; + wire m_axi_bready; + wire [1:0]m_axi_bresp; + wire m_axi_bvalid; + wire m_axi_rready; + wire m_axi_rvalid; + wire [13:0]\m_payload_i_reg[13] ; + wire [22:0]\m_payload_i_reg[34] ; + wire [46:0]\m_payload_i_reg[46] ; + wire r_push; + wire r_rlast; + wire [11:0]s_arid; + wire [11:0]s_arid_r; + wire [11:0]s_awid; + wire [31:0]s_axi_araddr; + wire [1:0]s_axi_arburst; + wire [11:0]s_axi_arid; + wire [3:0]s_axi_arlen; + wire [2:0]s_axi_arprot; + wire s_axi_arready; + wire [1:0]s_axi_arsize; + wire s_axi_arvalid; + wire [31:0]s_axi_awaddr; + wire [1:0]s_axi_awburst; + wire [11:0]s_axi_awid; + wire [3:0]s_axi_awlen; + wire [2:0]s_axi_awprot; + wire s_axi_awready; + wire [1:0]s_axi_awsize; + wire s_axi_awvalid; + wire s_axi_bready; + wire s_axi_bvalid; + wire s_axi_rready; + wire s_axi_rvalid; + wire sel_first; + wire shandshake; + wire [11:0]si_rs_araddr; + wire [1:1]si_rs_arburst; + wire [3:0]si_rs_arlen; + wire si_rs_arvalid; + wire [11:0]si_rs_awaddr; + wire [1:1]si_rs_awburst; + wire [3:0]si_rs_awlen; + wire si_rs_awvalid; + wire [11:0]si_rs_bid; + wire si_rs_bready; + wire [1:0]si_rs_bresp; + wire si_rs_bvalid; + wire [31:0]si_rs_rdata; + wire [11:0]si_rs_rid; + wire si_rs_rlast; + wire si_rs_rready; + wire [1:0]si_rs_rresp; + + NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_ar_channel \RD.ar_channel_0 + (.D({SI_REG_n_176,SI_REG_n_177,SI_REG_n_178,SI_REG_n_179,SI_REG_n_180,SI_REG_n_181,SI_REG_n_182}), + .E(\ar.ar_pipe/p_1_in ), + .\FSM_sequential_state_reg[0] (\RD.r_channel_0_n_1 ), + .\FSM_sequential_state_reg[1] (\RD.ar_channel_0_n_4 ), + .O({SI_REG_n_152,SI_REG_n_153,SI_REG_n_154,SI_REG_n_155}), + .Q(\ar_cmd_fsm_0/state ), + .S({SI_REG_n_128,SI_REG_n_129,SI_REG_n_130,SI_REG_n_131}), + .aclk(aclk), + .areset_d1(areset_d1), + .\axaddr_incr_reg[11] ({\RD.ar_channel_0_n_17 ,\RD.ar_channel_0_n_18 ,\RD.ar_channel_0_n_19 ,\RD.ar_channel_0_n_20 ,\RD.ar_channel_0_n_21 ,\RD.ar_channel_0_n_22 ,\RD.ar_channel_0_n_23 ,\RD.ar_channel_0_n_24 ,\RD.ar_channel_0_n_25 ,\RD.ar_channel_0_n_26 ,\RD.ar_channel_0_n_27 ,\RD.ar_channel_0_n_28 }), + .\axaddr_incr_reg[3] ({SI_REG_n_70,SI_REG_n_71,SI_REG_n_72,SI_REG_n_73}), + .\axaddr_incr_reg[3]_0 ({SI_REG_n_144,SI_REG_n_145,SI_REG_n_146,SI_REG_n_147}), + .\axaddr_incr_reg[7] ({SI_REG_n_148,SI_REG_n_149,SI_REG_n_150,SI_REG_n_151}), + .\axaddr_offset_r_reg[0] (SI_REG_n_184), + .\axaddr_offset_r_reg[1] (SI_REG_n_187), + .\axaddr_offset_r_reg[1]_0 (SI_REG_n_186), + .\axaddr_offset_r_reg[2] (SI_REG_n_188), + .\axaddr_offset_r_reg[2]_0 (SI_REG_n_183), + .\axaddr_offset_r_reg[3] (SI_REG_n_161), + .\axaddr_wrap_reg[11] ({\RD.ar_channel_0_n_5 ,\RD.ar_channel_0_n_6 ,\RD.ar_channel_0_n_7 ,\RD.ar_channel_0_n_8 ,\RD.ar_channel_0_n_9 ,\RD.ar_channel_0_n_10 ,\RD.ar_channel_0_n_11 ,\RD.ar_channel_0_n_12 ,\RD.ar_channel_0_n_13 ,\RD.ar_channel_0_n_14 ,\RD.ar_channel_0_n_15 ,\RD.ar_channel_0_n_16 }), + .\axlen_cnt_reg[3] (SI_REG_n_162), + .m_axi_arready(m_axi_arready), + .m_axi_arvalid(m_axi_arvalid), + .\m_payload_i_reg[3] ({\RD.ar_channel_0_n_47 ,\RD.ar_channel_0_n_48 ,\RD.ar_channel_0_n_49 ,\RD.ar_channel_0_n_50 }), + .m_valid_i0(\ar.ar_pipe/m_valid_i0 ), + .m_valid_i_reg(s_axi_arready), + .next_pending_r_reg(SI_REG_n_163), + .r_push(r_push), + .r_rlast(r_rlast), + .\s_arid_r_reg[11]_0 (s_arid_r), + .\s_arid_r_reg[11]_1 ({s_arid,si_rs_arlen,si_rs_arburst,SI_REG_n_91,SI_REG_n_92,si_rs_araddr}), + .s_axi_arvalid(s_axi_arvalid), + .s_ready_i0(\ar.ar_pipe/s_ready_i0 ), + .sel_first(\cmd_translator_0/incr_cmd_0/sel_first ), + .sel_first_reg(\RD.ar_channel_0_n_1 ), + .si_rs_arvalid(si_rs_arvalid), + .\wrap_second_len_r_reg[3] (SI_REG_n_160)); + NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_r_channel \RD.r_channel_0 + (.D(s_arid_r), + .aclk(aclk), + .areset_d1(areset_d1), + .\cnt_read_reg[2] (\RD.r_channel_0_n_0 ), + .\cnt_read_reg[4] (\RD.r_channel_0_n_1 ), + .\cnt_read_reg[4]_0 (SI_REG_n_164), + .in(in), + .m_axi_rready(m_axi_rready), + .m_axi_rvalid(m_axi_rvalid), + .out({si_rs_rresp,si_rs_rdata}), + .r_push(r_push), + .r_push_r_reg_0({si_rs_rid,si_rs_rlast}), + .r_rlast(r_rlast), + .si_rs_rready(si_rs_rready)); + NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axi_register_slice SI_REG + (.D({SI_REG_n_165,SI_REG_n_166,SI_REG_n_167,SI_REG_n_168,SI_REG_n_169,SI_REG_n_170,SI_REG_n_171}), + .E(\WR.aw_channel_0_n_5 ), + .\FSM_sequential_state_reg[0] (SI_REG_n_157), + .\FSM_sequential_state_reg[1] (SI_REG_n_160), + .O({SI_REG_n_152,SI_REG_n_153,SI_REG_n_154,SI_REG_n_155}), + .Q({\WR.aw_channel_0_n_19 ,\WR.aw_channel_0_n_20 ,\WR.aw_channel_0_n_21 ,\WR.aw_channel_0_n_22 ,\WR.aw_channel_0_n_23 ,\WR.aw_channel_0_n_24 ,\WR.aw_channel_0_n_25 ,\WR.aw_channel_0_n_26 ,\WR.aw_channel_0_n_27 ,\WR.aw_channel_0_n_28 ,\WR.aw_channel_0_n_29 ,\WR.aw_channel_0_n_30 }), + .S({SI_REG_n_8,SI_REG_n_9,SI_REG_n_10,SI_REG_n_11}), + .aclk(aclk), + .aresetn(aresetn), + .axaddr_incr(axaddr_incr), + .\axaddr_incr_reg[3] ({SI_REG_n_70,SI_REG_n_71,SI_REG_n_72,SI_REG_n_73}), + .\axaddr_incr_reg[3]_0 ({\WR.aw_channel_0_n_48 ,\WR.aw_channel_0_n_49 ,\WR.aw_channel_0_n_50 ,\WR.aw_channel_0_n_51 }), + .\axaddr_incr_reg[3]_1 ({\RD.ar_channel_0_n_47 ,\RD.ar_channel_0_n_48 ,\RD.ar_channel_0_n_49 ,\RD.ar_channel_0_n_50 }), + .\axaddr_wrap_reg[3] ({SI_REG_n_66,SI_REG_n_67,SI_REG_n_68,SI_REG_n_69}), + .\axaddr_wrap_reg[3]_0 ({SI_REG_n_128,SI_REG_n_129,SI_REG_n_130,SI_REG_n_131}), + .\axlen_cnt_reg[3] (\ar_cmd_fsm_0/state ), + .b_push(b_push), + .m_axi_araddr(m_axi_araddr), + .\m_axi_araddr[11] ({\RD.ar_channel_0_n_17 ,\RD.ar_channel_0_n_18 ,\RD.ar_channel_0_n_19 ,\RD.ar_channel_0_n_20 ,\RD.ar_channel_0_n_21 ,\RD.ar_channel_0_n_22 ,\RD.ar_channel_0_n_23 ,\RD.ar_channel_0_n_24 ,\RD.ar_channel_0_n_25 ,\RD.ar_channel_0_n_26 ,\RD.ar_channel_0_n_27 ,\RD.ar_channel_0_n_28 }), + .\m_axi_araddr[11]_0 ({\RD.ar_channel_0_n_5 ,\RD.ar_channel_0_n_6 ,\RD.ar_channel_0_n_7 ,\RD.ar_channel_0_n_8 ,\RD.ar_channel_0_n_9 ,\RD.ar_channel_0_n_10 ,\RD.ar_channel_0_n_11 ,\RD.ar_channel_0_n_12 ,\RD.ar_channel_0_n_13 ,\RD.ar_channel_0_n_14 ,\RD.ar_channel_0_n_15 ,\RD.ar_channel_0_n_16 }), + .\m_axi_araddr[11]_1 (\RD.ar_channel_0_n_1 ), + .m_axi_awaddr(m_axi_awaddr), + .\m_axi_awaddr[11] (axaddr_wrap), + .\m_payload_i_reg[0] (\ar.ar_pipe/p_1_in ), + .\m_payload_i_reg[13] (\m_payload_i_reg[13] ), + .\m_payload_i_reg[1] (SI_REG_n_173), + .\m_payload_i_reg[1]_0 (SI_REG_n_175), + .\m_payload_i_reg[1]_1 (SI_REG_n_184), + .\m_payload_i_reg[1]_2 (SI_REG_n_186), + .\m_payload_i_reg[2] (SI_REG_n_174), + .\m_payload_i_reg[2]_0 (SI_REG_n_183), + .\m_payload_i_reg[2]_1 (SI_REG_n_185), + .\m_payload_i_reg[2]_2 (SI_REG_n_187), + .\m_payload_i_reg[3] ({SI_REG_n_144,SI_REG_n_145,SI_REG_n_146,SI_REG_n_147}), + .\m_payload_i_reg[45] (SI_REG_n_156), + .\m_payload_i_reg[45]_0 (SI_REG_n_163), + .\m_payload_i_reg[46] (\m_payload_i_reg[46] ), + .\m_payload_i_reg[47] (SI_REG_n_162), + .\m_payload_i_reg[4] (SI_REG_n_172), + .\m_payload_i_reg[4]_0 (SI_REG_n_188), + .\m_payload_i_reg[5] (SI_REG_n_158), + .\m_payload_i_reg[61] ({s_awid,si_rs_awlen,si_rs_awburst,axsize,Q,si_rs_awaddr}), + .\m_payload_i_reg[61]_0 ({s_arid,si_rs_arlen,si_rs_arburst,SI_REG_n_91,SI_REG_n_92,\m_payload_i_reg[34] ,si_rs_araddr}), + .\m_payload_i_reg[6] (SI_REG_n_161), + .\m_payload_i_reg[6]_0 ({SI_REG_n_176,SI_REG_n_177,SI_REG_n_178,SI_REG_n_179,SI_REG_n_180,SI_REG_n_181,SI_REG_n_182}), + .\m_payload_i_reg[7] ({SI_REG_n_148,SI_REG_n_149,SI_REG_n_150,SI_REG_n_151}), + .m_valid_i0(\ar.ar_pipe/m_valid_i0 ), + .m_valid_i_reg(s_axi_bvalid), + .m_valid_i_reg_0(s_axi_rvalid), + .m_valid_i_reg_1(\RD.r_channel_0_n_0 ), + .next_pending_r_reg(\WR.aw_channel_0_n_4 ), + .next_pending_r_reg_0(\RD.ar_channel_0_n_4 ), + .out(si_rs_bid), + .s_axi_araddr(s_axi_araddr), + .s_axi_arburst(s_axi_arburst), + .s_axi_arid(s_axi_arid), + .s_axi_arlen(s_axi_arlen), + .s_axi_arprot(s_axi_arprot), + .s_axi_arsize(s_axi_arsize), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awburst(s_axi_awburst), + .s_axi_awid(s_axi_awid), + .s_axi_awlen(s_axi_awlen), + .s_axi_awprot(s_axi_awprot), + .s_axi_awsize(s_axi_awsize), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_bready(s_axi_bready), + .s_axi_rready(s_axi_rready), + .s_ready_i0(\ar.ar_pipe/s_ready_i0 ), + .s_ready_i_reg(s_axi_awready), + .s_ready_i_reg_0(s_axi_arready), + .s_ready_i_reg_1(SI_REG_n_164), + .sel_first(sel_first), + .sel_first_0(\cmd_translator_0/incr_cmd_0/sel_first_0 ), + .sel_first_1(\cmd_translator_0/incr_cmd_0/sel_first ), + .shandshake(shandshake), + .si_rs_arvalid(si_rs_arvalid), + .si_rs_awvalid(si_rs_awvalid), + .si_rs_bready(si_rs_bready), + .si_rs_bvalid(si_rs_bvalid), + .si_rs_rready(si_rs_rready), + .\skid_buffer_reg[1] (si_rs_bresp), + .\skid_buffer_reg[33] ({si_rs_rresp,si_rs_rdata}), + .\skid_buffer_reg[46] ({si_rs_rid,si_rs_rlast}), + .\wrap_second_len_r_reg[3] (\aw_cmd_fsm_0/state )); + NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_aw_channel \WR.aw_channel_0 + (.D({SI_REG_n_165,SI_REG_n_166,SI_REG_n_167,SI_REG_n_168,SI_REG_n_169,SI_REG_n_170,SI_REG_n_171}), + .E(\WR.aw_channel_0_n_5 ), + .\FSM_sequential_state_reg[0] (\WR.aw_channel_0_n_4 ), + .Q(\aw_cmd_fsm_0/state ), + .S({SI_REG_n_8,SI_REG_n_9,SI_REG_n_10,SI_REG_n_11}), + .aclk(aclk), + .areset_d1(areset_d1), + .axaddr_incr(axaddr_incr), + .\axaddr_incr_reg[11] ({\WR.aw_channel_0_n_19 ,\WR.aw_channel_0_n_20 ,\WR.aw_channel_0_n_21 ,\WR.aw_channel_0_n_22 ,\WR.aw_channel_0_n_23 ,\WR.aw_channel_0_n_24 ,\WR.aw_channel_0_n_25 ,\WR.aw_channel_0_n_26 ,\WR.aw_channel_0_n_27 ,\WR.aw_channel_0_n_28 ,\WR.aw_channel_0_n_29 ,\WR.aw_channel_0_n_30 }), + .\axaddr_offset_r_reg[0] (SI_REG_n_175), + .\axaddr_offset_r_reg[1] (SI_REG_n_185), + .\axaddr_offset_r_reg[1]_0 (SI_REG_n_173), + .\axaddr_offset_r_reg[2] (SI_REG_n_172), + .\axaddr_offset_r_reg[2]_0 (SI_REG_n_174), + .\axaddr_offset_r_reg[3] (SI_REG_n_158), + .\axaddr_wrap_reg[11] (axaddr_wrap), + .\axaddr_wrap_reg[3] ({SI_REG_n_66,SI_REG_n_67,SI_REG_n_68,SI_REG_n_69}), + .b_push(b_push), + .cnt_read(\bid_fifo_0/cnt_read ), + .in({b_awid,b_awlen}), + .m_axi_awready(m_axi_awready), + .m_axi_awvalid(m_axi_awvalid), + .\m_payload_i_reg[3] ({\WR.aw_channel_0_n_48 ,\WR.aw_channel_0_n_49 ,\WR.aw_channel_0_n_50 ,\WR.aw_channel_0_n_51 }), + .next_pending_r_reg(SI_REG_n_156), + .\s_awid_r_reg[11]_0 ({s_awid,si_rs_awlen,si_rs_awburst,axsize,si_rs_awaddr}), + .sel_first(sel_first), + .sel_first_0(\cmd_translator_0/incr_cmd_0/sel_first_0 ), + .si_rs_awvalid(si_rs_awvalid), + .\wrap_second_len_r_reg[3] (SI_REG_n_157)); + NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_b_channel \WR.b_channel_0 + (.aclk(aclk), + .areset_d1(areset_d1), + .b_push(b_push), + .cnt_read(\bid_fifo_0/cnt_read ), + .in({b_awid,b_awlen}), + .m_axi_bready(m_axi_bready), + .m_axi_bresp(m_axi_bresp), + .m_axi_bvalid(m_axi_bvalid), + .out(si_rs_bid), + .\s_bresp_acc_reg[1]_0 (si_rs_bresp), + .shandshake(shandshake), + .si_rs_bready(si_rs_bready), + .si_rs_bvalid(si_rs_bvalid)); + LUT1 #( + .INIT(2'h1)) + areset_d1_i_1 + (.I0(aresetn), + .O(areset_d1_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + areset_d1_reg + (.C(aclk), + .CE(1'b1), + .D(areset_d1_i_1_n_0), + .Q(areset_d1), + .R(1'b0)); +endmodule + +module NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_ar_channel + (sel_first, + sel_first_reg, + Q, + \FSM_sequential_state_reg[1] , + \axaddr_wrap_reg[11] , + \axaddr_incr_reg[11] , + r_push, + m_axi_arvalid, + m_valid_i0, + s_ready_i0, + E, + r_rlast, + \s_arid_r_reg[11]_0 , + \m_payload_i_reg[3] , + aclk, + si_rs_arvalid, + m_axi_arready, + \s_arid_r_reg[11]_1 , + S, + \axaddr_incr_reg[3] , + \wrap_second_len_r_reg[3] , + \axaddr_offset_r_reg[0] , + \FSM_sequential_state_reg[0] , + \axaddr_offset_r_reg[2] , + \axaddr_offset_r_reg[2]_0 , + next_pending_r_reg, + \axlen_cnt_reg[3] , + \axaddr_offset_r_reg[1] , + \axaddr_offset_r_reg[1]_0 , + \axaddr_offset_r_reg[3] , + areset_d1, + s_axi_arvalid, + m_valid_i_reg, + O, + \axaddr_incr_reg[7] , + \axaddr_incr_reg[3]_0 , + D); + output sel_first; + output sel_first_reg; + output [1:0]Q; + output \FSM_sequential_state_reg[1] ; + output [11:0]\axaddr_wrap_reg[11] ; + output [11:0]\axaddr_incr_reg[11] ; + output r_push; + output m_axi_arvalid; + output m_valid_i0; + output s_ready_i0; + output [0:0]E; + output r_rlast; + output [11:0]\s_arid_r_reg[11]_0 ; + output [3:0]\m_payload_i_reg[3] ; + input aclk; + input si_rs_arvalid; + input m_axi_arready; + input [30:0]\s_arid_r_reg[11]_1 ; + input [3:0]S; + input [3:0]\axaddr_incr_reg[3] ; + input \wrap_second_len_r_reg[3] ; + input \axaddr_offset_r_reg[0] ; + input \FSM_sequential_state_reg[0] ; + input \axaddr_offset_r_reg[2] ; + input \axaddr_offset_r_reg[2]_0 ; + input next_pending_r_reg; + input \axlen_cnt_reg[3] ; + input \axaddr_offset_r_reg[1] ; + input \axaddr_offset_r_reg[1]_0 ; + input \axaddr_offset_r_reg[3] ; + input areset_d1; + input s_axi_arvalid; + input m_valid_i_reg; + input [3:0]O; + input [3:0]\axaddr_incr_reg[7] ; + input [3:0]\axaddr_incr_reg[3]_0 ; + input [6:0]D; + + wire [6:0]D; + wire [0:0]E; + wire \FSM_sequential_state_reg[0] ; + wire \FSM_sequential_state_reg[1] ; + wire [3:0]O; + wire [1:0]Q; + wire [3:0]S; + wire aclk; + wire ar_cmd_fsm_0_n_0; + wire ar_cmd_fsm_0_n_1; + wire ar_cmd_fsm_0_n_10; + wire ar_cmd_fsm_0_n_16; + wire ar_cmd_fsm_0_n_17; + wire ar_cmd_fsm_0_n_19; + wire ar_cmd_fsm_0_n_2; + wire ar_cmd_fsm_0_n_20; + wire ar_cmd_fsm_0_n_21; + wire ar_cmd_fsm_0_n_22; + wire ar_cmd_fsm_0_n_23; + wire ar_cmd_fsm_0_n_24; + wire ar_cmd_fsm_0_n_25; + wire ar_cmd_fsm_0_n_26; + wire ar_cmd_fsm_0_n_27; + wire ar_cmd_fsm_0_n_28; + wire ar_cmd_fsm_0_n_29; + wire ar_cmd_fsm_0_n_3; + wire ar_cmd_fsm_0_n_30; + wire ar_cmd_fsm_0_n_31; + wire ar_cmd_fsm_0_n_32; + wire ar_cmd_fsm_0_n_33; + wire areset_d1; + wire [11:0]\axaddr_incr_reg[11] ; + wire [3:0]\axaddr_incr_reg[3] ; + wire [3:0]\axaddr_incr_reg[3]_0 ; + wire [3:0]\axaddr_incr_reg[7] ; + wire \axaddr_offset_r_reg[0] ; + wire \axaddr_offset_r_reg[1] ; + wire \axaddr_offset_r_reg[1]_0 ; + wire \axaddr_offset_r_reg[2] ; + wire \axaddr_offset_r_reg[2]_0 ; + wire \axaddr_offset_r_reg[3] ; + wire [11:0]\axaddr_wrap_reg[11] ; + wire \axlen_cnt_reg[3] ; + wire cmd_translator_0_n_0; + wire cmd_translator_0_n_20; + wire cmd_translator_0_n_21; + wire cmd_translator_0_n_22; + wire cmd_translator_0_n_23; + wire cmd_translator_0_n_24; + wire cmd_translator_0_n_25; + wire cmd_translator_0_n_26; + wire cmd_translator_0_n_27; + wire cmd_translator_0_n_3; + wire cmd_translator_0_n_4; + wire cmd_translator_0_n_40; + wire cmd_translator_0_n_42; + wire cmd_translator_0_n_5; + wire cmd_translator_0_n_51; + wire cmd_translator_0_n_52; + wire cmd_translator_0_n_53; + wire cmd_translator_0_n_54; + wire cmd_translator_0_n_55; + wire cmd_translator_0_n_56; + wire cmd_translator_0_n_57; + wire cmd_translator_0_n_58; + wire cmd_translator_0_n_59; + wire cmd_translator_0_n_6; + wire cmd_translator_0_n_60; + wire cmd_translator_0_n_61; + wire cmd_translator_0_n_62; + wire cmd_translator_0_n_7; + wire m_axi_arready; + wire m_axi_arvalid; + wire [3:0]\m_payload_i_reg[3] ; + wire m_valid_i0; + wire m_valid_i_reg; + wire next_pending_r_reg; + wire r_push; + wire r_rlast; + wire [11:0]\s_arid_r_reg[11]_0 ; + wire [30:0]\s_arid_r_reg[11]_1 ; + wire s_axi_arvalid; + wire s_ready_i0; + wire sel_first; + wire sel_first_i; + wire sel_first_reg; + wire si_rs_arvalid; + wire [3:0]\wrap_cmd_0/axaddr_offset ; + wire [3:0]\wrap_cmd_0/axaddr_offset_r ; + wire [3:0]\wrap_cmd_0/wrap_second_len ; + wire [3:0]\wrap_cmd_0/wrap_second_len_r ; + wire \wrap_second_len_r_reg[3] ; + + NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm ar_cmd_fsm_0 + (.D({ar_cmd_fsm_0_n_0,ar_cmd_fsm_0_n_1,ar_cmd_fsm_0_n_2,ar_cmd_fsm_0_n_3}), + .E(ar_cmd_fsm_0_n_20), + .\FSM_sequential_state_reg[0]_0 (\FSM_sequential_state_reg[0] ), + .\FSM_sequential_state_reg[1]_0 (ar_cmd_fsm_0_n_10), + .\FSM_sequential_state_reg[1]_1 (\FSM_sequential_state_reg[1] ), + .\FSM_sequential_state_reg[1]_2 (r_push), + .\FSM_sequential_state_reg[1]_3 (cmd_translator_0_n_40), + .O({cmd_translator_0_n_24,cmd_translator_0_n_25,cmd_translator_0_n_26,cmd_translator_0_n_27}), + .Q(Q), + .aclk(aclk), + .areset_d1(areset_d1), + .\axaddr_incr_reg[0] (sel_first), + .axaddr_offset(\wrap_cmd_0/axaddr_offset ), + .\axaddr_offset_r_reg[0] (\axaddr_offset_r_reg[0] ), + .\axaddr_offset_r_reg[1] (\axaddr_offset_r_reg[1] ), + .\axaddr_offset_r_reg[1]_0 (\axaddr_offset_r_reg[1]_0 ), + .\axaddr_offset_r_reg[2] (\axaddr_offset_r_reg[2] ), + .\axaddr_offset_r_reg[2]_0 (\axaddr_offset_r_reg[2]_0 ), + .\axaddr_offset_r_reg[3] (\wrap_cmd_0/axaddr_offset_r ), + .\axaddr_offset_r_reg[3]_0 ({\s_arid_r_reg[11]_1 [18],\s_arid_r_reg[11]_1 [15],\s_arid_r_reg[11]_1 [11:0]}), + .\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3] ), + .\axaddr_wrap_reg[10] (cmd_translator_0_n_42), + .\axaddr_wrap_reg[11] ({cmd_translator_0_n_51,cmd_translator_0_n_52,cmd_translator_0_n_53,cmd_translator_0_n_54,cmd_translator_0_n_55,cmd_translator_0_n_56,cmd_translator_0_n_57,cmd_translator_0_n_58,cmd_translator_0_n_59,cmd_translator_0_n_60,cmd_translator_0_n_61,cmd_translator_0_n_62}), + .\axaddr_wrap_reg[3] ({cmd_translator_0_n_4,cmd_translator_0_n_5,cmd_translator_0_n_6,cmd_translator_0_n_7}), + .\axaddr_wrap_reg[7] ({cmd_translator_0_n_20,cmd_translator_0_n_21,cmd_translator_0_n_22,cmd_translator_0_n_23}), + .\axlen_cnt_reg[7] (cmd_translator_0_n_3), + .m_axi_arready(m_axi_arready), + .m_axi_arready_0(ar_cmd_fsm_0_n_16), + .m_axi_arready_1(ar_cmd_fsm_0_n_17), + .m_axi_arready_2(ar_cmd_fsm_0_n_19), + .m_axi_arvalid(m_axi_arvalid), + .\m_payload_i_reg[11] ({ar_cmd_fsm_0_n_22,ar_cmd_fsm_0_n_23,ar_cmd_fsm_0_n_24,ar_cmd_fsm_0_n_25,ar_cmd_fsm_0_n_26,ar_cmd_fsm_0_n_27,ar_cmd_fsm_0_n_28,ar_cmd_fsm_0_n_29,ar_cmd_fsm_0_n_30,ar_cmd_fsm_0_n_31,ar_cmd_fsm_0_n_32,ar_cmd_fsm_0_n_33}), + .m_valid_i0(m_valid_i0), + .m_valid_i_reg(E), + .m_valid_i_reg_0(m_valid_i_reg), + .s_axi_arvalid(s_axi_arvalid), + .s_ready_i0(s_ready_i0), + .sel_first_i(sel_first_i), + .sel_first_reg(ar_cmd_fsm_0_n_21), + .sel_first_reg_0(sel_first_reg), + .sel_first_reg_1(cmd_translator_0_n_0), + .si_rs_arvalid(si_rs_arvalid), + .\wrap_second_len_r_reg[3] (\wrap_cmd_0/wrap_second_len ), + .\wrap_second_len_r_reg[3]_0 (\wrap_cmd_0/wrap_second_len_r ), + .\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3] )); + NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_cmd_translator_1 cmd_translator_0 + (.D(\wrap_cmd_0/axaddr_offset ), + .E(ar_cmd_fsm_0_n_20), + .O({cmd_translator_0_n_24,cmd_translator_0_n_25,cmd_translator_0_n_26,cmd_translator_0_n_27}), + .Q(Q), + .S(S), + .aclk(aclk), + .\axaddr_incr_reg[0] (ar_cmd_fsm_0_n_21), + .\axaddr_incr_reg[11] (\axaddr_incr_reg[11] ), + .\axaddr_incr_reg[11]_0 (O), + .\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ), + .\axaddr_incr_reg[3]_0 (\axaddr_incr_reg[3]_0 ), + .\axaddr_incr_reg[7] (\axaddr_incr_reg[7] ), + .\axaddr_offset_r_reg[3] (\wrap_cmd_0/axaddr_offset_r ), + .\axaddr_wrap_reg[0] (ar_cmd_fsm_0_n_19), + .\axaddr_wrap_reg[11] (\axaddr_wrap_reg[11] ), + .\axaddr_wrap_reg[11]_0 ({ar_cmd_fsm_0_n_22,ar_cmd_fsm_0_n_23,ar_cmd_fsm_0_n_24,ar_cmd_fsm_0_n_25,ar_cmd_fsm_0_n_26,ar_cmd_fsm_0_n_27,ar_cmd_fsm_0_n_28,ar_cmd_fsm_0_n_29,ar_cmd_fsm_0_n_30,ar_cmd_fsm_0_n_31,ar_cmd_fsm_0_n_32,ar_cmd_fsm_0_n_33}), + .\axaddr_wrap_reg[3] ({cmd_translator_0_n_4,cmd_translator_0_n_5,cmd_translator_0_n_6,cmd_translator_0_n_7}), + .\axaddr_wrap_reg[7] ({cmd_translator_0_n_20,cmd_translator_0_n_21,cmd_translator_0_n_22,cmd_translator_0_n_23}), + .\axlen_cnt_reg[0] (cmd_translator_0_n_42), + .\axlen_cnt_reg[1] (\FSM_sequential_state_reg[1] ), + .\axlen_cnt_reg[2] ({\s_arid_r_reg[11]_1 [17:7],\s_arid_r_reg[11]_1 [3:0]}), + .\axlen_cnt_reg[3] (\axlen_cnt_reg[3] ), + .\axlen_cnt_reg[7] (cmd_translator_0_n_3), + .\axlen_cnt_reg[7]_0 (ar_cmd_fsm_0_n_10), + .m_axi_arready(m_axi_arready), + .m_axi_arready_0(cmd_translator_0_n_40), + .\m_payload_i_reg[3] (\m_payload_i_reg[3] ), + .next_pending_r_reg(next_pending_r_reg), + .r_push(r_push), + .r_rlast(r_rlast), + .sel_first_i(sel_first_i), + .sel_first_reg_0(cmd_translator_0_n_0), + .sel_first_reg_1(sel_first), + .sel_first_reg_2(sel_first_reg), + .sel_first_reg_3(ar_cmd_fsm_0_n_17), + .sel_first_reg_4(ar_cmd_fsm_0_n_16), + .si_rs_arvalid(si_rs_arvalid), + .\wrap_boundary_axaddr_r_reg[11] ({cmd_translator_0_n_51,cmd_translator_0_n_52,cmd_translator_0_n_53,cmd_translator_0_n_54,cmd_translator_0_n_55,cmd_translator_0_n_56,cmd_translator_0_n_57,cmd_translator_0_n_58,cmd_translator_0_n_59,cmd_translator_0_n_60,cmd_translator_0_n_61,cmd_translator_0_n_62}), + .\wrap_boundary_axaddr_r_reg[6] (D), + .\wrap_cnt_r_reg[3] ({ar_cmd_fsm_0_n_0,ar_cmd_fsm_0_n_1,ar_cmd_fsm_0_n_2,ar_cmd_fsm_0_n_3}), + .\wrap_second_len_r_reg[3] (\wrap_cmd_0/wrap_second_len_r ), + .\wrap_second_len_r_reg[3]_0 (\wrap_cmd_0/wrap_second_len )); + FDRE \s_arid_r_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\s_arid_r_reg[11]_1 [19]), + .Q(\s_arid_r_reg[11]_0 [0]), + .R(1'b0)); + FDRE \s_arid_r_reg[10] + (.C(aclk), + .CE(1'b1), + .D(\s_arid_r_reg[11]_1 [29]), + .Q(\s_arid_r_reg[11]_0 [10]), + .R(1'b0)); + FDRE \s_arid_r_reg[11] + (.C(aclk), + .CE(1'b1), + .D(\s_arid_r_reg[11]_1 [30]), + .Q(\s_arid_r_reg[11]_0 [11]), + .R(1'b0)); + FDRE \s_arid_r_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\s_arid_r_reg[11]_1 [20]), + .Q(\s_arid_r_reg[11]_0 [1]), + .R(1'b0)); + FDRE \s_arid_r_reg[2] + (.C(aclk), + .CE(1'b1), + .D(\s_arid_r_reg[11]_1 [21]), + .Q(\s_arid_r_reg[11]_0 [2]), + .R(1'b0)); + FDRE \s_arid_r_reg[3] + (.C(aclk), + .CE(1'b1), + .D(\s_arid_r_reg[11]_1 [22]), + .Q(\s_arid_r_reg[11]_0 [3]), + .R(1'b0)); + FDRE \s_arid_r_reg[4] + (.C(aclk), + .CE(1'b1), + .D(\s_arid_r_reg[11]_1 [23]), + .Q(\s_arid_r_reg[11]_0 [4]), + .R(1'b0)); + FDRE \s_arid_r_reg[5] + (.C(aclk), + .CE(1'b1), + .D(\s_arid_r_reg[11]_1 [24]), + .Q(\s_arid_r_reg[11]_0 [5]), + .R(1'b0)); + FDRE \s_arid_r_reg[6] + (.C(aclk), + .CE(1'b1), + .D(\s_arid_r_reg[11]_1 [25]), + .Q(\s_arid_r_reg[11]_0 [6]), + .R(1'b0)); + FDRE \s_arid_r_reg[7] + (.C(aclk), + .CE(1'b1), + .D(\s_arid_r_reg[11]_1 [26]), + .Q(\s_arid_r_reg[11]_0 [7]), + .R(1'b0)); + FDRE \s_arid_r_reg[8] + (.C(aclk), + .CE(1'b1), + .D(\s_arid_r_reg[11]_1 [27]), + .Q(\s_arid_r_reg[11]_0 [8]), + .R(1'b0)); + FDRE \s_arid_r_reg[9] + (.C(aclk), + .CE(1'b1), + .D(\s_arid_r_reg[11]_1 [28]), + .Q(\s_arid_r_reg[11]_0 [9]), + .R(1'b0)); +endmodule + +module NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_aw_channel + (sel_first_0, + sel_first, + Q, + \FSM_sequential_state_reg[0] , + E, + b_push, + \axaddr_wrap_reg[11] , + \axaddr_incr_reg[11] , + m_axi_awvalid, + in, + \m_payload_i_reg[3] , + aclk, + \s_awid_r_reg[11]_0 , + si_rs_awvalid, + \axaddr_wrap_reg[3] , + S, + \wrap_second_len_r_reg[3] , + \axaddr_offset_r_reg[0] , + \axaddr_offset_r_reg[2] , + \axaddr_offset_r_reg[2]_0 , + next_pending_r_reg, + m_axi_awready, + areset_d1, + \axaddr_offset_r_reg[3] , + \axaddr_offset_r_reg[1] , + \axaddr_offset_r_reg[1]_0 , + cnt_read, + axaddr_incr, + D); + output sel_first_0; + output sel_first; + output [1:0]Q; + output \FSM_sequential_state_reg[0] ; + output [0:0]E; + output b_push; + output [11:0]\axaddr_wrap_reg[11] ; + output [11:0]\axaddr_incr_reg[11] ; + output m_axi_awvalid; + output [15:0]in; + output [3:0]\m_payload_i_reg[3] ; + input aclk; + input [30:0]\s_awid_r_reg[11]_0 ; + input si_rs_awvalid; + input [3:0]\axaddr_wrap_reg[3] ; + input [3:0]S; + input \wrap_second_len_r_reg[3] ; + input \axaddr_offset_r_reg[0] ; + input \axaddr_offset_r_reg[2] ; + input \axaddr_offset_r_reg[2]_0 ; + input next_pending_r_reg; + input m_axi_awready; + input areset_d1; + input \axaddr_offset_r_reg[3] ; + input \axaddr_offset_r_reg[1] ; + input \axaddr_offset_r_reg[1]_0 ; + input [1:0]cnt_read; + input [11:0]axaddr_incr; + input [6:0]D; + + wire [6:0]D; + wire [0:0]E; + wire \FSM_sequential_state_reg[0] ; + wire [1:0]Q; + wire [3:0]S; + wire aclk; + wire areset_d1; + wire aw_cmd_fsm_0_n_10; + wire aw_cmd_fsm_0_n_11; + wire aw_cmd_fsm_0_n_19; + wire aw_cmd_fsm_0_n_2; + wire aw_cmd_fsm_0_n_21; + wire aw_cmd_fsm_0_n_22; + wire aw_cmd_fsm_0_n_23; + wire aw_cmd_fsm_0_n_24; + wire aw_cmd_fsm_0_n_26; + wire aw_cmd_fsm_0_n_27; + wire aw_cmd_fsm_0_n_28; + wire aw_cmd_fsm_0_n_29; + wire aw_cmd_fsm_0_n_3; + wire aw_cmd_fsm_0_n_30; + wire aw_cmd_fsm_0_n_31; + wire aw_cmd_fsm_0_n_32; + wire aw_cmd_fsm_0_n_33; + wire aw_cmd_fsm_0_n_34; + wire aw_cmd_fsm_0_n_35; + wire aw_cmd_fsm_0_n_36; + wire aw_cmd_fsm_0_n_37; + wire [11:0]axaddr_incr; + wire [11:0]\axaddr_incr_reg[11] ; + wire \axaddr_offset_r_reg[0] ; + wire \axaddr_offset_r_reg[1] ; + wire \axaddr_offset_r_reg[1]_0 ; + wire \axaddr_offset_r_reg[2] ; + wire \axaddr_offset_r_reg[2]_0 ; + wire \axaddr_offset_r_reg[3] ; + wire [11:0]axaddr_wrap0; + wire [11:0]\axaddr_wrap_reg[11] ; + wire [3:0]\axaddr_wrap_reg[3] ; + wire b_push; + wire cmd_translator_0_n_2; + wire cmd_translator_0_n_43; + wire cmd_translator_0_n_44; + wire cmd_translator_0_n_5; + wire cmd_translator_0_n_6; + wire [1:0]cnt_read; + wire [15:0]in; + wire \incr_cmd_0/next_pending_r ; + wire m_axi_awready; + wire m_axi_awvalid; + wire [3:0]\m_payload_i_reg[3] ; + wire next; + wire next_pending_r_reg; + wire [30:0]\s_awid_r_reg[11]_0 ; + wire sel_first; + wire sel_first_0; + wire sel_first_i; + wire si_rs_awvalid; + wire [11:0]wrap_boundary_axaddr_r; + wire [3:0]\wrap_cmd_0/axaddr_offset ; + wire [3:0]\wrap_cmd_0/axaddr_offset_r ; + wire \wrap_cmd_0/next_pending_r ; + wire [3:0]\wrap_cmd_0/wrap_second_len ; + wire [3:0]\wrap_cmd_0/wrap_second_len_r ; + wire [3:2]wrap_cnt; + wire \wrap_second_len_r_reg[3] ; + + NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm aw_cmd_fsm_0 + (.D({wrap_cnt,aw_cmd_fsm_0_n_2,aw_cmd_fsm_0_n_3}), + .E(E), + .\FSM_sequential_state_reg[0]_0 (aw_cmd_fsm_0_n_10), + .\FSM_sequential_state_reg[0]_1 (aw_cmd_fsm_0_n_11), + .\FSM_sequential_state_reg[0]_2 (\FSM_sequential_state_reg[0] ), + .\FSM_sequential_state_reg[1]_0 (cmd_translator_0_n_43), + .Q(Q), + .aclk(aclk), + .areset_d1(areset_d1), + .axaddr_offset(\wrap_cmd_0/axaddr_offset ), + .\axaddr_offset_r_reg[0] (\axaddr_offset_r_reg[0] ), + .\axaddr_offset_r_reg[1] (\axaddr_offset_r_reg[1] ), + .\axaddr_offset_r_reg[1]_0 (\axaddr_offset_r_reg[1]_0 ), + .\axaddr_offset_r_reg[2] (\axaddr_offset_r_reg[2] ), + .\axaddr_offset_r_reg[2]_0 (\axaddr_offset_r_reg[2]_0 ), + .\axaddr_offset_r_reg[3] (\wrap_cmd_0/axaddr_offset_r ), + .\axaddr_offset_r_reg[3]_0 ({\s_awid_r_reg[11]_0 [18],\s_awid_r_reg[11]_0 [15:14],\s_awid_r_reg[11]_0 [11:0]}), + .\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3] ), + .axaddr_wrap0(axaddr_wrap0), + .\axaddr_wrap_reg[10] (cmd_translator_0_n_44), + .\axaddr_wrap_reg[11] (wrap_boundary_axaddr_r), + .\axlen_cnt_reg[2] (aw_cmd_fsm_0_n_19), + .\axlen_cnt_reg[2]_0 (aw_cmd_fsm_0_n_21), + .cnt_read(cnt_read), + .m_axi_awready(m_axi_awready), + .m_axi_awready_0(b_push), + .m_axi_awvalid(m_axi_awvalid), + .m_valid_i_reg(aw_cmd_fsm_0_n_22), + .next(next), + .next_pending_r(\incr_cmd_0/next_pending_r ), + .next_pending_r_0(\wrap_cmd_0/next_pending_r ), + .s_axburst_eq0_reg(cmd_translator_0_n_5), + .s_axburst_eq0_reg_0(cmd_translator_0_n_6), + .s_axburst_eq1_reg(next_pending_r_reg), + .sel_first(sel_first), + .sel_first_i(sel_first_i), + .sel_first_reg(aw_cmd_fsm_0_n_23), + .sel_first_reg_0(aw_cmd_fsm_0_n_24), + .sel_first_reg_1(sel_first_0), + .sel_first_reg_2(cmd_translator_0_n_2), + .si_rs_awvalid(si_rs_awvalid), + .\wrap_boundary_axaddr_r_reg[11] ({aw_cmd_fsm_0_n_26,aw_cmd_fsm_0_n_27,aw_cmd_fsm_0_n_28,aw_cmd_fsm_0_n_29,aw_cmd_fsm_0_n_30,aw_cmd_fsm_0_n_31,aw_cmd_fsm_0_n_32,aw_cmd_fsm_0_n_33,aw_cmd_fsm_0_n_34,aw_cmd_fsm_0_n_35,aw_cmd_fsm_0_n_36,aw_cmd_fsm_0_n_37}), + .\wrap_second_len_r_reg[3] (\wrap_cmd_0/wrap_second_len ), + .\wrap_second_len_r_reg[3]_0 (\wrap_cmd_0/wrap_second_len_r ), + .\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3] )); + NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_cmd_translator cmd_translator_0 + (.D(\wrap_cmd_0/axaddr_offset ), + .E(aw_cmd_fsm_0_n_22), + .Q(Q), + .S(S), + .aclk(aclk), + .axaddr_incr(axaddr_incr), + .\axaddr_incr_reg[11] (\axaddr_incr_reg[11] ), + .\axaddr_offset_r_reg[3] (\wrap_cmd_0/axaddr_offset_r ), + .axaddr_wrap0(axaddr_wrap0), + .\axaddr_wrap_reg[0] (aw_cmd_fsm_0_n_11), + .\axaddr_wrap_reg[11] (\axaddr_wrap_reg[11] ), + .\axaddr_wrap_reg[11]_0 ({aw_cmd_fsm_0_n_26,aw_cmd_fsm_0_n_27,aw_cmd_fsm_0_n_28,aw_cmd_fsm_0_n_29,aw_cmd_fsm_0_n_30,aw_cmd_fsm_0_n_31,aw_cmd_fsm_0_n_32,aw_cmd_fsm_0_n_33,aw_cmd_fsm_0_n_34,aw_cmd_fsm_0_n_35,aw_cmd_fsm_0_n_36,aw_cmd_fsm_0_n_37}), + .\axaddr_wrap_reg[3] (\axaddr_wrap_reg[3] ), + .\axlen_cnt_reg[0] (cmd_translator_0_n_44), + .\axlen_cnt_reg[2] (cmd_translator_0_n_6), + .\axlen_cnt_reg[3] ({\s_awid_r_reg[11]_0 [18:7],\s_awid_r_reg[11]_0 [3:0]}), + .\axlen_cnt_reg[3]_0 (\FSM_sequential_state_reg[0] ), + .\axlen_cnt_reg[5] (cmd_translator_0_n_5), + .\axlen_cnt_reg[5]_0 (aw_cmd_fsm_0_n_10), + .\m_payload_i_reg[3] (\m_payload_i_reg[3] ), + .next(next), + .next_pending_r(\incr_cmd_0/next_pending_r ), + .next_pending_r_0(\wrap_cmd_0/next_pending_r ), + .next_pending_r_reg(next_pending_r_reg), + .s_axburst_eq0_reg_0(aw_cmd_fsm_0_n_19), + .s_axburst_eq1_reg_0(cmd_translator_0_n_43), + .s_axburst_eq1_reg_1(aw_cmd_fsm_0_n_21), + .sel_first(sel_first), + .sel_first_i(sel_first_i), + .sel_first_reg_0(cmd_translator_0_n_2), + .sel_first_reg_1(sel_first_0), + .sel_first_reg_2(aw_cmd_fsm_0_n_24), + .sel_first_reg_3(aw_cmd_fsm_0_n_23), + .si_rs_awvalid(si_rs_awvalid), + .\wrap_boundary_axaddr_r_reg[11] (wrap_boundary_axaddr_r), + .\wrap_boundary_axaddr_r_reg[6] (D), + .\wrap_cnt_r_reg[3] ({wrap_cnt,aw_cmd_fsm_0_n_2,aw_cmd_fsm_0_n_3}), + .\wrap_second_len_r_reg[3] (\wrap_cmd_0/wrap_second_len_r ), + .\wrap_second_len_r_reg[3]_0 (\wrap_cmd_0/wrap_second_len )); + FDRE \s_awid_r_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\s_awid_r_reg[11]_0 [19]), + .Q(in[4]), + .R(1'b0)); + FDRE \s_awid_r_reg[10] + (.C(aclk), + .CE(1'b1), + .D(\s_awid_r_reg[11]_0 [29]), + .Q(in[14]), + .R(1'b0)); + FDRE \s_awid_r_reg[11] + (.C(aclk), + .CE(1'b1), + .D(\s_awid_r_reg[11]_0 [30]), + .Q(in[15]), + .R(1'b0)); + FDRE \s_awid_r_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\s_awid_r_reg[11]_0 [20]), + .Q(in[5]), + .R(1'b0)); + FDRE \s_awid_r_reg[2] + (.C(aclk), + .CE(1'b1), + .D(\s_awid_r_reg[11]_0 [21]), + .Q(in[6]), + .R(1'b0)); + FDRE \s_awid_r_reg[3] + (.C(aclk), + .CE(1'b1), + .D(\s_awid_r_reg[11]_0 [22]), + .Q(in[7]), + .R(1'b0)); + FDRE \s_awid_r_reg[4] + (.C(aclk), + .CE(1'b1), + .D(\s_awid_r_reg[11]_0 [23]), + .Q(in[8]), + .R(1'b0)); + FDRE \s_awid_r_reg[5] + (.C(aclk), + .CE(1'b1), + .D(\s_awid_r_reg[11]_0 [24]), + .Q(in[9]), + .R(1'b0)); + FDRE \s_awid_r_reg[6] + (.C(aclk), + .CE(1'b1), + .D(\s_awid_r_reg[11]_0 [25]), + .Q(in[10]), + .R(1'b0)); + FDRE \s_awid_r_reg[7] + (.C(aclk), + .CE(1'b1), + .D(\s_awid_r_reg[11]_0 [26]), + .Q(in[11]), + .R(1'b0)); + FDRE \s_awid_r_reg[8] + (.C(aclk), + .CE(1'b1), + .D(\s_awid_r_reg[11]_0 [27]), + .Q(in[12]), + .R(1'b0)); + FDRE \s_awid_r_reg[9] + (.C(aclk), + .CE(1'b1), + .D(\s_awid_r_reg[11]_0 [28]), + .Q(in[13]), + .R(1'b0)); + FDRE \s_awlen_r_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\s_awid_r_reg[11]_0 [15]), + .Q(in[0]), + .R(1'b0)); + FDRE \s_awlen_r_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\s_awid_r_reg[11]_0 [16]), + .Q(in[1]), + .R(1'b0)); + FDRE \s_awlen_r_reg[2] + (.C(aclk), + .CE(1'b1), + .D(\s_awid_r_reg[11]_0 [17]), + .Q(in[2]), + .R(1'b0)); + FDRE \s_awlen_r_reg[3] + (.C(aclk), + .CE(1'b1), + .D(\s_awid_r_reg[11]_0 [18]), + .Q(in[3]), + .R(1'b0)); +endmodule + +module NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_b_channel + (si_rs_bvalid, + cnt_read, + m_axi_bready, + out, + \s_bresp_acc_reg[1]_0 , + areset_d1, + shandshake, + aclk, + si_rs_bready, + m_axi_bvalid, + b_push, + in, + m_axi_bresp); + output si_rs_bvalid; + output [1:0]cnt_read; + output m_axi_bready; + output [11:0]out; + output [1:0]\s_bresp_acc_reg[1]_0 ; + input areset_d1; + input shandshake; + input aclk; + input si_rs_bready; + input m_axi_bvalid; + input b_push; + input [15:0]in; + input [1:0]m_axi_bresp; + + wire aclk; + wire areset_d1; + wire b_push; + wire bid_fifo_0_n_4; + wire bid_fifo_0_n_5; + wire \bresp_cnt[7]_i_3_n_0 ; + wire [7:0]bresp_cnt_reg; + wire bresp_fifo_0_n_0; + wire bresp_push; + wire [1:0]cnt_read; + wire [15:0]in; + wire m_axi_bready; + wire [1:0]m_axi_bresp; + wire m_axi_bvalid; + wire mhandshake; + wire mhandshake_r; + wire [11:0]out; + wire [7:0]p_0_in; + wire s_bresp_acc0; + wire \s_bresp_acc[0]_i_1_n_0 ; + wire \s_bresp_acc[1]_i_1_n_0 ; + wire [1:0]\s_bresp_acc_reg[1]_0 ; + wire \s_bresp_acc_reg_n_0_[0] ; + wire \s_bresp_acc_reg_n_0_[1] ; + wire shandshake; + wire shandshake_r; + wire si_rs_bready; + wire si_rs_bvalid; + + NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_simple_fifo bid_fifo_0 + (.Q(bresp_cnt_reg), + .SR(s_bresp_acc0), + .aclk(aclk), + .addr(cnt_read), + .areset_d1(areset_d1), + .b_push(b_push), + .\bresp_cnt_reg[1] (bid_fifo_0_n_4), + .\cnt_read_reg[1]_0 (bid_fifo_0_n_5), + .in(in), + .mhandshake_r(mhandshake_r), + .out(out), + .sel(bresp_push), + .shandshake_r(shandshake_r)); + LUT1 #( + .INIT(2'h1)) + \bresp_cnt[0]_i_1 + (.I0(bresp_cnt_reg[0]), + .O(p_0_in[0])); + (* SOFT_HLUTNM = "soft_lutpair126" *) + LUT2 #( + .INIT(4'h6)) + \bresp_cnt[1]_i_1 + (.I0(bresp_cnt_reg[1]), + .I1(bresp_cnt_reg[0]), + .O(p_0_in[1])); + (* SOFT_HLUTNM = "soft_lutpair126" *) + LUT3 #( + .INIT(8'h6A)) + \bresp_cnt[2]_i_1 + (.I0(bresp_cnt_reg[2]), + .I1(bresp_cnt_reg[0]), + .I2(bresp_cnt_reg[1]), + .O(p_0_in[2])); + (* SOFT_HLUTNM = "soft_lutpair124" *) + LUT4 #( + .INIT(16'h6AAA)) + \bresp_cnt[3]_i_1 + (.I0(bresp_cnt_reg[3]), + .I1(bresp_cnt_reg[1]), + .I2(bresp_cnt_reg[0]), + .I3(bresp_cnt_reg[2]), + .O(p_0_in[3])); + (* SOFT_HLUTNM = "soft_lutpair124" *) + LUT5 #( + .INIT(32'h6AAAAAAA)) + \bresp_cnt[4]_i_1 + (.I0(bresp_cnt_reg[4]), + .I1(bresp_cnt_reg[2]), + .I2(bresp_cnt_reg[0]), + .I3(bresp_cnt_reg[1]), + .I4(bresp_cnt_reg[3]), + .O(p_0_in[4])); + LUT6 #( + .INIT(64'h6AAAAAAAAAAAAAAA)) + \bresp_cnt[5]_i_1 + (.I0(bresp_cnt_reg[5]), + .I1(bresp_cnt_reg[3]), + .I2(bresp_cnt_reg[1]), + .I3(bresp_cnt_reg[0]), + .I4(bresp_cnt_reg[2]), + .I5(bresp_cnt_reg[4]), + .O(p_0_in[5])); + (* SOFT_HLUTNM = "soft_lutpair125" *) + LUT2 #( + .INIT(4'h6)) + \bresp_cnt[6]_i_1 + (.I0(bresp_cnt_reg[6]), + .I1(\bresp_cnt[7]_i_3_n_0 ), + .O(p_0_in[6])); + (* SOFT_HLUTNM = "soft_lutpair125" *) + LUT3 #( + .INIT(8'h6A)) + \bresp_cnt[7]_i_2 + (.I0(bresp_cnt_reg[7]), + .I1(\bresp_cnt[7]_i_3_n_0 ), + .I2(bresp_cnt_reg[6]), + .O(p_0_in[7])); + LUT6 #( + .INIT(64'h8000000000000000)) + \bresp_cnt[7]_i_3 + (.I0(bresp_cnt_reg[5]), + .I1(bresp_cnt_reg[3]), + .I2(bresp_cnt_reg[1]), + .I3(bresp_cnt_reg[0]), + .I4(bresp_cnt_reg[2]), + .I5(bresp_cnt_reg[4]), + .O(\bresp_cnt[7]_i_3_n_0 )); + FDRE \bresp_cnt_reg[0] + (.C(aclk), + .CE(mhandshake_r), + .D(p_0_in[0]), + .Q(bresp_cnt_reg[0]), + .R(s_bresp_acc0)); + FDRE \bresp_cnt_reg[1] + (.C(aclk), + .CE(mhandshake_r), + .D(p_0_in[1]), + .Q(bresp_cnt_reg[1]), + .R(s_bresp_acc0)); + FDRE \bresp_cnt_reg[2] + (.C(aclk), + .CE(mhandshake_r), + .D(p_0_in[2]), + .Q(bresp_cnt_reg[2]), + .R(s_bresp_acc0)); + FDRE \bresp_cnt_reg[3] + (.C(aclk), + .CE(mhandshake_r), + .D(p_0_in[3]), + .Q(bresp_cnt_reg[3]), + .R(s_bresp_acc0)); + FDRE \bresp_cnt_reg[4] + (.C(aclk), + .CE(mhandshake_r), + .D(p_0_in[4]), + .Q(bresp_cnt_reg[4]), + .R(s_bresp_acc0)); + FDRE \bresp_cnt_reg[5] + (.C(aclk), + .CE(mhandshake_r), + .D(p_0_in[5]), + .Q(bresp_cnt_reg[5]), + .R(s_bresp_acc0)); + FDRE \bresp_cnt_reg[6] + (.C(aclk), + .CE(mhandshake_r), + .D(p_0_in[6]), + .Q(bresp_cnt_reg[6]), + .R(s_bresp_acc0)); + FDRE \bresp_cnt_reg[7] + (.C(aclk), + .CE(mhandshake_r), + .D(p_0_in[7]), + .Q(bresp_cnt_reg[7]), + .R(s_bresp_acc0)); + NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized0 bresp_fifo_0 + (.aclk(aclk), + .areset_d1(areset_d1), + .areset_d1_reg(bresp_fifo_0_n_0), + .bvalid_i_reg(bid_fifo_0_n_5), + .\cnt_read_reg[1]_0 (bid_fifo_0_n_4), + .in({\s_bresp_acc_reg_n_0_[1] ,\s_bresp_acc_reg_n_0_[0] }), + .m_axi_bready(m_axi_bready), + .m_axi_bvalid(m_axi_bvalid), + .mhandshake(mhandshake), + .mhandshake_r(mhandshake_r), + .\s_bresp_acc_reg[1] (\s_bresp_acc_reg[1]_0 ), + .sel(bresp_push), + .shandshake_r(shandshake_r), + .si_rs_bready(si_rs_bready), + .si_rs_bvalid(si_rs_bvalid)); + FDRE #( + .INIT(1'b0)) + bvalid_i_reg + (.C(aclk), + .CE(1'b1), + .D(bresp_fifo_0_n_0), + .Q(si_rs_bvalid), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + mhandshake_r_reg + (.C(aclk), + .CE(1'b1), + .D(mhandshake), + .Q(mhandshake_r), + .R(areset_d1)); + LUT6 #( + .INIT(64'h00000000EACECCCC)) + \s_bresp_acc[0]_i_1 + (.I0(m_axi_bresp[0]), + .I1(\s_bresp_acc_reg_n_0_[0] ), + .I2(\s_bresp_acc_reg_n_0_[1] ), + .I3(m_axi_bresp[1]), + .I4(mhandshake), + .I5(s_bresp_acc0), + .O(\s_bresp_acc[0]_i_1_n_0 )); + LUT4 #( + .INIT(16'h00EA)) + \s_bresp_acc[1]_i_1 + (.I0(\s_bresp_acc_reg_n_0_[1] ), + .I1(m_axi_bresp[1]), + .I2(mhandshake), + .I3(s_bresp_acc0), + .O(\s_bresp_acc[1]_i_1_n_0 )); + FDRE \s_bresp_acc_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\s_bresp_acc[0]_i_1_n_0 ), + .Q(\s_bresp_acc_reg_n_0_[0] ), + .R(1'b0)); + FDRE \s_bresp_acc_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\s_bresp_acc[1]_i_1_n_0 ), + .Q(\s_bresp_acc_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + shandshake_r_reg + (.C(aclk), + .CE(1'b1), + .D(shandshake), + .Q(shandshake_r), + .R(areset_d1)); +endmodule + +module NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_cmd_translator + (next_pending_r, + next_pending_r_0, + sel_first_reg_0, + sel_first_reg_1, + sel_first, + \axlen_cnt_reg[5] , + \axlen_cnt_reg[2] , + axaddr_wrap0, + \axaddr_wrap_reg[11] , + \axaddr_incr_reg[11] , + s_axburst_eq1_reg_0, + \axlen_cnt_reg[0] , + \axaddr_offset_r_reg[3] , + \wrap_second_len_r_reg[3] , + \wrap_boundary_axaddr_r_reg[11] , + \m_payload_i_reg[3] , + aclk, + sel_first_i, + s_axburst_eq0_reg_0, + s_axburst_eq1_reg_1, + sel_first_reg_2, + sel_first_reg_3, + \axlen_cnt_reg[3] , + Q, + si_rs_awvalid, + \axlen_cnt_reg[3]_0 , + \axaddr_wrap_reg[3] , + S, + next, + \axaddr_wrap_reg[0] , + next_pending_r_reg, + axaddr_incr, + \axlen_cnt_reg[5]_0 , + D, + \wrap_second_len_r_reg[3]_0 , + \wrap_cnt_r_reg[3] , + E, + \wrap_boundary_axaddr_r_reg[6] , + \axaddr_wrap_reg[11]_0 ); + output next_pending_r; + output next_pending_r_0; + output sel_first_reg_0; + output sel_first_reg_1; + output sel_first; + output \axlen_cnt_reg[5] ; + output \axlen_cnt_reg[2] ; + output [11:0]axaddr_wrap0; + output [11:0]\axaddr_wrap_reg[11] ; + output [11:0]\axaddr_incr_reg[11] ; + output s_axburst_eq1_reg_0; + output \axlen_cnt_reg[0] ; + output [3:0]\axaddr_offset_r_reg[3] ; + output [3:0]\wrap_second_len_r_reg[3] ; + output [11:0]\wrap_boundary_axaddr_r_reg[11] ; + output [3:0]\m_payload_i_reg[3] ; + input aclk; + input sel_first_i; + input s_axburst_eq0_reg_0; + input s_axburst_eq1_reg_1; + input sel_first_reg_2; + input sel_first_reg_3; + input [15:0]\axlen_cnt_reg[3] ; + input [1:0]Q; + input si_rs_awvalid; + input \axlen_cnt_reg[3]_0 ; + input [3:0]\axaddr_wrap_reg[3] ; + input [3:0]S; + input next; + input \axaddr_wrap_reg[0] ; + input next_pending_r_reg; + input [11:0]axaddr_incr; + input \axlen_cnt_reg[5]_0 ; + input [3:0]D; + input [3:0]\wrap_second_len_r_reg[3]_0 ; + input [3:0]\wrap_cnt_r_reg[3] ; + input [0:0]E; + input [6:0]\wrap_boundary_axaddr_r_reg[6] ; + input [11:0]\axaddr_wrap_reg[11]_0 ; + + wire [3:0]D; + wire [0:0]E; + wire [1:0]Q; + wire [3:0]S; + wire aclk; + wire [11:0]axaddr_incr; + wire [11:0]\axaddr_incr_reg[11] ; + wire [3:0]\axaddr_offset_r_reg[3] ; + wire [11:0]axaddr_wrap0; + wire \axaddr_wrap_reg[0] ; + wire [11:0]\axaddr_wrap_reg[11] ; + wire [11:0]\axaddr_wrap_reg[11]_0 ; + wire [3:0]\axaddr_wrap_reg[3] ; + wire \axlen_cnt_reg[0] ; + wire \axlen_cnt_reg[2] ; + wire [15:0]\axlen_cnt_reg[3] ; + wire \axlen_cnt_reg[3]_0 ; + wire \axlen_cnt_reg[5] ; + wire \axlen_cnt_reg[5]_0 ; + wire [3:0]\m_payload_i_reg[3] ; + wire next; + wire next_pending_r; + wire next_pending_r_0; + wire next_pending_r_reg; + wire s_axburst_eq0; + wire s_axburst_eq0_reg_0; + wire s_axburst_eq1; + wire s_axburst_eq1_reg_0; + wire s_axburst_eq1_reg_1; + wire sel_first; + wire sel_first_i; + wire sel_first_reg_0; + wire sel_first_reg_1; + wire sel_first_reg_2; + wire sel_first_reg_3; + wire si_rs_awvalid; + wire [11:0]\wrap_boundary_axaddr_r_reg[11] ; + wire [6:0]\wrap_boundary_axaddr_r_reg[6] ; + wire [3:0]\wrap_cnt_r_reg[3] ; + wire [3:0]\wrap_second_len_r_reg[3] ; + wire [3:0]\wrap_second_len_r_reg[3]_0 ; + + LUT3 #( + .INIT(8'hB8)) + \FSM_sequential_state[1]_i_2 + (.I0(s_axburst_eq1), + .I1(\axlen_cnt_reg[3] [11]), + .I2(s_axburst_eq0), + .O(s_axburst_eq1_reg_0)); + NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_incr_cmd incr_cmd_0 + (.Q(Q), + .S(S), + .aclk(aclk), + .axaddr_incr(axaddr_incr), + .\axaddr_incr_reg[11]_0 (\axaddr_incr_reg[11] ), + .\axlen_cnt_reg[3]_0 ({\axlen_cnt_reg[3] [15:12],\axlen_cnt_reg[3] [10:9],\axlen_cnt_reg[3] [3:0]}), + .\axlen_cnt_reg[3]_1 (\axlen_cnt_reg[3]_0 ), + .\axlen_cnt_reg[4]_0 (\axaddr_wrap_reg[0] ), + .\axlen_cnt_reg[5]_0 (\axlen_cnt_reg[5] ), + .\axlen_cnt_reg[5]_1 (\axlen_cnt_reg[5]_0 ), + .\m_payload_i_reg[3] (\m_payload_i_reg[3] ), + .next(next), + .next_pending_r(next_pending_r), + .next_pending_r_reg_0(next_pending_r_reg), + .sel_first_reg_0(sel_first_reg_1), + .sel_first_reg_1(sel_first_reg_2), + .si_rs_awvalid(si_rs_awvalid)); + FDRE s_axburst_eq0_reg + (.C(aclk), + .CE(1'b1), + .D(s_axburst_eq0_reg_0), + .Q(s_axburst_eq0), + .R(1'b0)); + FDRE s_axburst_eq1_reg + (.C(aclk), + .CE(1'b1), + .D(s_axburst_eq1_reg_1), + .Q(s_axburst_eq1), + .R(1'b0)); + FDRE sel_first_reg + (.C(aclk), + .CE(1'b1), + .D(sel_first_i), + .Q(sel_first_reg_0), + .R(1'b0)); + NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_wrap_cmd wrap_cmd_0 + (.D(D), + .E(E), + .Q(Q), + .aclk(aclk), + .\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3] ), + .axaddr_wrap0(axaddr_wrap0), + .\axaddr_wrap_reg[0]_0 (\axaddr_wrap_reg[0] ), + .\axaddr_wrap_reg[11]_0 (\axaddr_wrap_reg[11] ), + .\axaddr_wrap_reg[11]_1 (\axaddr_wrap_reg[11]_0 ), + .\axaddr_wrap_reg[3]_0 (\axaddr_wrap_reg[3] ), + .\axlen_cnt_reg[0]_0 (\axlen_cnt_reg[0] ), + .\axlen_cnt_reg[2]_0 (\axlen_cnt_reg[2] ), + .\axlen_cnt_reg[3]_0 ({\axlen_cnt_reg[3] [15:12],\axlen_cnt_reg[3] [8:4]}), + .\axlen_cnt_reg[3]_1 (\axlen_cnt_reg[3]_0 ), + .next(next), + .next_pending_r_0(next_pending_r_0), + .next_pending_r_reg_0(next_pending_r_reg), + .sel_first(sel_first), + .sel_first_reg_0(sel_first_reg_3), + .si_rs_awvalid(si_rs_awvalid), + .\wrap_boundary_axaddr_r_reg[11]_0 (\wrap_boundary_axaddr_r_reg[11] ), + .\wrap_boundary_axaddr_r_reg[6]_0 (\wrap_boundary_axaddr_r_reg[6] ), + .\wrap_cnt_r_reg[3]_0 (\wrap_cnt_r_reg[3] ), + .\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3] ), + .\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3]_0 )); +endmodule + +(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_29_b2s_cmd_translator" *) +module NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_cmd_translator_1 + (sel_first_reg_0, + sel_first_reg_1, + sel_first_reg_2, + \axlen_cnt_reg[7] , + \axaddr_wrap_reg[3] , + \axaddr_wrap_reg[11] , + \axaddr_wrap_reg[7] , + O, + \axaddr_incr_reg[11] , + m_axi_arready_0, + r_rlast, + \axlen_cnt_reg[0] , + \axaddr_offset_r_reg[3] , + \wrap_second_len_r_reg[3] , + \wrap_boundary_axaddr_r_reg[11] , + \m_payload_i_reg[3] , + aclk, + sel_first_i, + sel_first_reg_3, + sel_first_reg_4, + \axlen_cnt_reg[1] , + \axlen_cnt_reg[2] , + Q, + si_rs_arvalid, + S, + \axaddr_incr_reg[3] , + r_push, + \axaddr_wrap_reg[0] , + next_pending_r_reg, + \axlen_cnt_reg[3] , + m_axi_arready, + \axaddr_incr_reg[11]_0 , + \axaddr_incr_reg[7] , + \axaddr_incr_reg[3]_0 , + \axlen_cnt_reg[7]_0 , + D, + \wrap_second_len_r_reg[3]_0 , + \wrap_cnt_r_reg[3] , + E, + \wrap_boundary_axaddr_r_reg[6] , + \axaddr_wrap_reg[11]_0 , + \axaddr_incr_reg[0] ); + output sel_first_reg_0; + output sel_first_reg_1; + output sel_first_reg_2; + output \axlen_cnt_reg[7] ; + output [3:0]\axaddr_wrap_reg[3] ; + output [11:0]\axaddr_wrap_reg[11] ; + output [3:0]\axaddr_wrap_reg[7] ; + output [3:0]O; + output [11:0]\axaddr_incr_reg[11] ; + output m_axi_arready_0; + output r_rlast; + output \axlen_cnt_reg[0] ; + output [3:0]\axaddr_offset_r_reg[3] ; + output [3:0]\wrap_second_len_r_reg[3] ; + output [11:0]\wrap_boundary_axaddr_r_reg[11] ; + output [3:0]\m_payload_i_reg[3] ; + input aclk; + input sel_first_i; + input sel_first_reg_3; + input sel_first_reg_4; + input \axlen_cnt_reg[1] ; + input [14:0]\axlen_cnt_reg[2] ; + input [1:0]Q; + input si_rs_arvalid; + input [3:0]S; + input [3:0]\axaddr_incr_reg[3] ; + input r_push; + input \axaddr_wrap_reg[0] ; + input next_pending_r_reg; + input \axlen_cnt_reg[3] ; + input m_axi_arready; + input [3:0]\axaddr_incr_reg[11]_0 ; + input [3:0]\axaddr_incr_reg[7] ; + input [3:0]\axaddr_incr_reg[3]_0 ; + input \axlen_cnt_reg[7]_0 ; + input [3:0]D; + input [3:0]\wrap_second_len_r_reg[3]_0 ; + input [3:0]\wrap_cnt_r_reg[3] ; + input [0:0]E; + input [6:0]\wrap_boundary_axaddr_r_reg[6] ; + input [11:0]\axaddr_wrap_reg[11]_0 ; + input [0:0]\axaddr_incr_reg[0] ; + + wire [3:0]D; + wire [0:0]E; + wire [3:0]O; + wire [1:0]Q; + wire [3:0]S; + wire aclk; + wire [0:0]\axaddr_incr_reg[0] ; + wire [11:0]\axaddr_incr_reg[11] ; + wire [3:0]\axaddr_incr_reg[11]_0 ; + wire [3:0]\axaddr_incr_reg[3] ; + wire [3:0]\axaddr_incr_reg[3]_0 ; + wire [3:0]\axaddr_incr_reg[7] ; + wire [3:0]\axaddr_offset_r_reg[3] ; + wire \axaddr_wrap_reg[0] ; + wire [11:0]\axaddr_wrap_reg[11] ; + wire [11:0]\axaddr_wrap_reg[11]_0 ; + wire [3:0]\axaddr_wrap_reg[3] ; + wire [3:0]\axaddr_wrap_reg[7] ; + wire \axlen_cnt_reg[0] ; + wire \axlen_cnt_reg[1] ; + wire [14:0]\axlen_cnt_reg[2] ; + wire \axlen_cnt_reg[3] ; + wire \axlen_cnt_reg[7] ; + wire \axlen_cnt_reg[7]_0 ; + wire incr_next_pending; + wire m_axi_arready; + wire m_axi_arready_0; + wire [3:0]\m_payload_i_reg[3] ; + wire next_pending_r_reg; + wire r_push; + wire r_rlast; + wire s_axburst_eq0; + wire s_axburst_eq1; + wire sel_first_i; + wire sel_first_reg_0; + wire sel_first_reg_1; + wire sel_first_reg_2; + wire sel_first_reg_3; + wire sel_first_reg_4; + wire si_rs_arvalid; + wire [11:0]\wrap_boundary_axaddr_r_reg[11] ; + wire [6:0]\wrap_boundary_axaddr_r_reg[6] ; + wire wrap_cmd_0_n_25; + wire wrap_cmd_0_n_26; + wire [3:0]\wrap_cnt_r_reg[3] ; + wire [3:0]\wrap_second_len_r_reg[3] ; + wire [3:0]\wrap_second_len_r_reg[3]_0 ; + + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT5 #( + .INIT(32'h00088808)) + \FSM_sequential_state[1]_i_3 + (.I0(m_axi_arready), + .I1(Q[0]), + .I2(s_axburst_eq0), + .I3(\axlen_cnt_reg[2] [11]), + .I4(s_axburst_eq1), + .O(m_axi_arready_0)); + NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_incr_cmd_2 incr_cmd_0 + (.Q(Q), + .aclk(aclk), + .\axaddr_incr_reg[0]_0 (\axaddr_incr_reg[0] ), + .\axaddr_incr_reg[11]_0 (\axaddr_incr_reg[11] ), + .\axaddr_incr_reg[11]_1 (\axaddr_incr_reg[11]_0 ), + .\axaddr_incr_reg[3]_0 (\axaddr_incr_reg[3] ), + .\axaddr_incr_reg[3]_1 (\axaddr_incr_reg[3]_0 ), + .\axaddr_incr_reg[7]_0 (\axaddr_incr_reg[7] ), + .\axlen_cnt_reg[2]_0 (\axlen_cnt_reg[1] ), + .\axlen_cnt_reg[2]_1 ({\axlen_cnt_reg[2] [14:12],\axlen_cnt_reg[2] [10:9],\axlen_cnt_reg[2] [3:0]}), + .\axlen_cnt_reg[3]_0 (\axlen_cnt_reg[3] ), + .\axlen_cnt_reg[4]_0 (\axaddr_wrap_reg[0] ), + .\axlen_cnt_reg[7]_0 (\axlen_cnt_reg[7] ), + .\axlen_cnt_reg[7]_1 (\axlen_cnt_reg[7]_0 ), + .incr_next_pending(incr_next_pending), + .m_axi_arready(m_axi_arready), + .\m_payload_i_reg[3] (\m_payload_i_reg[3] ), + .next_pending_r_reg_0(next_pending_r_reg), + .r_push(r_push), + .sel_first_reg_0(sel_first_reg_1), + .sel_first_reg_1(sel_first_reg_3), + .si_rs_arvalid(si_rs_arvalid)); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT3 #( + .INIT(8'h1D)) + r_rlast_r_i_1 + (.I0(s_axburst_eq0), + .I1(\axlen_cnt_reg[2] [11]), + .I2(s_axburst_eq1), + .O(r_rlast)); + FDRE s_axburst_eq0_reg + (.C(aclk), + .CE(1'b1), + .D(wrap_cmd_0_n_25), + .Q(s_axburst_eq0), + .R(1'b0)); + FDRE s_axburst_eq1_reg + (.C(aclk), + .CE(1'b1), + .D(wrap_cmd_0_n_26), + .Q(s_axburst_eq1), + .R(1'b0)); + FDRE sel_first_reg + (.C(aclk), + .CE(1'b1), + .D(sel_first_i), + .Q(sel_first_reg_0), + .R(1'b0)); + NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_wrap_cmd_3 wrap_cmd_0 + (.D(D), + .E(E), + .O(O), + .Q(Q[1]), + .S(S), + .aclk(aclk), + .\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3] ), + .\axaddr_wrap_reg[0]_0 (\axaddr_wrap_reg[0] ), + .\axaddr_wrap_reg[11]_0 (\axaddr_wrap_reg[11] ), + .\axaddr_wrap_reg[11]_1 (\axaddr_wrap_reg[11]_0 ), + .\axaddr_wrap_reg[3]_0 (\axaddr_wrap_reg[3] ), + .\axaddr_wrap_reg[7]_0 (\axaddr_wrap_reg[7] ), + .\axlen_cnt_reg[0]_0 (\axlen_cnt_reg[0] ), + .\axlen_cnt_reg[1]_0 (\axlen_cnt_reg[1] ), + .\axlen_cnt_reg[2]_0 ({\axlen_cnt_reg[2] [14:11],\axlen_cnt_reg[2] [8:4]}), + .\axlen_cnt_reg[3]_0 (\axlen_cnt_reg[3] ), + .incr_next_pending(incr_next_pending), + .\m_payload_i_reg[39] (wrap_cmd_0_n_25), + .\m_payload_i_reg[39]_0 (wrap_cmd_0_n_26), + .next_pending_r_reg_0(next_pending_r_reg), + .sel_first_i(sel_first_i), + .sel_first_reg_0(sel_first_reg_2), + .sel_first_reg_1(sel_first_reg_4), + .si_rs_arvalid(si_rs_arvalid), + .\wrap_boundary_axaddr_r_reg[11]_0 (\wrap_boundary_axaddr_r_reg[11] ), + .\wrap_boundary_axaddr_r_reg[6]_0 (\wrap_boundary_axaddr_r_reg[6] ), + .\wrap_cnt_r_reg[3]_0 (\wrap_cnt_r_reg[3] ), + .\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3] ), + .\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3]_0 )); +endmodule + +module NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_incr_cmd + (next_pending_r, + sel_first_reg_0, + \axlen_cnt_reg[5]_0 , + \axaddr_incr_reg[11]_0 , + \m_payload_i_reg[3] , + aclk, + sel_first_reg_1, + \axlen_cnt_reg[3]_0 , + Q, + si_rs_awvalid, + \axlen_cnt_reg[3]_1 , + S, + next, + \axlen_cnt_reg[4]_0 , + next_pending_r_reg_0, + axaddr_incr, + \axlen_cnt_reg[5]_1 ); + output next_pending_r; + output sel_first_reg_0; + output \axlen_cnt_reg[5]_0 ; + output [11:0]\axaddr_incr_reg[11]_0 ; + output [3:0]\m_payload_i_reg[3] ; + input aclk; + input sel_first_reg_1; + input [9:0]\axlen_cnt_reg[3]_0 ; + input [1:0]Q; + input si_rs_awvalid; + input \axlen_cnt_reg[3]_1 ; + input [3:0]S; + input next; + input \axlen_cnt_reg[4]_0 ; + input next_pending_r_reg_0; + input [11:0]axaddr_incr; + input \axlen_cnt_reg[5]_1 ; + + wire [1:0]Q; + wire [3:0]S; + wire aclk; + wire [11:0]axaddr_incr; + wire \axaddr_incr[11]_i_1_n_0 ; + wire [11:0]\axaddr_incr_reg[11]_0 ; + wire \axaddr_incr_reg[11]_i_4_n_1 ; + wire \axaddr_incr_reg[11]_i_4_n_2 ; + wire \axaddr_incr_reg[11]_i_4_n_3 ; + wire \axaddr_incr_reg[11]_i_4_n_4 ; + wire \axaddr_incr_reg[11]_i_4_n_5 ; + wire \axaddr_incr_reg[11]_i_4_n_6 ; + wire \axaddr_incr_reg[11]_i_4_n_7 ; + wire \axaddr_incr_reg[3]_i_3_n_0 ; + wire \axaddr_incr_reg[3]_i_3_n_1 ; + wire \axaddr_incr_reg[3]_i_3_n_2 ; + wire \axaddr_incr_reg[3]_i_3_n_3 ; + wire \axaddr_incr_reg[3]_i_3_n_4 ; + wire \axaddr_incr_reg[3]_i_3_n_5 ; + wire \axaddr_incr_reg[3]_i_3_n_6 ; + wire \axaddr_incr_reg[3]_i_3_n_7 ; + wire \axaddr_incr_reg[7]_i_3_n_0 ; + wire \axaddr_incr_reg[7]_i_3_n_1 ; + wire \axaddr_incr_reg[7]_i_3_n_2 ; + wire \axaddr_incr_reg[7]_i_3_n_3 ; + wire \axaddr_incr_reg[7]_i_3_n_4 ; + wire \axaddr_incr_reg[7]_i_3_n_5 ; + wire \axaddr_incr_reg[7]_i_3_n_6 ; + wire \axaddr_incr_reg[7]_i_3_n_7 ; + wire [7:0]axlen_cnt; + wire \axlen_cnt[0]_i_1_n_0 ; + wire \axlen_cnt[1]_i_1_n_0 ; + wire \axlen_cnt[2]_i_1_n_0 ; + wire \axlen_cnt[3]_i_2_n_0 ; + wire \axlen_cnt[3]_i_4_n_0 ; + wire \axlen_cnt[4]_i_1__2_n_0 ; + wire \axlen_cnt[5]_i_2_n_0 ; + wire \axlen_cnt[6]_i_1__0_n_0 ; + wire \axlen_cnt[7]_i_1__0_n_0 ; + wire \axlen_cnt[7]_i_2_n_0 ; + wire [9:0]\axlen_cnt_reg[3]_0 ; + wire \axlen_cnt_reg[3]_1 ; + wire \axlen_cnt_reg[4]_0 ; + wire \axlen_cnt_reg[5]_0 ; + wire \axlen_cnt_reg[5]_1 ; + wire incr_next_pending; + wire [3:0]\m_payload_i_reg[3] ; + wire next; + wire next_pending_r; + wire next_pending_r_i_5_n_0; + wire next_pending_r_reg_0; + wire [11:0]p_1_in; + wire sel_first_reg_0; + wire sel_first_reg_1; + wire si_rs_awvalid; + wire [3:3]\NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED ; + + (* SOFT_HLUTNM = "soft_lutpair119" *) + LUT3 #( + .INIT(8'hB8)) + \axaddr_incr[0]_i_1 + (.I0(axaddr_incr[0]), + .I1(sel_first_reg_0), + .I2(\axaddr_incr_reg[3]_i_3_n_7 ), + .O(p_1_in[0])); + (* SOFT_HLUTNM = "soft_lutpair115" *) + LUT3 #( + .INIT(8'hB8)) + \axaddr_incr[10]_i_1 + (.I0(axaddr_incr[10]), + .I1(sel_first_reg_0), + .I2(\axaddr_incr_reg[11]_i_4_n_5 ), + .O(p_1_in[10])); + LUT2 #( + .INIT(4'hE)) + \axaddr_incr[11]_i_1 + (.I0(sel_first_reg_0), + .I1(next), + .O(\axaddr_incr[11]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair114" *) + LUT3 #( + .INIT(8'hB8)) + \axaddr_incr[11]_i_2 + (.I0(axaddr_incr[11]), + .I1(sel_first_reg_0), + .I2(\axaddr_incr_reg[11]_i_4_n_4 ), + .O(p_1_in[11])); + (* SOFT_HLUTNM = "soft_lutpair119" *) + LUT3 #( + .INIT(8'hB8)) + \axaddr_incr[1]_i_1 + (.I0(axaddr_incr[1]), + .I1(sel_first_reg_0), + .I2(\axaddr_incr_reg[3]_i_3_n_6 ), + .O(p_1_in[1])); + (* SOFT_HLUTNM = "soft_lutpair118" *) + LUT3 #( + .INIT(8'hB8)) + \axaddr_incr[2]_i_1 + (.I0(axaddr_incr[2]), + .I1(sel_first_reg_0), + .I2(\axaddr_incr_reg[3]_i_3_n_5 ), + .O(p_1_in[2])); + (* SOFT_HLUTNM = "soft_lutpair118" *) + LUT3 #( + .INIT(8'hB8)) + \axaddr_incr[3]_i_1 + (.I0(axaddr_incr[3]), + .I1(sel_first_reg_0), + .I2(\axaddr_incr_reg[3]_i_3_n_4 ), + .O(p_1_in[3])); + LUT4 #( + .INIT(16'h0102)) + \axaddr_incr[3]_i_10 + (.I0(\axlen_cnt_reg[3]_0 [0]), + .I1(\axlen_cnt_reg[3]_0 [5]), + .I2(\axlen_cnt_reg[3]_0 [4]), + .I3(next), + .O(\m_payload_i_reg[3] [0])); + LUT4 #( + .INIT(16'h6AAA)) + \axaddr_incr[3]_i_7 + (.I0(\axlen_cnt_reg[3]_0 [3]), + .I1(\axlen_cnt_reg[3]_0 [5]), + .I2(\axlen_cnt_reg[3]_0 [4]), + .I3(next), + .O(\m_payload_i_reg[3] [3])); + LUT4 #( + .INIT(16'h1A2A)) + \axaddr_incr[3]_i_8 + (.I0(\axlen_cnt_reg[3]_0 [2]), + .I1(\axlen_cnt_reg[3]_0 [4]), + .I2(\axlen_cnt_reg[3]_0 [5]), + .I3(next), + .O(\m_payload_i_reg[3] [2])); + LUT4 #( + .INIT(16'h1222)) + \axaddr_incr[3]_i_9 + (.I0(\axlen_cnt_reg[3]_0 [1]), + .I1(\axlen_cnt_reg[3]_0 [5]), + .I2(\axlen_cnt_reg[3]_0 [4]), + .I3(next), + .O(\m_payload_i_reg[3] [1])); + (* SOFT_HLUTNM = "soft_lutpair117" *) + LUT3 #( + .INIT(8'hB8)) + \axaddr_incr[4]_i_1 + (.I0(axaddr_incr[4]), + .I1(sel_first_reg_0), + .I2(\axaddr_incr_reg[7]_i_3_n_7 ), + .O(p_1_in[4])); + (* SOFT_HLUTNM = "soft_lutpair115" *) + LUT3 #( + .INIT(8'hB8)) + \axaddr_incr[5]_i_1 + (.I0(axaddr_incr[5]), + .I1(sel_first_reg_0), + .I2(\axaddr_incr_reg[7]_i_3_n_6 ), + .O(p_1_in[5])); + (* SOFT_HLUTNM = "soft_lutpair117" *) + LUT3 #( + .INIT(8'hB8)) + \axaddr_incr[6]_i_1 + (.I0(axaddr_incr[6]), + .I1(sel_first_reg_0), + .I2(\axaddr_incr_reg[7]_i_3_n_5 ), + .O(p_1_in[6])); + (* SOFT_HLUTNM = "soft_lutpair116" *) + LUT3 #( + .INIT(8'hB8)) + \axaddr_incr[7]_i_1 + (.I0(axaddr_incr[7]), + .I1(sel_first_reg_0), + .I2(\axaddr_incr_reg[7]_i_3_n_4 ), + .O(p_1_in[7])); + (* SOFT_HLUTNM = "soft_lutpair116" *) + LUT3 #( + .INIT(8'hB8)) + \axaddr_incr[8]_i_1 + (.I0(axaddr_incr[8]), + .I1(sel_first_reg_0), + .I2(\axaddr_incr_reg[11]_i_4_n_7 ), + .O(p_1_in[8])); + (* SOFT_HLUTNM = "soft_lutpair114" *) + LUT3 #( + .INIT(8'hB8)) + \axaddr_incr[9]_i_1 + (.I0(axaddr_incr[9]), + .I1(sel_first_reg_0), + .I2(\axaddr_incr_reg[11]_i_4_n_6 ), + .O(p_1_in[9])); + FDRE \axaddr_incr_reg[0] + (.C(aclk), + .CE(\axaddr_incr[11]_i_1_n_0 ), + .D(p_1_in[0]), + .Q(\axaddr_incr_reg[11]_0 [0]), + .R(1'b0)); + FDRE \axaddr_incr_reg[10] + (.C(aclk), + .CE(\axaddr_incr[11]_i_1_n_0 ), + .D(p_1_in[10]), + .Q(\axaddr_incr_reg[11]_0 [10]), + .R(1'b0)); + FDRE \axaddr_incr_reg[11] + (.C(aclk), + .CE(\axaddr_incr[11]_i_1_n_0 ), + .D(p_1_in[11]), + .Q(\axaddr_incr_reg[11]_0 [11]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \axaddr_incr_reg[11]_i_4 + (.CI(\axaddr_incr_reg[7]_i_3_n_0 ), + .CO({\NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_4_n_1 ,\axaddr_incr_reg[11]_i_4_n_2 ,\axaddr_incr_reg[11]_i_4_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\axaddr_incr_reg[11]_i_4_n_4 ,\axaddr_incr_reg[11]_i_4_n_5 ,\axaddr_incr_reg[11]_i_4_n_6 ,\axaddr_incr_reg[11]_i_4_n_7 }), + .S(\axaddr_incr_reg[11]_0 [11:8])); + FDRE \axaddr_incr_reg[1] + (.C(aclk), + .CE(\axaddr_incr[11]_i_1_n_0 ), + .D(p_1_in[1]), + .Q(\axaddr_incr_reg[11]_0 [1]), + .R(1'b0)); + FDRE \axaddr_incr_reg[2] + (.C(aclk), + .CE(\axaddr_incr[11]_i_1_n_0 ), + .D(p_1_in[2]), + .Q(\axaddr_incr_reg[11]_0 [2]), + .R(1'b0)); + FDRE \axaddr_incr_reg[3] + (.C(aclk), + .CE(\axaddr_incr[11]_i_1_n_0 ), + .D(p_1_in[3]), + .Q(\axaddr_incr_reg[11]_0 [3]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \axaddr_incr_reg[3]_i_3 + (.CI(1'b0), + .CO({\axaddr_incr_reg[3]_i_3_n_0 ,\axaddr_incr_reg[3]_i_3_n_1 ,\axaddr_incr_reg[3]_i_3_n_2 ,\axaddr_incr_reg[3]_i_3_n_3 }), + .CYINIT(1'b0), + .DI(\axaddr_incr_reg[11]_0 [3:0]), + .O({\axaddr_incr_reg[3]_i_3_n_4 ,\axaddr_incr_reg[3]_i_3_n_5 ,\axaddr_incr_reg[3]_i_3_n_6 ,\axaddr_incr_reg[3]_i_3_n_7 }), + .S(S)); + FDRE \axaddr_incr_reg[4] + (.C(aclk), + .CE(\axaddr_incr[11]_i_1_n_0 ), + .D(p_1_in[4]), + .Q(\axaddr_incr_reg[11]_0 [4]), + .R(1'b0)); + FDRE \axaddr_incr_reg[5] + (.C(aclk), + .CE(\axaddr_incr[11]_i_1_n_0 ), + .D(p_1_in[5]), + .Q(\axaddr_incr_reg[11]_0 [5]), + .R(1'b0)); + FDRE \axaddr_incr_reg[6] + (.C(aclk), + .CE(\axaddr_incr[11]_i_1_n_0 ), + .D(p_1_in[6]), + .Q(\axaddr_incr_reg[11]_0 [6]), + .R(1'b0)); + FDRE \axaddr_incr_reg[7] + (.C(aclk), + .CE(\axaddr_incr[11]_i_1_n_0 ), + .D(p_1_in[7]), + .Q(\axaddr_incr_reg[11]_0 [7]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \axaddr_incr_reg[7]_i_3 + (.CI(\axaddr_incr_reg[3]_i_3_n_0 ), + .CO({\axaddr_incr_reg[7]_i_3_n_0 ,\axaddr_incr_reg[7]_i_3_n_1 ,\axaddr_incr_reg[7]_i_3_n_2 ,\axaddr_incr_reg[7]_i_3_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\axaddr_incr_reg[7]_i_3_n_4 ,\axaddr_incr_reg[7]_i_3_n_5 ,\axaddr_incr_reg[7]_i_3_n_6 ,\axaddr_incr_reg[7]_i_3_n_7 }), + .S(\axaddr_incr_reg[11]_0 [7:4])); + FDRE \axaddr_incr_reg[8] + (.C(aclk), + .CE(\axaddr_incr[11]_i_1_n_0 ), + .D(p_1_in[8]), + .Q(\axaddr_incr_reg[11]_0 [8]), + .R(1'b0)); + FDRE \axaddr_incr_reg[9] + (.C(aclk), + .CE(\axaddr_incr[11]_i_1_n_0 ), + .D(p_1_in[9]), + .Q(\axaddr_incr_reg[11]_0 [9]), + .R(1'b0)); + LUT6 #( + .INIT(64'h4444F44444444444)) + \axlen_cnt[0]_i_1 + (.I0(axlen_cnt[0]), + .I1(\axlen_cnt_reg[5]_0 ), + .I2(\axlen_cnt_reg[3]_0 [6]), + .I3(Q[0]), + .I4(Q[1]), + .I5(si_rs_awvalid), + .O(\axlen_cnt[0]_i_1_n_0 )); + LUT5 #( + .INIT(32'hF44F4444)) + \axlen_cnt[1]_i_1 + (.I0(\axlen_cnt_reg[3]_1 ), + .I1(\axlen_cnt_reg[3]_0 [7]), + .I2(axlen_cnt[1]), + .I3(axlen_cnt[0]), + .I4(\axlen_cnt_reg[5]_0 ), + .O(\axlen_cnt[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'hF4F4F44F44444444)) + \axlen_cnt[2]_i_1 + (.I0(\axlen_cnt_reg[3]_1 ), + .I1(\axlen_cnt_reg[3]_0 [8]), + .I2(axlen_cnt[2]), + .I3(axlen_cnt[0]), + .I4(axlen_cnt[1]), + .I5(\axlen_cnt_reg[5]_0 ), + .O(\axlen_cnt[2]_i_1_n_0 )); + LUT5 #( + .INIT(32'h4FF44444)) + \axlen_cnt[3]_i_2 + (.I0(\axlen_cnt_reg[3]_1 ), + .I1(\axlen_cnt_reg[3]_0 [9]), + .I2(axlen_cnt[3]), + .I3(\axlen_cnt[3]_i_4_n_0 ), + .I4(\axlen_cnt_reg[5]_0 ), + .O(\axlen_cnt[3]_i_2_n_0 )); + LUT3 #( + .INIT(8'h01)) + \axlen_cnt[3]_i_4 + (.I0(axlen_cnt[0]), + .I1(axlen_cnt[1]), + .I2(axlen_cnt[2]), + .O(\axlen_cnt[3]_i_4_n_0 )); + LUT6 #( + .INIT(64'h8888888888888882)) + \axlen_cnt[4]_i_1__2 + (.I0(\axlen_cnt_reg[5]_0 ), + .I1(axlen_cnt[4]), + .I2(axlen_cnt[3]), + .I3(axlen_cnt[0]), + .I4(axlen_cnt[1]), + .I5(axlen_cnt[2]), + .O(\axlen_cnt[4]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAAAAAAAAAA9)) + \axlen_cnt[5]_i_2 + (.I0(axlen_cnt[5]), + .I1(axlen_cnt[0]), + .I2(axlen_cnt[1]), + .I3(axlen_cnt[2]), + .I4(axlen_cnt[4]), + .I5(axlen_cnt[3]), + .O(\axlen_cnt[5]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair112" *) + LUT4 #( + .INIT(16'h8882)) + \axlen_cnt[6]_i_1__0 + (.I0(\axlen_cnt_reg[5]_0 ), + .I1(axlen_cnt[6]), + .I2(\axlen_cnt[7]_i_2_n_0 ), + .I3(axlen_cnt[5]), + .O(\axlen_cnt[6]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair112" *) + LUT5 #( + .INIT(32'h88888882)) + \axlen_cnt[7]_i_1__0 + (.I0(\axlen_cnt_reg[5]_0 ), + .I1(axlen_cnt[7]), + .I2(\axlen_cnt[7]_i_2_n_0 ), + .I3(axlen_cnt[6]), + .I4(axlen_cnt[5]), + .O(\axlen_cnt[7]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair113" *) + LUT5 #( + .INIT(32'hFFFFFFFE)) + \axlen_cnt[7]_i_2 + (.I0(axlen_cnt[3]), + .I1(axlen_cnt[4]), + .I2(axlen_cnt[2]), + .I3(axlen_cnt[1]), + .I4(axlen_cnt[0]), + .O(\axlen_cnt[7]_i_2_n_0 )); + FDRE \axlen_cnt_reg[0] + (.C(aclk), + .CE(\axlen_cnt_reg[4]_0 ), + .D(\axlen_cnt[0]_i_1_n_0 ), + .Q(axlen_cnt[0]), + .R(1'b0)); + FDRE \axlen_cnt_reg[1] + (.C(aclk), + .CE(\axlen_cnt_reg[4]_0 ), + .D(\axlen_cnt[1]_i_1_n_0 ), + .Q(axlen_cnt[1]), + .R(1'b0)); + FDRE \axlen_cnt_reg[2] + (.C(aclk), + .CE(\axlen_cnt_reg[4]_0 ), + .D(\axlen_cnt[2]_i_1_n_0 ), + .Q(axlen_cnt[2]), + .R(1'b0)); + FDRE \axlen_cnt_reg[3] + (.C(aclk), + .CE(\axlen_cnt_reg[4]_0 ), + .D(\axlen_cnt[3]_i_2_n_0 ), + .Q(axlen_cnt[3]), + .R(1'b0)); + FDRE \axlen_cnt_reg[4] + (.C(aclk), + .CE(\axlen_cnt_reg[4]_0 ), + .D(\axlen_cnt[4]_i_1__2_n_0 ), + .Q(axlen_cnt[4]), + .R(1'b0)); + FDRE \axlen_cnt_reg[5] + (.C(aclk), + .CE(\axlen_cnt_reg[4]_0 ), + .D(\axlen_cnt[5]_i_2_n_0 ), + .Q(axlen_cnt[5]), + .R(\axlen_cnt_reg[5]_1 )); + FDRE \axlen_cnt_reg[6] + (.C(aclk), + .CE(\axlen_cnt_reg[4]_0 ), + .D(\axlen_cnt[6]_i_1__0_n_0 ), + .Q(axlen_cnt[6]), + .R(1'b0)); + FDRE \axlen_cnt_reg[7] + (.C(aclk), + .CE(\axlen_cnt_reg[4]_0 ), + .D(\axlen_cnt[7]_i_1__0_n_0 ), + .Q(axlen_cnt[7]), + .R(1'b0)); + LUT5 #( + .INIT(32'hFFFF88F8)) + next_pending_r_i_1 + (.I0(\axlen_cnt_reg[5]_0 ), + .I1(next), + .I2(next_pending_r), + .I3(\axlen_cnt_reg[4]_0 ), + .I4(next_pending_r_reg_0), + .O(incr_next_pending)); + LUT5 #( + .INIT(32'hAAA8AAAA)) + next_pending_r_i_2 + (.I0(\axlen_cnt_reg[3]_1 ), + .I1(axlen_cnt[5]), + .I2(axlen_cnt[6]), + .I3(axlen_cnt[7]), + .I4(next_pending_r_i_5_n_0), + .O(\axlen_cnt_reg[5]_0 )); + (* SOFT_HLUTNM = "soft_lutpair113" *) + LUT4 #( + .INIT(16'h0001)) + next_pending_r_i_5 + (.I0(axlen_cnt[3]), + .I1(axlen_cnt[4]), + .I2(axlen_cnt[1]), + .I3(axlen_cnt[2]), + .O(next_pending_r_i_5_n_0)); + FDRE next_pending_r_reg + (.C(aclk), + .CE(1'b1), + .D(incr_next_pending), + .Q(next_pending_r), + .R(1'b0)); + FDRE sel_first_reg + (.C(aclk), + .CE(1'b1), + .D(sel_first_reg_1), + .Q(sel_first_reg_0), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_29_b2s_incr_cmd" *) +module NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_incr_cmd_2 + (incr_next_pending, + sel_first_reg_0, + \axlen_cnt_reg[7]_0 , + \axaddr_incr_reg[11]_0 , + \m_payload_i_reg[3] , + aclk, + sel_first_reg_1, + \axlen_cnt_reg[2]_0 , + \axlen_cnt_reg[2]_1 , + Q, + si_rs_arvalid, + \axaddr_incr_reg[3]_0 , + r_push, + \axlen_cnt_reg[4]_0 , + next_pending_r_reg_0, + \axlen_cnt_reg[3]_0 , + \axaddr_incr_reg[11]_1 , + \axaddr_incr_reg[7]_0 , + \axaddr_incr_reg[3]_1 , + \axlen_cnt_reg[7]_1 , + \axaddr_incr_reg[0]_0 , + m_axi_arready); + output incr_next_pending; + output sel_first_reg_0; + output \axlen_cnt_reg[7]_0 ; + output [11:0]\axaddr_incr_reg[11]_0 ; + output [3:0]\m_payload_i_reg[3] ; + input aclk; + input sel_first_reg_1; + input \axlen_cnt_reg[2]_0 ; + input [8:0]\axlen_cnt_reg[2]_1 ; + input [1:0]Q; + input si_rs_arvalid; + input [3:0]\axaddr_incr_reg[3]_0 ; + input r_push; + input \axlen_cnt_reg[4]_0 ; + input next_pending_r_reg_0; + input \axlen_cnt_reg[3]_0 ; + input [3:0]\axaddr_incr_reg[11]_1 ; + input [3:0]\axaddr_incr_reg[7]_0 ; + input [3:0]\axaddr_incr_reg[3]_1 ; + input \axlen_cnt_reg[7]_1 ; + input [0:0]\axaddr_incr_reg[0]_0 ; + input m_axi_arready; + + wire [1:0]Q; + wire aclk; + wire \axaddr_incr[0]_i_1__0_n_0 ; + wire \axaddr_incr[10]_i_1__0_n_0 ; + wire \axaddr_incr[11]_i_2__0_n_0 ; + wire \axaddr_incr[1]_i_1__0_n_0 ; + wire \axaddr_incr[2]_i_1__0_n_0 ; + wire \axaddr_incr[3]_i_1__0_n_0 ; + wire \axaddr_incr[4]_i_1__0_n_0 ; + wire \axaddr_incr[5]_i_1__0_n_0 ; + wire \axaddr_incr[6]_i_1__0_n_0 ; + wire \axaddr_incr[7]_i_1__0_n_0 ; + wire \axaddr_incr[8]_i_1__0_n_0 ; + wire \axaddr_incr[9]_i_1__0_n_0 ; + wire [0:0]\axaddr_incr_reg[0]_0 ; + wire [11:0]\axaddr_incr_reg[11]_0 ; + wire [3:0]\axaddr_incr_reg[11]_1 ; + wire \axaddr_incr_reg[11]_i_4__0_n_1 ; + wire \axaddr_incr_reg[11]_i_4__0_n_2 ; + wire \axaddr_incr_reg[11]_i_4__0_n_3 ; + wire \axaddr_incr_reg[11]_i_4__0_n_4 ; + wire \axaddr_incr_reg[11]_i_4__0_n_5 ; + wire \axaddr_incr_reg[11]_i_4__0_n_6 ; + wire \axaddr_incr_reg[11]_i_4__0_n_7 ; + wire [3:0]\axaddr_incr_reg[3]_0 ; + wire [3:0]\axaddr_incr_reg[3]_1 ; + wire \axaddr_incr_reg[3]_i_3__0_n_0 ; + wire \axaddr_incr_reg[3]_i_3__0_n_1 ; + wire \axaddr_incr_reg[3]_i_3__0_n_2 ; + wire \axaddr_incr_reg[3]_i_3__0_n_3 ; + wire \axaddr_incr_reg[3]_i_3__0_n_4 ; + wire \axaddr_incr_reg[3]_i_3__0_n_5 ; + wire \axaddr_incr_reg[3]_i_3__0_n_6 ; + wire \axaddr_incr_reg[3]_i_3__0_n_7 ; + wire [3:0]\axaddr_incr_reg[7]_0 ; + wire \axaddr_incr_reg[7]_i_3__0_n_0 ; + wire \axaddr_incr_reg[7]_i_3__0_n_1 ; + wire \axaddr_incr_reg[7]_i_3__0_n_2 ; + wire \axaddr_incr_reg[7]_i_3__0_n_3 ; + wire \axaddr_incr_reg[7]_i_3__0_n_4 ; + wire \axaddr_incr_reg[7]_i_3__0_n_5 ; + wire \axaddr_incr_reg[7]_i_3__0_n_6 ; + wire \axaddr_incr_reg[7]_i_3__0_n_7 ; + wire \axlen_cnt[0]_i_1__1_n_0 ; + wire \axlen_cnt[1]_i_1__1_n_0 ; + wire \axlen_cnt[2]_i_1__1_n_0 ; + wire \axlen_cnt[3]_i_2__0_n_0 ; + wire \axlen_cnt[4]_i_1__1_n_0 ; + wire \axlen_cnt[5]_i_1__0_n_0 ; + wire \axlen_cnt[6]_i_1_n_0 ; + wire \axlen_cnt[7]_i_2__0_n_0 ; + wire \axlen_cnt[7]_i_3_n_0 ; + wire \axlen_cnt_reg[2]_0 ; + wire [8:0]\axlen_cnt_reg[2]_1 ; + wire \axlen_cnt_reg[3]_0 ; + wire \axlen_cnt_reg[4]_0 ; + wire \axlen_cnt_reg[7]_0 ; + wire \axlen_cnt_reg[7]_1 ; + wire \axlen_cnt_reg_n_0_[0] ; + wire \axlen_cnt_reg_n_0_[1] ; + wire \axlen_cnt_reg_n_0_[2] ; + wire \axlen_cnt_reg_n_0_[3] ; + wire \axlen_cnt_reg_n_0_[4] ; + wire \axlen_cnt_reg_n_0_[5] ; + wire \axlen_cnt_reg_n_0_[6] ; + wire \axlen_cnt_reg_n_0_[7] ; + wire incr_next_pending; + wire m_axi_arready; + wire [3:0]\m_payload_i_reg[3] ; + wire next_pending_r; + wire next_pending_r_i_4__0_n_0; + wire next_pending_r_reg_0; + wire r_push; + wire sel_first_reg_0; + wire sel_first_reg_1; + wire si_rs_arvalid; + wire [3:3]\NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED ; + + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT3 #( + .INIT(8'hB8)) + \axaddr_incr[0]_i_1__0 + (.I0(\axaddr_incr_reg[3]_1 [0]), + .I1(sel_first_reg_0), + .I2(\axaddr_incr_reg[3]_i_3__0_n_7 ), + .O(\axaddr_incr[0]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT3 #( + .INIT(8'hB8)) + \axaddr_incr[10]_i_1__0 + (.I0(\axaddr_incr_reg[11]_1 [2]), + .I1(sel_first_reg_0), + .I2(\axaddr_incr_reg[11]_i_4__0_n_5 ), + .O(\axaddr_incr[10]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT3 #( + .INIT(8'hB8)) + \axaddr_incr[11]_i_2__0 + (.I0(\axaddr_incr_reg[11]_1 [3]), + .I1(sel_first_reg_0), + .I2(\axaddr_incr_reg[11]_i_4__0_n_4 ), + .O(\axaddr_incr[11]_i_2__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT3 #( + .INIT(8'hB8)) + \axaddr_incr[1]_i_1__0 + (.I0(\axaddr_incr_reg[3]_1 [1]), + .I1(sel_first_reg_0), + .I2(\axaddr_incr_reg[3]_i_3__0_n_6 ), + .O(\axaddr_incr[1]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT3 #( + .INIT(8'hB8)) + \axaddr_incr[2]_i_1__0 + (.I0(\axaddr_incr_reg[3]_1 [2]), + .I1(sel_first_reg_0), + .I2(\axaddr_incr_reg[3]_i_3__0_n_5 ), + .O(\axaddr_incr[2]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'h0102020202020202)) + \axaddr_incr[3]_i_10 + (.I0(\axlen_cnt_reg[2]_1 [0]), + .I1(\axlen_cnt_reg[2]_1 [5]), + .I2(\axlen_cnt_reg[2]_1 [4]), + .I3(Q[1]), + .I4(m_axi_arready), + .I5(Q[0]), + .O(\m_payload_i_reg[3] [0])); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT3 #( + .INIT(8'hB8)) + \axaddr_incr[3]_i_1__0 + (.I0(\axaddr_incr_reg[3]_1 [3]), + .I1(sel_first_reg_0), + .I2(\axaddr_incr_reg[3]_i_3__0_n_4 ), + .O(\axaddr_incr[3]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'h6AAAAAAAAAAAAAAA)) + \axaddr_incr[3]_i_7 + (.I0(\axlen_cnt_reg[2]_1 [3]), + .I1(\axlen_cnt_reg[2]_1 [5]), + .I2(\axlen_cnt_reg[2]_1 [4]), + .I3(Q[1]), + .I4(m_axi_arready), + .I5(Q[0]), + .O(\m_payload_i_reg[3] [3])); + LUT6 #( + .INIT(64'h1A2A2A2A2A2A2A2A)) + \axaddr_incr[3]_i_8 + (.I0(\axlen_cnt_reg[2]_1 [2]), + .I1(\axlen_cnt_reg[2]_1 [4]), + .I2(\axlen_cnt_reg[2]_1 [5]), + .I3(Q[1]), + .I4(m_axi_arready), + .I5(Q[0]), + .O(\m_payload_i_reg[3] [2])); + LUT6 #( + .INIT(64'h1222222222222222)) + \axaddr_incr[3]_i_9 + (.I0(\axlen_cnt_reg[2]_1 [1]), + .I1(\axlen_cnt_reg[2]_1 [5]), + .I2(\axlen_cnt_reg[2]_1 [4]), + .I3(Q[1]), + .I4(m_axi_arready), + .I5(Q[0]), + .O(\m_payload_i_reg[3] [1])); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT3 #( + .INIT(8'hB8)) + \axaddr_incr[4]_i_1__0 + (.I0(\axaddr_incr_reg[7]_0 [0]), + .I1(sel_first_reg_0), + .I2(\axaddr_incr_reg[7]_i_3__0_n_7 ), + .O(\axaddr_incr[4]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT3 #( + .INIT(8'hB8)) + \axaddr_incr[5]_i_1__0 + (.I0(\axaddr_incr_reg[7]_0 [1]), + .I1(sel_first_reg_0), + .I2(\axaddr_incr_reg[7]_i_3__0_n_6 ), + .O(\axaddr_incr[5]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT3 #( + .INIT(8'hB8)) + \axaddr_incr[6]_i_1__0 + (.I0(\axaddr_incr_reg[7]_0 [2]), + .I1(sel_first_reg_0), + .I2(\axaddr_incr_reg[7]_i_3__0_n_5 ), + .O(\axaddr_incr[6]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT3 #( + .INIT(8'hB8)) + \axaddr_incr[7]_i_1__0 + (.I0(\axaddr_incr_reg[7]_0 [3]), + .I1(sel_first_reg_0), + .I2(\axaddr_incr_reg[7]_i_3__0_n_4 ), + .O(\axaddr_incr[7]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT3 #( + .INIT(8'hB8)) + \axaddr_incr[8]_i_1__0 + (.I0(\axaddr_incr_reg[11]_1 [0]), + .I1(sel_first_reg_0), + .I2(\axaddr_incr_reg[11]_i_4__0_n_7 ), + .O(\axaddr_incr[8]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT3 #( + .INIT(8'hB8)) + \axaddr_incr[9]_i_1__0 + (.I0(\axaddr_incr_reg[11]_1 [1]), + .I1(sel_first_reg_0), + .I2(\axaddr_incr_reg[11]_i_4__0_n_6 ), + .O(\axaddr_incr[9]_i_1__0_n_0 )); + FDRE \axaddr_incr_reg[0] + (.C(aclk), + .CE(\axaddr_incr_reg[0]_0 ), + .D(\axaddr_incr[0]_i_1__0_n_0 ), + .Q(\axaddr_incr_reg[11]_0 [0]), + .R(1'b0)); + FDRE \axaddr_incr_reg[10] + (.C(aclk), + .CE(\axaddr_incr_reg[0]_0 ), + .D(\axaddr_incr[10]_i_1__0_n_0 ), + .Q(\axaddr_incr_reg[11]_0 [10]), + .R(1'b0)); + FDRE \axaddr_incr_reg[11] + (.C(aclk), + .CE(\axaddr_incr_reg[0]_0 ), + .D(\axaddr_incr[11]_i_2__0_n_0 ), + .Q(\axaddr_incr_reg[11]_0 [11]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \axaddr_incr_reg[11]_i_4__0 + (.CI(\axaddr_incr_reg[7]_i_3__0_n_0 ), + .CO({\NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_4__0_n_1 ,\axaddr_incr_reg[11]_i_4__0_n_2 ,\axaddr_incr_reg[11]_i_4__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\axaddr_incr_reg[11]_i_4__0_n_4 ,\axaddr_incr_reg[11]_i_4__0_n_5 ,\axaddr_incr_reg[11]_i_4__0_n_6 ,\axaddr_incr_reg[11]_i_4__0_n_7 }), + .S(\axaddr_incr_reg[11]_0 [11:8])); + FDRE \axaddr_incr_reg[1] + (.C(aclk), + .CE(\axaddr_incr_reg[0]_0 ), + .D(\axaddr_incr[1]_i_1__0_n_0 ), + .Q(\axaddr_incr_reg[11]_0 [1]), + .R(1'b0)); + FDRE \axaddr_incr_reg[2] + (.C(aclk), + .CE(\axaddr_incr_reg[0]_0 ), + .D(\axaddr_incr[2]_i_1__0_n_0 ), + .Q(\axaddr_incr_reg[11]_0 [2]), + .R(1'b0)); + FDRE \axaddr_incr_reg[3] + (.C(aclk), + .CE(\axaddr_incr_reg[0]_0 ), + .D(\axaddr_incr[3]_i_1__0_n_0 ), + .Q(\axaddr_incr_reg[11]_0 [3]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \axaddr_incr_reg[3]_i_3__0 + (.CI(1'b0), + .CO({\axaddr_incr_reg[3]_i_3__0_n_0 ,\axaddr_incr_reg[3]_i_3__0_n_1 ,\axaddr_incr_reg[3]_i_3__0_n_2 ,\axaddr_incr_reg[3]_i_3__0_n_3 }), + .CYINIT(1'b0), + .DI(\axaddr_incr_reg[11]_0 [3:0]), + .O({\axaddr_incr_reg[3]_i_3__0_n_4 ,\axaddr_incr_reg[3]_i_3__0_n_5 ,\axaddr_incr_reg[3]_i_3__0_n_6 ,\axaddr_incr_reg[3]_i_3__0_n_7 }), + .S(\axaddr_incr_reg[3]_0 )); + FDRE \axaddr_incr_reg[4] + (.C(aclk), + .CE(\axaddr_incr_reg[0]_0 ), + .D(\axaddr_incr[4]_i_1__0_n_0 ), + .Q(\axaddr_incr_reg[11]_0 [4]), + .R(1'b0)); + FDRE \axaddr_incr_reg[5] + (.C(aclk), + .CE(\axaddr_incr_reg[0]_0 ), + .D(\axaddr_incr[5]_i_1__0_n_0 ), + .Q(\axaddr_incr_reg[11]_0 [5]), + .R(1'b0)); + FDRE \axaddr_incr_reg[6] + (.C(aclk), + .CE(\axaddr_incr_reg[0]_0 ), + .D(\axaddr_incr[6]_i_1__0_n_0 ), + .Q(\axaddr_incr_reg[11]_0 [6]), + .R(1'b0)); + FDRE \axaddr_incr_reg[7] + (.C(aclk), + .CE(\axaddr_incr_reg[0]_0 ), + .D(\axaddr_incr[7]_i_1__0_n_0 ), + .Q(\axaddr_incr_reg[11]_0 [7]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \axaddr_incr_reg[7]_i_3__0 + (.CI(\axaddr_incr_reg[3]_i_3__0_n_0 ), + .CO({\axaddr_incr_reg[7]_i_3__0_n_0 ,\axaddr_incr_reg[7]_i_3__0_n_1 ,\axaddr_incr_reg[7]_i_3__0_n_2 ,\axaddr_incr_reg[7]_i_3__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\axaddr_incr_reg[7]_i_3__0_n_4 ,\axaddr_incr_reg[7]_i_3__0_n_5 ,\axaddr_incr_reg[7]_i_3__0_n_6 ,\axaddr_incr_reg[7]_i_3__0_n_7 }), + .S(\axaddr_incr_reg[11]_0 [7:4])); + FDRE \axaddr_incr_reg[8] + (.C(aclk), + .CE(\axaddr_incr_reg[0]_0 ), + .D(\axaddr_incr[8]_i_1__0_n_0 ), + .Q(\axaddr_incr_reg[11]_0 [8]), + .R(1'b0)); + FDRE \axaddr_incr_reg[9] + (.C(aclk), + .CE(\axaddr_incr_reg[0]_0 ), + .D(\axaddr_incr[9]_i_1__0_n_0 ), + .Q(\axaddr_incr_reg[11]_0 [9]), + .R(1'b0)); + LUT5 #( + .INIT(32'h44F44444)) + \axlen_cnt[0]_i_1__1 + (.I0(\axlen_cnt_reg_n_0_[0] ), + .I1(\axlen_cnt_reg[7]_0 ), + .I2(\axlen_cnt_reg[2]_1 [6]), + .I3(Q[1]), + .I4(si_rs_arvalid), + .O(\axlen_cnt[0]_i_1__1_n_0 )); + LUT5 #( + .INIT(32'hF44F4444)) + \axlen_cnt[1]_i_1__1 + (.I0(\axlen_cnt_reg[2]_0 ), + .I1(\axlen_cnt_reg[2]_1 [7]), + .I2(\axlen_cnt_reg_n_0_[1] ), + .I3(\axlen_cnt_reg_n_0_[0] ), + .I4(\axlen_cnt_reg[7]_0 ), + .O(\axlen_cnt[1]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hF4F4F44F44444444)) + \axlen_cnt[2]_i_1__1 + (.I0(\axlen_cnt_reg[2]_0 ), + .I1(\axlen_cnt_reg[2]_1 [8]), + .I2(\axlen_cnt_reg_n_0_[2] ), + .I3(\axlen_cnt_reg_n_0_[0] ), + .I4(\axlen_cnt_reg_n_0_[1] ), + .I5(\axlen_cnt_reg[7]_0 ), + .O(\axlen_cnt[2]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hEEEEEEEBAAAAAAAA)) + \axlen_cnt[3]_i_2__0 + (.I0(\axlen_cnt_reg[3]_0 ), + .I1(\axlen_cnt_reg_n_0_[3] ), + .I2(\axlen_cnt_reg_n_0_[2] ), + .I3(\axlen_cnt_reg_n_0_[1] ), + .I4(\axlen_cnt_reg_n_0_[0] ), + .I5(\axlen_cnt_reg[7]_0 ), + .O(\axlen_cnt[3]_i_2__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT5 #( + .INIT(32'hAAAAAAA9)) + \axlen_cnt[4]_i_1__1 + (.I0(\axlen_cnt_reg_n_0_[4] ), + .I1(\axlen_cnt_reg_n_0_[3] ), + .I2(\axlen_cnt_reg_n_0_[0] ), + .I3(\axlen_cnt_reg_n_0_[1] ), + .I4(\axlen_cnt_reg_n_0_[2] ), + .O(\axlen_cnt[4]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAAAAAAAAAA9)) + \axlen_cnt[5]_i_1__0 + (.I0(\axlen_cnt_reg_n_0_[5] ), + .I1(\axlen_cnt_reg_n_0_[0] ), + .I2(\axlen_cnt_reg_n_0_[1] ), + .I3(\axlen_cnt_reg_n_0_[2] ), + .I4(\axlen_cnt_reg_n_0_[4] ), + .I5(\axlen_cnt_reg_n_0_[3] ), + .O(\axlen_cnt[5]_i_1__0_n_0 )); + LUT5 #( + .INIT(32'hAAAAA9AA)) + \axlen_cnt[6]_i_1 + (.I0(\axlen_cnt_reg_n_0_[6] ), + .I1(\axlen_cnt_reg_n_0_[3] ), + .I2(\axlen_cnt_reg_n_0_[4] ), + .I3(\axlen_cnt[7]_i_3_n_0 ), + .I4(\axlen_cnt_reg_n_0_[5] ), + .O(\axlen_cnt[6]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAAAAAAAA9AA)) + \axlen_cnt[7]_i_2__0 + (.I0(\axlen_cnt_reg_n_0_[7] ), + .I1(\axlen_cnt_reg_n_0_[6] ), + .I2(\axlen_cnt_reg_n_0_[5] ), + .I3(\axlen_cnt[7]_i_3_n_0 ), + .I4(\axlen_cnt_reg_n_0_[4] ), + .I5(\axlen_cnt_reg_n_0_[3] ), + .O(\axlen_cnt[7]_i_2__0_n_0 )); + LUT3 #( + .INIT(8'h01)) + \axlen_cnt[7]_i_3 + (.I0(\axlen_cnt_reg_n_0_[0] ), + .I1(\axlen_cnt_reg_n_0_[1] ), + .I2(\axlen_cnt_reg_n_0_[2] ), + .O(\axlen_cnt[7]_i_3_n_0 )); + FDRE \axlen_cnt_reg[0] + (.C(aclk), + .CE(\axlen_cnt_reg[4]_0 ), + .D(\axlen_cnt[0]_i_1__1_n_0 ), + .Q(\axlen_cnt_reg_n_0_[0] ), + .R(1'b0)); + FDRE \axlen_cnt_reg[1] + (.C(aclk), + .CE(\axlen_cnt_reg[4]_0 ), + .D(\axlen_cnt[1]_i_1__1_n_0 ), + .Q(\axlen_cnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE \axlen_cnt_reg[2] + (.C(aclk), + .CE(\axlen_cnt_reg[4]_0 ), + .D(\axlen_cnt[2]_i_1__1_n_0 ), + .Q(\axlen_cnt_reg_n_0_[2] ), + .R(1'b0)); + FDRE \axlen_cnt_reg[3] + (.C(aclk), + .CE(\axlen_cnt_reg[4]_0 ), + .D(\axlen_cnt[3]_i_2__0_n_0 ), + .Q(\axlen_cnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE \axlen_cnt_reg[4] + (.C(aclk), + .CE(\axlen_cnt_reg[4]_0 ), + .D(\axlen_cnt[4]_i_1__1_n_0 ), + .Q(\axlen_cnt_reg_n_0_[4] ), + .R(\axlen_cnt_reg[7]_1 )); + FDRE \axlen_cnt_reg[5] + (.C(aclk), + .CE(\axlen_cnt_reg[4]_0 ), + .D(\axlen_cnt[5]_i_1__0_n_0 ), + .Q(\axlen_cnt_reg_n_0_[5] ), + .R(\axlen_cnt_reg[7]_1 )); + FDRE \axlen_cnt_reg[6] + (.C(aclk), + .CE(\axlen_cnt_reg[4]_0 ), + .D(\axlen_cnt[6]_i_1_n_0 ), + .Q(\axlen_cnt_reg_n_0_[6] ), + .R(\axlen_cnt_reg[7]_1 )); + FDRE \axlen_cnt_reg[7] + (.C(aclk), + .CE(\axlen_cnt_reg[4]_0 ), + .D(\axlen_cnt[7]_i_2__0_n_0 ), + .Q(\axlen_cnt_reg_n_0_[7] ), + .R(\axlen_cnt_reg[7]_1 )); + LUT5 #( + .INIT(32'hFFFF88F8)) + next_pending_r_i_1__1 + (.I0(\axlen_cnt_reg[7]_0 ), + .I1(r_push), + .I2(next_pending_r), + .I3(\axlen_cnt_reg[4]_0 ), + .I4(next_pending_r_reg_0), + .O(incr_next_pending)); + LUT5 #( + .INIT(32'hAAA8AAAA)) + next_pending_r_i_2__0 + (.I0(\axlen_cnt_reg[2]_0 ), + .I1(\axlen_cnt_reg_n_0_[7] ), + .I2(\axlen_cnt_reg_n_0_[5] ), + .I3(\axlen_cnt_reg_n_0_[6] ), + .I4(next_pending_r_i_4__0_n_0), + .O(\axlen_cnt_reg[7]_0 )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT4 #( + .INIT(16'h0001)) + next_pending_r_i_4__0 + (.I0(\axlen_cnt_reg_n_0_[3] ), + .I1(\axlen_cnt_reg_n_0_[4] ), + .I2(\axlen_cnt_reg_n_0_[1] ), + .I3(\axlen_cnt_reg_n_0_[2] ), + .O(next_pending_r_i_4__0_n_0)); + FDRE next_pending_r_reg + (.C(aclk), + .CE(1'b1), + .D(incr_next_pending), + .Q(next_pending_r), + .R(1'b0)); + FDRE sel_first_reg + (.C(aclk), + .CE(1'b1), + .D(sel_first_reg_1), + .Q(sel_first_reg_0), + .R(1'b0)); +endmodule + +module NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_r_channel + (\cnt_read_reg[2] , + \cnt_read_reg[4] , + m_axi_rready, + out, + r_push_r_reg_0, + r_push, + aclk, + r_rlast, + \cnt_read_reg[4]_0 , + si_rs_rready, + m_axi_rvalid, + in, + D, + areset_d1); + output \cnt_read_reg[2] ; + output \cnt_read_reg[4] ; + output m_axi_rready; + output [33:0]out; + output [12:0]r_push_r_reg_0; + input r_push; + input aclk; + input r_rlast; + input \cnt_read_reg[4]_0 ; + input si_rs_rready; + input m_axi_rvalid; + input [33:0]in; + input [11:0]D; + input areset_d1; + + wire [11:0]D; + wire aclk; + wire areset_d1; + wire \cnt_read_reg[2] ; + wire \cnt_read_reg[4] ; + wire \cnt_read_reg[4]_0 ; + wire [33:0]in; + wire m_axi_rready; + wire m_axi_rvalid; + wire [33:0]out; + wire r_push; + wire r_push_r; + wire [12:0]r_push_r_reg_0; + wire r_rlast; + wire rd_data_fifo_0_n_0; + wire rd_data_fifo_0_n_3; + wire si_rs_rready; + wire [12:0]trans_in; + wire transaction_fifo_0_n_1; + + FDRE \r_arid_r_reg[0] + (.C(aclk), + .CE(1'b1), + .D(D[0]), + .Q(trans_in[1]), + .R(1'b0)); + FDRE \r_arid_r_reg[10] + (.C(aclk), + .CE(1'b1), + .D(D[10]), + .Q(trans_in[11]), + .R(1'b0)); + FDRE \r_arid_r_reg[11] + (.C(aclk), + .CE(1'b1), + .D(D[11]), + .Q(trans_in[12]), + .R(1'b0)); + FDRE \r_arid_r_reg[1] + (.C(aclk), + .CE(1'b1), + .D(D[1]), + .Q(trans_in[2]), + .R(1'b0)); + FDRE \r_arid_r_reg[2] + (.C(aclk), + .CE(1'b1), + .D(D[2]), + .Q(trans_in[3]), + .R(1'b0)); + FDRE \r_arid_r_reg[3] + (.C(aclk), + .CE(1'b1), + .D(D[3]), + .Q(trans_in[4]), + .R(1'b0)); + FDRE \r_arid_r_reg[4] + (.C(aclk), + .CE(1'b1), + .D(D[4]), + .Q(trans_in[5]), + .R(1'b0)); + FDRE \r_arid_r_reg[5] + (.C(aclk), + .CE(1'b1), + .D(D[5]), + .Q(trans_in[6]), + .R(1'b0)); + FDRE \r_arid_r_reg[6] + (.C(aclk), + .CE(1'b1), + .D(D[6]), + .Q(trans_in[7]), + .R(1'b0)); + FDRE \r_arid_r_reg[7] + (.C(aclk), + .CE(1'b1), + .D(D[7]), + .Q(trans_in[8]), + .R(1'b0)); + FDRE \r_arid_r_reg[8] + (.C(aclk), + .CE(1'b1), + .D(D[8]), + .Q(trans_in[9]), + .R(1'b0)); + FDRE \r_arid_r_reg[9] + (.C(aclk), + .CE(1'b1), + .D(D[9]), + .Q(trans_in[10]), + .R(1'b0)); + FDRE r_push_r_reg + (.C(aclk), + .CE(1'b1), + .D(r_push), + .Q(r_push_r), + .R(1'b0)); + FDRE r_rlast_r_reg + (.C(aclk), + .CE(1'b1), + .D(r_rlast), + .Q(trans_in[0]), + .R(1'b0)); + NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized1 rd_data_fifo_0 + (.aclk(aclk), + .areset_d1(areset_d1), + .\cnt_read_reg[2]_0 (\cnt_read_reg[2] ), + .\cnt_read_reg[4]_0 (rd_data_fifo_0_n_3), + .\cnt_read_reg[4]_1 (\cnt_read_reg[4]_0 ), + .in(in), + .m_axi_rready(m_axi_rready), + .m_axi_rvalid(m_axi_rvalid), + .m_valid_i_reg(transaction_fifo_0_n_1), + .out(out), + .r_push_r(r_push_r), + .s_ready_i_reg(rd_data_fifo_0_n_0), + .si_rs_rready(si_rs_rready)); + NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized2 transaction_fifo_0 + (.\FSM_sequential_state_reg[0] (rd_data_fifo_0_n_3), + .aclk(aclk), + .areset_d1(areset_d1), + .\cnt_read_reg[4]_0 (\cnt_read_reg[4] ), + .\cnt_read_reg[4]_1 (transaction_fifo_0_n_1), + .\cnt_read_reg[4]_2 (\cnt_read_reg[4]_0 ), + .\cnt_read_reg[4]_3 (rd_data_fifo_0_n_0), + .in(trans_in), + .r_push_r(r_push_r), + .r_push_r_reg(r_push_r_reg_0)); +endmodule + +module NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm + (D, + axaddr_offset, + Q, + \FSM_sequential_state_reg[1]_0 , + \FSM_sequential_state_reg[1]_1 , + \wrap_second_len_r_reg[3] , + m_axi_arready_0, + m_axi_arready_1, + sel_first_i, + m_axi_arready_2, + E, + sel_first_reg, + \m_payload_i_reg[11] , + \FSM_sequential_state_reg[1]_2 , + m_axi_arvalid, + m_valid_i0, + s_ready_i0, + m_valid_i_reg, + si_rs_arvalid, + \wrap_second_len_r_reg[3]_0 , + m_axi_arready, + \axlen_cnt_reg[7] , + \wrap_second_len_r_reg[3]_1 , + \axaddr_offset_r_reg[3] , + \axaddr_offset_r_reg[3]_0 , + \axaddr_offset_r_reg[0] , + \FSM_sequential_state_reg[0]_0 , + \FSM_sequential_state_reg[1]_3 , + \axaddr_offset_r_reg[2] , + \axaddr_offset_r_reg[2]_0 , + \axaddr_offset_r_reg[1] , + \axaddr_offset_r_reg[1]_0 , + \axaddr_offset_r_reg[3]_1 , + sel_first_reg_0, + areset_d1, + \axaddr_incr_reg[0] , + sel_first_reg_1, + O, + \axaddr_wrap_reg[11] , + \axaddr_wrap_reg[3] , + \axaddr_wrap_reg[7] , + \axaddr_wrap_reg[10] , + s_axi_arvalid, + m_valid_i_reg_0, + aclk); + output [3:0]D; + output [3:0]axaddr_offset; + output [1:0]Q; + output \FSM_sequential_state_reg[1]_0 ; + output \FSM_sequential_state_reg[1]_1 ; + output [3:0]\wrap_second_len_r_reg[3] ; + output m_axi_arready_0; + output m_axi_arready_1; + output sel_first_i; + output m_axi_arready_2; + output [0:0]E; + output [0:0]sel_first_reg; + output [11:0]\m_payload_i_reg[11] ; + output \FSM_sequential_state_reg[1]_2 ; + output m_axi_arvalid; + output m_valid_i0; + output s_ready_i0; + output [0:0]m_valid_i_reg; + input si_rs_arvalid; + input [3:0]\wrap_second_len_r_reg[3]_0 ; + input m_axi_arready; + input \axlen_cnt_reg[7] ; + input \wrap_second_len_r_reg[3]_1 ; + input [3:0]\axaddr_offset_r_reg[3] ; + input [13:0]\axaddr_offset_r_reg[3]_0 ; + input \axaddr_offset_r_reg[0] ; + input \FSM_sequential_state_reg[0]_0 ; + input \FSM_sequential_state_reg[1]_3 ; + input \axaddr_offset_r_reg[2] ; + input \axaddr_offset_r_reg[2]_0 ; + input \axaddr_offset_r_reg[1] ; + input \axaddr_offset_r_reg[1]_0 ; + input \axaddr_offset_r_reg[3]_1 ; + input sel_first_reg_0; + input areset_d1; + input \axaddr_incr_reg[0] ; + input sel_first_reg_1; + input [3:0]O; + input [11:0]\axaddr_wrap_reg[11] ; + input [3:0]\axaddr_wrap_reg[3] ; + input [3:0]\axaddr_wrap_reg[7] ; + input \axaddr_wrap_reg[10] ; + input s_axi_arvalid; + input m_valid_i_reg_0; + input aclk; + + wire [3:0]D; + wire [0:0]E; + wire \FSM_sequential_state_reg[0]_0 ; + wire \FSM_sequential_state_reg[1]_0 ; + wire \FSM_sequential_state_reg[1]_1 ; + wire \FSM_sequential_state_reg[1]_2 ; + wire \FSM_sequential_state_reg[1]_3 ; + wire [3:0]O; + wire [1:0]Q; + wire aclk; + wire areset_d1; + wire \axaddr_incr_reg[0] ; + wire [3:0]axaddr_offset; + wire \axaddr_offset_r_reg[0] ; + wire \axaddr_offset_r_reg[1] ; + wire \axaddr_offset_r_reg[1]_0 ; + wire \axaddr_offset_r_reg[2] ; + wire \axaddr_offset_r_reg[2]_0 ; + wire [3:0]\axaddr_offset_r_reg[3] ; + wire [13:0]\axaddr_offset_r_reg[3]_0 ; + wire \axaddr_offset_r_reg[3]_1 ; + wire \axaddr_wrap[11]_i_2__0_n_0 ; + wire \axaddr_wrap[11]_i_4__0_n_0 ; + wire \axaddr_wrap_reg[10] ; + wire [11:0]\axaddr_wrap_reg[11] ; + wire [3:0]\axaddr_wrap_reg[3] ; + wire [3:0]\axaddr_wrap_reg[7] ; + wire \axlen_cnt_reg[7] ; + wire m_axi_arready; + wire m_axi_arready_0; + wire m_axi_arready_1; + wire m_axi_arready_2; + wire m_axi_arvalid; + wire [11:0]\m_payload_i_reg[11] ; + wire m_valid_i0; + wire [0:0]m_valid_i_reg; + wire m_valid_i_reg_0; + wire [1:0]next_state__0; + wire s_axi_arvalid; + wire s_ready_i0; + wire sel_first_i; + wire [0:0]sel_first_reg; + wire sel_first_reg_0; + wire sel_first_reg_1; + wire si_rs_arvalid; + wire \wrap_cnt_r[2]_i_2__0_n_0 ; + wire \wrap_cnt_r[3]_i_2__0_n_0 ; + wire [3:0]\wrap_second_len_r_reg[3] ; + wire [3:0]\wrap_second_len_r_reg[3]_0 ; + wire \wrap_second_len_r_reg[3]_1 ; + + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h555577F7)) + \FSM_sequential_state[0]_i_1__0 + (.I0(Q[1]), + .I1(\FSM_sequential_state_reg[0]_0 ), + .I2(Q[0]), + .I3(m_axi_arready), + .I4(\FSM_sequential_state_reg[1]_3 ), + .O(next_state__0[0])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h00FF4040)) + \FSM_sequential_state[1]_i_1__0 + (.I0(\FSM_sequential_state_reg[0]_0 ), + .I1(Q[0]), + .I2(si_rs_arvalid), + .I3(\FSM_sequential_state_reg[1]_3 ), + .I4(Q[1]), + .O(next_state__0[1])); + (* FSM_ENCODED_STATES = "SM_IDLE:01,SM_DONE:00,SM_CMD_ACCEPTED:10,SM_CMD_EN:11" *) + FDSE #( + .INIT(1'b1)) + \FSM_sequential_state_reg[0] + (.C(aclk), + .CE(1'b1), + .D(next_state__0[0]), + .Q(Q[0]), + .S(areset_d1)); + (* FSM_ENCODED_STATES = "SM_IDLE:01,SM_DONE:00,SM_CMD_ACCEPTED:10,SM_CMD_EN:11" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_state_reg[1] + (.C(aclk), + .CE(1'b1), + .D(next_state__0[1]), + .Q(Q[1]), + .R(areset_d1)); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT4 #( + .INIT(16'hEAAA)) + \axaddr_incr[11]_i_1__0 + (.I0(\axaddr_incr_reg[0] ), + .I1(Q[0]), + .I2(m_axi_arready), + .I3(Q[1]), + .O(sel_first_reg)); + LUT6 #( + .INIT(64'hAAEAAA2AAA2AAA2A)) + \axaddr_offset_r[0]_i_1__0 + (.I0(\axaddr_offset_r_reg[3] [0]), + .I1(si_rs_arvalid), + .I2(Q[0]), + .I3(Q[1]), + .I4(\axaddr_offset_r_reg[3]_0 [12]), + .I5(\axaddr_offset_r_reg[0] ), + .O(axaddr_offset[0])); + LUT6 #( + .INIT(64'hBAAABAAABAAA8AAA)) + \axaddr_offset_r[1]_i_1__0 + (.I0(\axaddr_offset_r_reg[3] [1]), + .I1(Q[1]), + .I2(Q[0]), + .I3(si_rs_arvalid), + .I4(\axaddr_offset_r_reg[1] ), + .I5(\axaddr_offset_r_reg[1]_0 ), + .O(axaddr_offset[1])); + LUT6 #( + .INIT(64'hBAAA8AAABAAABAAA)) + \axaddr_offset_r[2]_i_1__0 + (.I0(\axaddr_offset_r_reg[3] [2]), + .I1(Q[1]), + .I2(Q[0]), + .I3(si_rs_arvalid), + .I4(\axaddr_offset_r_reg[2] ), + .I5(\axaddr_offset_r_reg[2]_0 ), + .O(axaddr_offset[2])); + LUT6 #( + .INIT(64'hAAAAAAAA30AAAAAA)) + \axaddr_offset_r[3]_i_1__0 + (.I0(\axaddr_offset_r_reg[3] [3]), + .I1(\axaddr_offset_r_reg[3]_1 ), + .I2(\axaddr_offset_r_reg[3]_0 [13]), + .I3(si_rs_arvalid), + .I4(Q[0]), + .I5(Q[1]), + .O(axaddr_offset[3])); + LUT6 #( + .INIT(64'h44F444F4FFFF44F4)) + \axaddr_wrap[0]_i_1__0 + (.I0(\axaddr_wrap[11]_i_2__0_n_0 ), + .I1(\axaddr_wrap_reg[3] [0]), + .I2(\axaddr_offset_r_reg[3]_0 [0]), + .I3(\FSM_sequential_state_reg[1]_2 ), + .I4(\axaddr_wrap_reg[11] [0]), + .I5(\axaddr_wrap[11]_i_4__0_n_0 ), + .O(\m_payload_i_reg[11] [0])); + LUT6 #( + .INIT(64'h44F444F4FFFF44F4)) + \axaddr_wrap[10]_i_1__0 + (.I0(\axaddr_wrap[11]_i_2__0_n_0 ), + .I1(O[2]), + .I2(\axaddr_wrap_reg[11] [10]), + .I3(\axaddr_wrap[11]_i_4__0_n_0 ), + .I4(\axaddr_offset_r_reg[3]_0 [10]), + .I5(\FSM_sequential_state_reg[1]_2 ), + .O(\m_payload_i_reg[11] [10])); + LUT6 #( + .INIT(64'h44F444F4FFFF44F4)) + \axaddr_wrap[11]_i_1__0 + (.I0(\axaddr_wrap[11]_i_2__0_n_0 ), + .I1(O[3]), + .I2(\axaddr_offset_r_reg[3]_0 [11]), + .I3(\FSM_sequential_state_reg[1]_2 ), + .I4(\axaddr_wrap_reg[11] [11]), + .I5(\axaddr_wrap[11]_i_4__0_n_0 ), + .O(\m_payload_i_reg[11] [11])); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'hBFFF)) + \axaddr_wrap[11]_i_2__0 + (.I0(\axaddr_wrap_reg[10] ), + .I1(Q[0]), + .I2(m_axi_arready), + .I3(Q[1]), + .O(\axaddr_wrap[11]_i_2__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7FFF)) + \axaddr_wrap[11]_i_4__0 + (.I0(Q[0]), + .I1(m_axi_arready), + .I2(Q[1]), + .I3(\axaddr_wrap_reg[10] ), + .O(\axaddr_wrap[11]_i_4__0_n_0 )); + LUT6 #( + .INIT(64'h44F444F4FFFF44F4)) + \axaddr_wrap[1]_i_1__0 + (.I0(\axaddr_wrap[11]_i_2__0_n_0 ), + .I1(\axaddr_wrap_reg[3] [1]), + .I2(\axaddr_offset_r_reg[3]_0 [1]), + .I3(\FSM_sequential_state_reg[1]_2 ), + .I4(\axaddr_wrap_reg[11] [1]), + .I5(\axaddr_wrap[11]_i_4__0_n_0 ), + .O(\m_payload_i_reg[11] [1])); + LUT6 #( + .INIT(64'h44F444F4FFFF44F4)) + \axaddr_wrap[2]_i_1__0 + (.I0(\axaddr_wrap[11]_i_4__0_n_0 ), + .I1(\axaddr_wrap_reg[11] [2]), + .I2(\axaddr_wrap_reg[3] [2]), + .I3(\axaddr_wrap[11]_i_2__0_n_0 ), + .I4(\axaddr_offset_r_reg[3]_0 [2]), + .I5(\FSM_sequential_state_reg[1]_2 ), + .O(\m_payload_i_reg[11] [2])); + LUT6 #( + .INIT(64'h44F444F4FFFF44F4)) + \axaddr_wrap[3]_i_1__0 + (.I0(\axaddr_wrap[11]_i_2__0_n_0 ), + .I1(\axaddr_wrap_reg[3] [3]), + .I2(\axaddr_wrap_reg[11] [3]), + .I3(\axaddr_wrap[11]_i_4__0_n_0 ), + .I4(\axaddr_offset_r_reg[3]_0 [3]), + .I5(\FSM_sequential_state_reg[1]_2 ), + .O(\m_payload_i_reg[11] [3])); + LUT6 #( + .INIT(64'h44F444F4FFFF44F4)) + \axaddr_wrap[4]_i_1__0 + (.I0(\axaddr_wrap[11]_i_2__0_n_0 ), + .I1(\axaddr_wrap_reg[7] [0]), + .I2(\axaddr_wrap_reg[11] [4]), + .I3(\axaddr_wrap[11]_i_4__0_n_0 ), + .I4(\axaddr_offset_r_reg[3]_0 [4]), + .I5(\FSM_sequential_state_reg[1]_2 ), + .O(\m_payload_i_reg[11] [4])); + LUT6 #( + .INIT(64'h44F444F4FFFF44F4)) + \axaddr_wrap[5]_i_1__0 + (.I0(\axaddr_wrap[11]_i_2__0_n_0 ), + .I1(\axaddr_wrap_reg[7] [1]), + .I2(\axaddr_wrap_reg[11] [5]), + .I3(\axaddr_wrap[11]_i_4__0_n_0 ), + .I4(\axaddr_offset_r_reg[3]_0 [5]), + .I5(\FSM_sequential_state_reg[1]_2 ), + .O(\m_payload_i_reg[11] [5])); + LUT6 #( + .INIT(64'h44F444F4FFFF44F4)) + \axaddr_wrap[6]_i_1__0 + (.I0(\axaddr_wrap[11]_i_2__0_n_0 ), + .I1(\axaddr_wrap_reg[7] [2]), + .I2(\axaddr_wrap_reg[11] [6]), + .I3(\axaddr_wrap[11]_i_4__0_n_0 ), + .I4(\axaddr_offset_r_reg[3]_0 [6]), + .I5(\FSM_sequential_state_reg[1]_2 ), + .O(\m_payload_i_reg[11] [6])); + LUT6 #( + .INIT(64'h44F444F4FFFF44F4)) + \axaddr_wrap[7]_i_1__0 + (.I0(\axaddr_wrap[11]_i_2__0_n_0 ), + .I1(\axaddr_wrap_reg[7] [3]), + .I2(\axaddr_offset_r_reg[3]_0 [7]), + .I3(\FSM_sequential_state_reg[1]_2 ), + .I4(\axaddr_wrap_reg[11] [7]), + .I5(\axaddr_wrap[11]_i_4__0_n_0 ), + .O(\m_payload_i_reg[11] [7])); + LUT6 #( + .INIT(64'h44F444F4FFFF44F4)) + \axaddr_wrap[8]_i_1__0 + (.I0(\axaddr_wrap[11]_i_2__0_n_0 ), + .I1(O[0]), + .I2(\axaddr_offset_r_reg[3]_0 [8]), + .I3(\FSM_sequential_state_reg[1]_2 ), + .I4(\axaddr_wrap_reg[11] [8]), + .I5(\axaddr_wrap[11]_i_4__0_n_0 ), + .O(\m_payload_i_reg[11] [8])); + LUT6 #( + .INIT(64'h44F444F4FFFF44F4)) + \axaddr_wrap[9]_i_1__0 + (.I0(\axaddr_wrap[11]_i_2__0_n_0 ), + .I1(O[1]), + .I2(\axaddr_wrap_reg[11] [9]), + .I3(\axaddr_wrap[11]_i_4__0_n_0 ), + .I4(\axaddr_offset_r_reg[3]_0 [9]), + .I5(\FSM_sequential_state_reg[1]_2 ), + .O(\m_payload_i_reg[11] [9])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT3 #( + .INIT(8'hBF)) + \axlen_cnt[2]_i_2__0 + (.I0(Q[1]), + .I1(Q[0]), + .I2(si_rs_arvalid), + .O(\FSM_sequential_state_reg[1]_1 )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hA0C0)) + \axlen_cnt[3]_i_1__2 + (.I0(m_axi_arready), + .I1(si_rs_arvalid), + .I2(Q[0]), + .I3(Q[1]), + .O(m_axi_arready_2)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h0000C840)) + \axlen_cnt[7]_i_1 + (.I0(Q[1]), + .I1(Q[0]), + .I2(si_rs_arvalid), + .I3(m_axi_arready), + .I4(\axlen_cnt_reg[7] ), + .O(\FSM_sequential_state_reg[1]_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h8)) + m_axi_arvalid_INST_0 + (.I0(Q[1]), + .I1(Q[0]), + .O(m_axi_arvalid)); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT3 #( + .INIT(8'h57)) + \m_payload_i[31]_i_1 + (.I0(si_rs_arvalid), + .I1(Q[0]), + .I2(Q[1]), + .O(m_valid_i_reg)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT5 #( + .INIT(32'hFFE0FFFF)) + m_valid_i_i_1__0 + (.I0(Q[1]), + .I1(Q[0]), + .I2(si_rs_arvalid), + .I3(s_axi_arvalid), + .I4(m_valid_i_reg_0), + .O(m_valid_i0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h80)) + r_push_r_i_1 + (.I0(Q[1]), + .I1(m_axi_arready), + .I2(Q[0]), + .O(\FSM_sequential_state_reg[1]_2 )); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT5 #( + .INIT(32'h1FFF1F1F)) + s_ready_i_i_1__0 + (.I0(Q[1]), + .I1(Q[0]), + .I2(si_rs_arvalid), + .I3(s_axi_arvalid), + .I4(m_valid_i_reg_0), + .O(s_ready_i0)); + LUT6 #( + .INIT(64'hFFFFFFFF4FCC4CCC)) + sel_first_i_1__2 + (.I0(m_axi_arready), + .I1(sel_first_reg_0), + .I2(Q[1]), + .I3(Q[0]), + .I4(si_rs_arvalid), + .I5(areset_d1), + .O(m_axi_arready_0)); + LUT6 #( + .INIT(64'hFFFFFFFF4FCC4CCC)) + sel_first_i_1__3 + (.I0(m_axi_arready), + .I1(\axaddr_incr_reg[0] ), + .I2(Q[1]), + .I3(Q[0]), + .I4(si_rs_arvalid), + .I5(areset_d1), + .O(m_axi_arready_1)); + LUT6 #( + .INIT(64'hCFFFFFFFCECECCCC)) + sel_first_i_1__4 + (.I0(si_rs_arvalid), + .I1(areset_d1), + .I2(Q[1]), + .I3(m_axi_arready), + .I4(Q[0]), + .I5(sel_first_reg_1), + .O(sel_first_i)); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h08)) + \wrap_boundary_axaddr_r[11]_i_1__0 + (.I0(si_rs_arvalid), + .I1(Q[0]), + .I2(Q[1]), + .O(E)); + LUT6 #( + .INIT(64'h38333333C8CCCCCC)) + \wrap_cnt_r[0]_i_1__0 + (.I0(axaddr_offset[0]), + .I1(\wrap_cnt_r[2]_i_2__0_n_0 ), + .I2(Q[1]), + .I3(Q[0]), + .I4(si_rs_arvalid), + .I5(\wrap_second_len_r_reg[3]_0 [0]), + .O(D[0])); + LUT5 #( + .INIT(32'h3CCCA0A0)) + \wrap_cnt_r[1]_i_1__0 + (.I0(axaddr_offset[1]), + .I1(\wrap_second_len_r_reg[3]_0 [1]), + .I2(\wrap_cnt_r[2]_i_2__0_n_0 ), + .I3(\wrap_second_len_r_reg[3]_0 [0]), + .I4(\FSM_sequential_state_reg[1]_1 ), + .O(D[1])); + LUT6 #( + .INIT(64'h59A9AAAAAAAAAAAA)) + \wrap_cnt_r[2]_i_1__0 + (.I0(\wrap_second_len_r_reg[3] [2]), + .I1(axaddr_offset[0]), + .I2(\FSM_sequential_state_reg[1]_1 ), + .I3(\wrap_second_len_r_reg[3]_0 [0]), + .I4(\wrap_cnt_r[2]_i_2__0_n_0 ), + .I5(\wrap_second_len_r_reg[3] [1]), + .O(D[2])); + LUT4 #( + .INIT(16'hFFFE)) + \wrap_cnt_r[2]_i_2__0 + (.I0(axaddr_offset[1]), + .I1(axaddr_offset[2]), + .I2(axaddr_offset[0]), + .I3(axaddr_offset[3]), + .O(\wrap_cnt_r[2]_i_2__0_n_0 )); + LUT4 #( + .INIT(16'hA6AA)) + \wrap_cnt_r[3]_i_1__0 + (.I0(\wrap_second_len_r_reg[3] [3]), + .I1(\wrap_second_len_r_reg[3] [1]), + .I2(\wrap_cnt_r[3]_i_2__0_n_0 ), + .I3(\wrap_second_len_r_reg[3] [2]), + .O(D[3])); + LUT6 #( + .INIT(64'h772277227722772F)) + \wrap_cnt_r[3]_i_2__0 + (.I0(\FSM_sequential_state_reg[1]_1 ), + .I1(\wrap_second_len_r_reg[3]_0 [0]), + .I2(axaddr_offset[3]), + .I3(axaddr_offset[0]), + .I4(axaddr_offset[2]), + .I5(axaddr_offset[1]), + .O(\wrap_cnt_r[3]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'h88BB88BB88BB88B8)) + \wrap_second_len_r[0]_i_1__0 + (.I0(\wrap_second_len_r_reg[3]_0 [0]), + .I1(\FSM_sequential_state_reg[1]_1 ), + .I2(axaddr_offset[3]), + .I3(axaddr_offset[0]), + .I4(axaddr_offset[2]), + .I5(axaddr_offset[1]), + .O(\wrap_second_len_r_reg[3] [0])); + LUT6 #( + .INIT(64'hBB88BB8888BB88B8)) + \wrap_second_len_r[1]_i_1__0 + (.I0(\wrap_second_len_r_reg[3]_0 [1]), + .I1(\FSM_sequential_state_reg[1]_1 ), + .I2(axaddr_offset[3]), + .I3(axaddr_offset[0]), + .I4(axaddr_offset[2]), + .I5(axaddr_offset[1]), + .O(\wrap_second_len_r_reg[3] [1])); + LUT6 #( + .INIT(64'hBBBB8888BB8888B8)) + \wrap_second_len_r[2]_i_1__0 + (.I0(\wrap_second_len_r_reg[3]_0 [2]), + .I1(\FSM_sequential_state_reg[1]_1 ), + .I2(axaddr_offset[3]), + .I3(axaddr_offset[0]), + .I4(axaddr_offset[2]), + .I5(axaddr_offset[1]), + .O(\wrap_second_len_r_reg[3] [2])); + LUT6 #( + .INIT(64'hFFFFFFF888888888)) + \wrap_second_len_r[3]_i_1__0 + (.I0(\FSM_sequential_state_reg[1]_1 ), + .I1(\wrap_second_len_r_reg[3]_0 [3]), + .I2(axaddr_offset[0]), + .I3(axaddr_offset[1]), + .I4(axaddr_offset[2]), + .I5(\wrap_second_len_r_reg[3]_1 ), + .O(\wrap_second_len_r_reg[3] [3])); +endmodule + +module NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_simple_fifo + (sel, + addr, + SR, + \bresp_cnt_reg[1] , + \cnt_read_reg[1]_0 , + out, + Q, + mhandshake_r, + areset_d1, + b_push, + in, + aclk, + shandshake_r); + output sel; + output [1:0]addr; + output [0:0]SR; + output \bresp_cnt_reg[1] ; + output \cnt_read_reg[1]_0 ; + output [11:0]out; + input [7:0]Q; + input mhandshake_r; + input areset_d1; + input b_push; + input [15:0]in; + input aclk; + input shandshake_r; + + wire [7:0]Q; + wire [0:0]SR; + wire aclk; + wire [1:0]addr; + wire areset_d1; + wire b_push; + wire \bresp_cnt_reg[1] ; + wire \cnt_read[0]_i_1_n_0 ; + wire \cnt_read[1]_i_1_n_0 ; + wire \cnt_read[1]_i_3_n_0 ; + wire \cnt_read[1]_i_4_n_0 ; + wire \cnt_read_reg[1]_0 ; + wire [15:0]in; + wire \memory_reg[3][0]_srl4_i_2_n_0 ; + wire \memory_reg[3][0]_srl4_i_3_n_0 ; + wire \memory_reg[3][0]_srl4_i_4_n_0 ; + wire \memory_reg[3][0]_srl4_n_0 ; + wire \memory_reg[3][1]_srl4_n_0 ; + wire \memory_reg[3][2]_srl4_n_0 ; + wire \memory_reg[3][3]_srl4_n_0 ; + wire mhandshake_r; + wire [11:0]out; + wire sel; + wire shandshake_r; + + LUT2 #( + .INIT(4'hE)) + \bresp_cnt[7]_i_1 + (.I0(areset_d1), + .I1(\bresp_cnt_reg[1] ), + .O(SR)); + (* SOFT_HLUTNM = "soft_lutpair120" *) + LUT2 #( + .INIT(4'h8)) + bvalid_i_i_3 + (.I0(addr[1]), + .I1(addr[0]), + .O(\cnt_read_reg[1]_0 )); + (* SOFT_HLUTNM = "soft_lutpair121" *) + LUT3 #( + .INIT(8'h96)) + \cnt_read[0]_i_1 + (.I0(b_push), + .I1(shandshake_r), + .I2(addr[0]), + .O(\cnt_read[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair121" *) + LUT4 #( + .INIT(16'hDB24)) + \cnt_read[1]_i_1 + (.I0(addr[0]), + .I1(shandshake_r), + .I2(b_push), + .I3(addr[1]), + .O(\cnt_read[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000000041000041)) + \cnt_read[1]_i_2 + (.I0(\cnt_read[1]_i_3_n_0 ), + .I1(\memory_reg[3][1]_srl4_n_0 ), + .I2(Q[1]), + .I3(\memory_reg[3][2]_srl4_n_0 ), + .I4(Q[2]), + .I5(\cnt_read[1]_i_4_n_0 ), + .O(\bresp_cnt_reg[1] )); + LUT6 #( + .INIT(64'hEFFEFFFFFFFFEFFE)) + \cnt_read[1]_i_3 + (.I0(Q[5]), + .I1(Q[4]), + .I2(Q[0]), + .I3(\memory_reg[3][0]_srl4_n_0 ), + .I4(Q[3]), + .I5(\memory_reg[3][3]_srl4_n_0 ), + .O(\cnt_read[1]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair120" *) + LUT5 #( + .INIT(32'hFFFFF8FF)) + \cnt_read[1]_i_4 + (.I0(addr[0]), + .I1(addr[1]), + .I2(Q[7]), + .I3(mhandshake_r), + .I4(Q[6]), + .O(\cnt_read[1]_i_4_n_0 )); + FDSE #( + .INIT(1'b1)) + \cnt_read_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\cnt_read[0]_i_1_n_0 ), + .Q(addr[0]), + .S(areset_d1)); + FDSE #( + .INIT(1'b1)) + \cnt_read_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\cnt_read[1]_i_1_n_0 ), + .Q(addr[1]), + .S(areset_d1)); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \memory_reg[3][0]_srl4 + (.A0(addr[0]), + .A1(addr[1]), + .A2(1'b0), + .A3(1'b0), + .CE(b_push), + .CLK(aclk), + .D(in[0]), + .Q(\memory_reg[3][0]_srl4_n_0 )); + LUT6 #( + .INIT(64'h0000000000000200)) + \memory_reg[3][0]_srl4_i_1__0 + (.I0(\memory_reg[3][0]_srl4_i_2_n_0 ), + .I1(Q[4]), + .I2(Q[6]), + .I3(mhandshake_r), + .I4(\memory_reg[3][0]_srl4_i_3_n_0 ), + .I5(\memory_reg[3][0]_srl4_i_4_n_0 ), + .O(sel)); + LUT6 #( + .INIT(64'hDD0D00000000DD0D)) + \memory_reg[3][0]_srl4_i_2 + (.I0(\memory_reg[3][3]_srl4_n_0 ), + .I1(Q[3]), + .I2(\memory_reg[3][2]_srl4_n_0 ), + .I3(Q[2]), + .I4(\memory_reg[3][1]_srl4_n_0 ), + .I5(Q[1]), + .O(\memory_reg[3][0]_srl4_i_2_n_0 )); + LUT4 #( + .INIT(16'hFFF8)) + \memory_reg[3][0]_srl4_i_3 + (.I0(addr[0]), + .I1(addr[1]), + .I2(Q[7]), + .I3(Q[5]), + .O(\memory_reg[3][0]_srl4_i_3_n_0 )); + LUT6 #( + .INIT(64'h2FF22FF2FFFF2FF2)) + \memory_reg[3][0]_srl4_i_4 + (.I0(Q[2]), + .I1(\memory_reg[3][2]_srl4_n_0 ), + .I2(\memory_reg[3][0]_srl4_n_0 ), + .I3(Q[0]), + .I4(Q[3]), + .I5(\memory_reg[3][3]_srl4_n_0 ), + .O(\memory_reg[3][0]_srl4_i_4_n_0 )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \memory_reg[3][10]_srl4 + (.A0(addr[0]), + .A1(addr[1]), + .A2(1'b0), + .A3(1'b0), + .CE(b_push), + .CLK(aclk), + .D(in[6]), + .Q(out[2])); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \memory_reg[3][11]_srl4 + (.A0(addr[0]), + .A1(addr[1]), + .A2(1'b0), + .A3(1'b0), + .CE(b_push), + .CLK(aclk), + .D(in[7]), + .Q(out[3])); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \memory_reg[3][12]_srl4 + (.A0(addr[0]), + .A1(addr[1]), + .A2(1'b0), + .A3(1'b0), + .CE(b_push), + .CLK(aclk), + .D(in[8]), + .Q(out[4])); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \memory_reg[3][13]_srl4 + (.A0(addr[0]), + .A1(addr[1]), + .A2(1'b0), + .A3(1'b0), + .CE(b_push), + .CLK(aclk), + .D(in[9]), + .Q(out[5])); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \memory_reg[3][14]_srl4 + (.A0(addr[0]), + .A1(addr[1]), + .A2(1'b0), + .A3(1'b0), + .CE(b_push), + .CLK(aclk), + .D(in[10]), + .Q(out[6])); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \memory_reg[3][15]_srl4 + (.A0(addr[0]), + .A1(addr[1]), + .A2(1'b0), + .A3(1'b0), + .CE(b_push), + .CLK(aclk), + .D(in[11]), + .Q(out[7])); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \memory_reg[3][16]_srl4 + (.A0(addr[0]), + .A1(addr[1]), + .A2(1'b0), + .A3(1'b0), + .CE(b_push), + .CLK(aclk), + .D(in[12]), + .Q(out[8])); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \memory_reg[3][17]_srl4 + (.A0(addr[0]), + .A1(addr[1]), + .A2(1'b0), + .A3(1'b0), + .CE(b_push), + .CLK(aclk), + .D(in[13]), + .Q(out[9])); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \memory_reg[3][18]_srl4 + (.A0(addr[0]), + .A1(addr[1]), + .A2(1'b0), + .A3(1'b0), + .CE(b_push), + .CLK(aclk), + .D(in[14]), + .Q(out[10])); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \memory_reg[3][19]_srl4 + (.A0(addr[0]), + .A1(addr[1]), + .A2(1'b0), + .A3(1'b0), + .CE(b_push), + .CLK(aclk), + .D(in[15]), + .Q(out[11])); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \memory_reg[3][1]_srl4 + (.A0(addr[0]), + .A1(addr[1]), + .A2(1'b0), + .A3(1'b0), + .CE(b_push), + .CLK(aclk), + .D(in[1]), + .Q(\memory_reg[3][1]_srl4_n_0 )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \memory_reg[3][2]_srl4 + (.A0(addr[0]), + .A1(addr[1]), + .A2(1'b0), + .A3(1'b0), + .CE(b_push), + .CLK(aclk), + .D(in[2]), + .Q(\memory_reg[3][2]_srl4_n_0 )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \memory_reg[3][3]_srl4 + (.A0(addr[0]), + .A1(addr[1]), + .A2(1'b0), + .A3(1'b0), + .CE(b_push), + .CLK(aclk), + .D(in[3]), + .Q(\memory_reg[3][3]_srl4_n_0 )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \memory_reg[3][8]_srl4 + (.A0(addr[0]), + .A1(addr[1]), + .A2(1'b0), + .A3(1'b0), + .CE(b_push), + .CLK(aclk), + .D(in[4]), + .Q(out[0])); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \memory_reg[3][9]_srl4 + (.A0(addr[0]), + .A1(addr[1]), + .A2(1'b0), + .A3(1'b0), + .CE(b_push), + .CLK(aclk), + .D(in[5]), + .Q(out[1])); +endmodule + +(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_29_b2s_simple_fifo" *) +module NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized0 + (areset_d1_reg, + mhandshake, + m_axi_bready, + \s_bresp_acc_reg[1] , + areset_d1, + shandshake_r, + bvalid_i_reg, + si_rs_bvalid, + si_rs_bready, + m_axi_bvalid, + mhandshake_r, + sel, + in, + aclk, + \cnt_read_reg[1]_0 ); + output areset_d1_reg; + output mhandshake; + output m_axi_bready; + output [1:0]\s_bresp_acc_reg[1] ; + input areset_d1; + input shandshake_r; + input bvalid_i_reg; + input si_rs_bvalid; + input si_rs_bready; + input m_axi_bvalid; + input mhandshake_r; + input sel; + input [1:0]in; + input aclk; + input \cnt_read_reg[1]_0 ; + + wire aclk; + wire areset_d1; + wire areset_d1_reg; + wire bvalid_i_i_2_n_0; + wire bvalid_i_reg; + wire [1:0]cnt_read; + wire \cnt_read[0]_i_1_n_0 ; + wire \cnt_read[1]_i_1_n_0 ; + wire \cnt_read_reg[1]_0 ; + wire [1:0]in; + wire m_axi_bready; + wire m_axi_bvalid; + wire mhandshake; + wire mhandshake_r; + wire [1:0]\s_bresp_acc_reg[1] ; + wire sel; + wire shandshake_r; + wire si_rs_bready; + wire si_rs_bvalid; + + LUT6 #( + .INIT(64'h0000000155550001)) + bvalid_i_i_1 + (.I0(areset_d1), + .I1(bvalid_i_i_2_n_0), + .I2(shandshake_r), + .I3(bvalid_i_reg), + .I4(si_rs_bvalid), + .I5(si_rs_bready), + .O(areset_d1_reg)); + LUT2 #( + .INIT(4'h8)) + bvalid_i_i_2 + (.I0(cnt_read[1]), + .I1(cnt_read[0]), + .O(bvalid_i_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair122" *) + LUT3 #( + .INIT(8'h96)) + \cnt_read[0]_i_1 + (.I0(\cnt_read_reg[1]_0 ), + .I1(shandshake_r), + .I2(cnt_read[0]), + .O(\cnt_read[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair122" *) + LUT4 #( + .INIT(16'hDB24)) + \cnt_read[1]_i_1 + (.I0(cnt_read[0]), + .I1(shandshake_r), + .I2(\cnt_read_reg[1]_0 ), + .I3(cnt_read[1]), + .O(\cnt_read[1]_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \cnt_read_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\cnt_read[0]_i_1_n_0 ), + .Q(cnt_read[0]), + .S(areset_d1)); + FDSE #( + .INIT(1'b1)) + \cnt_read_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\cnt_read[1]_i_1_n_0 ), + .Q(cnt_read[1]), + .S(areset_d1)); + (* SOFT_HLUTNM = "soft_lutpair123" *) + LUT3 #( + .INIT(8'h08)) + m_axi_bready_INST_0 + (.I0(cnt_read[0]), + .I1(cnt_read[1]), + .I2(mhandshake_r), + .O(m_axi_bready)); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \memory_reg[3][0]_srl4 + (.A0(cnt_read[0]), + .A1(cnt_read[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sel), + .CLK(aclk), + .D(in[0]), + .Q(\s_bresp_acc_reg[1] [0])); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \memory_reg[3][1]_srl4 + (.A0(cnt_read[0]), + .A1(cnt_read[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sel), + .CLK(aclk), + .D(in[1]), + .Q(\s_bresp_acc_reg[1] [1])); + (* SOFT_HLUTNM = "soft_lutpair123" *) + LUT4 #( + .INIT(16'h2000)) + mhandshake_r_i_1 + (.I0(m_axi_bvalid), + .I1(mhandshake_r), + .I2(cnt_read[1]), + .I3(cnt_read[0]), + .O(mhandshake)); +endmodule + +(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_29_b2s_simple_fifo" *) +module NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized1 + (s_ready_i_reg, + \cnt_read_reg[2]_0 , + m_axi_rready, + \cnt_read_reg[4]_0 , + out, + \cnt_read_reg[4]_1 , + si_rs_rready, + r_push_r, + m_valid_i_reg, + m_axi_rvalid, + in, + aclk, + areset_d1); + output s_ready_i_reg; + output \cnt_read_reg[2]_0 ; + output m_axi_rready; + output \cnt_read_reg[4]_0 ; + output [33:0]out; + input \cnt_read_reg[4]_1 ; + input si_rs_rready; + input r_push_r; + input m_valid_i_reg; + input m_axi_rvalid; + input [33:0]in; + input aclk; + input areset_d1; + + wire aclk; + wire areset_d1; + wire \cnt_read[0]_i_1_n_0 ; + wire \cnt_read[1]_i_1__0_n_0 ; + wire \cnt_read[2]_i_1_n_0 ; + wire \cnt_read[3]_i_1_n_0 ; + wire \cnt_read[4]_i_1__0_n_0 ; + wire \cnt_read[4]_i_2_n_0 ; + wire \cnt_read[4]_i_4_n_0 ; + wire [4:0]cnt_read_reg; + wire \cnt_read_reg[2]_0 ; + wire \cnt_read_reg[4]_0 ; + wire \cnt_read_reg[4]_1 ; + wire [33:0]in; + wire m_axi_rready; + wire m_axi_rvalid; + wire m_valid_i_reg; + wire [33:0]out; + wire r_push_r; + wire s_ready_i_reg; + wire si_rs_rready; + wire wr_en0; + wire \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ; + + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT5 #( + .INIT(32'h08888800)) + \FSM_sequential_state[1]_i_4 + (.I0(cnt_read_reg[4]), + .I1(cnt_read_reg[3]), + .I2(cnt_read_reg[0]), + .I3(cnt_read_reg[1]), + .I4(cnt_read_reg[2]), + .O(\cnt_read_reg[4]_0 )); + LUT1 #( + .INIT(2'h1)) + \cnt_read[0]_i_1 + (.I0(cnt_read_reg[0]), + .O(\cnt_read[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT4 #( + .INIT(16'hD22D)) + \cnt_read[1]_i_1__0 + (.I0(wr_en0), + .I1(\cnt_read_reg[4]_1 ), + .I2(cnt_read_reg[1]), + .I3(cnt_read_reg[0]), + .O(\cnt_read[1]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT5 #( + .INIT(32'hA9A96AA9)) + \cnt_read[2]_i_1 + (.I0(cnt_read_reg[2]), + .I1(cnt_read_reg[1]), + .I2(cnt_read_reg[0]), + .I3(wr_en0), + .I4(\cnt_read_reg[4]_1 ), + .O(\cnt_read[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBFFF4000FFF4000B)) + \cnt_read[3]_i_1 + (.I0(\cnt_read_reg[4]_1 ), + .I1(wr_en0), + .I2(cnt_read_reg[0]), + .I3(cnt_read_reg[1]), + .I4(cnt_read_reg[3]), + .I5(cnt_read_reg[2]), + .O(\cnt_read[3]_i_1_n_0 )); + LUT2 #( + .INIT(4'h6)) + \cnt_read[4]_i_1__0 + (.I0(wr_en0), + .I1(\cnt_read_reg[4]_1 ), + .O(\cnt_read[4]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'h9AAAAAAAAAAAAAA6)) + \cnt_read[4]_i_2 + (.I0(cnt_read_reg[4]), + .I1(\cnt_read[4]_i_4_n_0 ), + .I2(cnt_read_reg[0]), + .I3(cnt_read_reg[1]), + .I4(cnt_read_reg[3]), + .I5(cnt_read_reg[2]), + .O(\cnt_read[4]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT3 #( + .INIT(8'h4F)) + \cnt_read[4]_i_3 + (.I0(\cnt_read_reg[2]_0 ), + .I1(si_rs_rready), + .I2(r_push_r), + .O(s_ready_i_reg)); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT3 #( + .INIT(8'h4F)) + \cnt_read[4]_i_4 + (.I0(\cnt_read_reg[2]_0 ), + .I1(si_rs_rready), + .I2(wr_en0), + .O(\cnt_read[4]_i_4_n_0 )); + FDSE #( + .INIT(1'b1)) + \cnt_read_reg[0] + (.C(aclk), + .CE(\cnt_read[4]_i_1__0_n_0 ), + .D(\cnt_read[0]_i_1_n_0 ), + .Q(cnt_read_reg[0]), + .S(areset_d1)); + FDSE #( + .INIT(1'b1)) + \cnt_read_reg[1] + (.C(aclk), + .CE(\cnt_read[4]_i_1__0_n_0 ), + .D(\cnt_read[1]_i_1__0_n_0 ), + .Q(cnt_read_reg[1]), + .S(areset_d1)); + FDSE #( + .INIT(1'b1)) + \cnt_read_reg[2] + (.C(aclk), + .CE(\cnt_read[4]_i_1__0_n_0 ), + .D(\cnt_read[2]_i_1_n_0 ), + .Q(cnt_read_reg[2]), + .S(areset_d1)); + FDSE #( + .INIT(1'b1)) + \cnt_read_reg[3] + (.C(aclk), + .CE(\cnt_read[4]_i_1__0_n_0 ), + .D(\cnt_read[3]_i_1_n_0 ), + .Q(cnt_read_reg[3]), + .S(areset_d1)); + FDSE #( + .INIT(1'b1)) + \cnt_read_reg[4] + (.C(aclk), + .CE(\cnt_read[4]_i_1__0_n_0 ), + .D(\cnt_read[4]_i_2_n_0 ), + .Q(cnt_read_reg[4]), + .S(areset_d1)); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT5 #( + .INIT(32'h91FFFFFF)) + m_axi_rready_INST_0 + (.I0(cnt_read_reg[2]), + .I1(cnt_read_reg[1]), + .I2(cnt_read_reg[0]), + .I3(cnt_read_reg[3]), + .I4(cnt_read_reg[4]), + .O(m_axi_rready)); + LUT6 #( + .INIT(64'hFFFFFFFF80000000)) + m_valid_i_i_2 + (.I0(cnt_read_reg[2]), + .I1(cnt_read_reg[1]), + .I2(cnt_read_reg[0]), + .I3(cnt_read_reg[4]), + .I4(cnt_read_reg[3]), + .I5(m_valid_i_reg), + .O(\cnt_read_reg[2]_0 )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][0]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[0]), + .Q(out[0]), + .Q31(\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED )); + LUT6 #( + .INIT(64'h8202AAAAAAAAAAAA)) + \memory_reg[31][0]_srl32_i_1 + (.I0(m_axi_rvalid), + .I1(cnt_read_reg[2]), + .I2(cnt_read_reg[1]), + .I3(cnt_read_reg[0]), + .I4(cnt_read_reg[3]), + .I5(cnt_read_reg[4]), + .O(wr_en0)); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][10]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[10]), + .Q(out[10]), + .Q31(\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][11]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[11]), + .Q(out[11]), + .Q31(\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][12]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[12]), + .Q(out[12]), + .Q31(\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][13]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[13]), + .Q(out[13]), + .Q31(\NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][14]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[14]), + .Q(out[14]), + .Q31(\NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][15]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[15]), + .Q(out[15]), + .Q31(\NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][16]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[16]), + .Q(out[16]), + .Q31(\NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][17]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[17]), + .Q(out[17]), + .Q31(\NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][18]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[18]), + .Q(out[18]), + .Q31(\NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][19]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[19]), + .Q(out[19]), + .Q31(\NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][1]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[1]), + .Q(out[1]), + .Q31(\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][20]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[20]), + .Q(out[20]), + .Q31(\NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][21]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[21]), + .Q(out[21]), + .Q31(\NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][22]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[22]), + .Q(out[22]), + .Q31(\NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][23]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[23]), + .Q(out[23]), + .Q31(\NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][24]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[24]), + .Q(out[24]), + .Q31(\NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][25]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[25]), + .Q(out[25]), + .Q31(\NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][26]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[26]), + .Q(out[26]), + .Q31(\NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][27]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[27]), + .Q(out[27]), + .Q31(\NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][28]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[28]), + .Q(out[28]), + .Q31(\NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][29]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[29]), + .Q(out[29]), + .Q31(\NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][2]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[2]), + .Q(out[2]), + .Q31(\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][30]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[30]), + .Q(out[30]), + .Q31(\NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][31]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[31]), + .Q(out[31]), + .Q31(\NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][32]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[32]), + .Q(out[32]), + .Q31(\NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][33]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[33]), + .Q(out[33]), + .Q31(\NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][3]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[3]), + .Q(out[3]), + .Q31(\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][4]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[4]), + .Q(out[4]), + .Q31(\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][5]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[5]), + .Q(out[5]), + .Q31(\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][6]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[6]), + .Q(out[6]), + .Q31(\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][7]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[7]), + .Q(out[7]), + .Q31(\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][8]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[8]), + .Q(out[8]), + .Q31(\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][9]_srl32 + (.A(cnt_read_reg), + .CE(wr_en0), + .CLK(aclk), + .D(in[9]), + .Q(out[9]), + .Q31(\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED )); +endmodule + +(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_29_b2s_simple_fifo" *) +module NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized2 + (\cnt_read_reg[4]_0 , + \cnt_read_reg[4]_1 , + r_push_r_reg, + r_push_r, + \cnt_read_reg[4]_2 , + \cnt_read_reg[4]_3 , + \FSM_sequential_state_reg[0] , + in, + aclk, + areset_d1); + output \cnt_read_reg[4]_0 ; + output \cnt_read_reg[4]_1 ; + output [12:0]r_push_r_reg; + input r_push_r; + input \cnt_read_reg[4]_2 ; + input \cnt_read_reg[4]_3 ; + input \FSM_sequential_state_reg[0] ; + input [12:0]in; + input aclk; + input areset_d1; + + wire \FSM_sequential_state_reg[0] ; + wire aclk; + wire areset_d1; + wire \cnt_read[0]_i_1__0_n_0 ; + wire \cnt_read[1]_i_1_n_0 ; + wire \cnt_read[2]_i_1__0_n_0 ; + wire \cnt_read[3]_i_1__0_n_0 ; + wire \cnt_read[4]_i_1_n_0 ; + wire \cnt_read[4]_i_2__0_n_0 ; + wire [4:0]cnt_read_reg; + wire \cnt_read_reg[4]_0 ; + wire \cnt_read_reg[4]_1 ; + wire \cnt_read_reg[4]_2 ; + wire \cnt_read_reg[4]_3 ; + wire [12:0]in; + wire r_push_r; + wire [12:0]r_push_r_reg; + wire \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ; + wire \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ; + + LUT6 #( + .INIT(64'hAAEAEAAAEAEAEAAA)) + \FSM_sequential_state[1]_i_2__0 + (.I0(\FSM_sequential_state_reg[0] ), + .I1(cnt_read_reg[4]), + .I2(cnt_read_reg[3]), + .I3(cnt_read_reg[2]), + .I4(cnt_read_reg[1]), + .I5(cnt_read_reg[0]), + .O(\cnt_read_reg[4]_0 )); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT1 #( + .INIT(2'h1)) + \cnt_read[0]_i_1__0 + (.I0(cnt_read_reg[0]), + .O(\cnt_read[0]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT4 #( + .INIT(16'hD22D)) + \cnt_read[1]_i_1 + (.I0(r_push_r), + .I1(\cnt_read_reg[4]_2 ), + .I2(cnt_read_reg[0]), + .I3(cnt_read_reg[1]), + .O(\cnt_read[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT5 #( + .INIT(32'hA6AAAA59)) + \cnt_read[2]_i_1__0 + (.I0(cnt_read_reg[2]), + .I1(r_push_r), + .I2(\cnt_read_reg[4]_2 ), + .I3(cnt_read_reg[0]), + .I4(cnt_read_reg[1]), + .O(\cnt_read[2]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hF7FFEFEE08001011)) + \cnt_read[3]_i_1__0 + (.I0(cnt_read_reg[1]), + .I1(cnt_read_reg[0]), + .I2(\cnt_read_reg[4]_2 ), + .I3(r_push_r), + .I4(cnt_read_reg[2]), + .I5(cnt_read_reg[3]), + .O(\cnt_read[3]_i_1__0_n_0 )); + LUT2 #( + .INIT(4'h6)) + \cnt_read[4]_i_1 + (.I0(r_push_r), + .I1(\cnt_read_reg[4]_2 ), + .O(\cnt_read[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAA6AAAAAAAAAA9AA)) + \cnt_read[4]_i_2__0 + (.I0(cnt_read_reg[4]), + .I1(cnt_read_reg[2]), + .I2(cnt_read_reg[3]), + .I3(\cnt_read_reg[4]_3 ), + .I4(cnt_read_reg[1]), + .I5(cnt_read_reg[0]), + .O(\cnt_read[4]_i_2__0_n_0 )); + FDSE #( + .INIT(1'b1)) + \cnt_read_reg[0] + (.C(aclk), + .CE(\cnt_read[4]_i_1_n_0 ), + .D(\cnt_read[0]_i_1__0_n_0 ), + .Q(cnt_read_reg[0]), + .S(areset_d1)); + FDSE #( + .INIT(1'b1)) + \cnt_read_reg[1] + (.C(aclk), + .CE(\cnt_read[4]_i_1_n_0 ), + .D(\cnt_read[1]_i_1_n_0 ), + .Q(cnt_read_reg[1]), + .S(areset_d1)); + FDSE #( + .INIT(1'b1)) + \cnt_read_reg[2] + (.C(aclk), + .CE(\cnt_read[4]_i_1_n_0 ), + .D(\cnt_read[2]_i_1__0_n_0 ), + .Q(cnt_read_reg[2]), + .S(areset_d1)); + FDSE #( + .INIT(1'b1)) + \cnt_read_reg[3] + (.C(aclk), + .CE(\cnt_read[4]_i_1_n_0 ), + .D(\cnt_read[3]_i_1__0_n_0 ), + .Q(cnt_read_reg[3]), + .S(areset_d1)); + FDSE #( + .INIT(1'b1)) + \cnt_read_reg[4] + (.C(aclk), + .CE(\cnt_read[4]_i_1_n_0 ), + .D(\cnt_read[4]_i_2__0_n_0 ), + .Q(cnt_read_reg[4]), + .S(areset_d1)); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT5 #( + .INIT(32'h80000000)) + m_valid_i_i_3 + (.I0(cnt_read_reg[4]), + .I1(cnt_read_reg[3]), + .I2(cnt_read_reg[2]), + .I3(cnt_read_reg[1]), + .I4(cnt_read_reg[0]), + .O(\cnt_read_reg[4]_1 )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][0]_srl32 + (.A(cnt_read_reg), + .CE(r_push_r), + .CLK(aclk), + .D(in[0]), + .Q(r_push_r_reg[0]), + .Q31(\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][10]_srl32 + (.A(cnt_read_reg), + .CE(r_push_r), + .CLK(aclk), + .D(in[10]), + .Q(r_push_r_reg[10]), + .Q31(\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][11]_srl32 + (.A(cnt_read_reg), + .CE(r_push_r), + .CLK(aclk), + .D(in[11]), + .Q(r_push_r_reg[11]), + .Q31(\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][12]_srl32 + (.A(cnt_read_reg), + .CE(r_push_r), + .CLK(aclk), + .D(in[12]), + .Q(r_push_r_reg[12]), + .Q31(\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][1]_srl32 + (.A(cnt_read_reg), + .CE(r_push_r), + .CLK(aclk), + .D(in[1]), + .Q(r_push_r_reg[1]), + .Q31(\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][2]_srl32 + (.A(cnt_read_reg), + .CE(r_push_r), + .CLK(aclk), + .D(in[2]), + .Q(r_push_r_reg[2]), + .Q31(\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][3]_srl32 + (.A(cnt_read_reg), + .CE(r_push_r), + .CLK(aclk), + .D(in[3]), + .Q(r_push_r_reg[3]), + .Q31(\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][4]_srl32 + (.A(cnt_read_reg), + .CE(r_push_r), + .CLK(aclk), + .D(in[4]), + .Q(r_push_r_reg[4]), + .Q31(\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][5]_srl32 + (.A(cnt_read_reg), + .CE(r_push_r), + .CLK(aclk), + .D(in[5]), + .Q(r_push_r_reg[5]), + .Q31(\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][6]_srl32 + (.A(cnt_read_reg), + .CE(r_push_r), + .CLK(aclk), + .D(in[6]), + .Q(r_push_r_reg[6]), + .Q31(\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][7]_srl32 + (.A(cnt_read_reg), + .CE(r_push_r), + .CLK(aclk), + .D(in[7]), + .Q(r_push_r_reg[7]), + .Q31(\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][8]_srl32 + (.A(cnt_read_reg), + .CE(r_push_r), + .CLK(aclk), + .D(in[8]), + .Q(r_push_r_reg[8]), + .Q31(\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED )); + (* srl_bus_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *) + (* srl_name = "inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \memory_reg[31][9]_srl32 + (.A(cnt_read_reg), + .CE(r_push_r), + .CLK(aclk), + .D(in[9]), + .Q(r_push_r_reg[9]), + .Q31(\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED )); +endmodule + +module NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm + (D, + axaddr_offset, + Q, + \FSM_sequential_state_reg[0]_0 , + \FSM_sequential_state_reg[0]_1 , + \FSM_sequential_state_reg[0]_2 , + E, + m_axi_awready_0, + \wrap_second_len_r_reg[3] , + \axlen_cnt_reg[2] , + next, + \axlen_cnt_reg[2]_0 , + m_valid_i_reg, + sel_first_reg, + sel_first_reg_0, + sel_first_i, + \wrap_boundary_axaddr_r_reg[11] , + m_axi_awvalid, + si_rs_awvalid, + \wrap_second_len_r_reg[3]_0 , + s_axburst_eq0_reg, + \wrap_second_len_r_reg[3]_1 , + \axaddr_offset_r_reg[3] , + \axaddr_offset_r_reg[3]_0 , + \axaddr_offset_r_reg[0] , + \axaddr_offset_r_reg[2] , + \axaddr_offset_r_reg[2]_0 , + s_axburst_eq0_reg_0, + \FSM_sequential_state_reg[1]_0 , + m_axi_awready, + s_axburst_eq1_reg, + next_pending_r, + next_pending_r_0, + sel_first, + areset_d1, + sel_first_reg_1, + sel_first_reg_2, + \axaddr_offset_r_reg[3]_1 , + \axaddr_offset_r_reg[1] , + \axaddr_offset_r_reg[1]_0 , + \axaddr_wrap_reg[11] , + axaddr_wrap0, + \axaddr_wrap_reg[10] , + cnt_read, + aclk); + output [3:0]D; + output [3:0]axaddr_offset; + output [1:0]Q; + output \FSM_sequential_state_reg[0]_0 ; + output \FSM_sequential_state_reg[0]_1 ; + output \FSM_sequential_state_reg[0]_2 ; + output [0:0]E; + output m_axi_awready_0; + output [3:0]\wrap_second_len_r_reg[3] ; + output \axlen_cnt_reg[2] ; + output next; + output \axlen_cnt_reg[2]_0 ; + output [0:0]m_valid_i_reg; + output sel_first_reg; + output sel_first_reg_0; + output sel_first_i; + output [11:0]\wrap_boundary_axaddr_r_reg[11] ; + output m_axi_awvalid; + input si_rs_awvalid; + input [3:0]\wrap_second_len_r_reg[3]_0 ; + input s_axburst_eq0_reg; + input \wrap_second_len_r_reg[3]_1 ; + input [3:0]\axaddr_offset_r_reg[3] ; + input [14:0]\axaddr_offset_r_reg[3]_0 ; + input \axaddr_offset_r_reg[0] ; + input \axaddr_offset_r_reg[2] ; + input \axaddr_offset_r_reg[2]_0 ; + input s_axburst_eq0_reg_0; + input \FSM_sequential_state_reg[1]_0 ; + input m_axi_awready; + input s_axburst_eq1_reg; + input next_pending_r; + input next_pending_r_0; + input sel_first; + input areset_d1; + input sel_first_reg_1; + input sel_first_reg_2; + input \axaddr_offset_r_reg[3]_1 ; + input \axaddr_offset_r_reg[1] ; + input \axaddr_offset_r_reg[1]_0 ; + input [11:0]\axaddr_wrap_reg[11] ; + input [11:0]axaddr_wrap0; + input \axaddr_wrap_reg[10] ; + input [1:0]cnt_read; + input aclk; + + wire [3:0]D; + wire [0:0]E; + wire \FSM_sequential_state_reg[0]_0 ; + wire \FSM_sequential_state_reg[0]_1 ; + wire \FSM_sequential_state_reg[0]_2 ; + wire \FSM_sequential_state_reg[1]_0 ; + wire [1:0]Q; + wire aclk; + wire areset_d1; + wire [3:0]axaddr_offset; + wire \axaddr_offset_r_reg[0] ; + wire \axaddr_offset_r_reg[1] ; + wire \axaddr_offset_r_reg[1]_0 ; + wire \axaddr_offset_r_reg[2] ; + wire \axaddr_offset_r_reg[2]_0 ; + wire [3:0]\axaddr_offset_r_reg[3] ; + wire [14:0]\axaddr_offset_r_reg[3]_0 ; + wire \axaddr_offset_r_reg[3]_1 ; + wire [11:0]axaddr_wrap0; + wire \axaddr_wrap[11]_i_2_n_0 ; + wire \axaddr_wrap[11]_i_4_n_0 ; + wire \axaddr_wrap_reg[10] ; + wire [11:0]\axaddr_wrap_reg[11] ; + wire \axlen_cnt_reg[2] ; + wire \axlen_cnt_reg[2]_0 ; + wire [1:0]cnt_read; + wire m_axi_awready; + wire m_axi_awready_0; + wire m_axi_awvalid; + wire [0:0]m_valid_i_reg; + wire next; + wire next_pending_r; + wire next_pending_r_0; + wire [1:0]next_state__0; + wire s_axburst_eq0_i_2_n_0; + wire s_axburst_eq0_i_3_n_0; + wire s_axburst_eq0_i_4_n_0; + wire s_axburst_eq0_i_5_n_0; + wire s_axburst_eq0_reg; + wire s_axburst_eq0_reg_0; + wire s_axburst_eq1_i_2_n_0; + wire s_axburst_eq1_reg; + wire sel_first; + wire sel_first_i; + wire sel_first_reg; + wire sel_first_reg_0; + wire sel_first_reg_1; + wire sel_first_reg_2; + wire si_rs_awvalid; + wire [11:0]\wrap_boundary_axaddr_r_reg[11] ; + wire \wrap_cnt_r[2]_i_2_n_0 ; + wire \wrap_cnt_r[3]_i_2_n_0 ; + wire [3:0]\wrap_second_len_r_reg[3] ; + wire [3:0]\wrap_second_len_r_reg[3]_0 ; + wire \wrap_second_len_r_reg[3]_1 ; + + LUT6 #( + .INIT(64'h7737FFFFFFFFFF0F)) + \FSM_sequential_state[0]_i_1 + (.I0(\FSM_sequential_state_reg[1]_0 ), + .I1(m_axi_awready), + .I2(cnt_read[1]), + .I3(cnt_read[0]), + .I4(Q[1]), + .I5(Q[0]), + .O(next_state__0[0])); + (* SOFT_HLUTNM = "soft_lutpair108" *) + LUT5 #( + .INIT(32'hACF0FCF0)) + \FSM_sequential_state[1]_i_1 + (.I0(\FSM_sequential_state_reg[1]_0 ), + .I1(si_rs_awvalid), + .I2(Q[1]), + .I3(Q[0]), + .I4(m_axi_awready), + .O(next_state__0[1])); + (* FSM_ENCODED_STATES = "SM_CMD_ACCEPTED:10,SM_CMD_EN:11,SM_IDLE:01,SM_DONE_WAIT:00" *) + FDSE #( + .INIT(1'b1)) + \FSM_sequential_state_reg[0] + (.C(aclk), + .CE(1'b1), + .D(next_state__0[0]), + .Q(Q[0]), + .S(areset_d1)); + (* FSM_ENCODED_STATES = "SM_CMD_ACCEPTED:10,SM_CMD_EN:11,SM_IDLE:01,SM_DONE_WAIT:00" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_state_reg[1] + (.C(aclk), + .CE(1'b1), + .D(next_state__0[1]), + .Q(Q[1]), + .R(areset_d1)); + LUT6 #( + .INIT(64'hAEAAA2AAA2AAA2AA)) + \axaddr_offset_r[0]_i_1 + (.I0(\axaddr_offset_r_reg[3] [0]), + .I1(si_rs_awvalid), + .I2(Q[1]), + .I3(Q[0]), + .I4(\axaddr_offset_r_reg[3]_0 [13]), + .I5(\axaddr_offset_r_reg[0] ), + .O(axaddr_offset[0])); + LUT6 #( + .INIT(64'hAEAAAEAAAEAAA2AA)) + \axaddr_offset_r[1]_i_1 + (.I0(\axaddr_offset_r_reg[3] [1]), + .I1(Q[0]), + .I2(Q[1]), + .I3(si_rs_awvalid), + .I4(\axaddr_offset_r_reg[1] ), + .I5(\axaddr_offset_r_reg[1]_0 ), + .O(axaddr_offset[1])); + LUT6 #( + .INIT(64'hAEAAA2AAAEAAAEAA)) + \axaddr_offset_r[2]_i_1 + (.I0(\axaddr_offset_r_reg[3] [2]), + .I1(Q[0]), + .I2(Q[1]), + .I3(si_rs_awvalid), + .I4(\axaddr_offset_r_reg[2] ), + .I5(\axaddr_offset_r_reg[2]_0 ), + .O(axaddr_offset[2])); + LUT6 #( + .INIT(64'hAAAA30AAAAAAAAAA)) + \axaddr_offset_r[3]_i_1 + (.I0(\axaddr_offset_r_reg[3] [3]), + .I1(\axaddr_offset_r_reg[3]_1 ), + .I2(\axaddr_offset_r_reg[3]_0 [14]), + .I3(si_rs_awvalid), + .I4(Q[1]), + .I5(Q[0]), + .O(axaddr_offset[3])); + LUT6 #( + .INIT(64'h44F444F4FFFF44F4)) + \axaddr_wrap[0]_i_1 + (.I0(\axaddr_wrap[11]_i_2_n_0 ), + .I1(\axaddr_wrap_reg[11] [0]), + .I2(axaddr_wrap0[0]), + .I3(\axaddr_wrap[11]_i_4_n_0 ), + .I4(\axaddr_offset_r_reg[3]_0 [0]), + .I5(next), + .O(\wrap_boundary_axaddr_r_reg[11] [0])); + LUT6 #( + .INIT(64'h44F444F4FFFF44F4)) + \axaddr_wrap[10]_i_1 + (.I0(\axaddr_wrap[11]_i_4_n_0 ), + .I1(axaddr_wrap0[10]), + .I2(\axaddr_offset_r_reg[3]_0 [10]), + .I3(next), + .I4(\axaddr_wrap_reg[11] [10]), + .I5(\axaddr_wrap[11]_i_2_n_0 ), + .O(\wrap_boundary_axaddr_r_reg[11] [10])); + LUT6 #( + .INIT(64'h44F444F4FFFF44F4)) + \axaddr_wrap[11]_i_1 + (.I0(\axaddr_wrap[11]_i_2_n_0 ), + .I1(\axaddr_wrap_reg[11] [11]), + .I2(\axaddr_offset_r_reg[3]_0 [11]), + .I3(next), + .I4(axaddr_wrap0[11]), + .I5(\axaddr_wrap[11]_i_4_n_0 ), + .O(\wrap_boundary_axaddr_r_reg[11] [11])); + (* SOFT_HLUTNM = "soft_lutpair110" *) + LUT4 #( + .INIT(16'h51FF)) + \axaddr_wrap[11]_i_2 + (.I0(m_axi_awready_0), + .I1(Q[1]), + .I2(Q[0]), + .I3(\axaddr_wrap_reg[10] ), + .O(\axaddr_wrap[11]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair110" *) + LUT4 #( + .INIT(16'hBBAB)) + \axaddr_wrap[11]_i_4 + (.I0(\axaddr_wrap_reg[10] ), + .I1(m_axi_awready_0), + .I2(Q[1]), + .I3(Q[0]), + .O(\axaddr_wrap[11]_i_4_n_0 )); + LUT6 #( + .INIT(64'h44F444F4FFFF44F4)) + \axaddr_wrap[1]_i_1 + (.I0(\axaddr_wrap[11]_i_4_n_0 ), + .I1(axaddr_wrap0[1]), + .I2(\axaddr_wrap_reg[11] [1]), + .I3(\axaddr_wrap[11]_i_2_n_0 ), + .I4(\axaddr_offset_r_reg[3]_0 [1]), + .I5(next), + .O(\wrap_boundary_axaddr_r_reg[11] [1])); + LUT6 #( + .INIT(64'h44F444F4FFFF44F4)) + \axaddr_wrap[2]_i_1 + (.I0(\axaddr_wrap[11]_i_4_n_0 ), + .I1(axaddr_wrap0[2]), + .I2(\axaddr_wrap_reg[11] [2]), + .I3(\axaddr_wrap[11]_i_2_n_0 ), + .I4(\axaddr_offset_r_reg[3]_0 [2]), + .I5(next), + .O(\wrap_boundary_axaddr_r_reg[11] [2])); + LUT6 #( + .INIT(64'h44F444F4FFFF44F4)) + \axaddr_wrap[3]_i_1 + (.I0(\axaddr_wrap[11]_i_2_n_0 ), + .I1(\axaddr_wrap_reg[11] [3]), + .I2(axaddr_wrap0[3]), + .I3(\axaddr_wrap[11]_i_4_n_0 ), + .I4(\axaddr_offset_r_reg[3]_0 [3]), + .I5(next), + .O(\wrap_boundary_axaddr_r_reg[11] [3])); + LUT6 #( + .INIT(64'h44F444F4FFFF44F4)) + \axaddr_wrap[4]_i_1 + (.I0(\axaddr_wrap[11]_i_2_n_0 ), + .I1(\axaddr_wrap_reg[11] [4]), + .I2(axaddr_wrap0[4]), + .I3(\axaddr_wrap[11]_i_4_n_0 ), + .I4(\axaddr_offset_r_reg[3]_0 [4]), + .I5(next), + .O(\wrap_boundary_axaddr_r_reg[11] [4])); + LUT6 #( + .INIT(64'h44F444F4FFFF44F4)) + \axaddr_wrap[5]_i_1 + (.I0(\axaddr_wrap[11]_i_2_n_0 ), + .I1(\axaddr_wrap_reg[11] [5]), + .I2(axaddr_wrap0[5]), + .I3(\axaddr_wrap[11]_i_4_n_0 ), + .I4(\axaddr_offset_r_reg[3]_0 [5]), + .I5(next), + .O(\wrap_boundary_axaddr_r_reg[11] [5])); + LUT6 #( + .INIT(64'h44F444F4FFFF44F4)) + \axaddr_wrap[6]_i_1 + (.I0(\axaddr_wrap[11]_i_2_n_0 ), + .I1(\axaddr_wrap_reg[11] [6]), + .I2(axaddr_wrap0[6]), + .I3(\axaddr_wrap[11]_i_4_n_0 ), + .I4(\axaddr_offset_r_reg[3]_0 [6]), + .I5(next), + .O(\wrap_boundary_axaddr_r_reg[11] [6])); + LUT6 #( + .INIT(64'h44F444F4FFFF44F4)) + \axaddr_wrap[7]_i_1 + (.I0(\axaddr_wrap[11]_i_4_n_0 ), + .I1(axaddr_wrap0[7]), + .I2(\axaddr_wrap_reg[11] [7]), + .I3(\axaddr_wrap[11]_i_2_n_0 ), + .I4(\axaddr_offset_r_reg[3]_0 [7]), + .I5(next), + .O(\wrap_boundary_axaddr_r_reg[11] [7])); + LUT6 #( + .INIT(64'h44F444F4FFFF44F4)) + \axaddr_wrap[8]_i_1 + (.I0(\axaddr_wrap[11]_i_2_n_0 ), + .I1(\axaddr_wrap_reg[11] [8]), + .I2(axaddr_wrap0[8]), + .I3(\axaddr_wrap[11]_i_4_n_0 ), + .I4(\axaddr_offset_r_reg[3]_0 [8]), + .I5(next), + .O(\wrap_boundary_axaddr_r_reg[11] [8])); + LUT6 #( + .INIT(64'h44F444F4FFFF44F4)) + \axaddr_wrap[9]_i_1 + (.I0(\axaddr_wrap[11]_i_4_n_0 ), + .I1(axaddr_wrap0[9]), + .I2(\axaddr_wrap_reg[11] [9]), + .I3(\axaddr_wrap[11]_i_2_n_0 ), + .I4(\axaddr_offset_r_reg[3]_0 [9]), + .I5(next), + .O(\wrap_boundary_axaddr_r_reg[11] [9])); + (* SOFT_HLUTNM = "soft_lutpair109" *) + LUT4 #( + .INIT(16'hFF64)) + \axlen_cnt[3]_i_1__0 + (.I0(Q[0]), + .I1(Q[1]), + .I2(si_rs_awvalid), + .I3(m_axi_awready_0), + .O(\FSM_sequential_state_reg[0]_1 )); + (* SOFT_HLUTNM = "soft_lutpair108" *) + LUT3 #( + .INIT(8'hDF)) + \axlen_cnt[3]_i_3__0 + (.I0(Q[0]), + .I1(Q[1]), + .I2(si_rs_awvalid), + .O(\FSM_sequential_state_reg[0]_2 )); + LUT2 #( + .INIT(4'h2)) + \axlen_cnt[5]_i_1 + (.I0(\FSM_sequential_state_reg[0]_1 ), + .I1(s_axburst_eq0_reg), + .O(\FSM_sequential_state_reg[0]_0 )); + LUT2 #( + .INIT(4'h8)) + m_axi_awvalid_INST_0 + (.I0(Q[1]), + .I1(Q[0]), + .O(m_axi_awvalid)); + LUT2 #( + .INIT(4'hB)) + \m_payload_i[31]_i_1__1 + (.I0(m_axi_awready_0), + .I1(si_rs_awvalid), + .O(E)); + LUT6 #( + .INIT(64'h0383038300000383)) + \memory_reg[3][0]_srl4_i_1 + (.I0(m_axi_awready), + .I1(Q[0]), + .I2(Q[1]), + .I3(\FSM_sequential_state_reg[1]_0 ), + .I4(cnt_read[1]), + .I5(cnt_read[0]), + .O(m_axi_awready_0)); + (* SOFT_HLUTNM = "soft_lutpair111" *) + LUT3 #( + .INIT(8'hF4)) + next_pending_r_i_3 + (.I0(Q[0]), + .I1(Q[1]), + .I2(m_axi_awready_0), + .O(next)); + LUT6 #( + .INIT(64'hEFEFCFCFEFE0C0C0)) + s_axburst_eq0_i_1 + (.I0(s_axburst_eq0_reg_0), + .I1(s_axburst_eq0_i_2_n_0), + .I2(s_axburst_eq0_i_3_n_0), + .I3(s_axburst_eq0_reg), + .I4(next), + .I5(s_axburst_eq0_i_4_n_0), + .O(\axlen_cnt_reg[2] )); + LUT6 #( + .INIT(64'hAAAAEBEFAAAAAAAA)) + s_axburst_eq0_i_2 + (.I0(s_axburst_eq1_reg), + .I1(Q[0]), + .I2(Q[1]), + .I3(si_rs_awvalid), + .I4(m_axi_awready_0), + .I5(next_pending_r_0), + .O(s_axburst_eq0_i_2_n_0)); + LUT6 #( + .INIT(64'h00000000A2A2AAA2)) + s_axburst_eq0_i_3 + (.I0(\axaddr_offset_r_reg[3]_0 [12]), + .I1(sel_first_reg_2), + .I2(m_axi_awready_0), + .I3(Q[1]), + .I4(Q[0]), + .I5(s_axburst_eq0_i_5_n_0), + .O(s_axburst_eq0_i_3_n_0)); + LUT6 #( + .INIT(64'hAAAAEBEFAAAAAAAA)) + s_axburst_eq0_i_4 + (.I0(s_axburst_eq1_reg), + .I1(Q[0]), + .I2(Q[1]), + .I3(si_rs_awvalid), + .I4(m_axi_awready_0), + .I5(next_pending_r), + .O(s_axburst_eq0_i_4_n_0)); + (* SOFT_HLUTNM = "soft_lutpair111" *) + LUT4 #( + .INIT(16'hAEAA)) + s_axburst_eq0_i_5 + (.I0(areset_d1), + .I1(si_rs_awvalid), + .I2(Q[1]), + .I3(Q[0]), + .O(s_axburst_eq0_i_5_n_0)); + LUT6 #( + .INIT(64'hEFEFCFCFEFE0C0C0)) + s_axburst_eq1_i_1 + (.I0(s_axburst_eq0_reg_0), + .I1(s_axburst_eq0_i_2_n_0), + .I2(s_axburst_eq1_i_2_n_0), + .I3(s_axburst_eq0_reg), + .I4(next), + .I5(s_axburst_eq0_i_4_n_0), + .O(\axlen_cnt_reg[2]_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFAEAEAAAE)) + s_axburst_eq1_i_2 + (.I0(\axaddr_offset_r_reg[3]_0 [12]), + .I1(sel_first_reg_2), + .I2(m_axi_awready_0), + .I3(Q[1]), + .I4(Q[0]), + .I5(s_axburst_eq0_i_5_n_0), + .O(s_axburst_eq1_i_2_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFF44F44444)) + sel_first_i_1 + (.I0(next), + .I1(sel_first), + .I2(Q[0]), + .I3(Q[1]), + .I4(si_rs_awvalid), + .I5(areset_d1), + .O(sel_first_reg)); + LUT6 #( + .INIT(64'hFFFFFFFF44F44444)) + sel_first_i_1__0 + (.I0(next), + .I1(sel_first_reg_1), + .I2(Q[0]), + .I3(Q[1]), + .I4(si_rs_awvalid), + .I5(areset_d1), + .O(sel_first_reg_0)); + LUT6 #( + .INIT(64'hCCECFCFFCCECCCEC)) + sel_first_i_1__1 + (.I0(si_rs_awvalid), + .I1(areset_d1), + .I2(Q[0]), + .I3(Q[1]), + .I4(m_axi_awready_0), + .I5(sel_first_reg_2), + .O(sel_first_i)); + (* SOFT_HLUTNM = "soft_lutpair109" *) + LUT3 #( + .INIT(8'h20)) + \wrap_boundary_axaddr_r[11]_i_1 + (.I0(si_rs_awvalid), + .I1(Q[1]), + .I2(Q[0]), + .O(m_valid_i_reg)); + LUT6 #( + .INIT(64'h33833333CC8CCCCC)) + \wrap_cnt_r[0]_i_1 + (.I0(axaddr_offset[0]), + .I1(\wrap_cnt_r[2]_i_2_n_0 ), + .I2(Q[0]), + .I3(Q[1]), + .I4(si_rs_awvalid), + .I5(\wrap_second_len_r_reg[3]_0 [0]), + .O(D[0])); + LUT5 #( + .INIT(32'h3CCCA0A0)) + \wrap_cnt_r[1]_i_1 + (.I0(axaddr_offset[1]), + .I1(\wrap_second_len_r_reg[3]_0 [1]), + .I2(\wrap_cnt_r[2]_i_2_n_0 ), + .I3(\wrap_second_len_r_reg[3]_0 [0]), + .I4(\FSM_sequential_state_reg[0]_2 ), + .O(D[1])); + LUT6 #( + .INIT(64'h59A9AAAAAAAAAAAA)) + \wrap_cnt_r[2]_i_1 + (.I0(\wrap_second_len_r_reg[3] [2]), + .I1(axaddr_offset[0]), + .I2(\FSM_sequential_state_reg[0]_2 ), + .I3(\wrap_second_len_r_reg[3]_0 [0]), + .I4(\wrap_cnt_r[2]_i_2_n_0 ), + .I5(\wrap_second_len_r_reg[3] [1]), + .O(D[2])); + LUT4 #( + .INIT(16'hFFFE)) + \wrap_cnt_r[2]_i_2 + (.I0(axaddr_offset[1]), + .I1(axaddr_offset[2]), + .I2(axaddr_offset[0]), + .I3(axaddr_offset[3]), + .O(\wrap_cnt_r[2]_i_2_n_0 )); + LUT4 #( + .INIT(16'hA6AA)) + \wrap_cnt_r[3]_i_1 + (.I0(\wrap_second_len_r_reg[3] [3]), + .I1(\wrap_second_len_r_reg[3] [1]), + .I2(\wrap_cnt_r[3]_i_2_n_0 ), + .I3(\wrap_second_len_r_reg[3] [2]), + .O(D[3])); + LUT6 #( + .INIT(64'h772277227722772F)) + \wrap_cnt_r[3]_i_2 + (.I0(\FSM_sequential_state_reg[0]_2 ), + .I1(\wrap_second_len_r_reg[3]_0 [0]), + .I2(axaddr_offset[3]), + .I3(axaddr_offset[0]), + .I4(axaddr_offset[2]), + .I5(axaddr_offset[1]), + .O(\wrap_cnt_r[3]_i_2_n_0 )); + LUT6 #( + .INIT(64'h88BB88BB88BB88B8)) + \wrap_second_len_r[0]_i_1 + (.I0(\wrap_second_len_r_reg[3]_0 [0]), + .I1(\FSM_sequential_state_reg[0]_2 ), + .I2(axaddr_offset[3]), + .I3(axaddr_offset[0]), + .I4(axaddr_offset[2]), + .I5(axaddr_offset[1]), + .O(\wrap_second_len_r_reg[3] [0])); + LUT6 #( + .INIT(64'hBB88BB8888BB88B8)) + \wrap_second_len_r[1]_i_1 + (.I0(\wrap_second_len_r_reg[3]_0 [1]), + .I1(\FSM_sequential_state_reg[0]_2 ), + .I2(axaddr_offset[3]), + .I3(axaddr_offset[0]), + .I4(axaddr_offset[2]), + .I5(axaddr_offset[1]), + .O(\wrap_second_len_r_reg[3] [1])); + LUT6 #( + .INIT(64'hBBBB8888BB8888B8)) + \wrap_second_len_r[2]_i_1 + (.I0(\wrap_second_len_r_reg[3]_0 [2]), + .I1(\FSM_sequential_state_reg[0]_2 ), + .I2(axaddr_offset[3]), + .I3(axaddr_offset[0]), + .I4(axaddr_offset[2]), + .I5(axaddr_offset[1]), + .O(\wrap_second_len_r_reg[3] [2])); + LUT6 #( + .INIT(64'hFFFFFFF888888888)) + \wrap_second_len_r[3]_i_1 + (.I0(\FSM_sequential_state_reg[0]_2 ), + .I1(\wrap_second_len_r_reg[3]_0 [3]), + .I2(axaddr_offset[0]), + .I3(axaddr_offset[1]), + .I4(axaddr_offset[2]), + .I5(\wrap_second_len_r_reg[3]_1 ), + .O(\wrap_second_len_r_reg[3] [3])); +endmodule + +module NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_wrap_cmd + (next_pending_r_0, + sel_first, + \axlen_cnt_reg[2]_0 , + axaddr_wrap0, + \axaddr_wrap_reg[11]_0 , + \axlen_cnt_reg[0]_0 , + \axaddr_offset_r_reg[3]_0 , + \wrap_second_len_r_reg[3]_0 , + \wrap_boundary_axaddr_r_reg[11]_0 , + aclk, + sel_first_reg_0, + \axlen_cnt_reg[3]_0 , + Q, + si_rs_awvalid, + \axaddr_wrap_reg[3]_0 , + \axlen_cnt_reg[3]_1 , + next, + \axaddr_wrap_reg[0]_0 , + next_pending_r_reg_0, + D, + \wrap_second_len_r_reg[3]_1 , + \wrap_cnt_r_reg[3]_0 , + E, + \wrap_boundary_axaddr_r_reg[6]_0 , + \axaddr_wrap_reg[11]_1 ); + output next_pending_r_0; + output sel_first; + output \axlen_cnt_reg[2]_0 ; + output [11:0]axaddr_wrap0; + output [11:0]\axaddr_wrap_reg[11]_0 ; + output \axlen_cnt_reg[0]_0 ; + output [3:0]\axaddr_offset_r_reg[3]_0 ; + output [3:0]\wrap_second_len_r_reg[3]_0 ; + output [11:0]\wrap_boundary_axaddr_r_reg[11]_0 ; + input aclk; + input sel_first_reg_0; + input [8:0]\axlen_cnt_reg[3]_0 ; + input [1:0]Q; + input si_rs_awvalid; + input [3:0]\axaddr_wrap_reg[3]_0 ; + input \axlen_cnt_reg[3]_1 ; + input next; + input \axaddr_wrap_reg[0]_0 ; + input next_pending_r_reg_0; + input [3:0]D; + input [3:0]\wrap_second_len_r_reg[3]_1 ; + input [3:0]\wrap_cnt_r_reg[3]_0 ; + input [0:0]E; + input [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ; + input [11:0]\axaddr_wrap_reg[11]_1 ; + + wire [3:0]D; + wire [0:0]E; + wire [1:0]Q; + wire aclk; + wire [3:0]\axaddr_offset_r_reg[3]_0 ; + wire [11:0]axaddr_wrap0; + wire \axaddr_wrap[11]_i_6_n_0 ; + wire \axaddr_wrap_reg[0]_0 ; + wire [11:0]\axaddr_wrap_reg[11]_0 ; + wire [11:0]\axaddr_wrap_reg[11]_1 ; + wire \axaddr_wrap_reg[11]_i_3_n_1 ; + wire \axaddr_wrap_reg[11]_i_3_n_2 ; + wire \axaddr_wrap_reg[11]_i_3_n_3 ; + wire [3:0]\axaddr_wrap_reg[3]_0 ; + wire \axaddr_wrap_reg[3]_i_2_n_0 ; + wire \axaddr_wrap_reg[3]_i_2_n_1 ; + wire \axaddr_wrap_reg[3]_i_2_n_2 ; + wire \axaddr_wrap_reg[3]_i_2_n_3 ; + wire \axaddr_wrap_reg[7]_i_2_n_0 ; + wire \axaddr_wrap_reg[7]_i_2_n_1 ; + wire \axaddr_wrap_reg[7]_i_2_n_2 ; + wire \axaddr_wrap_reg[7]_i_2_n_3 ; + wire \axlen_cnt[0]_i_1__0_n_0 ; + wire \axlen_cnt[1]_i_1__0_n_0 ; + wire \axlen_cnt[2]_i_1__0_n_0 ; + wire \axlen_cnt[3]_i_1_n_0 ; + wire \axlen_cnt[3]_i_2__2_n_0 ; + wire \axlen_cnt[4]_i_1_n_0 ; + wire \axlen_cnt_reg[0]_0 ; + wire \axlen_cnt_reg[2]_0 ; + wire [8:0]\axlen_cnt_reg[3]_0 ; + wire \axlen_cnt_reg[3]_1 ; + wire \axlen_cnt_reg_n_0_[0] ; + wire \axlen_cnt_reg_n_0_[1] ; + wire \axlen_cnt_reg_n_0_[2] ; + wire \axlen_cnt_reg_n_0_[3] ; + wire \axlen_cnt_reg_n_0_[4] ; + wire next; + wire next_pending_r_0; + wire next_pending_r_reg_0; + wire sel_first; + wire sel_first_reg_0; + wire si_rs_awvalid; + wire [11:0]\wrap_boundary_axaddr_r_reg[11]_0 ; + wire [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ; + wire [3:0]wrap_cnt_r; + wire [3:0]\wrap_cnt_r_reg[3]_0 ; + wire wrap_next_pending; + wire [3:0]\wrap_second_len_r_reg[3]_0 ; + wire [3:0]\wrap_second_len_r_reg[3]_1 ; + wire [3:3]\NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED ; + + FDRE \axaddr_offset_r_reg[0] + (.C(aclk), + .CE(1'b1), + .D(D[0]), + .Q(\axaddr_offset_r_reg[3]_0 [0]), + .R(1'b0)); + FDRE \axaddr_offset_r_reg[1] + (.C(aclk), + .CE(1'b1), + .D(D[1]), + .Q(\axaddr_offset_r_reg[3]_0 [1]), + .R(1'b0)); + FDRE \axaddr_offset_r_reg[2] + (.C(aclk), + .CE(1'b1), + .D(D[2]), + .Q(\axaddr_offset_r_reg[3]_0 [2]), + .R(1'b0)); + FDRE \axaddr_offset_r_reg[3] + (.C(aclk), + .CE(1'b1), + .D(D[3]), + .Q(\axaddr_offset_r_reg[3]_0 [3]), + .R(1'b0)); + LUT4 #( + .INIT(16'h0009)) + \axaddr_wrap[11]_i_5 + (.I0(\axlen_cnt_reg_n_0_[0] ), + .I1(wrap_cnt_r[0]), + .I2(\axlen_cnt_reg_n_0_[4] ), + .I3(\axaddr_wrap[11]_i_6_n_0 ), + .O(\axlen_cnt_reg[0]_0 )); + LUT6 #( + .INIT(64'h6FF6FFFFFFFF6FF6)) + \axaddr_wrap[11]_i_6 + (.I0(wrap_cnt_r[1]), + .I1(\axlen_cnt_reg_n_0_[1] ), + .I2(\axlen_cnt_reg_n_0_[2] ), + .I3(wrap_cnt_r[2]), + .I4(\axlen_cnt_reg_n_0_[3] ), + .I5(wrap_cnt_r[3]), + .O(\axaddr_wrap[11]_i_6_n_0 )); + FDRE \axaddr_wrap_reg[0] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axaddr_wrap_reg[11]_1 [0]), + .Q(\axaddr_wrap_reg[11]_0 [0]), + .R(1'b0)); + FDRE \axaddr_wrap_reg[10] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axaddr_wrap_reg[11]_1 [10]), + .Q(\axaddr_wrap_reg[11]_0 [10]), + .R(1'b0)); + FDRE \axaddr_wrap_reg[11] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axaddr_wrap_reg[11]_1 [11]), + .Q(\axaddr_wrap_reg[11]_0 [11]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \axaddr_wrap_reg[11]_i_3 + (.CI(\axaddr_wrap_reg[7]_i_2_n_0 ), + .CO({\NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED [3],\axaddr_wrap_reg[11]_i_3_n_1 ,\axaddr_wrap_reg[11]_i_3_n_2 ,\axaddr_wrap_reg[11]_i_3_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(axaddr_wrap0[11:8]), + .S(\axaddr_wrap_reg[11]_0 [11:8])); + FDRE \axaddr_wrap_reg[1] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axaddr_wrap_reg[11]_1 [1]), + .Q(\axaddr_wrap_reg[11]_0 [1]), + .R(1'b0)); + FDRE \axaddr_wrap_reg[2] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axaddr_wrap_reg[11]_1 [2]), + .Q(\axaddr_wrap_reg[11]_0 [2]), + .R(1'b0)); + FDRE \axaddr_wrap_reg[3] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axaddr_wrap_reg[11]_1 [3]), + .Q(\axaddr_wrap_reg[11]_0 [3]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \axaddr_wrap_reg[3]_i_2 + (.CI(1'b0), + .CO({\axaddr_wrap_reg[3]_i_2_n_0 ,\axaddr_wrap_reg[3]_i_2_n_1 ,\axaddr_wrap_reg[3]_i_2_n_2 ,\axaddr_wrap_reg[3]_i_2_n_3 }), + .CYINIT(1'b0), + .DI(\axaddr_wrap_reg[11]_0 [3:0]), + .O(axaddr_wrap0[3:0]), + .S(\axaddr_wrap_reg[3]_0 )); + FDRE \axaddr_wrap_reg[4] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axaddr_wrap_reg[11]_1 [4]), + .Q(\axaddr_wrap_reg[11]_0 [4]), + .R(1'b0)); + FDRE \axaddr_wrap_reg[5] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axaddr_wrap_reg[11]_1 [5]), + .Q(\axaddr_wrap_reg[11]_0 [5]), + .R(1'b0)); + FDRE \axaddr_wrap_reg[6] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axaddr_wrap_reg[11]_1 [6]), + .Q(\axaddr_wrap_reg[11]_0 [6]), + .R(1'b0)); + FDRE \axaddr_wrap_reg[7] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axaddr_wrap_reg[11]_1 [7]), + .Q(\axaddr_wrap_reg[11]_0 [7]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \axaddr_wrap_reg[7]_i_2 + (.CI(\axaddr_wrap_reg[3]_i_2_n_0 ), + .CO({\axaddr_wrap_reg[7]_i_2_n_0 ,\axaddr_wrap_reg[7]_i_2_n_1 ,\axaddr_wrap_reg[7]_i_2_n_2 ,\axaddr_wrap_reg[7]_i_2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(axaddr_wrap0[7:4]), + .S(\axaddr_wrap_reg[11]_0 [7:4])); + FDRE \axaddr_wrap_reg[8] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axaddr_wrap_reg[11]_1 [8]), + .Q(\axaddr_wrap_reg[11]_0 [8]), + .R(1'b0)); + FDRE \axaddr_wrap_reg[9] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axaddr_wrap_reg[11]_1 [9]), + .Q(\axaddr_wrap_reg[11]_0 [9]), + .R(1'b0)); + LUT6 #( + .INIT(64'h4444F44444444444)) + \axlen_cnt[0]_i_1__0 + (.I0(\axlen_cnt_reg_n_0_[0] ), + .I1(\axlen_cnt_reg[2]_0 ), + .I2(\axlen_cnt_reg[3]_0 [5]), + .I3(Q[0]), + .I4(Q[1]), + .I5(si_rs_awvalid), + .O(\axlen_cnt[0]_i_1__0_n_0 )); + LUT5 #( + .INIT(32'hF44F4444)) + \axlen_cnt[1]_i_1__0 + (.I0(\axlen_cnt_reg[3]_1 ), + .I1(\axlen_cnt_reg[3]_0 [6]), + .I2(\axlen_cnt_reg_n_0_[1] ), + .I3(\axlen_cnt_reg_n_0_[0] ), + .I4(\axlen_cnt_reg[2]_0 ), + .O(\axlen_cnt[1]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hF4F4F44F44444444)) + \axlen_cnt[2]_i_1__0 + (.I0(\axlen_cnt_reg[3]_1 ), + .I1(\axlen_cnt_reg[3]_0 [7]), + .I2(\axlen_cnt_reg_n_0_[2] ), + .I3(\axlen_cnt_reg_n_0_[0] ), + .I4(\axlen_cnt_reg_n_0_[1] ), + .I5(\axlen_cnt_reg[2]_0 ), + .O(\axlen_cnt[2]_i_1__0_n_0 )); + LUT5 #( + .INIT(32'hAAAAAAA8)) + \axlen_cnt[2]_i_2 + (.I0(\axlen_cnt_reg[3]_1 ), + .I1(\axlen_cnt_reg_n_0_[2] ), + .I2(\axlen_cnt_reg_n_0_[3] ), + .I3(\axlen_cnt_reg_n_0_[1] ), + .I4(\axlen_cnt_reg_n_0_[4] ), + .O(\axlen_cnt_reg[2]_0 )); + LUT5 #( + .INIT(32'h38FF3800)) + \axlen_cnt[3]_i_1 + (.I0(\axlen_cnt_reg_n_0_[4] ), + .I1(\axlen_cnt[3]_i_2__2_n_0 ), + .I2(\axlen_cnt_reg_n_0_[3] ), + .I3(\axlen_cnt_reg[3]_1 ), + .I4(\axlen_cnt_reg[3]_0 [8]), + .O(\axlen_cnt[3]_i_1_n_0 )); + LUT3 #( + .INIT(8'h01)) + \axlen_cnt[3]_i_2__2 + (.I0(\axlen_cnt_reg_n_0_[0] ), + .I1(\axlen_cnt_reg_n_0_[1] ), + .I2(\axlen_cnt_reg_n_0_[2] ), + .O(\axlen_cnt[3]_i_2__2_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \axlen_cnt[4]_i_1 + (.I0(\axlen_cnt_reg[3]_1 ), + .I1(\axlen_cnt_reg_n_0_[2] ), + .I2(\axlen_cnt_reg_n_0_[1] ), + .I3(\axlen_cnt_reg_n_0_[0] ), + .I4(\axlen_cnt_reg_n_0_[3] ), + .I5(\axlen_cnt_reg_n_0_[4] ), + .O(\axlen_cnt[4]_i_1_n_0 )); + FDRE \axlen_cnt_reg[0] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axlen_cnt[0]_i_1__0_n_0 ), + .Q(\axlen_cnt_reg_n_0_[0] ), + .R(1'b0)); + FDRE \axlen_cnt_reg[1] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axlen_cnt[1]_i_1__0_n_0 ), + .Q(\axlen_cnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE \axlen_cnt_reg[2] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axlen_cnt[2]_i_1__0_n_0 ), + .Q(\axlen_cnt_reg_n_0_[2] ), + .R(1'b0)); + FDRE \axlen_cnt_reg[3] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axlen_cnt[3]_i_1_n_0 ), + .Q(\axlen_cnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE \axlen_cnt_reg[4] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axlen_cnt[4]_i_1_n_0 ), + .Q(\axlen_cnt_reg_n_0_[4] ), + .R(1'b0)); + LUT5 #( + .INIT(32'hFFFF88F8)) + next_pending_r_i_1__0 + (.I0(\axlen_cnt_reg[2]_0 ), + .I1(next), + .I2(next_pending_r_0), + .I3(\axaddr_wrap_reg[0]_0 ), + .I4(next_pending_r_reg_0), + .O(wrap_next_pending)); + FDRE next_pending_r_reg + (.C(aclk), + .CE(1'b1), + .D(wrap_next_pending), + .Q(next_pending_r_0), + .R(1'b0)); + FDRE sel_first_reg + (.C(aclk), + .CE(1'b1), + .D(sel_first_reg_0), + .Q(sel_first), + .R(1'b0)); + FDRE \wrap_boundary_axaddr_r_reg[0] + (.C(aclk), + .CE(E), + .D(\wrap_boundary_axaddr_r_reg[6]_0 [0]), + .Q(\wrap_boundary_axaddr_r_reg[11]_0 [0]), + .R(1'b0)); + FDRE \wrap_boundary_axaddr_r_reg[10] + (.C(aclk), + .CE(E), + .D(\axlen_cnt_reg[3]_0 [3]), + .Q(\wrap_boundary_axaddr_r_reg[11]_0 [10]), + .R(1'b0)); + FDRE \wrap_boundary_axaddr_r_reg[11] + (.C(aclk), + .CE(E), + .D(\axlen_cnt_reg[3]_0 [4]), + .Q(\wrap_boundary_axaddr_r_reg[11]_0 [11]), + .R(1'b0)); + FDRE \wrap_boundary_axaddr_r_reg[1] + (.C(aclk), + .CE(E), + .D(\wrap_boundary_axaddr_r_reg[6]_0 [1]), + .Q(\wrap_boundary_axaddr_r_reg[11]_0 [1]), + .R(1'b0)); + FDRE \wrap_boundary_axaddr_r_reg[2] + (.C(aclk), + .CE(E), + .D(\wrap_boundary_axaddr_r_reg[6]_0 [2]), + .Q(\wrap_boundary_axaddr_r_reg[11]_0 [2]), + .R(1'b0)); + FDRE \wrap_boundary_axaddr_r_reg[3] + (.C(aclk), + .CE(E), + .D(\wrap_boundary_axaddr_r_reg[6]_0 [3]), + .Q(\wrap_boundary_axaddr_r_reg[11]_0 [3]), + .R(1'b0)); + FDRE \wrap_boundary_axaddr_r_reg[4] + (.C(aclk), + .CE(E), + .D(\wrap_boundary_axaddr_r_reg[6]_0 [4]), + .Q(\wrap_boundary_axaddr_r_reg[11]_0 [4]), + .R(1'b0)); + FDRE \wrap_boundary_axaddr_r_reg[5] + (.C(aclk), + .CE(E), + .D(\wrap_boundary_axaddr_r_reg[6]_0 [5]), + .Q(\wrap_boundary_axaddr_r_reg[11]_0 [5]), + .R(1'b0)); + FDRE \wrap_boundary_axaddr_r_reg[6] + (.C(aclk), + .CE(E), + .D(\wrap_boundary_axaddr_r_reg[6]_0 [6]), + .Q(\wrap_boundary_axaddr_r_reg[11]_0 [6]), + .R(1'b0)); + FDRE \wrap_boundary_axaddr_r_reg[7] + (.C(aclk), + .CE(E), + .D(\axlen_cnt_reg[3]_0 [0]), + .Q(\wrap_boundary_axaddr_r_reg[11]_0 [7]), + .R(1'b0)); + FDRE \wrap_boundary_axaddr_r_reg[8] + (.C(aclk), + .CE(E), + .D(\axlen_cnt_reg[3]_0 [1]), + .Q(\wrap_boundary_axaddr_r_reg[11]_0 [8]), + .R(1'b0)); + FDRE \wrap_boundary_axaddr_r_reg[9] + (.C(aclk), + .CE(E), + .D(\axlen_cnt_reg[3]_0 [2]), + .Q(\wrap_boundary_axaddr_r_reg[11]_0 [9]), + .R(1'b0)); + FDRE \wrap_cnt_r_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\wrap_cnt_r_reg[3]_0 [0]), + .Q(wrap_cnt_r[0]), + .R(1'b0)); + FDRE \wrap_cnt_r_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\wrap_cnt_r_reg[3]_0 [1]), + .Q(wrap_cnt_r[1]), + .R(1'b0)); + FDRE \wrap_cnt_r_reg[2] + (.C(aclk), + .CE(1'b1), + .D(\wrap_cnt_r_reg[3]_0 [2]), + .Q(wrap_cnt_r[2]), + .R(1'b0)); + FDRE \wrap_cnt_r_reg[3] + (.C(aclk), + .CE(1'b1), + .D(\wrap_cnt_r_reg[3]_0 [3]), + .Q(wrap_cnt_r[3]), + .R(1'b0)); + FDRE \wrap_second_len_r_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\wrap_second_len_r_reg[3]_1 [0]), + .Q(\wrap_second_len_r_reg[3]_0 [0]), + .R(1'b0)); + FDRE \wrap_second_len_r_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\wrap_second_len_r_reg[3]_1 [1]), + .Q(\wrap_second_len_r_reg[3]_0 [1]), + .R(1'b0)); + FDRE \wrap_second_len_r_reg[2] + (.C(aclk), + .CE(1'b1), + .D(\wrap_second_len_r_reg[3]_1 [2]), + .Q(\wrap_second_len_r_reg[3]_0 [2]), + .R(1'b0)); + FDRE \wrap_second_len_r_reg[3] + (.C(aclk), + .CE(1'b1), + .D(\wrap_second_len_r_reg[3]_1 [3]), + .Q(\wrap_second_len_r_reg[3]_0 [3]), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_29_b2s_wrap_cmd" *) +module NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_wrap_cmd_3 + (sel_first_reg_0, + \axaddr_wrap_reg[3]_0 , + \axaddr_wrap_reg[11]_0 , + \axaddr_wrap_reg[7]_0 , + O, + \m_payload_i_reg[39] , + \m_payload_i_reg[39]_0 , + \axlen_cnt_reg[0]_0 , + \axaddr_offset_r_reg[3]_0 , + \wrap_second_len_r_reg[3]_0 , + \wrap_boundary_axaddr_r_reg[11]_0 , + aclk, + sel_first_reg_1, + \axlen_cnt_reg[2]_0 , + Q, + si_rs_arvalid, + S, + sel_first_i, + incr_next_pending, + \axlen_cnt_reg[1]_0 , + \axlen_cnt_reg[3]_0 , + \axaddr_wrap_reg[0]_0 , + next_pending_r_reg_0, + D, + \wrap_second_len_r_reg[3]_1 , + \wrap_cnt_r_reg[3]_0 , + E, + \wrap_boundary_axaddr_r_reg[6]_0 , + \axaddr_wrap_reg[11]_1 ); + output sel_first_reg_0; + output [3:0]\axaddr_wrap_reg[3]_0 ; + output [11:0]\axaddr_wrap_reg[11]_0 ; + output [3:0]\axaddr_wrap_reg[7]_0 ; + output [3:0]O; + output \m_payload_i_reg[39] ; + output \m_payload_i_reg[39]_0 ; + output \axlen_cnt_reg[0]_0 ; + output [3:0]\axaddr_offset_r_reg[3]_0 ; + output [3:0]\wrap_second_len_r_reg[3]_0 ; + output [11:0]\wrap_boundary_axaddr_r_reg[11]_0 ; + input aclk; + input sel_first_reg_1; + input [8:0]\axlen_cnt_reg[2]_0 ; + input [0:0]Q; + input si_rs_arvalid; + input [3:0]S; + input sel_first_i; + input incr_next_pending; + input \axlen_cnt_reg[1]_0 ; + input \axlen_cnt_reg[3]_0 ; + input \axaddr_wrap_reg[0]_0 ; + input next_pending_r_reg_0; + input [3:0]D; + input [3:0]\wrap_second_len_r_reg[3]_1 ; + input [3:0]\wrap_cnt_r_reg[3]_0 ; + input [0:0]E; + input [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ; + input [11:0]\axaddr_wrap_reg[11]_1 ; + + wire [3:0]D; + wire [0:0]E; + wire [3:0]O; + wire [0:0]Q; + wire [3:0]S; + wire aclk; + wire [3:0]\axaddr_offset_r_reg[3]_0 ; + wire \axaddr_wrap[11]_i_6__0_n_0 ; + wire \axaddr_wrap_reg[0]_0 ; + wire [11:0]\axaddr_wrap_reg[11]_0 ; + wire [11:0]\axaddr_wrap_reg[11]_1 ; + wire \axaddr_wrap_reg[11]_i_3__0_n_1 ; + wire \axaddr_wrap_reg[11]_i_3__0_n_2 ; + wire \axaddr_wrap_reg[11]_i_3__0_n_3 ; + wire [3:0]\axaddr_wrap_reg[3]_0 ; + wire \axaddr_wrap_reg[3]_i_2__0_n_0 ; + wire \axaddr_wrap_reg[3]_i_2__0_n_1 ; + wire \axaddr_wrap_reg[3]_i_2__0_n_2 ; + wire \axaddr_wrap_reg[3]_i_2__0_n_3 ; + wire [3:0]\axaddr_wrap_reg[7]_0 ; + wire \axaddr_wrap_reg[7]_i_2__0_n_0 ; + wire \axaddr_wrap_reg[7]_i_2__0_n_1 ; + wire \axaddr_wrap_reg[7]_i_2__0_n_2 ; + wire \axaddr_wrap_reg[7]_i_2__0_n_3 ; + wire \axlen_cnt[0]_i_1__2_n_0 ; + wire \axlen_cnt[1]_i_1__2_n_0 ; + wire \axlen_cnt[2]_i_1__2_n_0 ; + wire \axlen_cnt[3]_i_1__1_n_0 ; + wire \axlen_cnt[3]_i_2__1_n_0 ; + wire \axlen_cnt[4]_i_1__0_n_0 ; + wire \axlen_cnt_reg[0]_0 ; + wire \axlen_cnt_reg[1]_0 ; + wire [8:0]\axlen_cnt_reg[2]_0 ; + wire \axlen_cnt_reg[3]_0 ; + wire \axlen_cnt_reg_n_0_[0] ; + wire \axlen_cnt_reg_n_0_[1] ; + wire \axlen_cnt_reg_n_0_[2] ; + wire \axlen_cnt_reg_n_0_[3] ; + wire \axlen_cnt_reg_n_0_[4] ; + wire incr_next_pending; + wire \m_payload_i_reg[39] ; + wire \m_payload_i_reg[39]_0 ; + wire next_pending_r; + wire next_pending_r_reg_0; + wire sel_first_i; + wire sel_first_reg_0; + wire sel_first_reg_1; + wire si_rs_arvalid; + wire [11:0]\wrap_boundary_axaddr_r_reg[11]_0 ; + wire [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ; + wire [3:0]\wrap_cnt_r_reg[3]_0 ; + wire \wrap_cnt_r_reg_n_0_[0] ; + wire \wrap_cnt_r_reg_n_0_[1] ; + wire \wrap_cnt_r_reg_n_0_[2] ; + wire \wrap_cnt_r_reg_n_0_[3] ; + wire wrap_next_pending; + wire [3:0]\wrap_second_len_r_reg[3]_0 ; + wire [3:0]\wrap_second_len_r_reg[3]_1 ; + wire [3:3]\NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED ; + + FDRE \axaddr_offset_r_reg[0] + (.C(aclk), + .CE(1'b1), + .D(D[0]), + .Q(\axaddr_offset_r_reg[3]_0 [0]), + .R(1'b0)); + FDRE \axaddr_offset_r_reg[1] + (.C(aclk), + .CE(1'b1), + .D(D[1]), + .Q(\axaddr_offset_r_reg[3]_0 [1]), + .R(1'b0)); + FDRE \axaddr_offset_r_reg[2] + (.C(aclk), + .CE(1'b1), + .D(D[2]), + .Q(\axaddr_offset_r_reg[3]_0 [2]), + .R(1'b0)); + FDRE \axaddr_offset_r_reg[3] + (.C(aclk), + .CE(1'b1), + .D(D[3]), + .Q(\axaddr_offset_r_reg[3]_0 [3]), + .R(1'b0)); + LUT4 #( + .INIT(16'h0009)) + \axaddr_wrap[11]_i_5__0 + (.I0(\axlen_cnt_reg_n_0_[0] ), + .I1(\wrap_cnt_r_reg_n_0_[0] ), + .I2(\axlen_cnt_reg_n_0_[4] ), + .I3(\axaddr_wrap[11]_i_6__0_n_0 ), + .O(\axlen_cnt_reg[0]_0 )); + LUT6 #( + .INIT(64'h6FF6FFFFFFFF6FF6)) + \axaddr_wrap[11]_i_6__0 + (.I0(\wrap_cnt_r_reg_n_0_[1] ), + .I1(\axlen_cnt_reg_n_0_[1] ), + .I2(\axlen_cnt_reg_n_0_[3] ), + .I3(\wrap_cnt_r_reg_n_0_[3] ), + .I4(\axlen_cnt_reg_n_0_[2] ), + .I5(\wrap_cnt_r_reg_n_0_[2] ), + .O(\axaddr_wrap[11]_i_6__0_n_0 )); + FDRE \axaddr_wrap_reg[0] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axaddr_wrap_reg[11]_1 [0]), + .Q(\axaddr_wrap_reg[11]_0 [0]), + .R(1'b0)); + FDRE \axaddr_wrap_reg[10] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axaddr_wrap_reg[11]_1 [10]), + .Q(\axaddr_wrap_reg[11]_0 [10]), + .R(1'b0)); + FDRE \axaddr_wrap_reg[11] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axaddr_wrap_reg[11]_1 [11]), + .Q(\axaddr_wrap_reg[11]_0 [11]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \axaddr_wrap_reg[11]_i_3__0 + (.CI(\axaddr_wrap_reg[7]_i_2__0_n_0 ), + .CO({\NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED [3],\axaddr_wrap_reg[11]_i_3__0_n_1 ,\axaddr_wrap_reg[11]_i_3__0_n_2 ,\axaddr_wrap_reg[11]_i_3__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(O), + .S(\axaddr_wrap_reg[11]_0 [11:8])); + FDRE \axaddr_wrap_reg[1] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axaddr_wrap_reg[11]_1 [1]), + .Q(\axaddr_wrap_reg[11]_0 [1]), + .R(1'b0)); + FDRE \axaddr_wrap_reg[2] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axaddr_wrap_reg[11]_1 [2]), + .Q(\axaddr_wrap_reg[11]_0 [2]), + .R(1'b0)); + FDRE \axaddr_wrap_reg[3] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axaddr_wrap_reg[11]_1 [3]), + .Q(\axaddr_wrap_reg[11]_0 [3]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \axaddr_wrap_reg[3]_i_2__0 + (.CI(1'b0), + .CO({\axaddr_wrap_reg[3]_i_2__0_n_0 ,\axaddr_wrap_reg[3]_i_2__0_n_1 ,\axaddr_wrap_reg[3]_i_2__0_n_2 ,\axaddr_wrap_reg[3]_i_2__0_n_3 }), + .CYINIT(1'b0), + .DI(\axaddr_wrap_reg[11]_0 [3:0]), + .O(\axaddr_wrap_reg[3]_0 ), + .S(S)); + FDRE \axaddr_wrap_reg[4] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axaddr_wrap_reg[11]_1 [4]), + .Q(\axaddr_wrap_reg[11]_0 [4]), + .R(1'b0)); + FDRE \axaddr_wrap_reg[5] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axaddr_wrap_reg[11]_1 [5]), + .Q(\axaddr_wrap_reg[11]_0 [5]), + .R(1'b0)); + FDRE \axaddr_wrap_reg[6] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axaddr_wrap_reg[11]_1 [6]), + .Q(\axaddr_wrap_reg[11]_0 [6]), + .R(1'b0)); + FDRE \axaddr_wrap_reg[7] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axaddr_wrap_reg[11]_1 [7]), + .Q(\axaddr_wrap_reg[11]_0 [7]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \axaddr_wrap_reg[7]_i_2__0 + (.CI(\axaddr_wrap_reg[3]_i_2__0_n_0 ), + .CO({\axaddr_wrap_reg[7]_i_2__0_n_0 ,\axaddr_wrap_reg[7]_i_2__0_n_1 ,\axaddr_wrap_reg[7]_i_2__0_n_2 ,\axaddr_wrap_reg[7]_i_2__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\axaddr_wrap_reg[7]_0 ), + .S(\axaddr_wrap_reg[11]_0 [7:4])); + FDRE \axaddr_wrap_reg[8] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axaddr_wrap_reg[11]_1 [8]), + .Q(\axaddr_wrap_reg[11]_0 [8]), + .R(1'b0)); + FDRE \axaddr_wrap_reg[9] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axaddr_wrap_reg[11]_1 [9]), + .Q(\axaddr_wrap_reg[11]_0 [9]), + .R(1'b0)); + LUT5 #( + .INIT(32'h44F44444)) + \axlen_cnt[0]_i_1__2 + (.I0(\axlen_cnt_reg_n_0_[0] ), + .I1(\axlen_cnt[3]_i_2__1_n_0 ), + .I2(\axlen_cnt_reg[2]_0 [6]), + .I3(Q), + .I4(si_rs_arvalid), + .O(\axlen_cnt[0]_i_1__2_n_0 )); + LUT5 #( + .INIT(32'hF44F4444)) + \axlen_cnt[1]_i_1__2 + (.I0(\axlen_cnt_reg[1]_0 ), + .I1(\axlen_cnt_reg[2]_0 [7]), + .I2(\axlen_cnt_reg_n_0_[1] ), + .I3(\axlen_cnt_reg_n_0_[0] ), + .I4(\axlen_cnt[3]_i_2__1_n_0 ), + .O(\axlen_cnt[1]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'hF4F4F44F44444444)) + \axlen_cnt[2]_i_1__2 + (.I0(\axlen_cnt_reg[1]_0 ), + .I1(\axlen_cnt_reg[2]_0 [8]), + .I2(\axlen_cnt_reg_n_0_[2] ), + .I3(\axlen_cnt_reg_n_0_[0] ), + .I4(\axlen_cnt_reg_n_0_[1] ), + .I5(\axlen_cnt[3]_i_2__1_n_0 ), + .O(\axlen_cnt[2]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'hEAEAEAEAEAEAEAAE)) + \axlen_cnt[3]_i_1__1 + (.I0(\axlen_cnt_reg[3]_0 ), + .I1(\axlen_cnt[3]_i_2__1_n_0 ), + .I2(\axlen_cnt_reg_n_0_[3] ), + .I3(\axlen_cnt_reg_n_0_[0] ), + .I4(\axlen_cnt_reg_n_0_[1] ), + .I5(\axlen_cnt_reg_n_0_[2] ), + .O(\axlen_cnt[3]_i_1__1_n_0 )); + LUT5 #( + .INIT(32'hAAAAAAA8)) + \axlen_cnt[3]_i_2__1 + (.I0(\axlen_cnt_reg[1]_0 ), + .I1(\axlen_cnt_reg_n_0_[2] ), + .I2(\axlen_cnt_reg_n_0_[3] ), + .I3(\axlen_cnt_reg_n_0_[1] ), + .I4(\axlen_cnt_reg_n_0_[4] ), + .O(\axlen_cnt[3]_i_2__1_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \axlen_cnt[4]_i_1__0 + (.I0(\axlen_cnt_reg[1]_0 ), + .I1(\axlen_cnt_reg_n_0_[2] ), + .I2(\axlen_cnt_reg_n_0_[1] ), + .I3(\axlen_cnt_reg_n_0_[0] ), + .I4(\axlen_cnt_reg_n_0_[3] ), + .I5(\axlen_cnt_reg_n_0_[4] ), + .O(\axlen_cnt[4]_i_1__0_n_0 )); + FDRE \axlen_cnt_reg[0] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axlen_cnt[0]_i_1__2_n_0 ), + .Q(\axlen_cnt_reg_n_0_[0] ), + .R(1'b0)); + FDRE \axlen_cnt_reg[1] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axlen_cnt[1]_i_1__2_n_0 ), + .Q(\axlen_cnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE \axlen_cnt_reg[2] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axlen_cnt[2]_i_1__2_n_0 ), + .Q(\axlen_cnt_reg_n_0_[2] ), + .R(1'b0)); + FDRE \axlen_cnt_reg[3] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axlen_cnt[3]_i_1__1_n_0 ), + .Q(\axlen_cnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE \axlen_cnt_reg[4] + (.C(aclk), + .CE(\axaddr_wrap_reg[0]_0 ), + .D(\axlen_cnt[4]_i_1__0_n_0 ), + .Q(\axlen_cnt_reg_n_0_[4] ), + .R(1'b0)); + LUT4 #( + .INIT(16'hFFAC)) + next_pending_r_i_1__2 + (.I0(\axlen_cnt[3]_i_2__1_n_0 ), + .I1(next_pending_r), + .I2(\axaddr_wrap_reg[0]_0 ), + .I3(next_pending_r_reg_0), + .O(wrap_next_pending)); + FDRE next_pending_r_reg + (.C(aclk), + .CE(1'b1), + .D(wrap_next_pending), + .Q(next_pending_r), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT4 #( + .INIT(16'hFB08)) + s_axburst_eq0_i_1__0 + (.I0(wrap_next_pending), + .I1(\axlen_cnt_reg[2]_0 [5]), + .I2(sel_first_i), + .I3(incr_next_pending), + .O(\m_payload_i_reg[39] )); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT4 #( + .INIT(16'hABA8)) + s_axburst_eq1_i_1__0 + (.I0(wrap_next_pending), + .I1(\axlen_cnt_reg[2]_0 [5]), + .I2(sel_first_i), + .I3(incr_next_pending), + .O(\m_payload_i_reg[39]_0 )); + FDRE sel_first_reg + (.C(aclk), + .CE(1'b1), + .D(sel_first_reg_1), + .Q(sel_first_reg_0), + .R(1'b0)); + FDRE \wrap_boundary_axaddr_r_reg[0] + (.C(aclk), + .CE(E), + .D(\wrap_boundary_axaddr_r_reg[6]_0 [0]), + .Q(\wrap_boundary_axaddr_r_reg[11]_0 [0]), + .R(1'b0)); + FDRE \wrap_boundary_axaddr_r_reg[10] + (.C(aclk), + .CE(E), + .D(\axlen_cnt_reg[2]_0 [3]), + .Q(\wrap_boundary_axaddr_r_reg[11]_0 [10]), + .R(1'b0)); + FDRE \wrap_boundary_axaddr_r_reg[11] + (.C(aclk), + .CE(E), + .D(\axlen_cnt_reg[2]_0 [4]), + .Q(\wrap_boundary_axaddr_r_reg[11]_0 [11]), + .R(1'b0)); + FDRE \wrap_boundary_axaddr_r_reg[1] + (.C(aclk), + .CE(E), + .D(\wrap_boundary_axaddr_r_reg[6]_0 [1]), + .Q(\wrap_boundary_axaddr_r_reg[11]_0 [1]), + .R(1'b0)); + FDRE \wrap_boundary_axaddr_r_reg[2] + (.C(aclk), + .CE(E), + .D(\wrap_boundary_axaddr_r_reg[6]_0 [2]), + .Q(\wrap_boundary_axaddr_r_reg[11]_0 [2]), + .R(1'b0)); + FDRE \wrap_boundary_axaddr_r_reg[3] + (.C(aclk), + .CE(E), + .D(\wrap_boundary_axaddr_r_reg[6]_0 [3]), + .Q(\wrap_boundary_axaddr_r_reg[11]_0 [3]), + .R(1'b0)); + FDRE \wrap_boundary_axaddr_r_reg[4] + (.C(aclk), + .CE(E), + .D(\wrap_boundary_axaddr_r_reg[6]_0 [4]), + .Q(\wrap_boundary_axaddr_r_reg[11]_0 [4]), + .R(1'b0)); + FDRE \wrap_boundary_axaddr_r_reg[5] + (.C(aclk), + .CE(E), + .D(\wrap_boundary_axaddr_r_reg[6]_0 [5]), + .Q(\wrap_boundary_axaddr_r_reg[11]_0 [5]), + .R(1'b0)); + FDRE \wrap_boundary_axaddr_r_reg[6] + (.C(aclk), + .CE(E), + .D(\wrap_boundary_axaddr_r_reg[6]_0 [6]), + .Q(\wrap_boundary_axaddr_r_reg[11]_0 [6]), + .R(1'b0)); + FDRE \wrap_boundary_axaddr_r_reg[7] + (.C(aclk), + .CE(E), + .D(\axlen_cnt_reg[2]_0 [0]), + .Q(\wrap_boundary_axaddr_r_reg[11]_0 [7]), + .R(1'b0)); + FDRE \wrap_boundary_axaddr_r_reg[8] + (.C(aclk), + .CE(E), + .D(\axlen_cnt_reg[2]_0 [1]), + .Q(\wrap_boundary_axaddr_r_reg[11]_0 [8]), + .R(1'b0)); + FDRE \wrap_boundary_axaddr_r_reg[9] + (.C(aclk), + .CE(E), + .D(\axlen_cnt_reg[2]_0 [2]), + .Q(\wrap_boundary_axaddr_r_reg[11]_0 [9]), + .R(1'b0)); + FDRE \wrap_cnt_r_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\wrap_cnt_r_reg[3]_0 [0]), + .Q(\wrap_cnt_r_reg_n_0_[0] ), + .R(1'b0)); + FDRE \wrap_cnt_r_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\wrap_cnt_r_reg[3]_0 [1]), + .Q(\wrap_cnt_r_reg_n_0_[1] ), + .R(1'b0)); + FDRE \wrap_cnt_r_reg[2] + (.C(aclk), + .CE(1'b1), + .D(\wrap_cnt_r_reg[3]_0 [2]), + .Q(\wrap_cnt_r_reg_n_0_[2] ), + .R(1'b0)); + FDRE \wrap_cnt_r_reg[3] + (.C(aclk), + .CE(1'b1), + .D(\wrap_cnt_r_reg[3]_0 [3]), + .Q(\wrap_cnt_r_reg_n_0_[3] ), + .R(1'b0)); + FDRE \wrap_second_len_r_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\wrap_second_len_r_reg[3]_1 [0]), + .Q(\wrap_second_len_r_reg[3]_0 [0]), + .R(1'b0)); + FDRE \wrap_second_len_r_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\wrap_second_len_r_reg[3]_1 [1]), + .Q(\wrap_second_len_r_reg[3]_0 [1]), + .R(1'b0)); + FDRE \wrap_second_len_r_reg[2] + (.C(aclk), + .CE(1'b1), + .D(\wrap_second_len_r_reg[3]_1 [2]), + .Q(\wrap_second_len_r_reg[3]_0 [2]), + .R(1'b0)); + FDRE \wrap_second_len_r_reg[3] + (.C(aclk), + .CE(1'b1), + .D(\wrap_second_len_r_reg[3]_1 [3]), + .Q(\wrap_second_len_r_reg[3]_0 [3]), + .R(1'b0)); +endmodule + +module NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axi_register_slice + (s_ready_i_reg, + s_ready_i_reg_0, + si_rs_awvalid, + m_valid_i_reg, + si_rs_bready, + si_rs_arvalid, + m_valid_i_reg_0, + si_rs_rready, + S, + \m_payload_i_reg[61] , + \axaddr_wrap_reg[3] , + \axaddr_incr_reg[3] , + \m_payload_i_reg[61]_0 , + \axaddr_wrap_reg[3]_0 , + axaddr_incr, + \m_payload_i_reg[3] , + \m_payload_i_reg[7] , + O, + \m_payload_i_reg[45] , + \FSM_sequential_state_reg[0] , + \m_payload_i_reg[5] , + shandshake, + \FSM_sequential_state_reg[1] , + \m_payload_i_reg[6] , + \m_payload_i_reg[47] , + \m_payload_i_reg[45]_0 , + s_ready_i_reg_1, + D, + \m_payload_i_reg[4] , + \m_payload_i_reg[1] , + \m_payload_i_reg[2] , + \m_payload_i_reg[1]_0 , + \m_payload_i_reg[6]_0 , + \m_payload_i_reg[2]_0 , + \m_payload_i_reg[1]_1 , + \m_payload_i_reg[2]_1 , + \m_payload_i_reg[1]_2 , + \m_payload_i_reg[2]_2 , + \m_payload_i_reg[4]_0 , + m_axi_awaddr, + m_axi_araddr, + \m_payload_i_reg[13] , + \m_payload_i_reg[46] , + aclk, + s_ready_i0, + m_valid_i0, + aresetn, + m_valid_i_reg_1, + s_axi_rready, + Q, + \m_axi_awaddr[11] , + \m_axi_araddr[11] , + \m_axi_araddr[11]_0 , + b_push, + s_axi_awvalid, + \axaddr_incr_reg[3]_0 , + \axaddr_incr_reg[3]_1 , + next_pending_r_reg, + \wrap_second_len_r_reg[3] , + si_rs_bvalid, + \axlen_cnt_reg[3] , + next_pending_r_reg_0, + s_axi_bready, + s_axi_awid, + s_axi_awlen, + s_axi_awburst, + s_axi_awsize, + s_axi_awprot, + s_axi_awaddr, + sel_first, + sel_first_0, + s_axi_arid, + s_axi_arlen, + s_axi_arburst, + s_axi_arsize, + s_axi_arprot, + s_axi_araddr, + \m_axi_araddr[11]_1 , + sel_first_1, + out, + \skid_buffer_reg[1] , + \skid_buffer_reg[46] , + \skid_buffer_reg[33] , + E, + \m_payload_i_reg[0] ); + output s_ready_i_reg; + output s_ready_i_reg_0; + output si_rs_awvalid; + output m_valid_i_reg; + output si_rs_bready; + output si_rs_arvalid; + output m_valid_i_reg_0; + output si_rs_rready; + output [3:0]S; + output [53:0]\m_payload_i_reg[61] ; + output [3:0]\axaddr_wrap_reg[3] ; + output [3:0]\axaddr_incr_reg[3] ; + output [53:0]\m_payload_i_reg[61]_0 ; + output [3:0]\axaddr_wrap_reg[3]_0 ; + output [11:0]axaddr_incr; + output [3:0]\m_payload_i_reg[3] ; + output [3:0]\m_payload_i_reg[7] ; + output [3:0]O; + output \m_payload_i_reg[45] ; + output \FSM_sequential_state_reg[0] ; + output \m_payload_i_reg[5] ; + output shandshake; + output \FSM_sequential_state_reg[1] ; + output \m_payload_i_reg[6] ; + output \m_payload_i_reg[47] ; + output \m_payload_i_reg[45]_0 ; + output s_ready_i_reg_1; + output [6:0]D; + output \m_payload_i_reg[4] ; + output \m_payload_i_reg[1] ; + output \m_payload_i_reg[2] ; + output \m_payload_i_reg[1]_0 ; + output [6:0]\m_payload_i_reg[6]_0 ; + output \m_payload_i_reg[2]_0 ; + output \m_payload_i_reg[1]_1 ; + output \m_payload_i_reg[2]_1 ; + output \m_payload_i_reg[1]_2 ; + output \m_payload_i_reg[2]_2 ; + output \m_payload_i_reg[4]_0 ; + output [11:0]m_axi_awaddr; + output [11:0]m_axi_araddr; + output [13:0]\m_payload_i_reg[13] ; + output [46:0]\m_payload_i_reg[46] ; + input aclk; + input s_ready_i0; + input m_valid_i0; + input aresetn; + input m_valid_i_reg_1; + input s_axi_rready; + input [11:0]Q; + input [11:0]\m_axi_awaddr[11] ; + input [11:0]\m_axi_araddr[11] ; + input [11:0]\m_axi_araddr[11]_0 ; + input b_push; + input s_axi_awvalid; + input [3:0]\axaddr_incr_reg[3]_0 ; + input [3:0]\axaddr_incr_reg[3]_1 ; + input next_pending_r_reg; + input [1:0]\wrap_second_len_r_reg[3] ; + input si_rs_bvalid; + input [1:0]\axlen_cnt_reg[3] ; + input next_pending_r_reg_0; + input s_axi_bready; + input [11:0]s_axi_awid; + input [3:0]s_axi_awlen; + input [1:0]s_axi_awburst; + input [1:0]s_axi_awsize; + input [2:0]s_axi_awprot; + input [31:0]s_axi_awaddr; + input sel_first; + input sel_first_0; + input [11:0]s_axi_arid; + input [3:0]s_axi_arlen; + input [1:0]s_axi_arburst; + input [1:0]s_axi_arsize; + input [2:0]s_axi_arprot; + input [31:0]s_axi_araddr; + input \m_axi_araddr[11]_1 ; + input sel_first_1; + input [11:0]out; + input [1:0]\skid_buffer_reg[1] ; + input [12:0]\skid_buffer_reg[46] ; + input [33:0]\skid_buffer_reg[33] ; + input [0:0]E; + input [0:0]\m_payload_i_reg[0] ; + + wire [6:0]D; + wire [0:0]E; + wire \FSM_sequential_state_reg[0] ; + wire \FSM_sequential_state_reg[1] ; + wire [3:0]O; + wire [11:0]Q; + wire [3:0]S; + wire aclk; + wire \ar.ar_pipe_n_2 ; + wire aresetn; + wire \aw.aw_pipe_n_1 ; + wire \aw.aw_pipe_n_104 ; + wire [11:0]axaddr_incr; + wire [3:0]\axaddr_incr_reg[3] ; + wire [3:0]\axaddr_incr_reg[3]_0 ; + wire [3:0]\axaddr_incr_reg[3]_1 ; + wire [3:0]\axaddr_wrap_reg[3] ; + wire [3:0]\axaddr_wrap_reg[3]_0 ; + wire [1:0]\axlen_cnt_reg[3] ; + wire b_push; + wire [11:0]m_axi_araddr; + wire [11:0]\m_axi_araddr[11] ; + wire [11:0]\m_axi_araddr[11]_0 ; + wire \m_axi_araddr[11]_1 ; + wire [11:0]m_axi_awaddr; + wire [11:0]\m_axi_awaddr[11] ; + wire [0:0]\m_payload_i_reg[0] ; + wire [13:0]\m_payload_i_reg[13] ; + wire \m_payload_i_reg[1] ; + wire \m_payload_i_reg[1]_0 ; + wire \m_payload_i_reg[1]_1 ; + wire \m_payload_i_reg[1]_2 ; + wire \m_payload_i_reg[2] ; + wire \m_payload_i_reg[2]_0 ; + wire \m_payload_i_reg[2]_1 ; + wire \m_payload_i_reg[2]_2 ; + wire [3:0]\m_payload_i_reg[3] ; + wire \m_payload_i_reg[45] ; + wire \m_payload_i_reg[45]_0 ; + wire [46:0]\m_payload_i_reg[46] ; + wire \m_payload_i_reg[47] ; + wire \m_payload_i_reg[4] ; + wire \m_payload_i_reg[4]_0 ; + wire \m_payload_i_reg[5] ; + wire [53:0]\m_payload_i_reg[61] ; + wire [53:0]\m_payload_i_reg[61]_0 ; + wire \m_payload_i_reg[6] ; + wire [6:0]\m_payload_i_reg[6]_0 ; + wire [3:0]\m_payload_i_reg[7] ; + wire m_valid_i0; + wire m_valid_i_reg; + wire m_valid_i_reg_0; + wire m_valid_i_reg_1; + wire next_pending_r_reg; + wire next_pending_r_reg_0; + wire [11:0]out; + wire [31:0]s_axi_araddr; + wire [1:0]s_axi_arburst; + wire [11:0]s_axi_arid; + wire [3:0]s_axi_arlen; + wire [2:0]s_axi_arprot; + wire [1:0]s_axi_arsize; + wire [31:0]s_axi_awaddr; + wire [1:0]s_axi_awburst; + wire [11:0]s_axi_awid; + wire [3:0]s_axi_awlen; + wire [2:0]s_axi_awprot; + wire [1:0]s_axi_awsize; + wire s_axi_awvalid; + wire s_axi_bready; + wire s_axi_rready; + wire s_ready_i0; + wire s_ready_i_reg; + wire s_ready_i_reg_0; + wire s_ready_i_reg_1; + wire sel_first; + wire sel_first_0; + wire sel_first_1; + wire shandshake; + wire si_rs_arvalid; + wire si_rs_awvalid; + wire si_rs_bready; + wire si_rs_bvalid; + wire si_rs_rready; + wire [1:0]\skid_buffer_reg[1] ; + wire [33:0]\skid_buffer_reg[33] ; + wire [12:0]\skid_buffer_reg[46] ; + wire [1:0]\wrap_second_len_r_reg[3] ; + + NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axic_register_slice \ar.ar_pipe + (.\FSM_sequential_state_reg[1] (\FSM_sequential_state_reg[1] ), + .O(O), + .Q(\m_payload_i_reg[61]_0 ), + .aclk(aclk), + .\aresetn_d_reg[1]_inv_0 (\ar.ar_pipe_n_2 ), + .\aresetn_d_reg[1]_inv_1 (\aw.aw_pipe_n_104 ), + .\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ), + .\axaddr_incr_reg[3]_0 (\axaddr_incr_reg[3]_1 ), + .\axaddr_wrap_reg[3] (\axaddr_wrap_reg[3]_0 ), + .\axlen_cnt_reg[3] (\axlen_cnt_reg[3] ), + .m_axi_araddr(m_axi_araddr), + .\m_axi_araddr[11] (\m_axi_araddr[11] ), + .\m_axi_araddr[11]_0 (\m_axi_araddr[11]_0 ), + .\m_axi_araddr[11]_1 (\m_axi_araddr[11]_1 ), + .\m_payload_i_reg[0]_0 (\m_payload_i_reg[0] ), + .\m_payload_i_reg[1]_0 (\m_payload_i_reg[1]_1 ), + .\m_payload_i_reg[1]_1 (\m_payload_i_reg[1]_2 ), + .\m_payload_i_reg[2]_0 (\m_payload_i_reg[2]_0 ), + .\m_payload_i_reg[2]_1 (\m_payload_i_reg[2]_2 ), + .\m_payload_i_reg[3]_0 (\m_payload_i_reg[3] ), + .\m_payload_i_reg[45]_0 (\m_payload_i_reg[45]_0 ), + .\m_payload_i_reg[47]_0 (\m_payload_i_reg[47] ), + .\m_payload_i_reg[4]_0 (\m_payload_i_reg[4]_0 ), + .\m_payload_i_reg[6]_0 (\m_payload_i_reg[6] ), + .\m_payload_i_reg[6]_1 (\m_payload_i_reg[6]_0 ), + .\m_payload_i_reg[7]_0 (\m_payload_i_reg[7] ), + .m_valid_i0(m_valid_i0), + .next_pending_r_reg(next_pending_r_reg_0), + .s_axi_araddr(s_axi_araddr), + .s_axi_arburst(s_axi_arburst), + .s_axi_arid(s_axi_arid), + .s_axi_arlen(s_axi_arlen), + .s_axi_arprot(s_axi_arprot), + .s_axi_arsize(s_axi_arsize), + .s_ready_i0(s_ready_i0), + .s_ready_i_reg_0(s_ready_i_reg_0), + .s_ready_i_reg_1(\aw.aw_pipe_n_1 ), + .sel_first_1(sel_first_1), + .si_rs_arvalid(si_rs_arvalid)); + NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axic_register_slice_0 \aw.aw_pipe + (.D(D), + .E(E), + .\FSM_sequential_state_reg[0] (\FSM_sequential_state_reg[0] ), + .Q(Q), + .S(S), + .aclk(aclk), + .aresetn(aresetn), + .\aresetn_d_reg[0]_0 (\aw.aw_pipe_n_1 ), + .\aresetn_d_reg[0]_1 (\aw.aw_pipe_n_104 ), + .axaddr_incr(axaddr_incr), + .\axaddr_incr_reg[3] (\axaddr_incr_reg[3]_0 ), + .\axaddr_wrap_reg[3] (\axaddr_wrap_reg[3] ), + .b_push(b_push), + .m_axi_awaddr(m_axi_awaddr), + .\m_axi_awaddr[11] (\m_axi_awaddr[11] ), + .\m_payload_i_reg[1]_0 (\m_payload_i_reg[1] ), + .\m_payload_i_reg[1]_1 (\m_payload_i_reg[1]_0 ), + .\m_payload_i_reg[2]_0 (\m_payload_i_reg[2] ), + .\m_payload_i_reg[2]_1 (\m_payload_i_reg[2]_1 ), + .\m_payload_i_reg[45]_0 (\m_payload_i_reg[45] ), + .\m_payload_i_reg[4]_0 (\m_payload_i_reg[4] ), + .\m_payload_i_reg[5]_0 (\m_payload_i_reg[5] ), + .\m_payload_i_reg[61]_0 (\m_payload_i_reg[61] ), + .m_valid_i_reg_0(si_rs_awvalid), + .m_valid_i_reg_1(\ar.ar_pipe_n_2 ), + .next_pending_r_reg(next_pending_r_reg), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awburst(s_axi_awburst), + .s_axi_awid(s_axi_awid), + .s_axi_awlen(s_axi_awlen), + .s_axi_awprot(s_axi_awprot), + .s_axi_awsize(s_axi_awsize), + .s_axi_awvalid(s_axi_awvalid), + .s_ready_i_reg_0(s_ready_i_reg), + .sel_first(sel_first), + .sel_first_0(sel_first_0), + .\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3] )); + NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axic_register_slice__parameterized1 \b.b_pipe + (.aclk(aclk), + .\m_payload_i_reg[13]_0 (\m_payload_i_reg[13] ), + .m_valid_i_reg_0(m_valid_i_reg), + .m_valid_i_reg_1(\ar.ar_pipe_n_2 ), + .out(out), + .s_axi_bready(s_axi_bready), + .s_ready_i_reg_0(si_rs_bready), + .s_ready_i_reg_1(\aw.aw_pipe_n_1 ), + .shandshake(shandshake), + .si_rs_bvalid(si_rs_bvalid), + .\skid_buffer_reg[1]_0 (\skid_buffer_reg[1] )); + NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axic_register_slice__parameterized2 \r.r_pipe + (.aclk(aclk), + .\m_payload_i_reg[46]_0 (\m_payload_i_reg[46] ), + .m_valid_i_reg_0(m_valid_i_reg_0), + .m_valid_i_reg_1(\ar.ar_pipe_n_2 ), + .m_valid_i_reg_2(m_valid_i_reg_1), + .s_axi_rready(s_axi_rready), + .s_ready_i_reg_0(si_rs_rready), + .s_ready_i_reg_1(s_ready_i_reg_1), + .s_ready_i_reg_2(\aw.aw_pipe_n_1 ), + .\skid_buffer_reg[33]_0 (\skid_buffer_reg[33] ), + .\skid_buffer_reg[46]_0 (\skid_buffer_reg[46] )); +endmodule + +module NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axic_register_slice + (s_ready_i_reg_0, + si_rs_arvalid, + \aresetn_d_reg[1]_inv_0 , + \axaddr_incr_reg[3] , + Q, + \axaddr_wrap_reg[3] , + \m_payload_i_reg[3]_0 , + \m_payload_i_reg[7]_0 , + O, + \FSM_sequential_state_reg[1] , + \m_payload_i_reg[6]_0 , + \m_payload_i_reg[47]_0 , + \m_payload_i_reg[45]_0 , + \m_payload_i_reg[6]_1 , + \m_payload_i_reg[2]_0 , + \m_payload_i_reg[1]_0 , + \m_payload_i_reg[1]_1 , + \m_payload_i_reg[2]_1 , + \m_payload_i_reg[4]_0 , + m_axi_araddr, + s_ready_i_reg_1, + s_ready_i0, + aclk, + m_valid_i0, + \aresetn_d_reg[1]_inv_1 , + \m_axi_araddr[11] , + \m_axi_araddr[11]_0 , + \axaddr_incr_reg[3]_0 , + \axlen_cnt_reg[3] , + next_pending_r_reg, + s_axi_arid, + s_axi_arlen, + s_axi_arburst, + s_axi_arsize, + s_axi_arprot, + s_axi_araddr, + \m_axi_araddr[11]_1 , + sel_first_1, + \m_payload_i_reg[0]_0 ); + output s_ready_i_reg_0; + output si_rs_arvalid; + output \aresetn_d_reg[1]_inv_0 ; + output [3:0]\axaddr_incr_reg[3] ; + output [53:0]Q; + output [3:0]\axaddr_wrap_reg[3] ; + output [3:0]\m_payload_i_reg[3]_0 ; + output [3:0]\m_payload_i_reg[7]_0 ; + output [3:0]O; + output \FSM_sequential_state_reg[1] ; + output \m_payload_i_reg[6]_0 ; + output \m_payload_i_reg[47]_0 ; + output \m_payload_i_reg[45]_0 ; + output [6:0]\m_payload_i_reg[6]_1 ; + output \m_payload_i_reg[2]_0 ; + output \m_payload_i_reg[1]_0 ; + output \m_payload_i_reg[1]_1 ; + output \m_payload_i_reg[2]_1 ; + output \m_payload_i_reg[4]_0 ; + output [11:0]m_axi_araddr; + input s_ready_i_reg_1; + input s_ready_i0; + input aclk; + input m_valid_i0; + input \aresetn_d_reg[1]_inv_1 ; + input [11:0]\m_axi_araddr[11] ; + input [11:0]\m_axi_araddr[11]_0 ; + input [3:0]\axaddr_incr_reg[3]_0 ; + input [1:0]\axlen_cnt_reg[3] ; + input next_pending_r_reg; + input [11:0]s_axi_arid; + input [3:0]s_axi_arlen; + input [1:0]s_axi_arburst; + input [1:0]s_axi_arsize; + input [2:0]s_axi_arprot; + input [31:0]s_axi_araddr; + input \m_axi_araddr[11]_1 ; + input sel_first_1; + input [0:0]\m_payload_i_reg[0]_0 ; + + wire \FSM_sequential_state_reg[1] ; + wire [3:0]O; + wire [53:0]Q; + wire aclk; + wire \aresetn_d_reg[1]_inv_0 ; + wire \aresetn_d_reg[1]_inv_1 ; + wire \axaddr_incr[3]_i_4__0_n_0 ; + wire \axaddr_incr[3]_i_5__0_n_0 ; + wire \axaddr_incr[3]_i_6__0_n_0 ; + wire \axaddr_incr_reg[11]_i_3__0_n_1 ; + wire \axaddr_incr_reg[11]_i_3__0_n_2 ; + wire \axaddr_incr_reg[11]_i_3__0_n_3 ; + wire [3:0]\axaddr_incr_reg[3] ; + wire [3:0]\axaddr_incr_reg[3]_0 ; + wire \axaddr_incr_reg[3]_i_2__0_n_0 ; + wire \axaddr_incr_reg[3]_i_2__0_n_1 ; + wire \axaddr_incr_reg[3]_i_2__0_n_2 ; + wire \axaddr_incr_reg[3]_i_2__0_n_3 ; + wire \axaddr_incr_reg[7]_i_2__0_n_0 ; + wire \axaddr_incr_reg[7]_i_2__0_n_1 ; + wire \axaddr_incr_reg[7]_i_2__0_n_2 ; + wire \axaddr_incr_reg[7]_i_2__0_n_3 ; + wire [3:0]\axaddr_wrap_reg[3] ; + wire [1:0]\axlen_cnt_reg[3] ; + wire [11:0]m_axi_araddr; + wire [11:0]\m_axi_araddr[11] ; + wire [11:0]\m_axi_araddr[11]_0 ; + wire \m_axi_araddr[11]_1 ; + wire \m_axi_araddr[11]_INST_0_i_1_n_0 ; + wire \m_payload_i[0]_i_1__0_n_0 ; + wire \m_payload_i[10]_i_1__0_n_0 ; + wire \m_payload_i[11]_i_1__0_n_0 ; + wire \m_payload_i[12]_i_1__0_n_0 ; + wire \m_payload_i[13]_i_1__1_n_0 ; + wire \m_payload_i[14]_i_1__0_n_0 ; + wire \m_payload_i[15]_i_1__0_n_0 ; + wire \m_payload_i[16]_i_1__0_n_0 ; + wire \m_payload_i[17]_i_1__0_n_0 ; + wire \m_payload_i[18]_i_1__0_n_0 ; + wire \m_payload_i[19]_i_1__0_n_0 ; + wire \m_payload_i[1]_i_1__0_n_0 ; + wire \m_payload_i[20]_i_1__0_n_0 ; + wire \m_payload_i[21]_i_1__0_n_0 ; + wire \m_payload_i[22]_i_1__0_n_0 ; + wire \m_payload_i[23]_i_1__0_n_0 ; + wire \m_payload_i[24]_i_1__0_n_0 ; + wire \m_payload_i[25]_i_1__0_n_0 ; + wire \m_payload_i[26]_i_1__0_n_0 ; + wire \m_payload_i[27]_i_1__0_n_0 ; + wire \m_payload_i[28]_i_1__0_n_0 ; + wire \m_payload_i[29]_i_1__0_n_0 ; + wire \m_payload_i[2]_i_1__0_n_0 ; + wire \m_payload_i[30]_i_1__0_n_0 ; + wire \m_payload_i[31]_i_2__0_n_0 ; + wire \m_payload_i[32]_i_1__0_n_0 ; + wire \m_payload_i[33]_i_1__0_n_0 ; + wire \m_payload_i[34]_i_1__0_n_0 ; + wire \m_payload_i[35]_i_1__0_n_0 ; + wire \m_payload_i[36]_i_1__0_n_0 ; + wire \m_payload_i[38]_i_1__0_n_0 ; + wire \m_payload_i[39]_i_1__0_n_0 ; + wire \m_payload_i[3]_i_1__0_n_0 ; + wire \m_payload_i[44]_i_1__0_n_0 ; + wire \m_payload_i[45]_i_1__0_n_0 ; + wire \m_payload_i[46]_i_1__1_n_0 ; + wire \m_payload_i[47]_i_1__0_n_0 ; + wire \m_payload_i[4]_i_1__0_n_0 ; + wire \m_payload_i[50]_i_1__0_n_0 ; + wire \m_payload_i[51]_i_1__0_n_0 ; + wire \m_payload_i[52]_i_1__0_n_0 ; + wire \m_payload_i[53]_i_1__0_n_0 ; + wire \m_payload_i[54]_i_1__0_n_0 ; + wire \m_payload_i[55]_i_1__0_n_0 ; + wire \m_payload_i[56]_i_1__0_n_0 ; + wire \m_payload_i[57]_i_1__0_n_0 ; + wire \m_payload_i[58]_i_1__0_n_0 ; + wire \m_payload_i[59]_i_1__0_n_0 ; + wire \m_payload_i[5]_i_1__0_n_0 ; + wire \m_payload_i[60]_i_1__0_n_0 ; + wire \m_payload_i[61]_i_1__0_n_0 ; + wire \m_payload_i[6]_i_1__0_n_0 ; + wire \m_payload_i[7]_i_1__0_n_0 ; + wire \m_payload_i[8]_i_1__0_n_0 ; + wire \m_payload_i[9]_i_1__0_n_0 ; + wire [0:0]\m_payload_i_reg[0]_0 ; + wire \m_payload_i_reg[1]_0 ; + wire \m_payload_i_reg[1]_1 ; + wire \m_payload_i_reg[2]_0 ; + wire \m_payload_i_reg[2]_1 ; + wire [3:0]\m_payload_i_reg[3]_0 ; + wire \m_payload_i_reg[45]_0 ; + wire \m_payload_i_reg[47]_0 ; + wire \m_payload_i_reg[4]_0 ; + wire \m_payload_i_reg[6]_0 ; + wire [6:0]\m_payload_i_reg[6]_1 ; + wire [3:0]\m_payload_i_reg[7]_0 ; + wire \m_payload_i_reg_n_0_[38] ; + wire m_valid_i0; + wire next_pending_r_reg; + wire [31:0]s_axi_araddr; + wire [1:0]s_axi_arburst; + wire [11:0]s_axi_arid; + wire [3:0]s_axi_arlen; + wire [2:0]s_axi_arprot; + wire [1:0]s_axi_arsize; + wire s_ready_i0; + wire s_ready_i_reg_0; + wire s_ready_i_reg_1; + wire sel_first_1; + wire si_rs_arvalid; + wire \skid_buffer_reg_n_0_[0] ; + wire \skid_buffer_reg_n_0_[10] ; + wire \skid_buffer_reg_n_0_[11] ; + wire \skid_buffer_reg_n_0_[12] ; + wire \skid_buffer_reg_n_0_[13] ; + wire \skid_buffer_reg_n_0_[14] ; + wire \skid_buffer_reg_n_0_[15] ; + wire \skid_buffer_reg_n_0_[16] ; + wire \skid_buffer_reg_n_0_[17] ; + wire \skid_buffer_reg_n_0_[18] ; + wire \skid_buffer_reg_n_0_[19] ; + wire \skid_buffer_reg_n_0_[1] ; + wire \skid_buffer_reg_n_0_[20] ; + wire \skid_buffer_reg_n_0_[21] ; + wire \skid_buffer_reg_n_0_[22] ; + wire \skid_buffer_reg_n_0_[23] ; + wire \skid_buffer_reg_n_0_[24] ; + wire \skid_buffer_reg_n_0_[25] ; + wire \skid_buffer_reg_n_0_[26] ; + wire \skid_buffer_reg_n_0_[27] ; + wire \skid_buffer_reg_n_0_[28] ; + wire \skid_buffer_reg_n_0_[29] ; + wire \skid_buffer_reg_n_0_[2] ; + wire \skid_buffer_reg_n_0_[30] ; + wire \skid_buffer_reg_n_0_[31] ; + wire \skid_buffer_reg_n_0_[32] ; + wire \skid_buffer_reg_n_0_[33] ; + wire \skid_buffer_reg_n_0_[34] ; + wire \skid_buffer_reg_n_0_[35] ; + wire \skid_buffer_reg_n_0_[36] ; + wire \skid_buffer_reg_n_0_[38] ; + wire \skid_buffer_reg_n_0_[39] ; + wire \skid_buffer_reg_n_0_[3] ; + wire \skid_buffer_reg_n_0_[44] ; + wire \skid_buffer_reg_n_0_[45] ; + wire \skid_buffer_reg_n_0_[46] ; + wire \skid_buffer_reg_n_0_[47] ; + wire \skid_buffer_reg_n_0_[4] ; + wire \skid_buffer_reg_n_0_[50] ; + wire \skid_buffer_reg_n_0_[51] ; + wire \skid_buffer_reg_n_0_[52] ; + wire \skid_buffer_reg_n_0_[53] ; + wire \skid_buffer_reg_n_0_[54] ; + wire \skid_buffer_reg_n_0_[55] ; + wire \skid_buffer_reg_n_0_[56] ; + wire \skid_buffer_reg_n_0_[57] ; + wire \skid_buffer_reg_n_0_[58] ; + wire \skid_buffer_reg_n_0_[59] ; + wire \skid_buffer_reg_n_0_[5] ; + wire \skid_buffer_reg_n_0_[60] ; + wire \skid_buffer_reg_n_0_[61] ; + wire \skid_buffer_reg_n_0_[6] ; + wire \skid_buffer_reg_n_0_[7] ; + wire \skid_buffer_reg_n_0_[8] ; + wire \skid_buffer_reg_n_0_[9] ; + wire \wrap_boundary_axaddr_r[3]_i_2__0_n_0 ; + wire [3:3]\NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED ; + + (* inverted = "yes" *) + FDRE #( + .INIT(1'b1)) + \aresetn_d_reg[1]_inv + (.C(aclk), + .CE(1'b1), + .D(\aresetn_d_reg[1]_inv_1 ), + .Q(\aresetn_d_reg[1]_inv_0 ), + .R(1'b0)); + LUT3 #( + .INIT(8'h6A)) + \axaddr_incr[3]_i_11__0 + (.I0(\m_axi_araddr[11] [3]), + .I1(Q[35]), + .I2(Q[36]), + .O(\axaddr_incr_reg[3] [3])); + LUT3 #( + .INIT(8'hA6)) + \axaddr_incr[3]_i_12__0 + (.I0(\m_axi_araddr[11] [2]), + .I1(Q[36]), + .I2(Q[35]), + .O(\axaddr_incr_reg[3] [2])); + LUT3 #( + .INIT(8'hA6)) + \axaddr_incr[3]_i_13__0 + (.I0(\m_axi_araddr[11] [1]), + .I1(Q[35]), + .I2(Q[36]), + .O(\axaddr_incr_reg[3] [1])); + LUT3 #( + .INIT(8'hA9)) + \axaddr_incr[3]_i_14__0 + (.I0(\m_axi_araddr[11] [0]), + .I1(Q[35]), + .I2(Q[36]), + .O(\axaddr_incr_reg[3] [0])); + LUT3 #( + .INIT(8'h2A)) + \axaddr_incr[3]_i_4__0 + (.I0(Q[2]), + .I1(Q[35]), + .I2(Q[36]), + .O(\axaddr_incr[3]_i_4__0_n_0 )); + LUT2 #( + .INIT(4'h2)) + \axaddr_incr[3]_i_5__0 + (.I0(Q[1]), + .I1(Q[36]), + .O(\axaddr_incr[3]_i_5__0_n_0 )); + LUT3 #( + .INIT(8'h02)) + \axaddr_incr[3]_i_6__0 + (.I0(Q[0]), + .I1(Q[35]), + .I2(Q[36]), + .O(\axaddr_incr[3]_i_6__0_n_0 )); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \axaddr_incr_reg[11]_i_3__0 + (.CI(\axaddr_incr_reg[7]_i_2__0_n_0 ), + .CO({\NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_3__0_n_1 ,\axaddr_incr_reg[11]_i_3__0_n_2 ,\axaddr_incr_reg[11]_i_3__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(O), + .S(Q[11:8])); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \axaddr_incr_reg[3]_i_2__0 + (.CI(1'b0), + .CO({\axaddr_incr_reg[3]_i_2__0_n_0 ,\axaddr_incr_reg[3]_i_2__0_n_1 ,\axaddr_incr_reg[3]_i_2__0_n_2 ,\axaddr_incr_reg[3]_i_2__0_n_3 }), + .CYINIT(1'b0), + .DI({Q[3],\axaddr_incr[3]_i_4__0_n_0 ,\axaddr_incr[3]_i_5__0_n_0 ,\axaddr_incr[3]_i_6__0_n_0 }), + .O(\m_payload_i_reg[3]_0 ), + .S(\axaddr_incr_reg[3]_0 )); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \axaddr_incr_reg[7]_i_2__0 + (.CI(\axaddr_incr_reg[3]_i_2__0_n_0 ), + .CO({\axaddr_incr_reg[7]_i_2__0_n_0 ,\axaddr_incr_reg[7]_i_2__0_n_1 ,\axaddr_incr_reg[7]_i_2__0_n_2 ,\axaddr_incr_reg[7]_i_2__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\m_payload_i_reg[7]_0 ), + .S(Q[7:4])); + LUT6 #( + .INIT(64'hCCAAF0FFCCAAF000)) + \axaddr_offset_r[0]_i_2__0 + (.I0(Q[1]), + .I1(Q[3]), + .I2(Q[2]), + .I3(Q[36]), + .I4(Q[35]), + .I5(Q[0]), + .O(\m_payload_i_reg[1]_0 )); + LUT5 #( + .INIT(32'h30800080)) + \axaddr_offset_r[1]_i_2__0 + (.I0(Q[2]), + .I1(Q[35]), + .I2(Q[39]), + .I3(Q[36]), + .I4(Q[3]), + .O(\m_payload_i_reg[2]_1 )); + LUT5 #( + .INIT(32'hC0000088)) + \axaddr_offset_r[1]_i_3__0 + (.I0(Q[1]), + .I1(Q[39]), + .I2(Q[4]), + .I3(Q[36]), + .I4(Q[35]), + .O(\m_payload_i_reg[1]_1 )); + LUT5 #( + .INIT(32'hC0008800)) + \axaddr_offset_r[2]_i_2__0 + (.I0(Q[4]), + .I1(Q[40]), + .I2(Q[5]), + .I3(Q[36]), + .I4(Q[35]), + .O(\m_payload_i_reg[4]_0 )); + LUT5 #( + .INIT(32'hFF3FFF77)) + \axaddr_offset_r[2]_i_3__0 + (.I0(Q[2]), + .I1(Q[40]), + .I2(Q[3]), + .I3(Q[36]), + .I4(Q[35]), + .O(\m_payload_i_reg[2]_0 )); + LUT6 #( + .INIT(64'h5533000F5533FF0F)) + \axaddr_offset_r[3]_i_2__0 + (.I0(Q[6]), + .I1(Q[5]), + .I2(Q[3]), + .I3(Q[35]), + .I4(Q[36]), + .I5(Q[4]), + .O(\m_payload_i_reg[6]_0 )); + LUT3 #( + .INIT(8'h6A)) + \axaddr_wrap[3]_i_3__0 + (.I0(\m_axi_araddr[11]_0 [3]), + .I1(Q[35]), + .I2(Q[36]), + .O(\axaddr_wrap_reg[3] [3])); + LUT3 #( + .INIT(8'hA6)) + \axaddr_wrap[3]_i_4__0 + (.I0(\m_axi_araddr[11]_0 [2]), + .I1(Q[36]), + .I2(Q[35]), + .O(\axaddr_wrap_reg[3] [2])); + LUT3 #( + .INIT(8'hA6)) + \axaddr_wrap[3]_i_5__0 + (.I0(\m_axi_araddr[11]_0 [1]), + .I1(Q[35]), + .I2(Q[36]), + .O(\axaddr_wrap_reg[3] [1])); + LUT3 #( + .INIT(8'hA9)) + \axaddr_wrap[3]_i_6__0 + (.I0(\m_axi_araddr[11]_0 [0]), + .I1(Q[35]), + .I2(Q[36]), + .O(\axaddr_wrap_reg[3] [0])); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT4 #( + .INIT(16'h0080)) + \axlen_cnt[3]_i_3 + (.I0(Q[41]), + .I1(si_rs_arvalid), + .I2(\axlen_cnt_reg[3] [0]), + .I3(\axlen_cnt_reg[3] [1]), + .O(\m_payload_i_reg[47]_0 )); + LUT6 #( + .INIT(64'hCACAFFC0CACACACA)) + \m_axi_araddr[0]_INST_0 + (.I0(Q[0]), + .I1(\m_axi_araddr[11] [0]), + .I2(\m_axi_araddr[11]_INST_0_i_1_n_0 ), + .I3(\m_axi_araddr[11]_0 [0]), + .I4(\m_axi_araddr[11]_1 ), + .I5(Q[37]), + .O(m_axi_araddr[0])); + LUT6 #( + .INIT(64'hCACAFFC0CACACACA)) + \m_axi_araddr[10]_INST_0 + (.I0(Q[10]), + .I1(\m_axi_araddr[11] [10]), + .I2(\m_axi_araddr[11]_INST_0_i_1_n_0 ), + .I3(\m_axi_araddr[11]_0 [10]), + .I4(\m_axi_araddr[11]_1 ), + .I5(Q[37]), + .O(m_axi_araddr[10])); + LUT6 #( + .INIT(64'hCACAFFC0CACACACA)) + \m_axi_araddr[11]_INST_0 + (.I0(Q[11]), + .I1(\m_axi_araddr[11] [11]), + .I2(\m_axi_araddr[11]_INST_0_i_1_n_0 ), + .I3(\m_axi_araddr[11]_0 [11]), + .I4(\m_axi_araddr[11]_1 ), + .I5(Q[37]), + .O(m_axi_araddr[11])); + LUT3 #( + .INIT(8'h04)) + \m_axi_araddr[11]_INST_0_i_1 + (.I0(Q[37]), + .I1(\m_payload_i_reg_n_0_[38] ), + .I2(sel_first_1), + .O(\m_axi_araddr[11]_INST_0_i_1_n_0 )); + LUT6 #( + .INIT(64'hCACAFFC0CACACACA)) + \m_axi_araddr[1]_INST_0 + (.I0(Q[1]), + .I1(\m_axi_araddr[11] [1]), + .I2(\m_axi_araddr[11]_INST_0_i_1_n_0 ), + .I3(\m_axi_araddr[11]_0 [1]), + .I4(\m_axi_araddr[11]_1 ), + .I5(Q[37]), + .O(m_axi_araddr[1])); + LUT6 #( + .INIT(64'hFFFF0C00ACAAACAA)) + \m_axi_araddr[2]_INST_0 + (.I0(Q[2]), + .I1(\m_axi_araddr[11]_0 [2]), + .I2(\m_axi_araddr[11]_1 ), + .I3(Q[37]), + .I4(\m_axi_araddr[11] [2]), + .I5(\m_axi_araddr[11]_INST_0_i_1_n_0 ), + .O(m_axi_araddr[2])); + LUT6 #( + .INIT(64'hCACAFFC0CACACACA)) + \m_axi_araddr[3]_INST_0 + (.I0(Q[3]), + .I1(\m_axi_araddr[11] [3]), + .I2(\m_axi_araddr[11]_INST_0_i_1_n_0 ), + .I3(\m_axi_araddr[11]_0 [3]), + .I4(\m_axi_araddr[11]_1 ), + .I5(Q[37]), + .O(m_axi_araddr[3])); + LUT6 #( + .INIT(64'hCACAFFC0CACACACA)) + \m_axi_araddr[4]_INST_0 + (.I0(Q[4]), + .I1(\m_axi_araddr[11] [4]), + .I2(\m_axi_araddr[11]_INST_0_i_1_n_0 ), + .I3(\m_axi_araddr[11]_0 [4]), + .I4(\m_axi_araddr[11]_1 ), + .I5(Q[37]), + .O(m_axi_araddr[4])); + LUT6 #( + .INIT(64'hCACAFFC0CACACACA)) + \m_axi_araddr[5]_INST_0 + (.I0(Q[5]), + .I1(\m_axi_araddr[11] [5]), + .I2(\m_axi_araddr[11]_INST_0_i_1_n_0 ), + .I3(\m_axi_araddr[11]_0 [5]), + .I4(\m_axi_araddr[11]_1 ), + .I5(Q[37]), + .O(m_axi_araddr[5])); + LUT6 #( + .INIT(64'hFFFF0C00ACAAACAA)) + \m_axi_araddr[6]_INST_0 + (.I0(Q[6]), + .I1(\m_axi_araddr[11]_0 [6]), + .I2(\m_axi_araddr[11]_1 ), + .I3(Q[37]), + .I4(\m_axi_araddr[11] [6]), + .I5(\m_axi_araddr[11]_INST_0_i_1_n_0 ), + .O(m_axi_araddr[6])); + LUT6 #( + .INIT(64'hCACAFFC0CACACACA)) + \m_axi_araddr[7]_INST_0 + (.I0(Q[7]), + .I1(\m_axi_araddr[11] [7]), + .I2(\m_axi_araddr[11]_INST_0_i_1_n_0 ), + .I3(\m_axi_araddr[11]_0 [7]), + .I4(\m_axi_araddr[11]_1 ), + .I5(Q[37]), + .O(m_axi_araddr[7])); + LUT6 #( + .INIT(64'hFFFF0C00ACAAACAA)) + \m_axi_araddr[8]_INST_0 + (.I0(Q[8]), + .I1(\m_axi_araddr[11]_0 [8]), + .I2(\m_axi_araddr[11]_1 ), + .I3(Q[37]), + .I4(\m_axi_araddr[11] [8]), + .I5(\m_axi_araddr[11]_INST_0_i_1_n_0 ), + .O(m_axi_araddr[8])); + LUT6 #( + .INIT(64'hCACAFFC0CACACACA)) + \m_axi_araddr[9]_INST_0 + (.I0(Q[9]), + .I1(\m_axi_araddr[11] [9]), + .I2(\m_axi_araddr[11]_INST_0_i_1_n_0 ), + .I3(\m_axi_araddr[11]_0 [9]), + .I4(\m_axi_araddr[11]_1 ), + .I5(Q[37]), + .O(m_axi_araddr[9])); + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[0]_i_1__0 + (.I0(s_axi_araddr[0]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[0] ), + .O(\m_payload_i[0]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair44" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[10]_i_1__0 + (.I0(s_axi_araddr[10]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[10] ), + .O(\m_payload_i[10]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair43" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[11]_i_1__0 + (.I0(s_axi_araddr[11]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[11] ), + .O(\m_payload_i[11]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair43" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[12]_i_1__0 + (.I0(s_axi_araddr[12]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[12] ), + .O(\m_payload_i[12]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair42" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[13]_i_1__1 + (.I0(s_axi_araddr[13]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[13] ), + .O(\m_payload_i[13]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair42" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[14]_i_1__0 + (.I0(s_axi_araddr[14]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[14] ), + .O(\m_payload_i[14]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair41" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[15]_i_1__0 + (.I0(s_axi_araddr[15]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[15] ), + .O(\m_payload_i[15]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair41" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[16]_i_1__0 + (.I0(s_axi_araddr[16]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[16] ), + .O(\m_payload_i[16]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair40" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[17]_i_1__0 + (.I0(s_axi_araddr[17]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[17] ), + .O(\m_payload_i[17]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair40" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[18]_i_1__0 + (.I0(s_axi_araddr[18]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[18] ), + .O(\m_payload_i[18]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair39" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[19]_i_1__0 + (.I0(s_axi_araddr[19]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[19] ), + .O(\m_payload_i[19]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair48" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[1]_i_1__0 + (.I0(s_axi_araddr[1]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[1] ), + .O(\m_payload_i[1]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair39" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[20]_i_1__0 + (.I0(s_axi_araddr[20]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[20] ), + .O(\m_payload_i[20]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair38" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[21]_i_1__0 + (.I0(s_axi_araddr[21]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[21] ), + .O(\m_payload_i[21]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair38" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[22]_i_1__0 + (.I0(s_axi_araddr[22]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[22] ), + .O(\m_payload_i[22]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair37" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[23]_i_1__0 + (.I0(s_axi_araddr[23]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[23] ), + .O(\m_payload_i[23]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair37" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[24]_i_1__0 + (.I0(s_axi_araddr[24]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[24] ), + .O(\m_payload_i[24]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[25]_i_1__0 + (.I0(s_axi_araddr[25]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[25] ), + .O(\m_payload_i[25]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[26]_i_1__0 + (.I0(s_axi_araddr[26]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[26] ), + .O(\m_payload_i[26]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[27]_i_1__0 + (.I0(s_axi_araddr[27]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[27] ), + .O(\m_payload_i[27]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[28]_i_1__0 + (.I0(s_axi_araddr[28]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[28] ), + .O(\m_payload_i[28]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[29]_i_1__0 + (.I0(s_axi_araddr[29]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[29] ), + .O(\m_payload_i[29]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair48" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[2]_i_1__0 + (.I0(s_axi_araddr[2]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[2] ), + .O(\m_payload_i[2]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[30]_i_1__0 + (.I0(s_axi_araddr[30]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[30] ), + .O(\m_payload_i[30]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[31]_i_2__0 + (.I0(s_axi_araddr[31]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[31] ), + .O(\m_payload_i[31]_i_2__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[32]_i_1__0 + (.I0(s_axi_arprot[0]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[32] ), + .O(\m_payload_i[32]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[33]_i_1__0 + (.I0(s_axi_arprot[1]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[33] ), + .O(\m_payload_i[33]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[34]_i_1__0 + (.I0(s_axi_arprot[2]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[34] ), + .O(\m_payload_i[34]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[35]_i_1__0 + (.I0(s_axi_arsize[0]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[35] ), + .O(\m_payload_i[35]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[36]_i_1__0 + (.I0(s_axi_arsize[1]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[36] ), + .O(\m_payload_i[36]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[38]_i_1__0 + (.I0(s_axi_arburst[0]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[38] ), + .O(\m_payload_i[38]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[39]_i_1__0 + (.I0(s_axi_arburst[1]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[39] ), + .O(\m_payload_i[39]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair47" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[3]_i_1__0 + (.I0(s_axi_araddr[3]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[3] ), + .O(\m_payload_i[3]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[44]_i_1__0 + (.I0(s_axi_arlen[0]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[44] ), + .O(\m_payload_i[44]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[45]_i_1__0 + (.I0(s_axi_arlen[1]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[45] ), + .O(\m_payload_i[45]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[46]_i_1__1 + (.I0(s_axi_arlen[2]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[46] ), + .O(\m_payload_i[46]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[47]_i_1__0 + (.I0(s_axi_arlen[3]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[47] ), + .O(\m_payload_i[47]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair47" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[4]_i_1__0 + (.I0(s_axi_araddr[4]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[4] ), + .O(\m_payload_i[4]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[50]_i_1__0 + (.I0(s_axi_arid[0]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[50] ), + .O(\m_payload_i[50]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[51]_i_1__0 + (.I0(s_axi_arid[1]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[51] ), + .O(\m_payload_i[51]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[52]_i_1__0 + (.I0(s_axi_arid[2]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[52] ), + .O(\m_payload_i[52]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[53]_i_1__0 + (.I0(s_axi_arid[3]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[53] ), + .O(\m_payload_i[53]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[54]_i_1__0 + (.I0(s_axi_arid[4]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[54] ), + .O(\m_payload_i[54]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[55]_i_1__0 + (.I0(s_axi_arid[5]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[55] ), + .O(\m_payload_i[55]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[56]_i_1__0 + (.I0(s_axi_arid[6]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[56] ), + .O(\m_payload_i[56]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[57]_i_1__0 + (.I0(s_axi_arid[7]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[57] ), + .O(\m_payload_i[57]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[58]_i_1__0 + (.I0(s_axi_arid[8]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[58] ), + .O(\m_payload_i[58]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[59]_i_1__0 + (.I0(s_axi_arid[9]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[59] ), + .O(\m_payload_i[59]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair46" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[5]_i_1__0 + (.I0(s_axi_araddr[5]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[5] ), + .O(\m_payload_i[5]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[60]_i_1__0 + (.I0(s_axi_arid[10]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[60] ), + .O(\m_payload_i[60]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[61]_i_1__0 + (.I0(s_axi_arid[11]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[61] ), + .O(\m_payload_i[61]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair46" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[6]_i_1__0 + (.I0(s_axi_araddr[6]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[6] ), + .O(\m_payload_i[6]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair45" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[7]_i_1__0 + (.I0(s_axi_araddr[7]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[7] ), + .O(\m_payload_i[7]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair45" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[8]_i_1__0 + (.I0(s_axi_araddr[8]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[8] ), + .O(\m_payload_i[8]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair44" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[9]_i_1__0 + (.I0(s_axi_araddr[9]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[9] ), + .O(\m_payload_i[9]_i_1__0_n_0 )); + FDRE \m_payload_i_reg[0] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[0]_i_1__0_n_0 ), + .Q(Q[0]), + .R(1'b0)); + FDRE \m_payload_i_reg[10] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[10]_i_1__0_n_0 ), + .Q(Q[10]), + .R(1'b0)); + FDRE \m_payload_i_reg[11] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[11]_i_1__0_n_0 ), + .Q(Q[11]), + .R(1'b0)); + FDRE \m_payload_i_reg[12] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[12]_i_1__0_n_0 ), + .Q(Q[12]), + .R(1'b0)); + FDRE \m_payload_i_reg[13] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[13]_i_1__1_n_0 ), + .Q(Q[13]), + .R(1'b0)); + FDRE \m_payload_i_reg[14] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[14]_i_1__0_n_0 ), + .Q(Q[14]), + .R(1'b0)); + FDRE \m_payload_i_reg[15] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[15]_i_1__0_n_0 ), + .Q(Q[15]), + .R(1'b0)); + FDRE \m_payload_i_reg[16] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[16]_i_1__0_n_0 ), + .Q(Q[16]), + .R(1'b0)); + FDRE \m_payload_i_reg[17] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[17]_i_1__0_n_0 ), + .Q(Q[17]), + .R(1'b0)); + FDRE \m_payload_i_reg[18] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[18]_i_1__0_n_0 ), + .Q(Q[18]), + .R(1'b0)); + FDRE \m_payload_i_reg[19] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[19]_i_1__0_n_0 ), + .Q(Q[19]), + .R(1'b0)); + FDRE \m_payload_i_reg[1] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[1]_i_1__0_n_0 ), + .Q(Q[1]), + .R(1'b0)); + FDRE \m_payload_i_reg[20] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[20]_i_1__0_n_0 ), + .Q(Q[20]), + .R(1'b0)); + FDRE \m_payload_i_reg[21] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[21]_i_1__0_n_0 ), + .Q(Q[21]), + .R(1'b0)); + FDRE \m_payload_i_reg[22] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[22]_i_1__0_n_0 ), + .Q(Q[22]), + .R(1'b0)); + FDRE \m_payload_i_reg[23] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[23]_i_1__0_n_0 ), + .Q(Q[23]), + .R(1'b0)); + FDRE \m_payload_i_reg[24] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[24]_i_1__0_n_0 ), + .Q(Q[24]), + .R(1'b0)); + FDRE \m_payload_i_reg[25] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[25]_i_1__0_n_0 ), + .Q(Q[25]), + .R(1'b0)); + FDRE \m_payload_i_reg[26] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[26]_i_1__0_n_0 ), + .Q(Q[26]), + .R(1'b0)); + FDRE \m_payload_i_reg[27] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[27]_i_1__0_n_0 ), + .Q(Q[27]), + .R(1'b0)); + FDRE \m_payload_i_reg[28] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[28]_i_1__0_n_0 ), + .Q(Q[28]), + .R(1'b0)); + FDRE \m_payload_i_reg[29] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[29]_i_1__0_n_0 ), + .Q(Q[29]), + .R(1'b0)); + FDRE \m_payload_i_reg[2] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[2]_i_1__0_n_0 ), + .Q(Q[2]), + .R(1'b0)); + FDRE \m_payload_i_reg[30] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[30]_i_1__0_n_0 ), + .Q(Q[30]), + .R(1'b0)); + FDRE \m_payload_i_reg[31] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[31]_i_2__0_n_0 ), + .Q(Q[31]), + .R(1'b0)); + FDRE \m_payload_i_reg[32] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[32]_i_1__0_n_0 ), + .Q(Q[32]), + .R(1'b0)); + FDRE \m_payload_i_reg[33] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[33]_i_1__0_n_0 ), + .Q(Q[33]), + .R(1'b0)); + FDRE \m_payload_i_reg[34] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[34]_i_1__0_n_0 ), + .Q(Q[34]), + .R(1'b0)); + FDRE \m_payload_i_reg[35] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[35]_i_1__0_n_0 ), + .Q(Q[35]), + .R(1'b0)); + FDRE \m_payload_i_reg[36] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[36]_i_1__0_n_0 ), + .Q(Q[36]), + .R(1'b0)); + FDRE \m_payload_i_reg[38] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[38]_i_1__0_n_0 ), + .Q(\m_payload_i_reg_n_0_[38] ), + .R(1'b0)); + FDRE \m_payload_i_reg[39] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[39]_i_1__0_n_0 ), + .Q(Q[37]), + .R(1'b0)); + FDRE \m_payload_i_reg[3] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[3]_i_1__0_n_0 ), + .Q(Q[3]), + .R(1'b0)); + FDRE \m_payload_i_reg[44] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[44]_i_1__0_n_0 ), + .Q(Q[38]), + .R(1'b0)); + FDRE \m_payload_i_reg[45] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[45]_i_1__0_n_0 ), + .Q(Q[39]), + .R(1'b0)); + FDRE \m_payload_i_reg[46] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[46]_i_1__1_n_0 ), + .Q(Q[40]), + .R(1'b0)); + FDRE \m_payload_i_reg[47] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[47]_i_1__0_n_0 ), + .Q(Q[41]), + .R(1'b0)); + FDRE \m_payload_i_reg[4] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[4]_i_1__0_n_0 ), + .Q(Q[4]), + .R(1'b0)); + FDRE \m_payload_i_reg[50] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[50]_i_1__0_n_0 ), + .Q(Q[42]), + .R(1'b0)); + FDRE \m_payload_i_reg[51] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[51]_i_1__0_n_0 ), + .Q(Q[43]), + .R(1'b0)); + FDRE \m_payload_i_reg[52] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[52]_i_1__0_n_0 ), + .Q(Q[44]), + .R(1'b0)); + FDRE \m_payload_i_reg[53] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[53]_i_1__0_n_0 ), + .Q(Q[45]), + .R(1'b0)); + FDRE \m_payload_i_reg[54] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[54]_i_1__0_n_0 ), + .Q(Q[46]), + .R(1'b0)); + FDRE \m_payload_i_reg[55] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[55]_i_1__0_n_0 ), + .Q(Q[47]), + .R(1'b0)); + FDRE \m_payload_i_reg[56] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[56]_i_1__0_n_0 ), + .Q(Q[48]), + .R(1'b0)); + FDRE \m_payload_i_reg[57] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[57]_i_1__0_n_0 ), + .Q(Q[49]), + .R(1'b0)); + FDRE \m_payload_i_reg[58] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[58]_i_1__0_n_0 ), + .Q(Q[50]), + .R(1'b0)); + FDRE \m_payload_i_reg[59] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[59]_i_1__0_n_0 ), + .Q(Q[51]), + .R(1'b0)); + FDRE \m_payload_i_reg[5] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[5]_i_1__0_n_0 ), + .Q(Q[5]), + .R(1'b0)); + FDRE \m_payload_i_reg[60] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[60]_i_1__0_n_0 ), + .Q(Q[52]), + .R(1'b0)); + FDRE \m_payload_i_reg[61] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[61]_i_1__0_n_0 ), + .Q(Q[53]), + .R(1'b0)); + FDRE \m_payload_i_reg[6] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[6]_i_1__0_n_0 ), + .Q(Q[6]), + .R(1'b0)); + FDRE \m_payload_i_reg[7] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[7]_i_1__0_n_0 ), + .Q(Q[7]), + .R(1'b0)); + FDRE \m_payload_i_reg[8] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[8]_i_1__0_n_0 ), + .Q(Q[8]), + .R(1'b0)); + FDRE \m_payload_i_reg[9] + (.C(aclk), + .CE(\m_payload_i_reg[0]_0 ), + .D(\m_payload_i[9]_i_1__0_n_0 ), + .Q(Q[9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + m_valid_i_reg + (.C(aclk), + .CE(1'b1), + .D(m_valid_i0), + .Q(si_rs_arvalid), + .R(\aresetn_d_reg[1]_inv_0 )); + LUT5 #( + .INIT(32'h0000FFFE)) + next_pending_r_i_3__0 + (.I0(Q[39]), + .I1(Q[38]), + .I2(Q[40]), + .I3(Q[41]), + .I4(next_pending_r_reg), + .O(\m_payload_i_reg[45]_0 )); + FDRE #( + .INIT(1'b0)) + s_ready_i_reg + (.C(aclk), + .CE(1'b1), + .D(s_ready_i0), + .Q(s_ready_i_reg_0), + .R(s_ready_i_reg_1)); + FDRE \skid_buffer_reg[0] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[0]), + .Q(\skid_buffer_reg_n_0_[0] ), + .R(1'b0)); + FDRE \skid_buffer_reg[10] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[10]), + .Q(\skid_buffer_reg_n_0_[10] ), + .R(1'b0)); + FDRE \skid_buffer_reg[11] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[11]), + .Q(\skid_buffer_reg_n_0_[11] ), + .R(1'b0)); + FDRE \skid_buffer_reg[12] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[12]), + .Q(\skid_buffer_reg_n_0_[12] ), + .R(1'b0)); + FDRE \skid_buffer_reg[13] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[13]), + .Q(\skid_buffer_reg_n_0_[13] ), + .R(1'b0)); + FDRE \skid_buffer_reg[14] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[14]), + .Q(\skid_buffer_reg_n_0_[14] ), + .R(1'b0)); + FDRE \skid_buffer_reg[15] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[15]), + .Q(\skid_buffer_reg_n_0_[15] ), + .R(1'b0)); + FDRE \skid_buffer_reg[16] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[16]), + .Q(\skid_buffer_reg_n_0_[16] ), + .R(1'b0)); + FDRE \skid_buffer_reg[17] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[17]), + .Q(\skid_buffer_reg_n_0_[17] ), + .R(1'b0)); + FDRE \skid_buffer_reg[18] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[18]), + .Q(\skid_buffer_reg_n_0_[18] ), + .R(1'b0)); + FDRE \skid_buffer_reg[19] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[19]), + .Q(\skid_buffer_reg_n_0_[19] ), + .R(1'b0)); + FDRE \skid_buffer_reg[1] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[1]), + .Q(\skid_buffer_reg_n_0_[1] ), + .R(1'b0)); + FDRE \skid_buffer_reg[20] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[20]), + .Q(\skid_buffer_reg_n_0_[20] ), + .R(1'b0)); + FDRE \skid_buffer_reg[21] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[21]), + .Q(\skid_buffer_reg_n_0_[21] ), + .R(1'b0)); + FDRE \skid_buffer_reg[22] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[22]), + .Q(\skid_buffer_reg_n_0_[22] ), + .R(1'b0)); + FDRE \skid_buffer_reg[23] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[23]), + .Q(\skid_buffer_reg_n_0_[23] ), + .R(1'b0)); + FDRE \skid_buffer_reg[24] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[24]), + .Q(\skid_buffer_reg_n_0_[24] ), + .R(1'b0)); + FDRE \skid_buffer_reg[25] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[25]), + .Q(\skid_buffer_reg_n_0_[25] ), + .R(1'b0)); + FDRE \skid_buffer_reg[26] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[26]), + .Q(\skid_buffer_reg_n_0_[26] ), + .R(1'b0)); + FDRE \skid_buffer_reg[27] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[27]), + .Q(\skid_buffer_reg_n_0_[27] ), + .R(1'b0)); + FDRE \skid_buffer_reg[28] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[28]), + .Q(\skid_buffer_reg_n_0_[28] ), + .R(1'b0)); + FDRE \skid_buffer_reg[29] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[29]), + .Q(\skid_buffer_reg_n_0_[29] ), + .R(1'b0)); + FDRE \skid_buffer_reg[2] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[2]), + .Q(\skid_buffer_reg_n_0_[2] ), + .R(1'b0)); + FDRE \skid_buffer_reg[30] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[30]), + .Q(\skid_buffer_reg_n_0_[30] ), + .R(1'b0)); + FDRE \skid_buffer_reg[31] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[31]), + .Q(\skid_buffer_reg_n_0_[31] ), + .R(1'b0)); + FDRE \skid_buffer_reg[32] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_arprot[0]), + .Q(\skid_buffer_reg_n_0_[32] ), + .R(1'b0)); + FDRE \skid_buffer_reg[33] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_arprot[1]), + .Q(\skid_buffer_reg_n_0_[33] ), + .R(1'b0)); + FDRE \skid_buffer_reg[34] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_arprot[2]), + .Q(\skid_buffer_reg_n_0_[34] ), + .R(1'b0)); + FDRE \skid_buffer_reg[35] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_arsize[0]), + .Q(\skid_buffer_reg_n_0_[35] ), + .R(1'b0)); + FDRE \skid_buffer_reg[36] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_arsize[1]), + .Q(\skid_buffer_reg_n_0_[36] ), + .R(1'b0)); + FDRE \skid_buffer_reg[38] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_arburst[0]), + .Q(\skid_buffer_reg_n_0_[38] ), + .R(1'b0)); + FDRE \skid_buffer_reg[39] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_arburst[1]), + .Q(\skid_buffer_reg_n_0_[39] ), + .R(1'b0)); + FDRE \skid_buffer_reg[3] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[3]), + .Q(\skid_buffer_reg_n_0_[3] ), + .R(1'b0)); + FDRE \skid_buffer_reg[44] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_arlen[0]), + .Q(\skid_buffer_reg_n_0_[44] ), + .R(1'b0)); + FDRE \skid_buffer_reg[45] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_arlen[1]), + .Q(\skid_buffer_reg_n_0_[45] ), + .R(1'b0)); + FDRE \skid_buffer_reg[46] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_arlen[2]), + .Q(\skid_buffer_reg_n_0_[46] ), + .R(1'b0)); + FDRE \skid_buffer_reg[47] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_arlen[3]), + .Q(\skid_buffer_reg_n_0_[47] ), + .R(1'b0)); + FDRE \skid_buffer_reg[4] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[4]), + .Q(\skid_buffer_reg_n_0_[4] ), + .R(1'b0)); + FDRE \skid_buffer_reg[50] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_arid[0]), + .Q(\skid_buffer_reg_n_0_[50] ), + .R(1'b0)); + FDRE \skid_buffer_reg[51] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_arid[1]), + .Q(\skid_buffer_reg_n_0_[51] ), + .R(1'b0)); + FDRE \skid_buffer_reg[52] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_arid[2]), + .Q(\skid_buffer_reg_n_0_[52] ), + .R(1'b0)); + FDRE \skid_buffer_reg[53] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_arid[3]), + .Q(\skid_buffer_reg_n_0_[53] ), + .R(1'b0)); + FDRE \skid_buffer_reg[54] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_arid[4]), + .Q(\skid_buffer_reg_n_0_[54] ), + .R(1'b0)); + FDRE \skid_buffer_reg[55] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_arid[5]), + .Q(\skid_buffer_reg_n_0_[55] ), + .R(1'b0)); + FDRE \skid_buffer_reg[56] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_arid[6]), + .Q(\skid_buffer_reg_n_0_[56] ), + .R(1'b0)); + FDRE \skid_buffer_reg[57] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_arid[7]), + .Q(\skid_buffer_reg_n_0_[57] ), + .R(1'b0)); + FDRE \skid_buffer_reg[58] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_arid[8]), + .Q(\skid_buffer_reg_n_0_[58] ), + .R(1'b0)); + FDRE \skid_buffer_reg[59] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_arid[9]), + .Q(\skid_buffer_reg_n_0_[59] ), + .R(1'b0)); + FDRE \skid_buffer_reg[5] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[5]), + .Q(\skid_buffer_reg_n_0_[5] ), + .R(1'b0)); + FDRE \skid_buffer_reg[60] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_arid[10]), + .Q(\skid_buffer_reg_n_0_[60] ), + .R(1'b0)); + FDRE \skid_buffer_reg[61] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_arid[11]), + .Q(\skid_buffer_reg_n_0_[61] ), + .R(1'b0)); + FDRE \skid_buffer_reg[6] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[6]), + .Q(\skid_buffer_reg_n_0_[6] ), + .R(1'b0)); + FDRE \skid_buffer_reg[7] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[7]), + .Q(\skid_buffer_reg_n_0_[7] ), + .R(1'b0)); + FDRE \skid_buffer_reg[8] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[8]), + .Q(\skid_buffer_reg_n_0_[8] ), + .R(1'b0)); + FDRE \skid_buffer_reg[9] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_araddr[9]), + .Q(\skid_buffer_reg_n_0_[9] ), + .R(1'b0)); + LUT4 #( + .INIT(16'hA8AA)) + \wrap_boundary_axaddr_r[0]_i_1__0 + (.I0(Q[0]), + .I1(Q[36]), + .I2(Q[35]), + .I3(Q[38]), + .O(\m_payload_i_reg[6]_1 [0])); + LUT5 #( + .INIT(32'hDDCF0000)) + \wrap_boundary_axaddr_r[1]_i_1__0 + (.I0(Q[38]), + .I1(Q[36]), + .I2(Q[39]), + .I3(Q[35]), + .I4(Q[1]), + .O(\m_payload_i_reg[6]_1 [1])); + LUT6 #( + .INIT(64'hA0A0202AAAAA202A)) + \wrap_boundary_axaddr_r[2]_i_1__0 + (.I0(Q[2]), + .I1(Q[38]), + .I2(Q[36]), + .I3(Q[40]), + .I4(Q[35]), + .I5(Q[39]), + .O(\m_payload_i_reg[6]_1 [2])); + LUT6 #( + .INIT(64'hFFFFFFFF00201030)) + \wrap_boundary_axaddr_r[3]_i_1__0 + (.I0(Q[36]), + .I1(Q[35]), + .I2(Q[3]), + .I3(Q[39]), + .I4(Q[41]), + .I5(\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ), + .O(\m_payload_i_reg[6]_1 [3])); + LUT5 #( + .INIT(32'h30500000)) + \wrap_boundary_axaddr_r[3]_i_2__0 + (.I0(Q[40]), + .I1(Q[38]), + .I2(Q[35]), + .I3(Q[36]), + .I4(Q[3]), + .O(\wrap_boundary_axaddr_r[3]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'h000A22AAAA0A22AA)) + \wrap_boundary_axaddr_r[4]_i_1__0 + (.I0(Q[4]), + .I1(Q[40]), + .I2(Q[41]), + .I3(Q[36]), + .I4(Q[35]), + .I5(Q[39]), + .O(\m_payload_i_reg[6]_1 [4])); + LUT5 #( + .INIT(32'h44CC0CCC)) + \wrap_boundary_axaddr_r[5]_i_1__0 + (.I0(Q[40]), + .I1(Q[5]), + .I2(Q[41]), + .I3(Q[36]), + .I4(Q[35]), + .O(\m_payload_i_reg[6]_1 [5])); + LUT4 #( + .INIT(16'h2AAA)) + \wrap_boundary_axaddr_r[6]_i_1__0 + (.I0(Q[6]), + .I1(Q[36]), + .I2(Q[35]), + .I3(Q[41]), + .O(\m_payload_i_reg[6]_1 [6])); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT5 #( + .INIT(32'h00004000)) + \wrap_second_len_r[3]_i_2__0 + (.I0(\axlen_cnt_reg[3] [1]), + .I1(\axlen_cnt_reg[3] [0]), + .I2(si_rs_arvalid), + .I3(Q[41]), + .I4(\m_payload_i_reg[6]_0 ), + .O(\FSM_sequential_state_reg[1] )); +endmodule + +(* ORIG_REF_NAME = "axi_register_slice_v2_1_29_axic_register_slice" *) +module NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axic_register_slice_0 + (s_ready_i_reg_0, + \aresetn_d_reg[0]_0 , + m_valid_i_reg_0, + S, + \m_payload_i_reg[61]_0 , + \axaddr_wrap_reg[3] , + axaddr_incr, + \m_payload_i_reg[45]_0 , + \FSM_sequential_state_reg[0] , + \m_payload_i_reg[5]_0 , + D, + \m_payload_i_reg[4]_0 , + \m_payload_i_reg[1]_0 , + \m_payload_i_reg[2]_0 , + \m_payload_i_reg[1]_1 , + \m_payload_i_reg[2]_1 , + m_axi_awaddr, + \aresetn_d_reg[0]_1 , + aclk, + m_valid_i_reg_1, + aresetn, + Q, + \m_axi_awaddr[11] , + b_push, + s_axi_awvalid, + \axaddr_incr_reg[3] , + next_pending_r_reg, + \wrap_second_len_r_reg[3] , + s_axi_awid, + s_axi_awlen, + s_axi_awburst, + s_axi_awsize, + s_axi_awprot, + s_axi_awaddr, + sel_first, + sel_first_0, + E); + output s_ready_i_reg_0; + output \aresetn_d_reg[0]_0 ; + output m_valid_i_reg_0; + output [3:0]S; + output [53:0]\m_payload_i_reg[61]_0 ; + output [3:0]\axaddr_wrap_reg[3] ; + output [11:0]axaddr_incr; + output \m_payload_i_reg[45]_0 ; + output \FSM_sequential_state_reg[0] ; + output \m_payload_i_reg[5]_0 ; + output [6:0]D; + output \m_payload_i_reg[4]_0 ; + output \m_payload_i_reg[1]_0 ; + output \m_payload_i_reg[2]_0 ; + output \m_payload_i_reg[1]_1 ; + output \m_payload_i_reg[2]_1 ; + output [11:0]m_axi_awaddr; + output \aresetn_d_reg[0]_1 ; + input aclk; + input m_valid_i_reg_1; + input aresetn; + input [11:0]Q; + input [11:0]\m_axi_awaddr[11] ; + input b_push; + input s_axi_awvalid; + input [3:0]\axaddr_incr_reg[3] ; + input next_pending_r_reg; + input [1:0]\wrap_second_len_r_reg[3] ; + input [11:0]s_axi_awid; + input [3:0]s_axi_awlen; + input [1:0]s_axi_awburst; + input [1:0]s_axi_awsize; + input [2:0]s_axi_awprot; + input [31:0]s_axi_awaddr; + input sel_first; + input sel_first_0; + input [0:0]E; + + wire [6:0]D; + wire [0:0]E; + wire \FSM_sequential_state_reg[0] ; + wire [11:0]Q; + wire [3:0]S; + wire aclk; + wire aresetn; + wire \aresetn_d_reg[0]_0 ; + wire \aresetn_d_reg[0]_1 ; + wire \aresetn_d_reg_n_0_[0] ; + wire [11:0]axaddr_incr; + wire \axaddr_incr[3]_i_4_n_0 ; + wire \axaddr_incr[3]_i_5_n_0 ; + wire \axaddr_incr[3]_i_6_n_0 ; + wire \axaddr_incr_reg[11]_i_3_n_1 ; + wire \axaddr_incr_reg[11]_i_3_n_2 ; + wire \axaddr_incr_reg[11]_i_3_n_3 ; + wire [3:0]\axaddr_incr_reg[3] ; + wire \axaddr_incr_reg[3]_i_2_n_0 ; + wire \axaddr_incr_reg[3]_i_2_n_1 ; + wire \axaddr_incr_reg[3]_i_2_n_2 ; + wire \axaddr_incr_reg[3]_i_2_n_3 ; + wire \axaddr_incr_reg[7]_i_2_n_0 ; + wire \axaddr_incr_reg[7]_i_2_n_1 ; + wire \axaddr_incr_reg[7]_i_2_n_2 ; + wire \axaddr_incr_reg[7]_i_2_n_3 ; + wire [3:0]\axaddr_wrap_reg[3] ; + wire b_push; + wire [11:0]m_axi_awaddr; + wire [11:0]\m_axi_awaddr[11] ; + wire \m_axi_awaddr[11]_INST_0_i_1_n_0 ; + wire \m_payload_i_reg[1]_0 ; + wire \m_payload_i_reg[1]_1 ; + wire \m_payload_i_reg[2]_0 ; + wire \m_payload_i_reg[2]_1 ; + wire \m_payload_i_reg[45]_0 ; + wire \m_payload_i_reg[4]_0 ; + wire \m_payload_i_reg[5]_0 ; + wire [53:0]\m_payload_i_reg[61]_0 ; + wire \m_payload_i_reg_n_0_[38] ; + wire m_valid_i0; + wire m_valid_i_reg_0; + wire m_valid_i_reg_1; + wire next_pending_r_reg; + wire [31:0]s_axi_awaddr; + wire [1:0]s_axi_awburst; + wire [11:0]s_axi_awid; + wire [3:0]s_axi_awlen; + wire [2:0]s_axi_awprot; + wire [1:0]s_axi_awsize; + wire s_axi_awvalid; + wire s_ready_i0; + wire s_ready_i_reg_0; + wire sel_first; + wire sel_first_0; + wire [61:0]skid_buffer; + wire \skid_buffer_reg_n_0_[0] ; + wire \skid_buffer_reg_n_0_[10] ; + wire \skid_buffer_reg_n_0_[11] ; + wire \skid_buffer_reg_n_0_[12] ; + wire \skid_buffer_reg_n_0_[13] ; + wire \skid_buffer_reg_n_0_[14] ; + wire \skid_buffer_reg_n_0_[15] ; + wire \skid_buffer_reg_n_0_[16] ; + wire \skid_buffer_reg_n_0_[17] ; + wire \skid_buffer_reg_n_0_[18] ; + wire \skid_buffer_reg_n_0_[19] ; + wire \skid_buffer_reg_n_0_[1] ; + wire \skid_buffer_reg_n_0_[20] ; + wire \skid_buffer_reg_n_0_[21] ; + wire \skid_buffer_reg_n_0_[22] ; + wire \skid_buffer_reg_n_0_[23] ; + wire \skid_buffer_reg_n_0_[24] ; + wire \skid_buffer_reg_n_0_[25] ; + wire \skid_buffer_reg_n_0_[26] ; + wire \skid_buffer_reg_n_0_[27] ; + wire \skid_buffer_reg_n_0_[28] ; + wire \skid_buffer_reg_n_0_[29] ; + wire \skid_buffer_reg_n_0_[2] ; + wire \skid_buffer_reg_n_0_[30] ; + wire \skid_buffer_reg_n_0_[31] ; + wire \skid_buffer_reg_n_0_[32] ; + wire \skid_buffer_reg_n_0_[33] ; + wire \skid_buffer_reg_n_0_[34] ; + wire \skid_buffer_reg_n_0_[35] ; + wire \skid_buffer_reg_n_0_[36] ; + wire \skid_buffer_reg_n_0_[38] ; + wire \skid_buffer_reg_n_0_[39] ; + wire \skid_buffer_reg_n_0_[3] ; + wire \skid_buffer_reg_n_0_[44] ; + wire \skid_buffer_reg_n_0_[45] ; + wire \skid_buffer_reg_n_0_[46] ; + wire \skid_buffer_reg_n_0_[47] ; + wire \skid_buffer_reg_n_0_[4] ; + wire \skid_buffer_reg_n_0_[50] ; + wire \skid_buffer_reg_n_0_[51] ; + wire \skid_buffer_reg_n_0_[52] ; + wire \skid_buffer_reg_n_0_[53] ; + wire \skid_buffer_reg_n_0_[54] ; + wire \skid_buffer_reg_n_0_[55] ; + wire \skid_buffer_reg_n_0_[56] ; + wire \skid_buffer_reg_n_0_[57] ; + wire \skid_buffer_reg_n_0_[58] ; + wire \skid_buffer_reg_n_0_[59] ; + wire \skid_buffer_reg_n_0_[5] ; + wire \skid_buffer_reg_n_0_[60] ; + wire \skid_buffer_reg_n_0_[61] ; + wire \skid_buffer_reg_n_0_[6] ; + wire \skid_buffer_reg_n_0_[7] ; + wire \skid_buffer_reg_n_0_[8] ; + wire \skid_buffer_reg_n_0_[9] ; + wire \wrap_boundary_axaddr_r[3]_i_2_n_0 ; + wire [1:0]\wrap_second_len_r_reg[3] ; + wire [3:3]\NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED ; + + LUT2 #( + .INIT(4'h7)) + \aresetn_d[1]_inv_i_1 + (.I0(\aresetn_d_reg_n_0_[0] ), + .I1(aresetn), + .O(\aresetn_d_reg[0]_1 )); + FDRE #( + .INIT(1'b0)) + \aresetn_d_reg[0] + (.C(aclk), + .CE(1'b1), + .D(aresetn), + .Q(\aresetn_d_reg_n_0_[0] ), + .R(1'b0)); + LUT3 #( + .INIT(8'h6A)) + \axaddr_incr[3]_i_11 + (.I0(Q[3]), + .I1(\m_payload_i_reg[61]_0 [35]), + .I2(\m_payload_i_reg[61]_0 [36]), + .O(S[3])); + LUT3 #( + .INIT(8'hA6)) + \axaddr_incr[3]_i_12 + (.I0(Q[2]), + .I1(\m_payload_i_reg[61]_0 [36]), + .I2(\m_payload_i_reg[61]_0 [35]), + .O(S[2])); + LUT3 #( + .INIT(8'hA6)) + \axaddr_incr[3]_i_13 + (.I0(Q[1]), + .I1(\m_payload_i_reg[61]_0 [35]), + .I2(\m_payload_i_reg[61]_0 [36]), + .O(S[1])); + LUT3 #( + .INIT(8'hA9)) + \axaddr_incr[3]_i_14 + (.I0(Q[0]), + .I1(\m_payload_i_reg[61]_0 [35]), + .I2(\m_payload_i_reg[61]_0 [36]), + .O(S[0])); + LUT3 #( + .INIT(8'h2A)) + \axaddr_incr[3]_i_4 + (.I0(\m_payload_i_reg[61]_0 [2]), + .I1(\m_payload_i_reg[61]_0 [35]), + .I2(\m_payload_i_reg[61]_0 [36]), + .O(\axaddr_incr[3]_i_4_n_0 )); + LUT2 #( + .INIT(4'h2)) + \axaddr_incr[3]_i_5 + (.I0(\m_payload_i_reg[61]_0 [1]), + .I1(\m_payload_i_reg[61]_0 [36]), + .O(\axaddr_incr[3]_i_5_n_0 )); + LUT3 #( + .INIT(8'h02)) + \axaddr_incr[3]_i_6 + (.I0(\m_payload_i_reg[61]_0 [0]), + .I1(\m_payload_i_reg[61]_0 [35]), + .I2(\m_payload_i_reg[61]_0 [36]), + .O(\axaddr_incr[3]_i_6_n_0 )); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \axaddr_incr_reg[11]_i_3 + (.CI(\axaddr_incr_reg[7]_i_2_n_0 ), + .CO({\NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_3_n_1 ,\axaddr_incr_reg[11]_i_3_n_2 ,\axaddr_incr_reg[11]_i_3_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(axaddr_incr[11:8]), + .S(\m_payload_i_reg[61]_0 [11:8])); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \axaddr_incr_reg[3]_i_2 + (.CI(1'b0), + .CO({\axaddr_incr_reg[3]_i_2_n_0 ,\axaddr_incr_reg[3]_i_2_n_1 ,\axaddr_incr_reg[3]_i_2_n_2 ,\axaddr_incr_reg[3]_i_2_n_3 }), + .CYINIT(1'b0), + .DI({\m_payload_i_reg[61]_0 [3],\axaddr_incr[3]_i_4_n_0 ,\axaddr_incr[3]_i_5_n_0 ,\axaddr_incr[3]_i_6_n_0 }), + .O(axaddr_incr[3:0]), + .S(\axaddr_incr_reg[3] )); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \axaddr_incr_reg[7]_i_2 + (.CI(\axaddr_incr_reg[3]_i_2_n_0 ), + .CO({\axaddr_incr_reg[7]_i_2_n_0 ,\axaddr_incr_reg[7]_i_2_n_1 ,\axaddr_incr_reg[7]_i_2_n_2 ,\axaddr_incr_reg[7]_i_2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(axaddr_incr[7:4]), + .S(\m_payload_i_reg[61]_0 [7:4])); + LUT6 #( + .INIT(64'hCCAAF0FFCCAAF000)) + \axaddr_offset_r[0]_i_2 + (.I0(\m_payload_i_reg[61]_0 [1]), + .I1(\m_payload_i_reg[61]_0 [3]), + .I2(\m_payload_i_reg[61]_0 [2]), + .I3(\m_payload_i_reg[61]_0 [36]), + .I4(\m_payload_i_reg[61]_0 [35]), + .I5(\m_payload_i_reg[61]_0 [0]), + .O(\m_payload_i_reg[1]_1 )); + LUT5 #( + .INIT(32'h30800080)) + \axaddr_offset_r[1]_i_2 + (.I0(\m_payload_i_reg[61]_0 [2]), + .I1(\m_payload_i_reg[61]_0 [35]), + .I2(\m_payload_i_reg[61]_0 [39]), + .I3(\m_payload_i_reg[61]_0 [36]), + .I4(\m_payload_i_reg[61]_0 [3]), + .O(\m_payload_i_reg[2]_1 )); + LUT5 #( + .INIT(32'hC0000088)) + \axaddr_offset_r[1]_i_3 + (.I0(\m_payload_i_reg[61]_0 [1]), + .I1(\m_payload_i_reg[61]_0 [39]), + .I2(\m_payload_i_reg[61]_0 [4]), + .I3(\m_payload_i_reg[61]_0 [36]), + .I4(\m_payload_i_reg[61]_0 [35]), + .O(\m_payload_i_reg[1]_0 )); + LUT5 #( + .INIT(32'hC0008800)) + \axaddr_offset_r[2]_i_2 + (.I0(\m_payload_i_reg[61]_0 [4]), + .I1(\m_payload_i_reg[61]_0 [40]), + .I2(\m_payload_i_reg[61]_0 [5]), + .I3(\m_payload_i_reg[61]_0 [36]), + .I4(\m_payload_i_reg[61]_0 [35]), + .O(\m_payload_i_reg[4]_0 )); + LUT5 #( + .INIT(32'hFF3FFF77)) + \axaddr_offset_r[2]_i_3 + (.I0(\m_payload_i_reg[61]_0 [2]), + .I1(\m_payload_i_reg[61]_0 [40]), + .I2(\m_payload_i_reg[61]_0 [3]), + .I3(\m_payload_i_reg[61]_0 [36]), + .I4(\m_payload_i_reg[61]_0 [35]), + .O(\m_payload_i_reg[2]_0 )); + LUT6 #( + .INIT(64'h33550F0033550FFF)) + \axaddr_offset_r[3]_i_2 + (.I0(\m_payload_i_reg[61]_0 [5]), + .I1(\m_payload_i_reg[61]_0 [6]), + .I2(\m_payload_i_reg[61]_0 [4]), + .I3(\m_payload_i_reg[61]_0 [35]), + .I4(\m_payload_i_reg[61]_0 [36]), + .I5(\m_payload_i_reg[61]_0 [3]), + .O(\m_payload_i_reg[5]_0 )); + LUT3 #( + .INIT(8'h6A)) + \axaddr_wrap[3]_i_3 + (.I0(\m_axi_awaddr[11] [3]), + .I1(\m_payload_i_reg[61]_0 [35]), + .I2(\m_payload_i_reg[61]_0 [36]), + .O(\axaddr_wrap_reg[3] [3])); + LUT3 #( + .INIT(8'hA6)) + \axaddr_wrap[3]_i_4 + (.I0(\m_axi_awaddr[11] [2]), + .I1(\m_payload_i_reg[61]_0 [36]), + .I2(\m_payload_i_reg[61]_0 [35]), + .O(\axaddr_wrap_reg[3] [2])); + LUT3 #( + .INIT(8'hA6)) + \axaddr_wrap[3]_i_5 + (.I0(\m_axi_awaddr[11] [1]), + .I1(\m_payload_i_reg[61]_0 [35]), + .I2(\m_payload_i_reg[61]_0 [36]), + .O(\axaddr_wrap_reg[3] [1])); + LUT3 #( + .INIT(8'hA9)) + \axaddr_wrap[3]_i_6 + (.I0(\m_axi_awaddr[11] [0]), + .I1(\m_payload_i_reg[61]_0 [35]), + .I2(\m_payload_i_reg[61]_0 [36]), + .O(\axaddr_wrap_reg[3] [0])); + LUT6 #( + .INIT(64'hCACAFFC0CACACACA)) + \m_axi_awaddr[0]_INST_0 + (.I0(\m_payload_i_reg[61]_0 [0]), + .I1(Q[0]), + .I2(\m_axi_awaddr[11]_INST_0_i_1_n_0 ), + .I3(\m_axi_awaddr[11] [0]), + .I4(sel_first), + .I5(\m_payload_i_reg[61]_0 [37]), + .O(m_axi_awaddr[0])); + LUT6 #( + .INIT(64'hCACAFFC0CACACACA)) + \m_axi_awaddr[10]_INST_0 + (.I0(\m_payload_i_reg[61]_0 [10]), + .I1(Q[10]), + .I2(\m_axi_awaddr[11]_INST_0_i_1_n_0 ), + .I3(\m_axi_awaddr[11] [10]), + .I4(sel_first), + .I5(\m_payload_i_reg[61]_0 [37]), + .O(m_axi_awaddr[10])); + LUT6 #( + .INIT(64'hCACAFFC0CACACACA)) + \m_axi_awaddr[11]_INST_0 + (.I0(\m_payload_i_reg[61]_0 [11]), + .I1(Q[11]), + .I2(\m_axi_awaddr[11]_INST_0_i_1_n_0 ), + .I3(\m_axi_awaddr[11] [11]), + .I4(sel_first), + .I5(\m_payload_i_reg[61]_0 [37]), + .O(m_axi_awaddr[11])); + LUT3 #( + .INIT(8'h04)) + \m_axi_awaddr[11]_INST_0_i_1 + (.I0(\m_payload_i_reg[61]_0 [37]), + .I1(\m_payload_i_reg_n_0_[38] ), + .I2(sel_first_0), + .O(\m_axi_awaddr[11]_INST_0_i_1_n_0 )); + LUT6 #( + .INIT(64'hCACAFFC0CACACACA)) + \m_axi_awaddr[1]_INST_0 + (.I0(\m_payload_i_reg[61]_0 [1]), + .I1(Q[1]), + .I2(\m_axi_awaddr[11]_INST_0_i_1_n_0 ), + .I3(\m_axi_awaddr[11] [1]), + .I4(sel_first), + .I5(\m_payload_i_reg[61]_0 [37]), + .O(m_axi_awaddr[1])); + LUT6 #( + .INIT(64'hCACAFFC0CACACACA)) + \m_axi_awaddr[2]_INST_0 + (.I0(\m_payload_i_reg[61]_0 [2]), + .I1(Q[2]), + .I2(\m_axi_awaddr[11]_INST_0_i_1_n_0 ), + .I3(\m_axi_awaddr[11] [2]), + .I4(sel_first), + .I5(\m_payload_i_reg[61]_0 [37]), + .O(m_axi_awaddr[2])); + LUT6 #( + .INIT(64'hCACAFFC0CACACACA)) + \m_axi_awaddr[3]_INST_0 + (.I0(\m_payload_i_reg[61]_0 [3]), + .I1(Q[3]), + .I2(\m_axi_awaddr[11]_INST_0_i_1_n_0 ), + .I3(\m_axi_awaddr[11] [3]), + .I4(sel_first), + .I5(\m_payload_i_reg[61]_0 [37]), + .O(m_axi_awaddr[3])); + LUT6 #( + .INIT(64'hCACAFFC0CACACACA)) + \m_axi_awaddr[4]_INST_0 + (.I0(\m_payload_i_reg[61]_0 [4]), + .I1(Q[4]), + .I2(\m_axi_awaddr[11]_INST_0_i_1_n_0 ), + .I3(\m_axi_awaddr[11] [4]), + .I4(sel_first), + .I5(\m_payload_i_reg[61]_0 [37]), + .O(m_axi_awaddr[4])); + LUT6 #( + .INIT(64'hCACAFFC0CACACACA)) + \m_axi_awaddr[5]_INST_0 + (.I0(\m_payload_i_reg[61]_0 [5]), + .I1(Q[5]), + .I2(\m_axi_awaddr[11]_INST_0_i_1_n_0 ), + .I3(\m_axi_awaddr[11] [5]), + .I4(sel_first), + .I5(\m_payload_i_reg[61]_0 [37]), + .O(m_axi_awaddr[5])); + LUT6 #( + .INIT(64'hCACAFFC0CACACACA)) + \m_axi_awaddr[6]_INST_0 + (.I0(\m_payload_i_reg[61]_0 [6]), + .I1(Q[6]), + .I2(\m_axi_awaddr[11]_INST_0_i_1_n_0 ), + .I3(\m_axi_awaddr[11] [6]), + .I4(sel_first), + .I5(\m_payload_i_reg[61]_0 [37]), + .O(m_axi_awaddr[6])); + LUT6 #( + .INIT(64'hCACAFFC0CACACACA)) + \m_axi_awaddr[7]_INST_0 + (.I0(\m_payload_i_reg[61]_0 [7]), + .I1(Q[7]), + .I2(\m_axi_awaddr[11]_INST_0_i_1_n_0 ), + .I3(\m_axi_awaddr[11] [7]), + .I4(sel_first), + .I5(\m_payload_i_reg[61]_0 [37]), + .O(m_axi_awaddr[7])); + LUT6 #( + .INIT(64'hCACAFFC0CACACACA)) + \m_axi_awaddr[8]_INST_0 + (.I0(\m_payload_i_reg[61]_0 [8]), + .I1(Q[8]), + .I2(\m_axi_awaddr[11]_INST_0_i_1_n_0 ), + .I3(\m_axi_awaddr[11] [8]), + .I4(sel_first), + .I5(\m_payload_i_reg[61]_0 [37]), + .O(m_axi_awaddr[8])); + LUT6 #( + .INIT(64'hCACAFFC0CACACACA)) + \m_axi_awaddr[9]_INST_0 + (.I0(\m_payload_i_reg[61]_0 [9]), + .I1(Q[9]), + .I2(\m_axi_awaddr[11]_INST_0_i_1_n_0 ), + .I3(\m_axi_awaddr[11] [9]), + .I4(sel_first), + .I5(\m_payload_i_reg[61]_0 [37]), + .O(m_axi_awaddr[9])); + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[0]_i_1 + (.I0(s_axi_awaddr[0]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[0] ), + .O(skid_buffer[0])); + (* SOFT_HLUTNM = "soft_lutpair71" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[10]_i_1 + (.I0(s_axi_awaddr[10]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[10] ), + .O(skid_buffer[10])); + (* SOFT_HLUTNM = "soft_lutpair70" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[11]_i_1 + (.I0(s_axi_awaddr[11]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[11] ), + .O(skid_buffer[11])); + (* SOFT_HLUTNM = "soft_lutpair70" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[12]_i_1 + (.I0(s_axi_awaddr[12]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[12] ), + .O(skid_buffer[12])); + (* SOFT_HLUTNM = "soft_lutpair69" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[13]_i_1__0 + (.I0(s_axi_awaddr[13]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[13] ), + .O(skid_buffer[13])); + (* SOFT_HLUTNM = "soft_lutpair69" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[14]_i_1 + (.I0(s_axi_awaddr[14]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[14] ), + .O(skid_buffer[14])); + (* SOFT_HLUTNM = "soft_lutpair68" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[15]_i_1 + (.I0(s_axi_awaddr[15]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[15] ), + .O(skid_buffer[15])); + (* SOFT_HLUTNM = "soft_lutpair68" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[16]_i_1 + (.I0(s_axi_awaddr[16]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[16] ), + .O(skid_buffer[16])); + (* SOFT_HLUTNM = "soft_lutpair67" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[17]_i_1 + (.I0(s_axi_awaddr[17]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[17] ), + .O(skid_buffer[17])); + (* SOFT_HLUTNM = "soft_lutpair67" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[18]_i_1 + (.I0(s_axi_awaddr[18]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[18] ), + .O(skid_buffer[18])); + (* SOFT_HLUTNM = "soft_lutpair66" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[19]_i_1 + (.I0(s_axi_awaddr[19]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[19] ), + .O(skid_buffer[19])); + (* SOFT_HLUTNM = "soft_lutpair75" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[1]_i_1 + (.I0(s_axi_awaddr[1]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[1] ), + .O(skid_buffer[1])); + (* SOFT_HLUTNM = "soft_lutpair66" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[20]_i_1 + (.I0(s_axi_awaddr[20]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[20] ), + .O(skid_buffer[20])); + (* SOFT_HLUTNM = "soft_lutpair65" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[21]_i_1 + (.I0(s_axi_awaddr[21]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[21] ), + .O(skid_buffer[21])); + (* SOFT_HLUTNM = "soft_lutpair65" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[22]_i_1 + (.I0(s_axi_awaddr[22]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[22] ), + .O(skid_buffer[22])); + (* SOFT_HLUTNM = "soft_lutpair64" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[23]_i_1 + (.I0(s_axi_awaddr[23]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[23] ), + .O(skid_buffer[23])); + (* SOFT_HLUTNM = "soft_lutpair64" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[24]_i_1 + (.I0(s_axi_awaddr[24]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[24] ), + .O(skid_buffer[24])); + (* SOFT_HLUTNM = "soft_lutpair63" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[25]_i_1 + (.I0(s_axi_awaddr[25]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[25] ), + .O(skid_buffer[25])); + (* SOFT_HLUTNM = "soft_lutpair63" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[26]_i_1 + (.I0(s_axi_awaddr[26]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[26] ), + .O(skid_buffer[26])); + (* SOFT_HLUTNM = "soft_lutpair62" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[27]_i_1 + (.I0(s_axi_awaddr[27]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[27] ), + .O(skid_buffer[27])); + (* SOFT_HLUTNM = "soft_lutpair62" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[28]_i_1 + (.I0(s_axi_awaddr[28]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[28] ), + .O(skid_buffer[28])); + (* SOFT_HLUTNM = "soft_lutpair61" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[29]_i_1 + (.I0(s_axi_awaddr[29]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[29] ), + .O(skid_buffer[29])); + (* SOFT_HLUTNM = "soft_lutpair75" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[2]_i_1 + (.I0(s_axi_awaddr[2]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[2] ), + .O(skid_buffer[2])); + (* SOFT_HLUTNM = "soft_lutpair61" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[30]_i_1 + (.I0(s_axi_awaddr[30]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[30] ), + .O(skid_buffer[30])); + (* SOFT_HLUTNM = "soft_lutpair60" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[31]_i_2 + (.I0(s_axi_awaddr[31]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[31] ), + .O(skid_buffer[31])); + (* SOFT_HLUTNM = "soft_lutpair60" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[32]_i_1 + (.I0(s_axi_awprot[0]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[32] ), + .O(skid_buffer[32])); + (* SOFT_HLUTNM = "soft_lutpair59" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[33]_i_1 + (.I0(s_axi_awprot[1]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[33] ), + .O(skid_buffer[33])); + (* SOFT_HLUTNM = "soft_lutpair59" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[34]_i_1 + (.I0(s_axi_awprot[2]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[34] ), + .O(skid_buffer[34])); + (* SOFT_HLUTNM = "soft_lutpair58" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[35]_i_1 + (.I0(s_axi_awsize[0]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[35] ), + .O(skid_buffer[35])); + (* SOFT_HLUTNM = "soft_lutpair58" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[36]_i_1 + (.I0(s_axi_awsize[1]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[36] ), + .O(skid_buffer[36])); + (* SOFT_HLUTNM = "soft_lutpair57" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[38]_i_1 + (.I0(s_axi_awburst[0]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[38] ), + .O(skid_buffer[38])); + (* SOFT_HLUTNM = "soft_lutpair57" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[39]_i_1 + (.I0(s_axi_awburst[1]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[39] ), + .O(skid_buffer[39])); + (* SOFT_HLUTNM = "soft_lutpair74" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[3]_i_1 + (.I0(s_axi_awaddr[3]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[3] ), + .O(skid_buffer[3])); + (* SOFT_HLUTNM = "soft_lutpair56" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[44]_i_1 + (.I0(s_axi_awlen[0]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[44] ), + .O(skid_buffer[44])); + (* SOFT_HLUTNM = "soft_lutpair56" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[45]_i_1 + (.I0(s_axi_awlen[1]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[45] ), + .O(skid_buffer[45])); + (* SOFT_HLUTNM = "soft_lutpair55" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[46]_i_1__0 + (.I0(s_axi_awlen[2]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[46] ), + .O(skid_buffer[46])); + (* SOFT_HLUTNM = "soft_lutpair55" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[47]_i_1 + (.I0(s_axi_awlen[3]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[47] ), + .O(skid_buffer[47])); + (* SOFT_HLUTNM = "soft_lutpair74" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[4]_i_1 + (.I0(s_axi_awaddr[4]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[4] ), + .O(skid_buffer[4])); + (* SOFT_HLUTNM = "soft_lutpair54" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[50]_i_1 + (.I0(s_axi_awid[0]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[50] ), + .O(skid_buffer[50])); + (* SOFT_HLUTNM = "soft_lutpair54" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[51]_i_1 + (.I0(s_axi_awid[1]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[51] ), + .O(skid_buffer[51])); + (* SOFT_HLUTNM = "soft_lutpair53" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[52]_i_1 + (.I0(s_axi_awid[2]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[52] ), + .O(skid_buffer[52])); + (* SOFT_HLUTNM = "soft_lutpair53" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[53]_i_1 + (.I0(s_axi_awid[3]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[53] ), + .O(skid_buffer[53])); + (* SOFT_HLUTNM = "soft_lutpair52" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[54]_i_1 + (.I0(s_axi_awid[4]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[54] ), + .O(skid_buffer[54])); + (* SOFT_HLUTNM = "soft_lutpair52" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[55]_i_1 + (.I0(s_axi_awid[5]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[55] ), + .O(skid_buffer[55])); + (* SOFT_HLUTNM = "soft_lutpair51" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[56]_i_1 + (.I0(s_axi_awid[6]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[56] ), + .O(skid_buffer[56])); + (* SOFT_HLUTNM = "soft_lutpair51" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[57]_i_1 + (.I0(s_axi_awid[7]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[57] ), + .O(skid_buffer[57])); + (* SOFT_HLUTNM = "soft_lutpair50" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[58]_i_1 + (.I0(s_axi_awid[8]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[58] ), + .O(skid_buffer[58])); + (* SOFT_HLUTNM = "soft_lutpair50" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[59]_i_1 + (.I0(s_axi_awid[9]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[59] ), + .O(skid_buffer[59])); + (* SOFT_HLUTNM = "soft_lutpair73" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[5]_i_1 + (.I0(s_axi_awaddr[5]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[5] ), + .O(skid_buffer[5])); + (* SOFT_HLUTNM = "soft_lutpair49" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[60]_i_1 + (.I0(s_axi_awid[10]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[60] ), + .O(skid_buffer[60])); + (* SOFT_HLUTNM = "soft_lutpair49" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[61]_i_1 + (.I0(s_axi_awid[11]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[61] ), + .O(skid_buffer[61])); + (* SOFT_HLUTNM = "soft_lutpair73" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[6]_i_1 + (.I0(s_axi_awaddr[6]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[6] ), + .O(skid_buffer[6])); + (* SOFT_HLUTNM = "soft_lutpair72" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[7]_i_1 + (.I0(s_axi_awaddr[7]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[7] ), + .O(skid_buffer[7])); + (* SOFT_HLUTNM = "soft_lutpair72" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[8]_i_1 + (.I0(s_axi_awaddr[8]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[8] ), + .O(skid_buffer[8])); + (* SOFT_HLUTNM = "soft_lutpair71" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[9]_i_1 + (.I0(s_axi_awaddr[9]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[9] ), + .O(skid_buffer[9])); + FDRE \m_payload_i_reg[0] + (.C(aclk), + .CE(E), + .D(skid_buffer[0]), + .Q(\m_payload_i_reg[61]_0 [0]), + .R(1'b0)); + FDRE \m_payload_i_reg[10] + (.C(aclk), + .CE(E), + .D(skid_buffer[10]), + .Q(\m_payload_i_reg[61]_0 [10]), + .R(1'b0)); + FDRE \m_payload_i_reg[11] + (.C(aclk), + .CE(E), + .D(skid_buffer[11]), + .Q(\m_payload_i_reg[61]_0 [11]), + .R(1'b0)); + FDRE \m_payload_i_reg[12] + (.C(aclk), + .CE(E), + .D(skid_buffer[12]), + .Q(\m_payload_i_reg[61]_0 [12]), + .R(1'b0)); + FDRE \m_payload_i_reg[13] + (.C(aclk), + .CE(E), + .D(skid_buffer[13]), + .Q(\m_payload_i_reg[61]_0 [13]), + .R(1'b0)); + FDRE \m_payload_i_reg[14] + (.C(aclk), + .CE(E), + .D(skid_buffer[14]), + .Q(\m_payload_i_reg[61]_0 [14]), + .R(1'b0)); + FDRE \m_payload_i_reg[15] + (.C(aclk), + .CE(E), + .D(skid_buffer[15]), + .Q(\m_payload_i_reg[61]_0 [15]), + .R(1'b0)); + FDRE \m_payload_i_reg[16] + (.C(aclk), + .CE(E), + .D(skid_buffer[16]), + .Q(\m_payload_i_reg[61]_0 [16]), + .R(1'b0)); + FDRE \m_payload_i_reg[17] + (.C(aclk), + .CE(E), + .D(skid_buffer[17]), + .Q(\m_payload_i_reg[61]_0 [17]), + .R(1'b0)); + FDRE \m_payload_i_reg[18] + (.C(aclk), + .CE(E), + .D(skid_buffer[18]), + .Q(\m_payload_i_reg[61]_0 [18]), + .R(1'b0)); + FDRE \m_payload_i_reg[19] + (.C(aclk), + .CE(E), + .D(skid_buffer[19]), + .Q(\m_payload_i_reg[61]_0 [19]), + .R(1'b0)); + FDRE \m_payload_i_reg[1] + (.C(aclk), + .CE(E), + .D(skid_buffer[1]), + .Q(\m_payload_i_reg[61]_0 [1]), + .R(1'b0)); + FDRE \m_payload_i_reg[20] + (.C(aclk), + .CE(E), + .D(skid_buffer[20]), + .Q(\m_payload_i_reg[61]_0 [20]), + .R(1'b0)); + FDRE \m_payload_i_reg[21] + (.C(aclk), + .CE(E), + .D(skid_buffer[21]), + .Q(\m_payload_i_reg[61]_0 [21]), + .R(1'b0)); + FDRE \m_payload_i_reg[22] + (.C(aclk), + .CE(E), + .D(skid_buffer[22]), + .Q(\m_payload_i_reg[61]_0 [22]), + .R(1'b0)); + FDRE \m_payload_i_reg[23] + (.C(aclk), + .CE(E), + .D(skid_buffer[23]), + .Q(\m_payload_i_reg[61]_0 [23]), + .R(1'b0)); + FDRE \m_payload_i_reg[24] + (.C(aclk), + .CE(E), + .D(skid_buffer[24]), + .Q(\m_payload_i_reg[61]_0 [24]), + .R(1'b0)); + FDRE \m_payload_i_reg[25] + (.C(aclk), + .CE(E), + .D(skid_buffer[25]), + .Q(\m_payload_i_reg[61]_0 [25]), + .R(1'b0)); + FDRE \m_payload_i_reg[26] + (.C(aclk), + .CE(E), + .D(skid_buffer[26]), + .Q(\m_payload_i_reg[61]_0 [26]), + .R(1'b0)); + FDRE \m_payload_i_reg[27] + (.C(aclk), + .CE(E), + .D(skid_buffer[27]), + .Q(\m_payload_i_reg[61]_0 [27]), + .R(1'b0)); + FDRE \m_payload_i_reg[28] + (.C(aclk), + .CE(E), + .D(skid_buffer[28]), + .Q(\m_payload_i_reg[61]_0 [28]), + .R(1'b0)); + FDRE \m_payload_i_reg[29] + (.C(aclk), + .CE(E), + .D(skid_buffer[29]), + .Q(\m_payload_i_reg[61]_0 [29]), + .R(1'b0)); + FDRE \m_payload_i_reg[2] + (.C(aclk), + .CE(E), + .D(skid_buffer[2]), + .Q(\m_payload_i_reg[61]_0 [2]), + .R(1'b0)); + FDRE \m_payload_i_reg[30] + (.C(aclk), + .CE(E), + .D(skid_buffer[30]), + .Q(\m_payload_i_reg[61]_0 [30]), + .R(1'b0)); + FDRE \m_payload_i_reg[31] + (.C(aclk), + .CE(E), + .D(skid_buffer[31]), + .Q(\m_payload_i_reg[61]_0 [31]), + .R(1'b0)); + FDRE \m_payload_i_reg[32] + (.C(aclk), + .CE(E), + .D(skid_buffer[32]), + .Q(\m_payload_i_reg[61]_0 [32]), + .R(1'b0)); + FDRE \m_payload_i_reg[33] + (.C(aclk), + .CE(E), + .D(skid_buffer[33]), + .Q(\m_payload_i_reg[61]_0 [33]), + .R(1'b0)); + FDRE \m_payload_i_reg[34] + (.C(aclk), + .CE(E), + .D(skid_buffer[34]), + .Q(\m_payload_i_reg[61]_0 [34]), + .R(1'b0)); + FDRE \m_payload_i_reg[35] + (.C(aclk), + .CE(E), + .D(skid_buffer[35]), + .Q(\m_payload_i_reg[61]_0 [35]), + .R(1'b0)); + FDRE \m_payload_i_reg[36] + (.C(aclk), + .CE(E), + .D(skid_buffer[36]), + .Q(\m_payload_i_reg[61]_0 [36]), + .R(1'b0)); + FDRE \m_payload_i_reg[38] + (.C(aclk), + .CE(E), + .D(skid_buffer[38]), + .Q(\m_payload_i_reg_n_0_[38] ), + .R(1'b0)); + FDRE \m_payload_i_reg[39] + (.C(aclk), + .CE(E), + .D(skid_buffer[39]), + .Q(\m_payload_i_reg[61]_0 [37]), + .R(1'b0)); + FDRE \m_payload_i_reg[3] + (.C(aclk), + .CE(E), + .D(skid_buffer[3]), + .Q(\m_payload_i_reg[61]_0 [3]), + .R(1'b0)); + FDRE \m_payload_i_reg[44] + (.C(aclk), + .CE(E), + .D(skid_buffer[44]), + .Q(\m_payload_i_reg[61]_0 [38]), + .R(1'b0)); + FDRE \m_payload_i_reg[45] + (.C(aclk), + .CE(E), + .D(skid_buffer[45]), + .Q(\m_payload_i_reg[61]_0 [39]), + .R(1'b0)); + FDRE \m_payload_i_reg[46] + (.C(aclk), + .CE(E), + .D(skid_buffer[46]), + .Q(\m_payload_i_reg[61]_0 [40]), + .R(1'b0)); + FDRE \m_payload_i_reg[47] + (.C(aclk), + .CE(E), + .D(skid_buffer[47]), + .Q(\m_payload_i_reg[61]_0 [41]), + .R(1'b0)); + FDRE \m_payload_i_reg[4] + (.C(aclk), + .CE(E), + .D(skid_buffer[4]), + .Q(\m_payload_i_reg[61]_0 [4]), + .R(1'b0)); + FDRE \m_payload_i_reg[50] + (.C(aclk), + .CE(E), + .D(skid_buffer[50]), + .Q(\m_payload_i_reg[61]_0 [42]), + .R(1'b0)); + FDRE \m_payload_i_reg[51] + (.C(aclk), + .CE(E), + .D(skid_buffer[51]), + .Q(\m_payload_i_reg[61]_0 [43]), + .R(1'b0)); + FDRE \m_payload_i_reg[52] + (.C(aclk), + .CE(E), + .D(skid_buffer[52]), + .Q(\m_payload_i_reg[61]_0 [44]), + .R(1'b0)); + FDRE \m_payload_i_reg[53] + (.C(aclk), + .CE(E), + .D(skid_buffer[53]), + .Q(\m_payload_i_reg[61]_0 [45]), + .R(1'b0)); + FDRE \m_payload_i_reg[54] + (.C(aclk), + .CE(E), + .D(skid_buffer[54]), + .Q(\m_payload_i_reg[61]_0 [46]), + .R(1'b0)); + FDRE \m_payload_i_reg[55] + (.C(aclk), + .CE(E), + .D(skid_buffer[55]), + .Q(\m_payload_i_reg[61]_0 [47]), + .R(1'b0)); + FDRE \m_payload_i_reg[56] + (.C(aclk), + .CE(E), + .D(skid_buffer[56]), + .Q(\m_payload_i_reg[61]_0 [48]), + .R(1'b0)); + FDRE \m_payload_i_reg[57] + (.C(aclk), + .CE(E), + .D(skid_buffer[57]), + .Q(\m_payload_i_reg[61]_0 [49]), + .R(1'b0)); + FDRE \m_payload_i_reg[58] + (.C(aclk), + .CE(E), + .D(skid_buffer[58]), + .Q(\m_payload_i_reg[61]_0 [50]), + .R(1'b0)); + FDRE \m_payload_i_reg[59] + (.C(aclk), + .CE(E), + .D(skid_buffer[59]), + .Q(\m_payload_i_reg[61]_0 [51]), + .R(1'b0)); + FDRE \m_payload_i_reg[5] + (.C(aclk), + .CE(E), + .D(skid_buffer[5]), + .Q(\m_payload_i_reg[61]_0 [5]), + .R(1'b0)); + FDRE \m_payload_i_reg[60] + (.C(aclk), + .CE(E), + .D(skid_buffer[60]), + .Q(\m_payload_i_reg[61]_0 [52]), + .R(1'b0)); + FDRE \m_payload_i_reg[61] + (.C(aclk), + .CE(E), + .D(skid_buffer[61]), + .Q(\m_payload_i_reg[61]_0 [53]), + .R(1'b0)); + FDRE \m_payload_i_reg[6] + (.C(aclk), + .CE(E), + .D(skid_buffer[6]), + .Q(\m_payload_i_reg[61]_0 [6]), + .R(1'b0)); + FDRE \m_payload_i_reg[7] + (.C(aclk), + .CE(E), + .D(skid_buffer[7]), + .Q(\m_payload_i_reg[61]_0 [7]), + .R(1'b0)); + FDRE \m_payload_i_reg[8] + (.C(aclk), + .CE(E), + .D(skid_buffer[8]), + .Q(\m_payload_i_reg[61]_0 [8]), + .R(1'b0)); + FDRE \m_payload_i_reg[9] + (.C(aclk), + .CE(E), + .D(skid_buffer[9]), + .Q(\m_payload_i_reg[61]_0 [9]), + .R(1'b0)); + LUT4 #( + .INIT(16'hF4FF)) + m_valid_i_i_1__2 + (.I0(b_push), + .I1(m_valid_i_reg_0), + .I2(s_axi_awvalid), + .I3(s_ready_i_reg_0), + .O(m_valid_i0)); + FDRE #( + .INIT(1'b0)) + m_valid_i_reg + (.C(aclk), + .CE(1'b1), + .D(m_valid_i0), + .Q(m_valid_i_reg_0), + .R(m_valid_i_reg_1)); + LUT5 #( + .INIT(32'h0000FFFE)) + next_pending_r_i_4 + (.I0(\m_payload_i_reg[61]_0 [39]), + .I1(\m_payload_i_reg[61]_0 [38]), + .I2(\m_payload_i_reg[61]_0 [40]), + .I3(\m_payload_i_reg[61]_0 [41]), + .I4(next_pending_r_reg), + .O(\m_payload_i_reg[45]_0 )); + LUT1 #( + .INIT(2'h1)) + s_ready_i_i_1__1 + (.I0(\aresetn_d_reg_n_0_[0] ), + .O(\aresetn_d_reg[0]_0 )); + LUT4 #( + .INIT(16'hBFBB)) + s_ready_i_i_2 + (.I0(b_push), + .I1(m_valid_i_reg_0), + .I2(s_axi_awvalid), + .I3(s_ready_i_reg_0), + .O(s_ready_i0)); + FDRE #( + .INIT(1'b0)) + s_ready_i_reg + (.C(aclk), + .CE(1'b1), + .D(s_ready_i0), + .Q(s_ready_i_reg_0), + .R(\aresetn_d_reg[0]_0 )); + FDRE \skid_buffer_reg[0] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[0]), + .Q(\skid_buffer_reg_n_0_[0] ), + .R(1'b0)); + FDRE \skid_buffer_reg[10] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[10]), + .Q(\skid_buffer_reg_n_0_[10] ), + .R(1'b0)); + FDRE \skid_buffer_reg[11] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[11]), + .Q(\skid_buffer_reg_n_0_[11] ), + .R(1'b0)); + FDRE \skid_buffer_reg[12] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[12]), + .Q(\skid_buffer_reg_n_0_[12] ), + .R(1'b0)); + FDRE \skid_buffer_reg[13] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[13]), + .Q(\skid_buffer_reg_n_0_[13] ), + .R(1'b0)); + FDRE \skid_buffer_reg[14] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[14]), + .Q(\skid_buffer_reg_n_0_[14] ), + .R(1'b0)); + FDRE \skid_buffer_reg[15] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[15]), + .Q(\skid_buffer_reg_n_0_[15] ), + .R(1'b0)); + FDRE \skid_buffer_reg[16] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[16]), + .Q(\skid_buffer_reg_n_0_[16] ), + .R(1'b0)); + FDRE \skid_buffer_reg[17] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[17]), + .Q(\skid_buffer_reg_n_0_[17] ), + .R(1'b0)); + FDRE \skid_buffer_reg[18] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[18]), + .Q(\skid_buffer_reg_n_0_[18] ), + .R(1'b0)); + FDRE \skid_buffer_reg[19] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[19]), + .Q(\skid_buffer_reg_n_0_[19] ), + .R(1'b0)); + FDRE \skid_buffer_reg[1] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[1]), + .Q(\skid_buffer_reg_n_0_[1] ), + .R(1'b0)); + FDRE \skid_buffer_reg[20] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[20]), + .Q(\skid_buffer_reg_n_0_[20] ), + .R(1'b0)); + FDRE \skid_buffer_reg[21] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[21]), + .Q(\skid_buffer_reg_n_0_[21] ), + .R(1'b0)); + FDRE \skid_buffer_reg[22] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[22]), + .Q(\skid_buffer_reg_n_0_[22] ), + .R(1'b0)); + FDRE \skid_buffer_reg[23] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[23]), + .Q(\skid_buffer_reg_n_0_[23] ), + .R(1'b0)); + FDRE \skid_buffer_reg[24] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[24]), + .Q(\skid_buffer_reg_n_0_[24] ), + .R(1'b0)); + FDRE \skid_buffer_reg[25] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[25]), + .Q(\skid_buffer_reg_n_0_[25] ), + .R(1'b0)); + FDRE \skid_buffer_reg[26] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[26]), + .Q(\skid_buffer_reg_n_0_[26] ), + .R(1'b0)); + FDRE \skid_buffer_reg[27] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[27]), + .Q(\skid_buffer_reg_n_0_[27] ), + .R(1'b0)); + FDRE \skid_buffer_reg[28] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[28]), + .Q(\skid_buffer_reg_n_0_[28] ), + .R(1'b0)); + FDRE \skid_buffer_reg[29] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[29]), + .Q(\skid_buffer_reg_n_0_[29] ), + .R(1'b0)); + FDRE \skid_buffer_reg[2] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[2]), + .Q(\skid_buffer_reg_n_0_[2] ), + .R(1'b0)); + FDRE \skid_buffer_reg[30] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[30]), + .Q(\skid_buffer_reg_n_0_[30] ), + .R(1'b0)); + FDRE \skid_buffer_reg[31] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[31]), + .Q(\skid_buffer_reg_n_0_[31] ), + .R(1'b0)); + FDRE \skid_buffer_reg[32] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awprot[0]), + .Q(\skid_buffer_reg_n_0_[32] ), + .R(1'b0)); + FDRE \skid_buffer_reg[33] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awprot[1]), + .Q(\skid_buffer_reg_n_0_[33] ), + .R(1'b0)); + FDRE \skid_buffer_reg[34] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awprot[2]), + .Q(\skid_buffer_reg_n_0_[34] ), + .R(1'b0)); + FDRE \skid_buffer_reg[35] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awsize[0]), + .Q(\skid_buffer_reg_n_0_[35] ), + .R(1'b0)); + FDRE \skid_buffer_reg[36] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awsize[1]), + .Q(\skid_buffer_reg_n_0_[36] ), + .R(1'b0)); + FDRE \skid_buffer_reg[38] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awburst[0]), + .Q(\skid_buffer_reg_n_0_[38] ), + .R(1'b0)); + FDRE \skid_buffer_reg[39] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awburst[1]), + .Q(\skid_buffer_reg_n_0_[39] ), + .R(1'b0)); + FDRE \skid_buffer_reg[3] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[3]), + .Q(\skid_buffer_reg_n_0_[3] ), + .R(1'b0)); + FDRE \skid_buffer_reg[44] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awlen[0]), + .Q(\skid_buffer_reg_n_0_[44] ), + .R(1'b0)); + FDRE \skid_buffer_reg[45] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awlen[1]), + .Q(\skid_buffer_reg_n_0_[45] ), + .R(1'b0)); + FDRE \skid_buffer_reg[46] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awlen[2]), + .Q(\skid_buffer_reg_n_0_[46] ), + .R(1'b0)); + FDRE \skid_buffer_reg[47] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awlen[3]), + .Q(\skid_buffer_reg_n_0_[47] ), + .R(1'b0)); + FDRE \skid_buffer_reg[4] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[4]), + .Q(\skid_buffer_reg_n_0_[4] ), + .R(1'b0)); + FDRE \skid_buffer_reg[50] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awid[0]), + .Q(\skid_buffer_reg_n_0_[50] ), + .R(1'b0)); + FDRE \skid_buffer_reg[51] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awid[1]), + .Q(\skid_buffer_reg_n_0_[51] ), + .R(1'b0)); + FDRE \skid_buffer_reg[52] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awid[2]), + .Q(\skid_buffer_reg_n_0_[52] ), + .R(1'b0)); + FDRE \skid_buffer_reg[53] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awid[3]), + .Q(\skid_buffer_reg_n_0_[53] ), + .R(1'b0)); + FDRE \skid_buffer_reg[54] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awid[4]), + .Q(\skid_buffer_reg_n_0_[54] ), + .R(1'b0)); + FDRE \skid_buffer_reg[55] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awid[5]), + .Q(\skid_buffer_reg_n_0_[55] ), + .R(1'b0)); + FDRE \skid_buffer_reg[56] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awid[6]), + .Q(\skid_buffer_reg_n_0_[56] ), + .R(1'b0)); + FDRE \skid_buffer_reg[57] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awid[7]), + .Q(\skid_buffer_reg_n_0_[57] ), + .R(1'b0)); + FDRE \skid_buffer_reg[58] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awid[8]), + .Q(\skid_buffer_reg_n_0_[58] ), + .R(1'b0)); + FDRE \skid_buffer_reg[59] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awid[9]), + .Q(\skid_buffer_reg_n_0_[59] ), + .R(1'b0)); + FDRE \skid_buffer_reg[5] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[5]), + .Q(\skid_buffer_reg_n_0_[5] ), + .R(1'b0)); + FDRE \skid_buffer_reg[60] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awid[10]), + .Q(\skid_buffer_reg_n_0_[60] ), + .R(1'b0)); + FDRE \skid_buffer_reg[61] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awid[11]), + .Q(\skid_buffer_reg_n_0_[61] ), + .R(1'b0)); + FDRE \skid_buffer_reg[6] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[6]), + .Q(\skid_buffer_reg_n_0_[6] ), + .R(1'b0)); + FDRE \skid_buffer_reg[7] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[7]), + .Q(\skid_buffer_reg_n_0_[7] ), + .R(1'b0)); + FDRE \skid_buffer_reg[8] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[8]), + .Q(\skid_buffer_reg_n_0_[8] ), + .R(1'b0)); + FDRE \skid_buffer_reg[9] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(s_axi_awaddr[9]), + .Q(\skid_buffer_reg_n_0_[9] ), + .R(1'b0)); + LUT4 #( + .INIT(16'hA8AA)) + \wrap_boundary_axaddr_r[0]_i_1 + (.I0(\m_payload_i_reg[61]_0 [0]), + .I1(\m_payload_i_reg[61]_0 [36]), + .I2(\m_payload_i_reg[61]_0 [35]), + .I3(\m_payload_i_reg[61]_0 [38]), + .O(D[0])); + LUT5 #( + .INIT(32'hDDCF0000)) + \wrap_boundary_axaddr_r[1]_i_1 + (.I0(\m_payload_i_reg[61]_0 [38]), + .I1(\m_payload_i_reg[61]_0 [36]), + .I2(\m_payload_i_reg[61]_0 [39]), + .I3(\m_payload_i_reg[61]_0 [35]), + .I4(\m_payload_i_reg[61]_0 [1]), + .O(D[1])); + LUT6 #( + .INIT(64'hA0A0202AAAAA202A)) + \wrap_boundary_axaddr_r[2]_i_1 + (.I0(\m_payload_i_reg[61]_0 [2]), + .I1(\m_payload_i_reg[61]_0 [38]), + .I2(\m_payload_i_reg[61]_0 [36]), + .I3(\m_payload_i_reg[61]_0 [40]), + .I4(\m_payload_i_reg[61]_0 [35]), + .I5(\m_payload_i_reg[61]_0 [39]), + .O(D[2])); + LUT6 #( + .INIT(64'hFFFFFFFF008020A0)) + \wrap_boundary_axaddr_r[3]_i_1 + (.I0(\m_payload_i_reg[61]_0 [3]), + .I1(\m_payload_i_reg[61]_0 [36]), + .I2(\m_payload_i_reg[61]_0 [35]), + .I3(\m_payload_i_reg[61]_0 [38]), + .I4(\m_payload_i_reg[61]_0 [40]), + .I5(\wrap_boundary_axaddr_r[3]_i_2_n_0 ), + .O(D[3])); + LUT5 #( + .INIT(32'h00300050)) + \wrap_boundary_axaddr_r[3]_i_2 + (.I0(\m_payload_i_reg[61]_0 [41]), + .I1(\m_payload_i_reg[61]_0 [39]), + .I2(\m_payload_i_reg[61]_0 [3]), + .I3(\m_payload_i_reg[61]_0 [35]), + .I4(\m_payload_i_reg[61]_0 [36]), + .O(\wrap_boundary_axaddr_r[3]_i_2_n_0 )); + LUT6 #( + .INIT(64'h000A22AAAA0A22AA)) + \wrap_boundary_axaddr_r[4]_i_1 + (.I0(\m_payload_i_reg[61]_0 [4]), + .I1(\m_payload_i_reg[61]_0 [40]), + .I2(\m_payload_i_reg[61]_0 [41]), + .I3(\m_payload_i_reg[61]_0 [36]), + .I4(\m_payload_i_reg[61]_0 [35]), + .I5(\m_payload_i_reg[61]_0 [39]), + .O(D[4])); + LUT5 #( + .INIT(32'h737F0000)) + \wrap_boundary_axaddr_r[5]_i_1 + (.I0(\m_payload_i_reg[61]_0 [40]), + .I1(\m_payload_i_reg[61]_0 [36]), + .I2(\m_payload_i_reg[61]_0 [35]), + .I3(\m_payload_i_reg[61]_0 [41]), + .I4(\m_payload_i_reg[61]_0 [5]), + .O(D[5])); + LUT4 #( + .INIT(16'h2AAA)) + \wrap_boundary_axaddr_r[6]_i_1 + (.I0(\m_payload_i_reg[61]_0 [6]), + .I1(\m_payload_i_reg[61]_0 [41]), + .I2(\m_payload_i_reg[61]_0 [36]), + .I3(\m_payload_i_reg[61]_0 [35]), + .O(D[6])); + LUT5 #( + .INIT(32'h00002000)) + \wrap_second_len_r[3]_i_2 + (.I0(\wrap_second_len_r_reg[3] [0]), + .I1(\wrap_second_len_r_reg[3] [1]), + .I2(m_valid_i_reg_0), + .I3(\m_payload_i_reg[61]_0 [41]), + .I4(\m_payload_i_reg[5]_0 ), + .O(\FSM_sequential_state_reg[0] )); +endmodule + +(* ORIG_REF_NAME = "axi_register_slice_v2_1_29_axic_register_slice" *) +module NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axic_register_slice__parameterized1 + (m_valid_i_reg_0, + s_ready_i_reg_0, + shandshake, + \m_payload_i_reg[13]_0 , + m_valid_i_reg_1, + aclk, + s_ready_i_reg_1, + si_rs_bvalid, + s_axi_bready, + out, + \skid_buffer_reg[1]_0 ); + output m_valid_i_reg_0; + output s_ready_i_reg_0; + output shandshake; + output [13:0]\m_payload_i_reg[13]_0 ; + input m_valid_i_reg_1; + input aclk; + input s_ready_i_reg_1; + input si_rs_bvalid; + input s_axi_bready; + input [11:0]out; + input [1:0]\skid_buffer_reg[1]_0 ; + + wire aclk; + wire \m_payload_i[0]_i_1__1_n_0 ; + wire \m_payload_i[10]_i_1__1_n_0 ; + wire \m_payload_i[11]_i_1__1_n_0 ; + wire \m_payload_i[12]_i_1__1_n_0 ; + wire \m_payload_i[13]_i_2_n_0 ; + wire \m_payload_i[1]_i_1__1_n_0 ; + wire \m_payload_i[2]_i_1__1_n_0 ; + wire \m_payload_i[3]_i_1__1_n_0 ; + wire \m_payload_i[4]_i_1__1_n_0 ; + wire \m_payload_i[5]_i_1__1_n_0 ; + wire \m_payload_i[6]_i_1__1_n_0 ; + wire \m_payload_i[7]_i_1__1_n_0 ; + wire \m_payload_i[8]_i_1__1_n_0 ; + wire \m_payload_i[9]_i_1__1_n_0 ; + wire [13:0]\m_payload_i_reg[13]_0 ; + wire m_valid_i0; + wire m_valid_i_reg_0; + wire m_valid_i_reg_1; + wire [11:0]out; + wire p_1_in; + wire s_axi_bready; + wire s_ready_i0; + wire s_ready_i_reg_0; + wire s_ready_i_reg_1; + wire shandshake; + wire si_rs_bvalid; + wire [1:0]\skid_buffer_reg[1]_0 ; + wire \skid_buffer_reg_n_0_[0] ; + wire \skid_buffer_reg_n_0_[10] ; + wire \skid_buffer_reg_n_0_[11] ; + wire \skid_buffer_reg_n_0_[12] ; + wire \skid_buffer_reg_n_0_[13] ; + wire \skid_buffer_reg_n_0_[1] ; + wire \skid_buffer_reg_n_0_[2] ; + wire \skid_buffer_reg_n_0_[3] ; + wire \skid_buffer_reg_n_0_[4] ; + wire \skid_buffer_reg_n_0_[5] ; + wire \skid_buffer_reg_n_0_[6] ; + wire \skid_buffer_reg_n_0_[7] ; + wire \skid_buffer_reg_n_0_[8] ; + wire \skid_buffer_reg_n_0_[9] ; + + (* SOFT_HLUTNM = "soft_lutpair83" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[0]_i_1__1 + (.I0(\skid_buffer_reg[1]_0 [0]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[0] ), + .O(\m_payload_i[0]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair78" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[10]_i_1__1 + (.I0(out[8]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[10] ), + .O(\m_payload_i[10]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair78" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[11]_i_1__1 + (.I0(out[9]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[11] ), + .O(\m_payload_i[11]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair77" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[12]_i_1__1 + (.I0(out[10]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[12] ), + .O(\m_payload_i[12]_i_1__1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \m_payload_i[13]_i_1 + (.I0(s_axi_bready), + .I1(m_valid_i_reg_0), + .O(p_1_in)); + (* SOFT_HLUTNM = "soft_lutpair77" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[13]_i_2 + (.I0(out[11]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[13] ), + .O(\m_payload_i[13]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair83" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[1]_i_1__1 + (.I0(\skid_buffer_reg[1]_0 [1]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[1] ), + .O(\m_payload_i[1]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair82" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[2]_i_1__1 + (.I0(out[0]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[2] ), + .O(\m_payload_i[2]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair82" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[3]_i_1__1 + (.I0(out[1]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[3] ), + .O(\m_payload_i[3]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair81" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[4]_i_1__1 + (.I0(out[2]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[4] ), + .O(\m_payload_i[4]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair81" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[5]_i_1__1 + (.I0(out[3]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[5] ), + .O(\m_payload_i[5]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair80" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[6]_i_1__1 + (.I0(out[4]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[6] ), + .O(\m_payload_i[6]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair80" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[7]_i_1__1 + (.I0(out[5]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[7] ), + .O(\m_payload_i[7]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair79" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[8]_i_1__1 + (.I0(out[6]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[8] ), + .O(\m_payload_i[8]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair79" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[9]_i_1__1 + (.I0(out[7]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[9] ), + .O(\m_payload_i[9]_i_1__1_n_0 )); + FDRE \m_payload_i_reg[0] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[0]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[13]_0 [0]), + .R(1'b0)); + FDRE \m_payload_i_reg[10] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[10]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[13]_0 [10]), + .R(1'b0)); + FDRE \m_payload_i_reg[11] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[11]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[13]_0 [11]), + .R(1'b0)); + FDRE \m_payload_i_reg[12] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[12]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[13]_0 [12]), + .R(1'b0)); + FDRE \m_payload_i_reg[13] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[13]_i_2_n_0 ), + .Q(\m_payload_i_reg[13]_0 [13]), + .R(1'b0)); + FDRE \m_payload_i_reg[1] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[1]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[13]_0 [1]), + .R(1'b0)); + FDRE \m_payload_i_reg[2] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[2]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[13]_0 [2]), + .R(1'b0)); + FDRE \m_payload_i_reg[3] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[3]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[13]_0 [3]), + .R(1'b0)); + FDRE \m_payload_i_reg[4] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[4]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[13]_0 [4]), + .R(1'b0)); + FDRE \m_payload_i_reg[5] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[5]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[13]_0 [5]), + .R(1'b0)); + FDRE \m_payload_i_reg[6] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[6]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[13]_0 [6]), + .R(1'b0)); + FDRE \m_payload_i_reg[7] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[7]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[13]_0 [7]), + .R(1'b0)); + FDRE \m_payload_i_reg[8] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[8]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[13]_0 [8]), + .R(1'b0)); + FDRE \m_payload_i_reg[9] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[9]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[13]_0 [9]), + .R(1'b0)); + LUT4 #( + .INIT(16'hF4FF)) + m_valid_i_i_1 + (.I0(s_axi_bready), + .I1(m_valid_i_reg_0), + .I2(si_rs_bvalid), + .I3(s_ready_i_reg_0), + .O(m_valid_i0)); + FDRE #( + .INIT(1'b0)) + m_valid_i_reg + (.C(aclk), + .CE(1'b1), + .D(m_valid_i0), + .Q(m_valid_i_reg_0), + .R(m_valid_i_reg_1)); + (* SOFT_HLUTNM = "soft_lutpair76" *) + LUT4 #( + .INIT(16'hF4FF)) + s_ready_i_i_1 + (.I0(si_rs_bvalid), + .I1(s_ready_i_reg_0), + .I2(s_axi_bready), + .I3(m_valid_i_reg_0), + .O(s_ready_i0)); + FDRE #( + .INIT(1'b0)) + s_ready_i_reg + (.C(aclk), + .CE(1'b1), + .D(s_ready_i0), + .Q(s_ready_i_reg_0), + .R(s_ready_i_reg_1)); + (* SOFT_HLUTNM = "soft_lutpair76" *) + LUT2 #( + .INIT(4'h8)) + shandshake_r_i_1 + (.I0(s_ready_i_reg_0), + .I1(si_rs_bvalid), + .O(shandshake)); + FDRE \skid_buffer_reg[0] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[1]_0 [0]), + .Q(\skid_buffer_reg_n_0_[0] ), + .R(1'b0)); + FDRE \skid_buffer_reg[10] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(out[8]), + .Q(\skid_buffer_reg_n_0_[10] ), + .R(1'b0)); + FDRE \skid_buffer_reg[11] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(out[9]), + .Q(\skid_buffer_reg_n_0_[11] ), + .R(1'b0)); + FDRE \skid_buffer_reg[12] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(out[10]), + .Q(\skid_buffer_reg_n_0_[12] ), + .R(1'b0)); + FDRE \skid_buffer_reg[13] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(out[11]), + .Q(\skid_buffer_reg_n_0_[13] ), + .R(1'b0)); + FDRE \skid_buffer_reg[1] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[1]_0 [1]), + .Q(\skid_buffer_reg_n_0_[1] ), + .R(1'b0)); + FDRE \skid_buffer_reg[2] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(out[0]), + .Q(\skid_buffer_reg_n_0_[2] ), + .R(1'b0)); + FDRE \skid_buffer_reg[3] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(out[1]), + .Q(\skid_buffer_reg_n_0_[3] ), + .R(1'b0)); + FDRE \skid_buffer_reg[4] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(out[2]), + .Q(\skid_buffer_reg_n_0_[4] ), + .R(1'b0)); + FDRE \skid_buffer_reg[5] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(out[3]), + .Q(\skid_buffer_reg_n_0_[5] ), + .R(1'b0)); + FDRE \skid_buffer_reg[6] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(out[4]), + .Q(\skid_buffer_reg_n_0_[6] ), + .R(1'b0)); + FDRE \skid_buffer_reg[7] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(out[5]), + .Q(\skid_buffer_reg_n_0_[7] ), + .R(1'b0)); + FDRE \skid_buffer_reg[8] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(out[6]), + .Q(\skid_buffer_reg_n_0_[8] ), + .R(1'b0)); + FDRE \skid_buffer_reg[9] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(out[7]), + .Q(\skid_buffer_reg_n_0_[9] ), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "axi_register_slice_v2_1_29_axic_register_slice" *) +module NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axic_register_slice__parameterized2 + (m_valid_i_reg_0, + s_ready_i_reg_0, + s_ready_i_reg_1, + \m_payload_i_reg[46]_0 , + m_valid_i_reg_1, + aclk, + s_ready_i_reg_2, + m_valid_i_reg_2, + s_axi_rready, + \skid_buffer_reg[46]_0 , + \skid_buffer_reg[33]_0 ); + output m_valid_i_reg_0; + output s_ready_i_reg_0; + output s_ready_i_reg_1; + output [46:0]\m_payload_i_reg[46]_0 ; + input m_valid_i_reg_1; + input aclk; + input s_ready_i_reg_2; + input m_valid_i_reg_2; + input s_axi_rready; + input [12:0]\skid_buffer_reg[46]_0 ; + input [33:0]\skid_buffer_reg[33]_0 ; + + wire aclk; + wire \m_payload_i[0]_i_1__2_n_0 ; + wire \m_payload_i[10]_i_1__2_n_0 ; + wire \m_payload_i[11]_i_1__2_n_0 ; + wire \m_payload_i[12]_i_1__2_n_0 ; + wire \m_payload_i[13]_i_1__2_n_0 ; + wire \m_payload_i[14]_i_1__1_n_0 ; + wire \m_payload_i[15]_i_1__1_n_0 ; + wire \m_payload_i[16]_i_1__1_n_0 ; + wire \m_payload_i[17]_i_1__1_n_0 ; + wire \m_payload_i[18]_i_1__1_n_0 ; + wire \m_payload_i[19]_i_1__1_n_0 ; + wire \m_payload_i[1]_i_1__2_n_0 ; + wire \m_payload_i[20]_i_1__1_n_0 ; + wire \m_payload_i[21]_i_1__1_n_0 ; + wire \m_payload_i[22]_i_1__1_n_0 ; + wire \m_payload_i[23]_i_1__1_n_0 ; + wire \m_payload_i[24]_i_1__1_n_0 ; + wire \m_payload_i[25]_i_1__1_n_0 ; + wire \m_payload_i[26]_i_1__1_n_0 ; + wire \m_payload_i[27]_i_1__1_n_0 ; + wire \m_payload_i[28]_i_1__1_n_0 ; + wire \m_payload_i[29]_i_1__1_n_0 ; + wire \m_payload_i[2]_i_1__2_n_0 ; + wire \m_payload_i[30]_i_1__1_n_0 ; + wire \m_payload_i[31]_i_1__0_n_0 ; + wire \m_payload_i[32]_i_1__1_n_0 ; + wire \m_payload_i[33]_i_1__1_n_0 ; + wire \m_payload_i[34]_i_1__1_n_0 ; + wire \m_payload_i[35]_i_1__1_n_0 ; + wire \m_payload_i[36]_i_1__1_n_0 ; + wire \m_payload_i[37]_i_1_n_0 ; + wire \m_payload_i[38]_i_1__1_n_0 ; + wire \m_payload_i[39]_i_1__1_n_0 ; + wire \m_payload_i[3]_i_1__2_n_0 ; + wire \m_payload_i[40]_i_1_n_0 ; + wire \m_payload_i[41]_i_1_n_0 ; + wire \m_payload_i[42]_i_1_n_0 ; + wire \m_payload_i[43]_i_1_n_0 ; + wire \m_payload_i[44]_i_1__1_n_0 ; + wire \m_payload_i[45]_i_1__1_n_0 ; + wire \m_payload_i[46]_i_2_n_0 ; + wire \m_payload_i[4]_i_1__2_n_0 ; + wire \m_payload_i[5]_i_1__2_n_0 ; + wire \m_payload_i[6]_i_1__2_n_0 ; + wire \m_payload_i[7]_i_1__2_n_0 ; + wire \m_payload_i[8]_i_1__2_n_0 ; + wire \m_payload_i[9]_i_1__2_n_0 ; + wire [46:0]\m_payload_i_reg[46]_0 ; + wire m_valid_i_i_1__1_n_0; + wire m_valid_i_reg_0; + wire m_valid_i_reg_1; + wire m_valid_i_reg_2; + wire p_1_in; + wire s_axi_rready; + wire s_ready_i_i_1__2_n_0; + wire s_ready_i_reg_0; + wire s_ready_i_reg_1; + wire s_ready_i_reg_2; + wire [33:0]\skid_buffer_reg[33]_0 ; + wire [12:0]\skid_buffer_reg[46]_0 ; + wire \skid_buffer_reg_n_0_[0] ; + wire \skid_buffer_reg_n_0_[10] ; + wire \skid_buffer_reg_n_0_[11] ; + wire \skid_buffer_reg_n_0_[12] ; + wire \skid_buffer_reg_n_0_[13] ; + wire \skid_buffer_reg_n_0_[14] ; + wire \skid_buffer_reg_n_0_[15] ; + wire \skid_buffer_reg_n_0_[16] ; + wire \skid_buffer_reg_n_0_[17] ; + wire \skid_buffer_reg_n_0_[18] ; + wire \skid_buffer_reg_n_0_[19] ; + wire \skid_buffer_reg_n_0_[1] ; + wire \skid_buffer_reg_n_0_[20] ; + wire \skid_buffer_reg_n_0_[21] ; + wire \skid_buffer_reg_n_0_[22] ; + wire \skid_buffer_reg_n_0_[23] ; + wire \skid_buffer_reg_n_0_[24] ; + wire \skid_buffer_reg_n_0_[25] ; + wire \skid_buffer_reg_n_0_[26] ; + wire \skid_buffer_reg_n_0_[27] ; + wire \skid_buffer_reg_n_0_[28] ; + wire \skid_buffer_reg_n_0_[29] ; + wire \skid_buffer_reg_n_0_[2] ; + wire \skid_buffer_reg_n_0_[30] ; + wire \skid_buffer_reg_n_0_[31] ; + wire \skid_buffer_reg_n_0_[32] ; + wire \skid_buffer_reg_n_0_[33] ; + wire \skid_buffer_reg_n_0_[34] ; + wire \skid_buffer_reg_n_0_[35] ; + wire \skid_buffer_reg_n_0_[36] ; + wire \skid_buffer_reg_n_0_[37] ; + wire \skid_buffer_reg_n_0_[38] ; + wire \skid_buffer_reg_n_0_[39] ; + wire \skid_buffer_reg_n_0_[3] ; + wire \skid_buffer_reg_n_0_[40] ; + wire \skid_buffer_reg_n_0_[41] ; + wire \skid_buffer_reg_n_0_[42] ; + wire \skid_buffer_reg_n_0_[43] ; + wire \skid_buffer_reg_n_0_[44] ; + wire \skid_buffer_reg_n_0_[45] ; + wire \skid_buffer_reg_n_0_[46] ; + wire \skid_buffer_reg_n_0_[4] ; + wire \skid_buffer_reg_n_0_[5] ; + wire \skid_buffer_reg_n_0_[6] ; + wire \skid_buffer_reg_n_0_[7] ; + wire \skid_buffer_reg_n_0_[8] ; + wire \skid_buffer_reg_n_0_[9] ; + + (* SOFT_HLUTNM = "soft_lutpair84" *) + LUT2 #( + .INIT(4'h2)) + \cnt_read[4]_i_3__0 + (.I0(s_ready_i_reg_0), + .I1(m_valid_i_reg_2), + .O(s_ready_i_reg_1)); + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[0]_i_1__2 + (.I0(\skid_buffer_reg[33]_0 [0]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[0] ), + .O(\m_payload_i[0]_i_1__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair103" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[10]_i_1__2 + (.I0(\skid_buffer_reg[33]_0 [10]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[10] ), + .O(\m_payload_i[10]_i_1__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair102" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[11]_i_1__2 + (.I0(\skid_buffer_reg[33]_0 [11]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[11] ), + .O(\m_payload_i[11]_i_1__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair102" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[12]_i_1__2 + (.I0(\skid_buffer_reg[33]_0 [12]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[12] ), + .O(\m_payload_i[12]_i_1__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair101" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[13]_i_1__2 + (.I0(\skid_buffer_reg[33]_0 [13]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[13] ), + .O(\m_payload_i[13]_i_1__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair101" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[14]_i_1__1 + (.I0(\skid_buffer_reg[33]_0 [14]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[14] ), + .O(\m_payload_i[14]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair100" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[15]_i_1__1 + (.I0(\skid_buffer_reg[33]_0 [15]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[15] ), + .O(\m_payload_i[15]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair100" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[16]_i_1__1 + (.I0(\skid_buffer_reg[33]_0 [16]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[16] ), + .O(\m_payload_i[16]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair99" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[17]_i_1__1 + (.I0(\skid_buffer_reg[33]_0 [17]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[17] ), + .O(\m_payload_i[17]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair99" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[18]_i_1__1 + (.I0(\skid_buffer_reg[33]_0 [18]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[18] ), + .O(\m_payload_i[18]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair98" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[19]_i_1__1 + (.I0(\skid_buffer_reg[33]_0 [19]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[19] ), + .O(\m_payload_i[19]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair107" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[1]_i_1__2 + (.I0(\skid_buffer_reg[33]_0 [1]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[1] ), + .O(\m_payload_i[1]_i_1__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair98" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[20]_i_1__1 + (.I0(\skid_buffer_reg[33]_0 [20]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[20] ), + .O(\m_payload_i[20]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair97" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[21]_i_1__1 + (.I0(\skid_buffer_reg[33]_0 [21]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[21] ), + .O(\m_payload_i[21]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair97" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[22]_i_1__1 + (.I0(\skid_buffer_reg[33]_0 [22]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[22] ), + .O(\m_payload_i[22]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair96" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[23]_i_1__1 + (.I0(\skid_buffer_reg[33]_0 [23]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[23] ), + .O(\m_payload_i[23]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair96" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[24]_i_1__1 + (.I0(\skid_buffer_reg[33]_0 [24]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[24] ), + .O(\m_payload_i[24]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair95" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[25]_i_1__1 + (.I0(\skid_buffer_reg[33]_0 [25]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[25] ), + .O(\m_payload_i[25]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair95" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[26]_i_1__1 + (.I0(\skid_buffer_reg[33]_0 [26]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[26] ), + .O(\m_payload_i[26]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair94" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[27]_i_1__1 + (.I0(\skid_buffer_reg[33]_0 [27]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[27] ), + .O(\m_payload_i[27]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair94" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[28]_i_1__1 + (.I0(\skid_buffer_reg[33]_0 [28]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[28] ), + .O(\m_payload_i[28]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair93" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[29]_i_1__1 + (.I0(\skid_buffer_reg[33]_0 [29]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[29] ), + .O(\m_payload_i[29]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair107" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[2]_i_1__2 + (.I0(\skid_buffer_reg[33]_0 [2]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[2] ), + .O(\m_payload_i[2]_i_1__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair93" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[30]_i_1__1 + (.I0(\skid_buffer_reg[33]_0 [30]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[30] ), + .O(\m_payload_i[30]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair92" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[31]_i_1__0 + (.I0(\skid_buffer_reg[33]_0 [31]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[31] ), + .O(\m_payload_i[31]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair92" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[32]_i_1__1 + (.I0(\skid_buffer_reg[33]_0 [32]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[32] ), + .O(\m_payload_i[32]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair91" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[33]_i_1__1 + (.I0(\skid_buffer_reg[33]_0 [33]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[33] ), + .O(\m_payload_i[33]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair91" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[34]_i_1__1 + (.I0(\skid_buffer_reg[46]_0 [0]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[34] ), + .O(\m_payload_i[34]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair90" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[35]_i_1__1 + (.I0(\skid_buffer_reg[46]_0 [1]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[35] ), + .O(\m_payload_i[35]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair90" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[36]_i_1__1 + (.I0(\skid_buffer_reg[46]_0 [2]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[36] ), + .O(\m_payload_i[36]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair89" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[37]_i_1 + (.I0(\skid_buffer_reg[46]_0 [3]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[37] ), + .O(\m_payload_i[37]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair89" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[38]_i_1__1 + (.I0(\skid_buffer_reg[46]_0 [4]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[38] ), + .O(\m_payload_i[38]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair88" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[39]_i_1__1 + (.I0(\skid_buffer_reg[46]_0 [5]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[39] ), + .O(\m_payload_i[39]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair106" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[3]_i_1__2 + (.I0(\skid_buffer_reg[33]_0 [3]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[3] ), + .O(\m_payload_i[3]_i_1__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair88" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[40]_i_1 + (.I0(\skid_buffer_reg[46]_0 [6]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[40] ), + .O(\m_payload_i[40]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair87" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[41]_i_1 + (.I0(\skid_buffer_reg[46]_0 [7]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[41] ), + .O(\m_payload_i[41]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair87" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[42]_i_1 + (.I0(\skid_buffer_reg[46]_0 [8]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[42] ), + .O(\m_payload_i[42]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair86" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[43]_i_1 + (.I0(\skid_buffer_reg[46]_0 [9]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[43] ), + .O(\m_payload_i[43]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair86" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[44]_i_1__1 + (.I0(\skid_buffer_reg[46]_0 [10]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[44] ), + .O(\m_payload_i[44]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair85" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[45]_i_1__1 + (.I0(\skid_buffer_reg[46]_0 [11]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[45] ), + .O(\m_payload_i[45]_i_1__1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \m_payload_i[46]_i_1 + (.I0(s_axi_rready), + .I1(m_valid_i_reg_0), + .O(p_1_in)); + (* SOFT_HLUTNM = "soft_lutpair85" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[46]_i_2 + (.I0(\skid_buffer_reg[46]_0 [12]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[46] ), + .O(\m_payload_i[46]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair106" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[4]_i_1__2 + (.I0(\skid_buffer_reg[33]_0 [4]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[4] ), + .O(\m_payload_i[4]_i_1__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair105" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[5]_i_1__2 + (.I0(\skid_buffer_reg[33]_0 [5]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[5] ), + .O(\m_payload_i[5]_i_1__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair105" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[6]_i_1__2 + (.I0(\skid_buffer_reg[33]_0 [6]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[6] ), + .O(\m_payload_i[6]_i_1__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair104" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[7]_i_1__2 + (.I0(\skid_buffer_reg[33]_0 [7]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[7] ), + .O(\m_payload_i[7]_i_1__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair104" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[8]_i_1__2 + (.I0(\skid_buffer_reg[33]_0 [8]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[8] ), + .O(\m_payload_i[8]_i_1__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair103" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[9]_i_1__2 + (.I0(\skid_buffer_reg[33]_0 [9]), + .I1(s_ready_i_reg_0), + .I2(\skid_buffer_reg_n_0_[9] ), + .O(\m_payload_i[9]_i_1__2_n_0 )); + FDRE \m_payload_i_reg[0] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[0]_i_1__2_n_0 ), + .Q(\m_payload_i_reg[46]_0 [0]), + .R(1'b0)); + FDRE \m_payload_i_reg[10] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[10]_i_1__2_n_0 ), + .Q(\m_payload_i_reg[46]_0 [10]), + .R(1'b0)); + FDRE \m_payload_i_reg[11] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[11]_i_1__2_n_0 ), + .Q(\m_payload_i_reg[46]_0 [11]), + .R(1'b0)); + FDRE \m_payload_i_reg[12] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[12]_i_1__2_n_0 ), + .Q(\m_payload_i_reg[46]_0 [12]), + .R(1'b0)); + FDRE \m_payload_i_reg[13] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[13]_i_1__2_n_0 ), + .Q(\m_payload_i_reg[46]_0 [13]), + .R(1'b0)); + FDRE \m_payload_i_reg[14] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[14]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [14]), + .R(1'b0)); + FDRE \m_payload_i_reg[15] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[15]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [15]), + .R(1'b0)); + FDRE \m_payload_i_reg[16] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[16]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [16]), + .R(1'b0)); + FDRE \m_payload_i_reg[17] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[17]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [17]), + .R(1'b0)); + FDRE \m_payload_i_reg[18] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[18]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [18]), + .R(1'b0)); + FDRE \m_payload_i_reg[19] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[19]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [19]), + .R(1'b0)); + FDRE \m_payload_i_reg[1] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[1]_i_1__2_n_0 ), + .Q(\m_payload_i_reg[46]_0 [1]), + .R(1'b0)); + FDRE \m_payload_i_reg[20] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[20]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [20]), + .R(1'b0)); + FDRE \m_payload_i_reg[21] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[21]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [21]), + .R(1'b0)); + FDRE \m_payload_i_reg[22] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[22]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [22]), + .R(1'b0)); + FDRE \m_payload_i_reg[23] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[23]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [23]), + .R(1'b0)); + FDRE \m_payload_i_reg[24] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[24]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [24]), + .R(1'b0)); + FDRE \m_payload_i_reg[25] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[25]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [25]), + .R(1'b0)); + FDRE \m_payload_i_reg[26] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[26]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [26]), + .R(1'b0)); + FDRE \m_payload_i_reg[27] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[27]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [27]), + .R(1'b0)); + FDRE \m_payload_i_reg[28] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[28]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [28]), + .R(1'b0)); + FDRE \m_payload_i_reg[29] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[29]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [29]), + .R(1'b0)); + FDRE \m_payload_i_reg[2] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[2]_i_1__2_n_0 ), + .Q(\m_payload_i_reg[46]_0 [2]), + .R(1'b0)); + FDRE \m_payload_i_reg[30] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[30]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [30]), + .R(1'b0)); + FDRE \m_payload_i_reg[31] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[31]_i_1__0_n_0 ), + .Q(\m_payload_i_reg[46]_0 [31]), + .R(1'b0)); + FDRE \m_payload_i_reg[32] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[32]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [32]), + .R(1'b0)); + FDRE \m_payload_i_reg[33] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[33]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [33]), + .R(1'b0)); + FDRE \m_payload_i_reg[34] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[34]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [34]), + .R(1'b0)); + FDRE \m_payload_i_reg[35] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[35]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [35]), + .R(1'b0)); + FDRE \m_payload_i_reg[36] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[36]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [36]), + .R(1'b0)); + FDRE \m_payload_i_reg[37] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[37]_i_1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [37]), + .R(1'b0)); + FDRE \m_payload_i_reg[38] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[38]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [38]), + .R(1'b0)); + FDRE \m_payload_i_reg[39] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[39]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [39]), + .R(1'b0)); + FDRE \m_payload_i_reg[3] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[3]_i_1__2_n_0 ), + .Q(\m_payload_i_reg[46]_0 [3]), + .R(1'b0)); + FDRE \m_payload_i_reg[40] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[40]_i_1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [40]), + .R(1'b0)); + FDRE \m_payload_i_reg[41] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[41]_i_1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [41]), + .R(1'b0)); + FDRE \m_payload_i_reg[42] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[42]_i_1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [42]), + .R(1'b0)); + FDRE \m_payload_i_reg[43] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[43]_i_1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [43]), + .R(1'b0)); + FDRE \m_payload_i_reg[44] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[44]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [44]), + .R(1'b0)); + FDRE \m_payload_i_reg[45] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[45]_i_1__1_n_0 ), + .Q(\m_payload_i_reg[46]_0 [45]), + .R(1'b0)); + FDRE \m_payload_i_reg[46] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[46]_i_2_n_0 ), + .Q(\m_payload_i_reg[46]_0 [46]), + .R(1'b0)); + FDRE \m_payload_i_reg[4] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[4]_i_1__2_n_0 ), + .Q(\m_payload_i_reg[46]_0 [4]), + .R(1'b0)); + FDRE \m_payload_i_reg[5] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[5]_i_1__2_n_0 ), + .Q(\m_payload_i_reg[46]_0 [5]), + .R(1'b0)); + FDRE \m_payload_i_reg[6] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[6]_i_1__2_n_0 ), + .Q(\m_payload_i_reg[46]_0 [6]), + .R(1'b0)); + FDRE \m_payload_i_reg[7] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[7]_i_1__2_n_0 ), + .Q(\m_payload_i_reg[46]_0 [7]), + .R(1'b0)); + FDRE \m_payload_i_reg[8] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[8]_i_1__2_n_0 ), + .Q(\m_payload_i_reg[46]_0 [8]), + .R(1'b0)); + FDRE \m_payload_i_reg[9] + (.C(aclk), + .CE(p_1_in), + .D(\m_payload_i[9]_i_1__2_n_0 ), + .Q(\m_payload_i_reg[46]_0 [9]), + .R(1'b0)); + LUT4 #( + .INIT(16'h4FFF)) + m_valid_i_i_1__1 + (.I0(s_axi_rready), + .I1(m_valid_i_reg_0), + .I2(m_valid_i_reg_2), + .I3(s_ready_i_reg_0), + .O(m_valid_i_i_1__1_n_0)); + FDRE #( + .INIT(1'b0)) + m_valid_i_reg + (.C(aclk), + .CE(1'b1), + .D(m_valid_i_i_1__1_n_0), + .Q(m_valid_i_reg_0), + .R(m_valid_i_reg_1)); + (* SOFT_HLUTNM = "soft_lutpair84" *) + LUT4 #( + .INIT(16'hF8FF)) + s_ready_i_i_1__2 + (.I0(m_valid_i_reg_2), + .I1(s_ready_i_reg_0), + .I2(s_axi_rready), + .I3(m_valid_i_reg_0), + .O(s_ready_i_i_1__2_n_0)); + FDRE #( + .INIT(1'b0)) + s_ready_i_reg + (.C(aclk), + .CE(1'b1), + .D(s_ready_i_i_1__2_n_0), + .Q(s_ready_i_reg_0), + .R(s_ready_i_reg_2)); + FDRE \skid_buffer_reg[0] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [0]), + .Q(\skid_buffer_reg_n_0_[0] ), + .R(1'b0)); + FDRE \skid_buffer_reg[10] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [10]), + .Q(\skid_buffer_reg_n_0_[10] ), + .R(1'b0)); + FDRE \skid_buffer_reg[11] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [11]), + .Q(\skid_buffer_reg_n_0_[11] ), + .R(1'b0)); + FDRE \skid_buffer_reg[12] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [12]), + .Q(\skid_buffer_reg_n_0_[12] ), + .R(1'b0)); + FDRE \skid_buffer_reg[13] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [13]), + .Q(\skid_buffer_reg_n_0_[13] ), + .R(1'b0)); + FDRE \skid_buffer_reg[14] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [14]), + .Q(\skid_buffer_reg_n_0_[14] ), + .R(1'b0)); + FDRE \skid_buffer_reg[15] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [15]), + .Q(\skid_buffer_reg_n_0_[15] ), + .R(1'b0)); + FDRE \skid_buffer_reg[16] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [16]), + .Q(\skid_buffer_reg_n_0_[16] ), + .R(1'b0)); + FDRE \skid_buffer_reg[17] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [17]), + .Q(\skid_buffer_reg_n_0_[17] ), + .R(1'b0)); + FDRE \skid_buffer_reg[18] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [18]), + .Q(\skid_buffer_reg_n_0_[18] ), + .R(1'b0)); + FDRE \skid_buffer_reg[19] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [19]), + .Q(\skid_buffer_reg_n_0_[19] ), + .R(1'b0)); + FDRE \skid_buffer_reg[1] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [1]), + .Q(\skid_buffer_reg_n_0_[1] ), + .R(1'b0)); + FDRE \skid_buffer_reg[20] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [20]), + .Q(\skid_buffer_reg_n_0_[20] ), + .R(1'b0)); + FDRE \skid_buffer_reg[21] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [21]), + .Q(\skid_buffer_reg_n_0_[21] ), + .R(1'b0)); + FDRE \skid_buffer_reg[22] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [22]), + .Q(\skid_buffer_reg_n_0_[22] ), + .R(1'b0)); + FDRE \skid_buffer_reg[23] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [23]), + .Q(\skid_buffer_reg_n_0_[23] ), + .R(1'b0)); + FDRE \skid_buffer_reg[24] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [24]), + .Q(\skid_buffer_reg_n_0_[24] ), + .R(1'b0)); + FDRE \skid_buffer_reg[25] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [25]), + .Q(\skid_buffer_reg_n_0_[25] ), + .R(1'b0)); + FDRE \skid_buffer_reg[26] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [26]), + .Q(\skid_buffer_reg_n_0_[26] ), + .R(1'b0)); + FDRE \skid_buffer_reg[27] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [27]), + .Q(\skid_buffer_reg_n_0_[27] ), + .R(1'b0)); + FDRE \skid_buffer_reg[28] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [28]), + .Q(\skid_buffer_reg_n_0_[28] ), + .R(1'b0)); + FDRE \skid_buffer_reg[29] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [29]), + .Q(\skid_buffer_reg_n_0_[29] ), + .R(1'b0)); + FDRE \skid_buffer_reg[2] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [2]), + .Q(\skid_buffer_reg_n_0_[2] ), + .R(1'b0)); + FDRE \skid_buffer_reg[30] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [30]), + .Q(\skid_buffer_reg_n_0_[30] ), + .R(1'b0)); + FDRE \skid_buffer_reg[31] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [31]), + .Q(\skid_buffer_reg_n_0_[31] ), + .R(1'b0)); + FDRE \skid_buffer_reg[32] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [32]), + .Q(\skid_buffer_reg_n_0_[32] ), + .R(1'b0)); + FDRE \skid_buffer_reg[33] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [33]), + .Q(\skid_buffer_reg_n_0_[33] ), + .R(1'b0)); + FDRE \skid_buffer_reg[34] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[46]_0 [0]), + .Q(\skid_buffer_reg_n_0_[34] ), + .R(1'b0)); + FDRE \skid_buffer_reg[35] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[46]_0 [1]), + .Q(\skid_buffer_reg_n_0_[35] ), + .R(1'b0)); + FDRE \skid_buffer_reg[36] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[46]_0 [2]), + .Q(\skid_buffer_reg_n_0_[36] ), + .R(1'b0)); + FDRE \skid_buffer_reg[37] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[46]_0 [3]), + .Q(\skid_buffer_reg_n_0_[37] ), + .R(1'b0)); + FDRE \skid_buffer_reg[38] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[46]_0 [4]), + .Q(\skid_buffer_reg_n_0_[38] ), + .R(1'b0)); + FDRE \skid_buffer_reg[39] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[46]_0 [5]), + .Q(\skid_buffer_reg_n_0_[39] ), + .R(1'b0)); + FDRE \skid_buffer_reg[3] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [3]), + .Q(\skid_buffer_reg_n_0_[3] ), + .R(1'b0)); + FDRE \skid_buffer_reg[40] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[46]_0 [6]), + .Q(\skid_buffer_reg_n_0_[40] ), + .R(1'b0)); + FDRE \skid_buffer_reg[41] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[46]_0 [7]), + .Q(\skid_buffer_reg_n_0_[41] ), + .R(1'b0)); + FDRE \skid_buffer_reg[42] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[46]_0 [8]), + .Q(\skid_buffer_reg_n_0_[42] ), + .R(1'b0)); + FDRE \skid_buffer_reg[43] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[46]_0 [9]), + .Q(\skid_buffer_reg_n_0_[43] ), + .R(1'b0)); + FDRE \skid_buffer_reg[44] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[46]_0 [10]), + .Q(\skid_buffer_reg_n_0_[44] ), + .R(1'b0)); + FDRE \skid_buffer_reg[45] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[46]_0 [11]), + .Q(\skid_buffer_reg_n_0_[45] ), + .R(1'b0)); + FDRE \skid_buffer_reg[46] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[46]_0 [12]), + .Q(\skid_buffer_reg_n_0_[46] ), + .R(1'b0)); + FDRE \skid_buffer_reg[4] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [4]), + .Q(\skid_buffer_reg_n_0_[4] ), + .R(1'b0)); + FDRE \skid_buffer_reg[5] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [5]), + .Q(\skid_buffer_reg_n_0_[5] ), + .R(1'b0)); + FDRE \skid_buffer_reg[6] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [6]), + .Q(\skid_buffer_reg_n_0_[6] ), + .R(1'b0)); + FDRE \skid_buffer_reg[7] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [7]), + .Q(\skid_buffer_reg_n_0_[7] ), + .R(1'b0)); + FDRE \skid_buffer_reg[8] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [8]), + .Q(\skid_buffer_reg_n_0_[8] ), + .R(1'b0)); + FDRE \skid_buffer_reg[9] + (.C(aclk), + .CE(s_ready_i_reg_0), + .D(\skid_buffer_reg[33]_0 [9]), + .Q(\skid_buffer_reg_n_0_[9] ), + .R(1'b0)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_auto_pc_0/NewExtInst_TOP_auto_pc_0_sim_netlist.vhdl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_auto_pc_0/NewExtInst_TOP_auto_pc_0_sim_netlist.vhdl new file mode 100644 index 0000000..0823f1e --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_auto_pc_0/NewExtInst_TOP_auto_pc_0_sim_netlist.vhdl @@ -0,0 +1,14896 @@ +-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +-- Date : Fri May 15 15:27:03 2026 +-- Host : mkb running 64-bit unknown +-- Command : write_vhdl -force -mode funcsim -rename_top NewExtInst_TOP_auto_pc_0 -prefix +-- NewExtInst_TOP_auto_pc_0_ NewExtInst_TOP_auto_pc_0_sim_netlist.vhdl +-- Design : NewExtInst_TOP_auto_pc_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z035ffg676-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_incr_cmd is + port ( + next_pending_r : out STD_LOGIC; + sel_first_reg_0 : out STD_LOGIC; + \axlen_cnt_reg[5]_0\ : out STD_LOGIC; + \axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); + \m_payload_i_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + aclk : in STD_LOGIC; + sel_first_reg_1 : in STD_LOGIC; + \axlen_cnt_reg[3]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); + si_rs_awvalid : in STD_LOGIC; + \axlen_cnt_reg[3]_1\ : in STD_LOGIC; + S : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \next\ : in STD_LOGIC; + \axlen_cnt_reg[4]_0\ : in STD_LOGIC; + next_pending_r_reg_0 : in STD_LOGIC; + axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \axlen_cnt_reg[5]_1\ : in STD_LOGIC + ); +end NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_incr_cmd; + +architecture STRUCTURE of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_incr_cmd is + signal \axaddr_incr[11]_i_1_n_0\ : STD_LOGIC; + signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \axaddr_incr_reg[11]_i_4_n_1\ : STD_LOGIC; + signal \axaddr_incr_reg[11]_i_4_n_2\ : STD_LOGIC; + signal \axaddr_incr_reg[11]_i_4_n_3\ : STD_LOGIC; + signal \axaddr_incr_reg[11]_i_4_n_4\ : STD_LOGIC; + signal \axaddr_incr_reg[11]_i_4_n_5\ : STD_LOGIC; + signal \axaddr_incr_reg[11]_i_4_n_6\ : STD_LOGIC; + signal \axaddr_incr_reg[11]_i_4_n_7\ : STD_LOGIC; + signal \axaddr_incr_reg[3]_i_3_n_0\ : STD_LOGIC; + signal \axaddr_incr_reg[3]_i_3_n_1\ : STD_LOGIC; + signal \axaddr_incr_reg[3]_i_3_n_2\ : STD_LOGIC; + signal \axaddr_incr_reg[3]_i_3_n_3\ : STD_LOGIC; + signal \axaddr_incr_reg[3]_i_3_n_4\ : STD_LOGIC; + signal \axaddr_incr_reg[3]_i_3_n_5\ : STD_LOGIC; + signal \axaddr_incr_reg[3]_i_3_n_6\ : STD_LOGIC; + signal \axaddr_incr_reg[3]_i_3_n_7\ : STD_LOGIC; + signal \axaddr_incr_reg[7]_i_3_n_0\ : STD_LOGIC; + signal \axaddr_incr_reg[7]_i_3_n_1\ : STD_LOGIC; + signal \axaddr_incr_reg[7]_i_3_n_2\ : STD_LOGIC; + signal \axaddr_incr_reg[7]_i_3_n_3\ : STD_LOGIC; + signal \axaddr_incr_reg[7]_i_3_n_4\ : STD_LOGIC; + signal \axaddr_incr_reg[7]_i_3_n_5\ : STD_LOGIC; + signal \axaddr_incr_reg[7]_i_3_n_6\ : STD_LOGIC; + signal \axaddr_incr_reg[7]_i_3_n_7\ : STD_LOGIC; + signal axlen_cnt : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \axlen_cnt[0]_i_1_n_0\ : STD_LOGIC; + signal \axlen_cnt[1]_i_1_n_0\ : STD_LOGIC; + signal \axlen_cnt[2]_i_1_n_0\ : STD_LOGIC; + signal \axlen_cnt[3]_i_2_n_0\ : STD_LOGIC; + signal \axlen_cnt[3]_i_4_n_0\ : STD_LOGIC; + signal \axlen_cnt[4]_i_1__2_n_0\ : STD_LOGIC; + signal \axlen_cnt[5]_i_2_n_0\ : STD_LOGIC; + signal \axlen_cnt[6]_i_1__0_n_0\ : STD_LOGIC; + signal \axlen_cnt[7]_i_1__0_n_0\ : STD_LOGIC; + signal \axlen_cnt[7]_i_2_n_0\ : STD_LOGIC; + signal \^axlen_cnt_reg[5]_0\ : STD_LOGIC; + signal incr_next_pending : STD_LOGIC; + signal \^next_pending_r\ : STD_LOGIC; + signal next_pending_r_i_5_n_0 : STD_LOGIC; + signal p_1_in : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \^sel_first_reg_0\ : STD_LOGIC; + signal \NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1\ : label is "soft_lutpair119"; + attribute SOFT_HLUTNM of \axaddr_incr[10]_i_1\ : label is "soft_lutpair115"; + attribute SOFT_HLUTNM of \axaddr_incr[11]_i_2\ : label is "soft_lutpair114"; + attribute SOFT_HLUTNM of \axaddr_incr[1]_i_1\ : label is "soft_lutpair119"; + attribute SOFT_HLUTNM of \axaddr_incr[2]_i_1\ : label is "soft_lutpair118"; + attribute SOFT_HLUTNM of \axaddr_incr[3]_i_1\ : label is "soft_lutpair118"; + attribute SOFT_HLUTNM of \axaddr_incr[4]_i_1\ : label is "soft_lutpair117"; + attribute SOFT_HLUTNM of \axaddr_incr[5]_i_1\ : label is "soft_lutpair115"; + attribute SOFT_HLUTNM of \axaddr_incr[6]_i_1\ : label is "soft_lutpair117"; + attribute SOFT_HLUTNM of \axaddr_incr[7]_i_1\ : label is "soft_lutpair116"; + attribute SOFT_HLUTNM of \axaddr_incr[8]_i_1\ : label is "soft_lutpair116"; + attribute SOFT_HLUTNM of \axaddr_incr[9]_i_1\ : label is "soft_lutpair114"; + attribute ADDER_THRESHOLD : integer; + attribute ADDER_THRESHOLD of \axaddr_incr_reg[11]_i_4\ : label is 35; + attribute ADDER_THRESHOLD of \axaddr_incr_reg[3]_i_3\ : label is 35; + attribute ADDER_THRESHOLD of \axaddr_incr_reg[7]_i_3\ : label is 35; + attribute SOFT_HLUTNM of \axlen_cnt[6]_i_1__0\ : label is "soft_lutpair112"; + attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1__0\ : label is "soft_lutpair112"; + attribute SOFT_HLUTNM of \axlen_cnt[7]_i_2\ : label is "soft_lutpair113"; + attribute SOFT_HLUTNM of next_pending_r_i_5 : label is "soft_lutpair113"; +begin + \axaddr_incr_reg[11]_0\(11 downto 0) <= \^axaddr_incr_reg[11]_0\(11 downto 0); + \axlen_cnt_reg[5]_0\ <= \^axlen_cnt_reg[5]_0\; + next_pending_r <= \^next_pending_r\; + sel_first_reg_0 <= \^sel_first_reg_0\; +\axaddr_incr[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => axaddr_incr(0), + I1 => \^sel_first_reg_0\, + I2 => \axaddr_incr_reg[3]_i_3_n_7\, + O => p_1_in(0) + ); +\axaddr_incr[10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => axaddr_incr(10), + I1 => \^sel_first_reg_0\, + I2 => \axaddr_incr_reg[11]_i_4_n_5\, + O => p_1_in(10) + ); +\axaddr_incr[11]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^sel_first_reg_0\, + I1 => \next\, + O => \axaddr_incr[11]_i_1_n_0\ + ); +\axaddr_incr[11]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => axaddr_incr(11), + I1 => \^sel_first_reg_0\, + I2 => \axaddr_incr_reg[11]_i_4_n_4\, + O => p_1_in(11) + ); +\axaddr_incr[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => axaddr_incr(1), + I1 => \^sel_first_reg_0\, + I2 => \axaddr_incr_reg[3]_i_3_n_6\, + O => p_1_in(1) + ); +\axaddr_incr[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => axaddr_incr(2), + I1 => \^sel_first_reg_0\, + I2 => \axaddr_incr_reg[3]_i_3_n_5\, + O => p_1_in(2) + ); +\axaddr_incr[3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => axaddr_incr(3), + I1 => \^sel_first_reg_0\, + I2 => \axaddr_incr_reg[3]_i_3_n_4\, + O => p_1_in(3) + ); +\axaddr_incr[3]_i_10\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0102" + ) + port map ( + I0 => \axlen_cnt_reg[3]_0\(0), + I1 => \axlen_cnt_reg[3]_0\(5), + I2 => \axlen_cnt_reg[3]_0\(4), + I3 => \next\, + O => \m_payload_i_reg[3]\(0) + ); +\axaddr_incr[3]_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => \axlen_cnt_reg[3]_0\(3), + I1 => \axlen_cnt_reg[3]_0\(5), + I2 => \axlen_cnt_reg[3]_0\(4), + I3 => \next\, + O => \m_payload_i_reg[3]\(3) + ); +\axaddr_incr[3]_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"1A2A" + ) + port map ( + I0 => \axlen_cnt_reg[3]_0\(2), + I1 => \axlen_cnt_reg[3]_0\(4), + I2 => \axlen_cnt_reg[3]_0\(5), + I3 => \next\, + O => \m_payload_i_reg[3]\(2) + ); +\axaddr_incr[3]_i_9\: unisim.vcomponents.LUT4 + generic map( + INIT => X"1222" + ) + port map ( + I0 => \axlen_cnt_reg[3]_0\(1), + I1 => \axlen_cnt_reg[3]_0\(5), + I2 => \axlen_cnt_reg[3]_0\(4), + I3 => \next\, + O => \m_payload_i_reg[3]\(1) + ); +\axaddr_incr[4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => axaddr_incr(4), + I1 => \^sel_first_reg_0\, + I2 => \axaddr_incr_reg[7]_i_3_n_7\, + O => p_1_in(4) + ); +\axaddr_incr[5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => axaddr_incr(5), + I1 => \^sel_first_reg_0\, + I2 => \axaddr_incr_reg[7]_i_3_n_6\, + O => p_1_in(5) + ); +\axaddr_incr[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => axaddr_incr(6), + I1 => \^sel_first_reg_0\, + I2 => \axaddr_incr_reg[7]_i_3_n_5\, + O => p_1_in(6) + ); +\axaddr_incr[7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => axaddr_incr(7), + I1 => \^sel_first_reg_0\, + I2 => \axaddr_incr_reg[7]_i_3_n_4\, + O => p_1_in(7) + ); +\axaddr_incr[8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => axaddr_incr(8), + I1 => \^sel_first_reg_0\, + I2 => \axaddr_incr_reg[11]_i_4_n_7\, + O => p_1_in(8) + ); +\axaddr_incr[9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => axaddr_incr(9), + I1 => \^sel_first_reg_0\, + I2 => \axaddr_incr_reg[11]_i_4_n_6\, + O => p_1_in(9) + ); +\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_incr[11]_i_1_n_0\, + D => p_1_in(0), + Q => \^axaddr_incr_reg[11]_0\(0), + R => '0' + ); +\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_incr[11]_i_1_n_0\, + D => p_1_in(10), + Q => \^axaddr_incr_reg[11]_0\(10), + R => '0' + ); +\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_incr[11]_i_1_n_0\, + D => p_1_in(11), + Q => \^axaddr_incr_reg[11]_0\(11), + R => '0' + ); +\axaddr_incr_reg[11]_i_4\: unisim.vcomponents.CARRY4 + port map ( + CI => \axaddr_incr_reg[7]_i_3_n_0\, + CO(3) => \NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED\(3), + CO(2) => \axaddr_incr_reg[11]_i_4_n_1\, + CO(1) => \axaddr_incr_reg[11]_i_4_n_2\, + CO(0) => \axaddr_incr_reg[11]_i_4_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \axaddr_incr_reg[11]_i_4_n_4\, + O(2) => \axaddr_incr_reg[11]_i_4_n_5\, + O(1) => \axaddr_incr_reg[11]_i_4_n_6\, + O(0) => \axaddr_incr_reg[11]_i_4_n_7\, + S(3 downto 0) => \^axaddr_incr_reg[11]_0\(11 downto 8) + ); +\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_incr[11]_i_1_n_0\, + D => p_1_in(1), + Q => \^axaddr_incr_reg[11]_0\(1), + R => '0' + ); +\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_incr[11]_i_1_n_0\, + D => p_1_in(2), + Q => \^axaddr_incr_reg[11]_0\(2), + R => '0' + ); +\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_incr[11]_i_1_n_0\, + D => p_1_in(3), + Q => \^axaddr_incr_reg[11]_0\(3), + R => '0' + ); +\axaddr_incr_reg[3]_i_3\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \axaddr_incr_reg[3]_i_3_n_0\, + CO(2) => \axaddr_incr_reg[3]_i_3_n_1\, + CO(1) => \axaddr_incr_reg[3]_i_3_n_2\, + CO(0) => \axaddr_incr_reg[3]_i_3_n_3\, + CYINIT => '0', + DI(3 downto 0) => \^axaddr_incr_reg[11]_0\(3 downto 0), + O(3) => \axaddr_incr_reg[3]_i_3_n_4\, + O(2) => \axaddr_incr_reg[3]_i_3_n_5\, + O(1) => \axaddr_incr_reg[3]_i_3_n_6\, + O(0) => \axaddr_incr_reg[3]_i_3_n_7\, + S(3 downto 0) => S(3 downto 0) + ); +\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_incr[11]_i_1_n_0\, + D => p_1_in(4), + Q => \^axaddr_incr_reg[11]_0\(4), + R => '0' + ); +\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_incr[11]_i_1_n_0\, + D => p_1_in(5), + Q => \^axaddr_incr_reg[11]_0\(5), + R => '0' + ); +\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_incr[11]_i_1_n_0\, + D => p_1_in(6), + Q => \^axaddr_incr_reg[11]_0\(6), + R => '0' + ); +\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_incr[11]_i_1_n_0\, + D => p_1_in(7), + Q => \^axaddr_incr_reg[11]_0\(7), + R => '0' + ); +\axaddr_incr_reg[7]_i_3\: unisim.vcomponents.CARRY4 + port map ( + CI => \axaddr_incr_reg[3]_i_3_n_0\, + CO(3) => \axaddr_incr_reg[7]_i_3_n_0\, + CO(2) => \axaddr_incr_reg[7]_i_3_n_1\, + CO(1) => \axaddr_incr_reg[7]_i_3_n_2\, + CO(0) => \axaddr_incr_reg[7]_i_3_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \axaddr_incr_reg[7]_i_3_n_4\, + O(2) => \axaddr_incr_reg[7]_i_3_n_5\, + O(1) => \axaddr_incr_reg[7]_i_3_n_6\, + O(0) => \axaddr_incr_reg[7]_i_3_n_7\, + S(3 downto 0) => \^axaddr_incr_reg[11]_0\(7 downto 4) + ); +\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_incr[11]_i_1_n_0\, + D => p_1_in(8), + Q => \^axaddr_incr_reg[11]_0\(8), + R => '0' + ); +\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_incr[11]_i_1_n_0\, + D => p_1_in(9), + Q => \^axaddr_incr_reg[11]_0\(9), + R => '0' + ); +\axlen_cnt[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4444F44444444444" + ) + port map ( + I0 => axlen_cnt(0), + I1 => \^axlen_cnt_reg[5]_0\, + I2 => \axlen_cnt_reg[3]_0\(6), + I3 => Q(0), + I4 => Q(1), + I5 => si_rs_awvalid, + O => \axlen_cnt[0]_i_1_n_0\ + ); +\axlen_cnt[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F44F4444" + ) + port map ( + I0 => \axlen_cnt_reg[3]_1\, + I1 => \axlen_cnt_reg[3]_0\(7), + I2 => axlen_cnt(1), + I3 => axlen_cnt(0), + I4 => \^axlen_cnt_reg[5]_0\, + O => \axlen_cnt[1]_i_1_n_0\ + ); +\axlen_cnt[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F4F4F44F44444444" + ) + port map ( + I0 => \axlen_cnt_reg[3]_1\, + I1 => \axlen_cnt_reg[3]_0\(8), + I2 => axlen_cnt(2), + I3 => axlen_cnt(0), + I4 => axlen_cnt(1), + I5 => \^axlen_cnt_reg[5]_0\, + O => \axlen_cnt[2]_i_1_n_0\ + ); +\axlen_cnt[3]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"4FF44444" + ) + port map ( + I0 => \axlen_cnt_reg[3]_1\, + I1 => \axlen_cnt_reg[3]_0\(9), + I2 => axlen_cnt(3), + I3 => \axlen_cnt[3]_i_4_n_0\, + I4 => \^axlen_cnt_reg[5]_0\, + O => \axlen_cnt[3]_i_2_n_0\ + ); +\axlen_cnt[3]_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"01" + ) + port map ( + I0 => axlen_cnt(0), + I1 => axlen_cnt(1), + I2 => axlen_cnt(2), + O => \axlen_cnt[3]_i_4_n_0\ + ); +\axlen_cnt[4]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8888888888888882" + ) + port map ( + I0 => \^axlen_cnt_reg[5]_0\, + I1 => axlen_cnt(4), + I2 => axlen_cnt(3), + I3 => axlen_cnt(0), + I4 => axlen_cnt(1), + I5 => axlen_cnt(2), + O => \axlen_cnt[4]_i_1__2_n_0\ + ); +\axlen_cnt[5]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAAAAAAAA9" + ) + port map ( + I0 => axlen_cnt(5), + I1 => axlen_cnt(0), + I2 => axlen_cnt(1), + I3 => axlen_cnt(2), + I4 => axlen_cnt(4), + I5 => axlen_cnt(3), + O => \axlen_cnt[5]_i_2_n_0\ + ); +\axlen_cnt[6]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8882" + ) + port map ( + I0 => \^axlen_cnt_reg[5]_0\, + I1 => axlen_cnt(6), + I2 => \axlen_cnt[7]_i_2_n_0\, + I3 => axlen_cnt(5), + O => \axlen_cnt[6]_i_1__0_n_0\ + ); +\axlen_cnt[7]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888882" + ) + port map ( + I0 => \^axlen_cnt_reg[5]_0\, + I1 => axlen_cnt(7), + I2 => \axlen_cnt[7]_i_2_n_0\, + I3 => axlen_cnt(6), + I4 => axlen_cnt(5), + O => \axlen_cnt[7]_i_1__0_n_0\ + ); +\axlen_cnt[7]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => axlen_cnt(3), + I1 => axlen_cnt(4), + I2 => axlen_cnt(2), + I3 => axlen_cnt(1), + I4 => axlen_cnt(0), + O => \axlen_cnt[7]_i_2_n_0\ + ); +\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axlen_cnt_reg[4]_0\, + D => \axlen_cnt[0]_i_1_n_0\, + Q => axlen_cnt(0), + R => '0' + ); +\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axlen_cnt_reg[4]_0\, + D => \axlen_cnt[1]_i_1_n_0\, + Q => axlen_cnt(1), + R => '0' + ); +\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axlen_cnt_reg[4]_0\, + D => \axlen_cnt[2]_i_1_n_0\, + Q => axlen_cnt(2), + R => '0' + ); +\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axlen_cnt_reg[4]_0\, + D => \axlen_cnt[3]_i_2_n_0\, + Q => axlen_cnt(3), + R => '0' + ); +\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axlen_cnt_reg[4]_0\, + D => \axlen_cnt[4]_i_1__2_n_0\, + Q => axlen_cnt(4), + R => '0' + ); +\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axlen_cnt_reg[4]_0\, + D => \axlen_cnt[5]_i_2_n_0\, + Q => axlen_cnt(5), + R => \axlen_cnt_reg[5]_1\ + ); +\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axlen_cnt_reg[4]_0\, + D => \axlen_cnt[6]_i_1__0_n_0\, + Q => axlen_cnt(6), + R => '0' + ); +\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axlen_cnt_reg[4]_0\, + D => \axlen_cnt[7]_i_1__0_n_0\, + Q => axlen_cnt(7), + R => '0' + ); +next_pending_r_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF88F8" + ) + port map ( + I0 => \^axlen_cnt_reg[5]_0\, + I1 => \next\, + I2 => \^next_pending_r\, + I3 => \axlen_cnt_reg[4]_0\, + I4 => next_pending_r_reg_0, + O => incr_next_pending + ); +next_pending_r_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAA8AAAA" + ) + port map ( + I0 => \axlen_cnt_reg[3]_1\, + I1 => axlen_cnt(5), + I2 => axlen_cnt(6), + I3 => axlen_cnt(7), + I4 => next_pending_r_i_5_n_0, + O => \^axlen_cnt_reg[5]_0\ + ); +next_pending_r_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => axlen_cnt(3), + I1 => axlen_cnt(4), + I2 => axlen_cnt(1), + I3 => axlen_cnt(2), + O => next_pending_r_i_5_n_0 + ); +next_pending_r_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => incr_next_pending, + Q => \^next_pending_r\, + R => '0' + ); +sel_first_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => sel_first_reg_1, + Q => \^sel_first_reg_0\, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_incr_cmd_2 is + port ( + incr_next_pending : out STD_LOGIC; + sel_first_reg_0 : out STD_LOGIC; + \axlen_cnt_reg[7]_0\ : out STD_LOGIC; + \axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); + \m_payload_i_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + aclk : in STD_LOGIC; + sel_first_reg_1 : in STD_LOGIC; + \axlen_cnt_reg[2]_0\ : in STD_LOGIC; + \axlen_cnt_reg[2]_1\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); + si_rs_arvalid : in STD_LOGIC; + \axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + r_push : in STD_LOGIC; + \axlen_cnt_reg[4]_0\ : in STD_LOGIC; + next_pending_r_reg_0 : in STD_LOGIC; + \axlen_cnt_reg[3]_0\ : in STD_LOGIC; + \axaddr_incr_reg[11]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \axaddr_incr_reg[7]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \axaddr_incr_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \axlen_cnt_reg[7]_1\ : in STD_LOGIC; + \axaddr_incr_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_arready : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_incr_cmd_2 : entity is "axi_protocol_converter_v2_1_29_b2s_incr_cmd"; +end NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_incr_cmd_2; + +architecture STRUCTURE of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_incr_cmd_2 is + signal \axaddr_incr[0]_i_1__0_n_0\ : STD_LOGIC; + signal \axaddr_incr[10]_i_1__0_n_0\ : STD_LOGIC; + signal \axaddr_incr[11]_i_2__0_n_0\ : STD_LOGIC; + signal \axaddr_incr[1]_i_1__0_n_0\ : STD_LOGIC; + signal \axaddr_incr[2]_i_1__0_n_0\ : STD_LOGIC; + signal \axaddr_incr[3]_i_1__0_n_0\ : STD_LOGIC; + signal \axaddr_incr[4]_i_1__0_n_0\ : STD_LOGIC; + signal \axaddr_incr[5]_i_1__0_n_0\ : STD_LOGIC; + signal \axaddr_incr[6]_i_1__0_n_0\ : STD_LOGIC; + signal \axaddr_incr[7]_i_1__0_n_0\ : STD_LOGIC; + signal \axaddr_incr[8]_i_1__0_n_0\ : STD_LOGIC; + signal \axaddr_incr[9]_i_1__0_n_0\ : STD_LOGIC; + signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \axaddr_incr_reg[11]_i_4__0_n_1\ : STD_LOGIC; + signal \axaddr_incr_reg[11]_i_4__0_n_2\ : STD_LOGIC; + signal \axaddr_incr_reg[11]_i_4__0_n_3\ : STD_LOGIC; + signal \axaddr_incr_reg[11]_i_4__0_n_4\ : STD_LOGIC; + signal \axaddr_incr_reg[11]_i_4__0_n_5\ : STD_LOGIC; + signal \axaddr_incr_reg[11]_i_4__0_n_6\ : STD_LOGIC; + signal \axaddr_incr_reg[11]_i_4__0_n_7\ : STD_LOGIC; + signal \axaddr_incr_reg[3]_i_3__0_n_0\ : STD_LOGIC; + signal \axaddr_incr_reg[3]_i_3__0_n_1\ : STD_LOGIC; + signal \axaddr_incr_reg[3]_i_3__0_n_2\ : STD_LOGIC; + signal \axaddr_incr_reg[3]_i_3__0_n_3\ : STD_LOGIC; + signal \axaddr_incr_reg[3]_i_3__0_n_4\ : STD_LOGIC; + signal \axaddr_incr_reg[3]_i_3__0_n_5\ : STD_LOGIC; + signal \axaddr_incr_reg[3]_i_3__0_n_6\ : STD_LOGIC; + signal \axaddr_incr_reg[3]_i_3__0_n_7\ : STD_LOGIC; + signal \axaddr_incr_reg[7]_i_3__0_n_0\ : STD_LOGIC; + signal \axaddr_incr_reg[7]_i_3__0_n_1\ : STD_LOGIC; + signal \axaddr_incr_reg[7]_i_3__0_n_2\ : STD_LOGIC; + signal \axaddr_incr_reg[7]_i_3__0_n_3\ : STD_LOGIC; + signal \axaddr_incr_reg[7]_i_3__0_n_4\ : STD_LOGIC; + signal \axaddr_incr_reg[7]_i_3__0_n_5\ : STD_LOGIC; + signal \axaddr_incr_reg[7]_i_3__0_n_6\ : STD_LOGIC; + signal \axaddr_incr_reg[7]_i_3__0_n_7\ : STD_LOGIC; + signal \axlen_cnt[0]_i_1__1_n_0\ : STD_LOGIC; + signal \axlen_cnt[1]_i_1__1_n_0\ : STD_LOGIC; + signal \axlen_cnt[2]_i_1__1_n_0\ : STD_LOGIC; + signal \axlen_cnt[3]_i_2__0_n_0\ : STD_LOGIC; + signal \axlen_cnt[4]_i_1__1_n_0\ : STD_LOGIC; + signal \axlen_cnt[5]_i_1__0_n_0\ : STD_LOGIC; + signal \axlen_cnt[6]_i_1_n_0\ : STD_LOGIC; + signal \axlen_cnt[7]_i_2__0_n_0\ : STD_LOGIC; + signal \axlen_cnt[7]_i_3_n_0\ : STD_LOGIC; + signal \^axlen_cnt_reg[7]_0\ : STD_LOGIC; + signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC; + signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; + signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; + signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; + signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC; + signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC; + signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC; + signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC; + signal \^incr_next_pending\ : STD_LOGIC; + signal next_pending_r : STD_LOGIC; + signal \next_pending_r_i_4__0_n_0\ : STD_LOGIC; + signal \^sel_first_reg_0\ : STD_LOGIC; + signal \NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1__0\ : label is "soft_lutpair13"; + attribute SOFT_HLUTNM of \axaddr_incr[10]_i_1__0\ : label is "soft_lutpair9"; + attribute SOFT_HLUTNM of \axaddr_incr[11]_i_2__0\ : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of \axaddr_incr[1]_i_1__0\ : label is "soft_lutpair13"; + attribute SOFT_HLUTNM of \axaddr_incr[2]_i_1__0\ : label is "soft_lutpair12"; + attribute SOFT_HLUTNM of \axaddr_incr[3]_i_1__0\ : label is "soft_lutpair12"; + attribute SOFT_HLUTNM of \axaddr_incr[4]_i_1__0\ : label is "soft_lutpair11"; + attribute SOFT_HLUTNM of \axaddr_incr[5]_i_1__0\ : label is "soft_lutpair9"; + attribute SOFT_HLUTNM of \axaddr_incr[6]_i_1__0\ : label is "soft_lutpair11"; + attribute SOFT_HLUTNM of \axaddr_incr[7]_i_1__0\ : label is "soft_lutpair10"; + attribute SOFT_HLUTNM of \axaddr_incr[8]_i_1__0\ : label is "soft_lutpair10"; + attribute SOFT_HLUTNM of \axaddr_incr[9]_i_1__0\ : label is "soft_lutpair8"; + attribute ADDER_THRESHOLD : integer; + attribute ADDER_THRESHOLD of \axaddr_incr_reg[11]_i_4__0\ : label is 35; + attribute ADDER_THRESHOLD of \axaddr_incr_reg[3]_i_3__0\ : label is 35; + attribute ADDER_THRESHOLD of \axaddr_incr_reg[7]_i_3__0\ : label is 35; + attribute SOFT_HLUTNM of \axlen_cnt[4]_i_1__1\ : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of \next_pending_r_i_4__0\ : label is "soft_lutpair7"; +begin + \axaddr_incr_reg[11]_0\(11 downto 0) <= \^axaddr_incr_reg[11]_0\(11 downto 0); + \axlen_cnt_reg[7]_0\ <= \^axlen_cnt_reg[7]_0\; + incr_next_pending <= \^incr_next_pending\; + sel_first_reg_0 <= \^sel_first_reg_0\; +\axaddr_incr[0]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \axaddr_incr_reg[3]_1\(0), + I1 => \^sel_first_reg_0\, + I2 => \axaddr_incr_reg[3]_i_3__0_n_7\, + O => \axaddr_incr[0]_i_1__0_n_0\ + ); +\axaddr_incr[10]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \axaddr_incr_reg[11]_1\(2), + I1 => \^sel_first_reg_0\, + I2 => \axaddr_incr_reg[11]_i_4__0_n_5\, + O => \axaddr_incr[10]_i_1__0_n_0\ + ); +\axaddr_incr[11]_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \axaddr_incr_reg[11]_1\(3), + I1 => \^sel_first_reg_0\, + I2 => \axaddr_incr_reg[11]_i_4__0_n_4\, + O => \axaddr_incr[11]_i_2__0_n_0\ + ); +\axaddr_incr[1]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \axaddr_incr_reg[3]_1\(1), + I1 => \^sel_first_reg_0\, + I2 => \axaddr_incr_reg[3]_i_3__0_n_6\, + O => \axaddr_incr[1]_i_1__0_n_0\ + ); +\axaddr_incr[2]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \axaddr_incr_reg[3]_1\(2), + I1 => \^sel_first_reg_0\, + I2 => \axaddr_incr_reg[3]_i_3__0_n_5\, + O => \axaddr_incr[2]_i_1__0_n_0\ + ); +\axaddr_incr[3]_i_10\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0102020202020202" + ) + port map ( + I0 => \axlen_cnt_reg[2]_1\(0), + I1 => \axlen_cnt_reg[2]_1\(5), + I2 => \axlen_cnt_reg[2]_1\(4), + I3 => Q(1), + I4 => m_axi_arready, + I5 => Q(0), + O => \m_payload_i_reg[3]\(0) + ); +\axaddr_incr[3]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \axaddr_incr_reg[3]_1\(3), + I1 => \^sel_first_reg_0\, + I2 => \axaddr_incr_reg[3]_i_3__0_n_4\, + O => \axaddr_incr[3]_i_1__0_n_0\ + ); +\axaddr_incr[3]_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"6AAAAAAAAAAAAAAA" + ) + port map ( + I0 => \axlen_cnt_reg[2]_1\(3), + I1 => \axlen_cnt_reg[2]_1\(5), + I2 => \axlen_cnt_reg[2]_1\(4), + I3 => Q(1), + I4 => m_axi_arready, + I5 => Q(0), + O => \m_payload_i_reg[3]\(3) + ); +\axaddr_incr[3]_i_8\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1A2A2A2A2A2A2A2A" + ) + port map ( + I0 => \axlen_cnt_reg[2]_1\(2), + I1 => \axlen_cnt_reg[2]_1\(4), + I2 => \axlen_cnt_reg[2]_1\(5), + I3 => Q(1), + I4 => m_axi_arready, + I5 => Q(0), + O => \m_payload_i_reg[3]\(2) + ); +\axaddr_incr[3]_i_9\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1222222222222222" + ) + port map ( + I0 => \axlen_cnt_reg[2]_1\(1), + I1 => \axlen_cnt_reg[2]_1\(5), + I2 => \axlen_cnt_reg[2]_1\(4), + I3 => Q(1), + I4 => m_axi_arready, + I5 => Q(0), + O => \m_payload_i_reg[3]\(1) + ); +\axaddr_incr[4]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \axaddr_incr_reg[7]_0\(0), + I1 => \^sel_first_reg_0\, + I2 => \axaddr_incr_reg[7]_i_3__0_n_7\, + O => \axaddr_incr[4]_i_1__0_n_0\ + ); +\axaddr_incr[5]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \axaddr_incr_reg[7]_0\(1), + I1 => \^sel_first_reg_0\, + I2 => \axaddr_incr_reg[7]_i_3__0_n_6\, + O => \axaddr_incr[5]_i_1__0_n_0\ + ); +\axaddr_incr[6]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \axaddr_incr_reg[7]_0\(2), + I1 => \^sel_first_reg_0\, + I2 => \axaddr_incr_reg[7]_i_3__0_n_5\, + O => \axaddr_incr[6]_i_1__0_n_0\ + ); +\axaddr_incr[7]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \axaddr_incr_reg[7]_0\(3), + I1 => \^sel_first_reg_0\, + I2 => \axaddr_incr_reg[7]_i_3__0_n_4\, + O => \axaddr_incr[7]_i_1__0_n_0\ + ); +\axaddr_incr[8]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \axaddr_incr_reg[11]_1\(0), + I1 => \^sel_first_reg_0\, + I2 => \axaddr_incr_reg[11]_i_4__0_n_7\, + O => \axaddr_incr[8]_i_1__0_n_0\ + ); +\axaddr_incr[9]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \axaddr_incr_reg[11]_1\(1), + I1 => \^sel_first_reg_0\, + I2 => \axaddr_incr_reg[11]_i_4__0_n_6\, + O => \axaddr_incr[9]_i_1__0_n_0\ + ); +\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_incr_reg[0]_0\(0), + D => \axaddr_incr[0]_i_1__0_n_0\, + Q => \^axaddr_incr_reg[11]_0\(0), + R => '0' + ); +\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_incr_reg[0]_0\(0), + D => \axaddr_incr[10]_i_1__0_n_0\, + Q => \^axaddr_incr_reg[11]_0\(10), + R => '0' + ); +\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_incr_reg[0]_0\(0), + D => \axaddr_incr[11]_i_2__0_n_0\, + Q => \^axaddr_incr_reg[11]_0\(11), + R => '0' + ); +\axaddr_incr_reg[11]_i_4__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \axaddr_incr_reg[7]_i_3__0_n_0\, + CO(3) => \NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED\(3), + CO(2) => \axaddr_incr_reg[11]_i_4__0_n_1\, + CO(1) => \axaddr_incr_reg[11]_i_4__0_n_2\, + CO(0) => \axaddr_incr_reg[11]_i_4__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \axaddr_incr_reg[11]_i_4__0_n_4\, + O(2) => \axaddr_incr_reg[11]_i_4__0_n_5\, + O(1) => \axaddr_incr_reg[11]_i_4__0_n_6\, + O(0) => \axaddr_incr_reg[11]_i_4__0_n_7\, + S(3 downto 0) => \^axaddr_incr_reg[11]_0\(11 downto 8) + ); +\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_incr_reg[0]_0\(0), + D => \axaddr_incr[1]_i_1__0_n_0\, + Q => \^axaddr_incr_reg[11]_0\(1), + R => '0' + ); +\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_incr_reg[0]_0\(0), + D => \axaddr_incr[2]_i_1__0_n_0\, + Q => \^axaddr_incr_reg[11]_0\(2), + R => '0' + ); +\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_incr_reg[0]_0\(0), + D => \axaddr_incr[3]_i_1__0_n_0\, + Q => \^axaddr_incr_reg[11]_0\(3), + R => '0' + ); +\axaddr_incr_reg[3]_i_3__0\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \axaddr_incr_reg[3]_i_3__0_n_0\, + CO(2) => \axaddr_incr_reg[3]_i_3__0_n_1\, + CO(1) => \axaddr_incr_reg[3]_i_3__0_n_2\, + CO(0) => \axaddr_incr_reg[3]_i_3__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => \^axaddr_incr_reg[11]_0\(3 downto 0), + O(3) => \axaddr_incr_reg[3]_i_3__0_n_4\, + O(2) => \axaddr_incr_reg[3]_i_3__0_n_5\, + O(1) => \axaddr_incr_reg[3]_i_3__0_n_6\, + O(0) => \axaddr_incr_reg[3]_i_3__0_n_7\, + S(3 downto 0) => \axaddr_incr_reg[3]_0\(3 downto 0) + ); +\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_incr_reg[0]_0\(0), + D => \axaddr_incr[4]_i_1__0_n_0\, + Q => \^axaddr_incr_reg[11]_0\(4), + R => '0' + ); +\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_incr_reg[0]_0\(0), + D => \axaddr_incr[5]_i_1__0_n_0\, + Q => \^axaddr_incr_reg[11]_0\(5), + R => '0' + ); +\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_incr_reg[0]_0\(0), + D => \axaddr_incr[6]_i_1__0_n_0\, + Q => \^axaddr_incr_reg[11]_0\(6), + R => '0' + ); +\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_incr_reg[0]_0\(0), + D => \axaddr_incr[7]_i_1__0_n_0\, + Q => \^axaddr_incr_reg[11]_0\(7), + R => '0' + ); +\axaddr_incr_reg[7]_i_3__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \axaddr_incr_reg[3]_i_3__0_n_0\, + CO(3) => \axaddr_incr_reg[7]_i_3__0_n_0\, + CO(2) => \axaddr_incr_reg[7]_i_3__0_n_1\, + CO(1) => \axaddr_incr_reg[7]_i_3__0_n_2\, + CO(0) => \axaddr_incr_reg[7]_i_3__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \axaddr_incr_reg[7]_i_3__0_n_4\, + O(2) => \axaddr_incr_reg[7]_i_3__0_n_5\, + O(1) => \axaddr_incr_reg[7]_i_3__0_n_6\, + O(0) => \axaddr_incr_reg[7]_i_3__0_n_7\, + S(3 downto 0) => \^axaddr_incr_reg[11]_0\(7 downto 4) + ); +\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_incr_reg[0]_0\(0), + D => \axaddr_incr[8]_i_1__0_n_0\, + Q => \^axaddr_incr_reg[11]_0\(8), + R => '0' + ); +\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_incr_reg[0]_0\(0), + D => \axaddr_incr[9]_i_1__0_n_0\, + Q => \^axaddr_incr_reg[11]_0\(9), + R => '0' + ); +\axlen_cnt[0]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"44F44444" + ) + port map ( + I0 => \axlen_cnt_reg_n_0_[0]\, + I1 => \^axlen_cnt_reg[7]_0\, + I2 => \axlen_cnt_reg[2]_1\(6), + I3 => Q(1), + I4 => si_rs_arvalid, + O => \axlen_cnt[0]_i_1__1_n_0\ + ); +\axlen_cnt[1]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F44F4444" + ) + port map ( + I0 => \axlen_cnt_reg[2]_0\, + I1 => \axlen_cnt_reg[2]_1\(7), + I2 => \axlen_cnt_reg_n_0_[1]\, + I3 => \axlen_cnt_reg_n_0_[0]\, + I4 => \^axlen_cnt_reg[7]_0\, + O => \axlen_cnt[1]_i_1__1_n_0\ + ); +\axlen_cnt[2]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F4F4F44F44444444" + ) + port map ( + I0 => \axlen_cnt_reg[2]_0\, + I1 => \axlen_cnt_reg[2]_1\(8), + I2 => \axlen_cnt_reg_n_0_[2]\, + I3 => \axlen_cnt_reg_n_0_[0]\, + I4 => \axlen_cnt_reg_n_0_[1]\, + I5 => \^axlen_cnt_reg[7]_0\, + O => \axlen_cnt[2]_i_1__1_n_0\ + ); +\axlen_cnt[3]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EEEEEEEBAAAAAAAA" + ) + port map ( + I0 => \axlen_cnt_reg[3]_0\, + I1 => \axlen_cnt_reg_n_0_[3]\, + I2 => \axlen_cnt_reg_n_0_[2]\, + I3 => \axlen_cnt_reg_n_0_[1]\, + I4 => \axlen_cnt_reg_n_0_[0]\, + I5 => \^axlen_cnt_reg[7]_0\, + O => \axlen_cnt[3]_i_2__0_n_0\ + ); +\axlen_cnt[4]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAAAAAA9" + ) + port map ( + I0 => \axlen_cnt_reg_n_0_[4]\, + I1 => \axlen_cnt_reg_n_0_[3]\, + I2 => \axlen_cnt_reg_n_0_[0]\, + I3 => \axlen_cnt_reg_n_0_[1]\, + I4 => \axlen_cnt_reg_n_0_[2]\, + O => \axlen_cnt[4]_i_1__1_n_0\ + ); +\axlen_cnt[5]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAAAAAAAA9" + ) + port map ( + I0 => \axlen_cnt_reg_n_0_[5]\, + I1 => \axlen_cnt_reg_n_0_[0]\, + I2 => \axlen_cnt_reg_n_0_[1]\, + I3 => \axlen_cnt_reg_n_0_[2]\, + I4 => \axlen_cnt_reg_n_0_[4]\, + I5 => \axlen_cnt_reg_n_0_[3]\, + O => \axlen_cnt[5]_i_1__0_n_0\ + ); +\axlen_cnt[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAAAA9AA" + ) + port map ( + I0 => \axlen_cnt_reg_n_0_[6]\, + I1 => \axlen_cnt_reg_n_0_[3]\, + I2 => \axlen_cnt_reg_n_0_[4]\, + I3 => \axlen_cnt[7]_i_3_n_0\, + I4 => \axlen_cnt_reg_n_0_[5]\, + O => \axlen_cnt[6]_i_1_n_0\ + ); +\axlen_cnt[7]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAAAAAA9AA" + ) + port map ( + I0 => \axlen_cnt_reg_n_0_[7]\, + I1 => \axlen_cnt_reg_n_0_[6]\, + I2 => \axlen_cnt_reg_n_0_[5]\, + I3 => \axlen_cnt[7]_i_3_n_0\, + I4 => \axlen_cnt_reg_n_0_[4]\, + I5 => \axlen_cnt_reg_n_0_[3]\, + O => \axlen_cnt[7]_i_2__0_n_0\ + ); +\axlen_cnt[7]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"01" + ) + port map ( + I0 => \axlen_cnt_reg_n_0_[0]\, + I1 => \axlen_cnt_reg_n_0_[1]\, + I2 => \axlen_cnt_reg_n_0_[2]\, + O => \axlen_cnt[7]_i_3_n_0\ + ); +\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axlen_cnt_reg[4]_0\, + D => \axlen_cnt[0]_i_1__1_n_0\, + Q => \axlen_cnt_reg_n_0_[0]\, + R => '0' + ); +\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axlen_cnt_reg[4]_0\, + D => \axlen_cnt[1]_i_1__1_n_0\, + Q => \axlen_cnt_reg_n_0_[1]\, + R => '0' + ); +\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axlen_cnt_reg[4]_0\, + D => \axlen_cnt[2]_i_1__1_n_0\, + Q => \axlen_cnt_reg_n_0_[2]\, + R => '0' + ); +\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axlen_cnt_reg[4]_0\, + D => \axlen_cnt[3]_i_2__0_n_0\, + Q => \axlen_cnt_reg_n_0_[3]\, + R => '0' + ); +\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axlen_cnt_reg[4]_0\, + D => \axlen_cnt[4]_i_1__1_n_0\, + Q => \axlen_cnt_reg_n_0_[4]\, + R => \axlen_cnt_reg[7]_1\ + ); +\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axlen_cnt_reg[4]_0\, + D => \axlen_cnt[5]_i_1__0_n_0\, + Q => \axlen_cnt_reg_n_0_[5]\, + R => \axlen_cnt_reg[7]_1\ + ); +\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axlen_cnt_reg[4]_0\, + D => \axlen_cnt[6]_i_1_n_0\, + Q => \axlen_cnt_reg_n_0_[6]\, + R => \axlen_cnt_reg[7]_1\ + ); +\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axlen_cnt_reg[4]_0\, + D => \axlen_cnt[7]_i_2__0_n_0\, + Q => \axlen_cnt_reg_n_0_[7]\, + R => \axlen_cnt_reg[7]_1\ + ); +\next_pending_r_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF88F8" + ) + port map ( + I0 => \^axlen_cnt_reg[7]_0\, + I1 => r_push, + I2 => next_pending_r, + I3 => \axlen_cnt_reg[4]_0\, + I4 => next_pending_r_reg_0, + O => \^incr_next_pending\ + ); +\next_pending_r_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAA8AAAA" + ) + port map ( + I0 => \axlen_cnt_reg[2]_0\, + I1 => \axlen_cnt_reg_n_0_[7]\, + I2 => \axlen_cnt_reg_n_0_[5]\, + I3 => \axlen_cnt_reg_n_0_[6]\, + I4 => \next_pending_r_i_4__0_n_0\, + O => \^axlen_cnt_reg[7]_0\ + ); +\next_pending_r_i_4__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => \axlen_cnt_reg_n_0_[3]\, + I1 => \axlen_cnt_reg_n_0_[4]\, + I2 => \axlen_cnt_reg_n_0_[1]\, + I3 => \axlen_cnt_reg_n_0_[2]\, + O => \next_pending_r_i_4__0_n_0\ + ); +next_pending_r_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \^incr_next_pending\, + Q => next_pending_r, + R => '0' + ); +sel_first_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => sel_first_reg_1, + Q => \^sel_first_reg_0\, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is + port ( + D : out STD_LOGIC_VECTOR ( 3 downto 0 ); + axaddr_offset : out STD_LOGIC_VECTOR ( 3 downto 0 ); + Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \FSM_sequential_state_reg[1]_0\ : out STD_LOGIC; + \FSM_sequential_state_reg[1]_1\ : out STD_LOGIC; + \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arready_0 : out STD_LOGIC; + m_axi_arready_1 : out STD_LOGIC; + sel_first_i : out STD_LOGIC; + m_axi_arready_2 : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + sel_first_reg : out STD_LOGIC_VECTOR ( 0 to 0 ); + \m_payload_i_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); + \FSM_sequential_state_reg[1]_2\ : out STD_LOGIC; + m_axi_arvalid : out STD_LOGIC; + m_valid_i0 : out STD_LOGIC; + s_ready_i0 : out STD_LOGIC; + m_valid_i_reg : out STD_LOGIC_VECTOR ( 0 to 0 ); + si_rs_arvalid : in STD_LOGIC; + \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arready : in STD_LOGIC; + \axlen_cnt_reg[7]\ : in STD_LOGIC; + \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC; + \axaddr_offset_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 13 downto 0 ); + \axaddr_offset_r_reg[0]\ : in STD_LOGIC; + \FSM_sequential_state_reg[0]_0\ : in STD_LOGIC; + \FSM_sequential_state_reg[1]_3\ : in STD_LOGIC; + \axaddr_offset_r_reg[2]\ : in STD_LOGIC; + \axaddr_offset_r_reg[2]_0\ : in STD_LOGIC; + \axaddr_offset_r_reg[1]\ : in STD_LOGIC; + \axaddr_offset_r_reg[1]_0\ : in STD_LOGIC; + \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; + sel_first_reg_0 : in STD_LOGIC; + areset_d1 : in STD_LOGIC; + \axaddr_incr_reg[0]\ : in STD_LOGIC; + sel_first_reg_1 : in STD_LOGIC; + O : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \axaddr_wrap_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \axaddr_wrap_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \axaddr_wrap_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \axaddr_wrap_reg[10]\ : in STD_LOGIC; + s_axi_arvalid : in STD_LOGIC; + m_valid_i_reg_0 : in STD_LOGIC; + aclk : in STD_LOGIC + ); +end NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm; + +architecture STRUCTURE of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is + signal \^fsm_sequential_state_reg[1]_1\ : STD_LOGIC; + signal \^fsm_sequential_state_reg[1]_2\ : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \axaddr_wrap[11]_i_2__0_n_0\ : STD_LOGIC; + signal \axaddr_wrap[11]_i_4__0_n_0\ : STD_LOGIC; + signal \next_state__0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \wrap_cnt_r[2]_i_2__0_n_0\ : STD_LOGIC; + signal \wrap_cnt_r[3]_i_2__0_n_0\ : STD_LOGIC; + signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_state[0]_i_1__0\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \FSM_sequential_state[1]_i_1__0\ : label is "soft_lutpair1"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_state_reg[0]\ : label is "SM_IDLE:01,SM_DONE:00,SM_CMD_ACCEPTED:10,SM_CMD_EN:11"; + attribute FSM_ENCODED_STATES of \FSM_sequential_state_reg[1]\ : label is "SM_IDLE:01,SM_DONE:00,SM_CMD_ACCEPTED:10,SM_CMD_EN:11"; + attribute SOFT_HLUTNM of \axaddr_incr[11]_i_1__0\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \axaddr_wrap[11]_i_2__0\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \axaddr_wrap[11]_i_4__0\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \axlen_cnt[2]_i_2__0\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \axlen_cnt[3]_i_1__2\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of m_axi_arvalid_INST_0 : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \m_valid_i_i_1__0\ : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of r_push_r_i_1 : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \s_ready_i_i_1__0\ : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1__0\ : label is "soft_lutpair5"; +begin + \FSM_sequential_state_reg[1]_1\ <= \^fsm_sequential_state_reg[1]_1\; + \FSM_sequential_state_reg[1]_2\ <= \^fsm_sequential_state_reg[1]_2\; + Q(1 downto 0) <= \^q\(1 downto 0); + axaddr_offset(3 downto 0) <= \^axaddr_offset\(3 downto 0); + \wrap_second_len_r_reg[3]\(3 downto 0) <= \^wrap_second_len_r_reg[3]\(3 downto 0); +\FSM_sequential_state[0]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"555577F7" + ) + port map ( + I0 => \^q\(1), + I1 => \FSM_sequential_state_reg[0]_0\, + I2 => \^q\(0), + I3 => m_axi_arready, + I4 => \FSM_sequential_state_reg[1]_3\, + O => \next_state__0\(0) + ); +\FSM_sequential_state[1]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00FF4040" + ) + port map ( + I0 => \FSM_sequential_state_reg[0]_0\, + I1 => \^q\(0), + I2 => si_rs_arvalid, + I3 => \FSM_sequential_state_reg[1]_3\, + I4 => \^q\(1), + O => \next_state__0\(1) + ); +\FSM_sequential_state_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => aclk, + CE => '1', + D => \next_state__0\(0), + Q => \^q\(0), + S => areset_d1 + ); +\FSM_sequential_state_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \next_state__0\(1), + Q => \^q\(1), + R => areset_d1 + ); +\axaddr_incr[11]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EAAA" + ) + port map ( + I0 => \axaddr_incr_reg[0]\, + I1 => \^q\(0), + I2 => m_axi_arready, + I3 => \^q\(1), + O => sel_first_reg(0) + ); +\axaddr_offset_r[0]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAEAAA2AAA2AAA2A" + ) + port map ( + I0 => \axaddr_offset_r_reg[3]\(0), + I1 => si_rs_arvalid, + I2 => \^q\(0), + I3 => \^q\(1), + I4 => \axaddr_offset_r_reg[3]_0\(12), + I5 => \axaddr_offset_r_reg[0]\, + O => \^axaddr_offset\(0) + ); +\axaddr_offset_r[1]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BAAABAAABAAA8AAA" + ) + port map ( + I0 => \axaddr_offset_r_reg[3]\(1), + I1 => \^q\(1), + I2 => \^q\(0), + I3 => si_rs_arvalid, + I4 => \axaddr_offset_r_reg[1]\, + I5 => \axaddr_offset_r_reg[1]_0\, + O => \^axaddr_offset\(1) + ); +\axaddr_offset_r[2]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BAAA8AAABAAABAAA" + ) + port map ( + I0 => \axaddr_offset_r_reg[3]\(2), + I1 => \^q\(1), + I2 => \^q\(0), + I3 => si_rs_arvalid, + I4 => \axaddr_offset_r_reg[2]\, + I5 => \axaddr_offset_r_reg[2]_0\, + O => \^axaddr_offset\(2) + ); +\axaddr_offset_r[3]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAA30AAAAAA" + ) + port map ( + I0 => \axaddr_offset_r_reg[3]\(3), + I1 => \axaddr_offset_r_reg[3]_1\, + I2 => \axaddr_offset_r_reg[3]_0\(13), + I3 => si_rs_arvalid, + I4 => \^q\(0), + I5 => \^q\(1), + O => \^axaddr_offset\(3) + ); +\axaddr_wrap[0]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44F444F4FFFF44F4" + ) + port map ( + I0 => \axaddr_wrap[11]_i_2__0_n_0\, + I1 => \axaddr_wrap_reg[3]\(0), + I2 => \axaddr_offset_r_reg[3]_0\(0), + I3 => \^fsm_sequential_state_reg[1]_2\, + I4 => \axaddr_wrap_reg[11]\(0), + I5 => \axaddr_wrap[11]_i_4__0_n_0\, + O => \m_payload_i_reg[11]\(0) + ); +\axaddr_wrap[10]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44F444F4FFFF44F4" + ) + port map ( + I0 => \axaddr_wrap[11]_i_2__0_n_0\, + I1 => O(2), + I2 => \axaddr_wrap_reg[11]\(10), + I3 => \axaddr_wrap[11]_i_4__0_n_0\, + I4 => \axaddr_offset_r_reg[3]_0\(10), + I5 => \^fsm_sequential_state_reg[1]_2\, + O => \m_payload_i_reg[11]\(10) + ); +\axaddr_wrap[11]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44F444F4FFFF44F4" + ) + port map ( + I0 => \axaddr_wrap[11]_i_2__0_n_0\, + I1 => O(3), + I2 => \axaddr_offset_r_reg[3]_0\(11), + I3 => \^fsm_sequential_state_reg[1]_2\, + I4 => \axaddr_wrap_reg[11]\(11), + I5 => \axaddr_wrap[11]_i_4__0_n_0\, + O => \m_payload_i_reg[11]\(11) + ); +\axaddr_wrap[11]_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BFFF" + ) + port map ( + I0 => \axaddr_wrap_reg[10]\, + I1 => \^q\(0), + I2 => m_axi_arready, + I3 => \^q\(1), + O => \axaddr_wrap[11]_i_2__0_n_0\ + ); +\axaddr_wrap[11]_i_4__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => \^q\(0), + I1 => m_axi_arready, + I2 => \^q\(1), + I3 => \axaddr_wrap_reg[10]\, + O => \axaddr_wrap[11]_i_4__0_n_0\ + ); +\axaddr_wrap[1]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44F444F4FFFF44F4" + ) + port map ( + I0 => \axaddr_wrap[11]_i_2__0_n_0\, + I1 => \axaddr_wrap_reg[3]\(1), + I2 => \axaddr_offset_r_reg[3]_0\(1), + I3 => \^fsm_sequential_state_reg[1]_2\, + I4 => \axaddr_wrap_reg[11]\(1), + I5 => \axaddr_wrap[11]_i_4__0_n_0\, + O => \m_payload_i_reg[11]\(1) + ); +\axaddr_wrap[2]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44F444F4FFFF44F4" + ) + port map ( + I0 => \axaddr_wrap[11]_i_4__0_n_0\, + I1 => \axaddr_wrap_reg[11]\(2), + I2 => \axaddr_wrap_reg[3]\(2), + I3 => \axaddr_wrap[11]_i_2__0_n_0\, + I4 => \axaddr_offset_r_reg[3]_0\(2), + I5 => \^fsm_sequential_state_reg[1]_2\, + O => \m_payload_i_reg[11]\(2) + ); +\axaddr_wrap[3]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44F444F4FFFF44F4" + ) + port map ( + I0 => \axaddr_wrap[11]_i_2__0_n_0\, + I1 => \axaddr_wrap_reg[3]\(3), + I2 => \axaddr_wrap_reg[11]\(3), + I3 => \axaddr_wrap[11]_i_4__0_n_0\, + I4 => \axaddr_offset_r_reg[3]_0\(3), + I5 => \^fsm_sequential_state_reg[1]_2\, + O => \m_payload_i_reg[11]\(3) + ); +\axaddr_wrap[4]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44F444F4FFFF44F4" + ) + port map ( + I0 => \axaddr_wrap[11]_i_2__0_n_0\, + I1 => \axaddr_wrap_reg[7]\(0), + I2 => \axaddr_wrap_reg[11]\(4), + I3 => \axaddr_wrap[11]_i_4__0_n_0\, + I4 => \axaddr_offset_r_reg[3]_0\(4), + I5 => \^fsm_sequential_state_reg[1]_2\, + O => \m_payload_i_reg[11]\(4) + ); +\axaddr_wrap[5]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44F444F4FFFF44F4" + ) + port map ( + I0 => \axaddr_wrap[11]_i_2__0_n_0\, + I1 => \axaddr_wrap_reg[7]\(1), + I2 => \axaddr_wrap_reg[11]\(5), + I3 => \axaddr_wrap[11]_i_4__0_n_0\, + I4 => \axaddr_offset_r_reg[3]_0\(5), + I5 => \^fsm_sequential_state_reg[1]_2\, + O => \m_payload_i_reg[11]\(5) + ); +\axaddr_wrap[6]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44F444F4FFFF44F4" + ) + port map ( + I0 => \axaddr_wrap[11]_i_2__0_n_0\, + I1 => \axaddr_wrap_reg[7]\(2), + I2 => \axaddr_wrap_reg[11]\(6), + I3 => \axaddr_wrap[11]_i_4__0_n_0\, + I4 => \axaddr_offset_r_reg[3]_0\(6), + I5 => \^fsm_sequential_state_reg[1]_2\, + O => \m_payload_i_reg[11]\(6) + ); +\axaddr_wrap[7]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44F444F4FFFF44F4" + ) + port map ( + I0 => \axaddr_wrap[11]_i_2__0_n_0\, + I1 => \axaddr_wrap_reg[7]\(3), + I2 => \axaddr_offset_r_reg[3]_0\(7), + I3 => \^fsm_sequential_state_reg[1]_2\, + I4 => \axaddr_wrap_reg[11]\(7), + I5 => \axaddr_wrap[11]_i_4__0_n_0\, + O => \m_payload_i_reg[11]\(7) + ); +\axaddr_wrap[8]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44F444F4FFFF44F4" + ) + port map ( + I0 => \axaddr_wrap[11]_i_2__0_n_0\, + I1 => O(0), + I2 => \axaddr_offset_r_reg[3]_0\(8), + I3 => \^fsm_sequential_state_reg[1]_2\, + I4 => \axaddr_wrap_reg[11]\(8), + I5 => \axaddr_wrap[11]_i_4__0_n_0\, + O => \m_payload_i_reg[11]\(8) + ); +\axaddr_wrap[9]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44F444F4FFFF44F4" + ) + port map ( + I0 => \axaddr_wrap[11]_i_2__0_n_0\, + I1 => O(1), + I2 => \axaddr_wrap_reg[11]\(9), + I3 => \axaddr_wrap[11]_i_4__0_n_0\, + I4 => \axaddr_offset_r_reg[3]_0\(9), + I5 => \^fsm_sequential_state_reg[1]_2\, + O => \m_payload_i_reg[11]\(9) + ); +\axlen_cnt[2]_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"BF" + ) + port map ( + I0 => \^q\(1), + I1 => \^q\(0), + I2 => si_rs_arvalid, + O => \^fsm_sequential_state_reg[1]_1\ + ); +\axlen_cnt[3]_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"A0C0" + ) + port map ( + I0 => m_axi_arready, + I1 => si_rs_arvalid, + I2 => \^q\(0), + I3 => \^q\(1), + O => m_axi_arready_2 + ); +\axlen_cnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000C840" + ) + port map ( + I0 => \^q\(1), + I1 => \^q\(0), + I2 => si_rs_arvalid, + I3 => m_axi_arready, + I4 => \axlen_cnt_reg[7]\, + O => \FSM_sequential_state_reg[1]_0\ + ); +m_axi_arvalid_INST_0: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^q\(1), + I1 => \^q\(0), + O => m_axi_arvalid + ); +\m_payload_i[31]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"57" + ) + port map ( + I0 => si_rs_arvalid, + I1 => \^q\(0), + I2 => \^q\(1), + O => m_valid_i_reg(0) + ); +\m_valid_i_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFE0FFFF" + ) + port map ( + I0 => \^q\(1), + I1 => \^q\(0), + I2 => si_rs_arvalid, + I3 => s_axi_arvalid, + I4 => m_valid_i_reg_0, + O => m_valid_i0 + ); +r_push_r_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \^q\(1), + I1 => m_axi_arready, + I2 => \^q\(0), + O => \^fsm_sequential_state_reg[1]_2\ + ); +\s_ready_i_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"1FFF1F1F" + ) + port map ( + I0 => \^q\(1), + I1 => \^q\(0), + I2 => si_rs_arvalid, + I3 => s_axi_arvalid, + I4 => m_valid_i_reg_0, + O => s_ready_i0 + ); +\sel_first_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF4FCC4CCC" + ) + port map ( + I0 => m_axi_arready, + I1 => sel_first_reg_0, + I2 => \^q\(1), + I3 => \^q\(0), + I4 => si_rs_arvalid, + I5 => areset_d1, + O => m_axi_arready_0 + ); +\sel_first_i_1__3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF4FCC4CCC" + ) + port map ( + I0 => m_axi_arready, + I1 => \axaddr_incr_reg[0]\, + I2 => \^q\(1), + I3 => \^q\(0), + I4 => si_rs_arvalid, + I5 => areset_d1, + O => m_axi_arready_1 + ); +\sel_first_i_1__4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CFFFFFFFCECECCCC" + ) + port map ( + I0 => si_rs_arvalid, + I1 => areset_d1, + I2 => \^q\(1), + I3 => m_axi_arready, + I4 => \^q\(0), + I5 => sel_first_reg_1, + O => sel_first_i + ); +\wrap_boundary_axaddr_r[11]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => si_rs_arvalid, + I1 => \^q\(0), + I2 => \^q\(1), + O => E(0) + ); +\wrap_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"38333333C8CCCCCC" + ) + port map ( + I0 => \^axaddr_offset\(0), + I1 => \wrap_cnt_r[2]_i_2__0_n_0\, + I2 => \^q\(1), + I3 => \^q\(0), + I4 => si_rs_arvalid, + I5 => \wrap_second_len_r_reg[3]_0\(0), + O => D(0) + ); +\wrap_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"3CCCA0A0" + ) + port map ( + I0 => \^axaddr_offset\(1), + I1 => \wrap_second_len_r_reg[3]_0\(1), + I2 => \wrap_cnt_r[2]_i_2__0_n_0\, + I3 => \wrap_second_len_r_reg[3]_0\(0), + I4 => \^fsm_sequential_state_reg[1]_1\, + O => D(1) + ); +\wrap_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"59A9AAAAAAAAAAAA" + ) + port map ( + I0 => \^wrap_second_len_r_reg[3]\(2), + I1 => \^axaddr_offset\(0), + I2 => \^fsm_sequential_state_reg[1]_1\, + I3 => \wrap_second_len_r_reg[3]_0\(0), + I4 => \wrap_cnt_r[2]_i_2__0_n_0\, + I5 => \^wrap_second_len_r_reg[3]\(1), + O => D(2) + ); +\wrap_cnt_r[2]_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \^axaddr_offset\(1), + I1 => \^axaddr_offset\(2), + I2 => \^axaddr_offset\(0), + I3 => \^axaddr_offset\(3), + O => \wrap_cnt_r[2]_i_2__0_n_0\ + ); +\wrap_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"A6AA" + ) + port map ( + I0 => \^wrap_second_len_r_reg[3]\(3), + I1 => \^wrap_second_len_r_reg[3]\(1), + I2 => \wrap_cnt_r[3]_i_2__0_n_0\, + I3 => \^wrap_second_len_r_reg[3]\(2), + O => D(3) + ); +\wrap_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"772277227722772F" + ) + port map ( + I0 => \^fsm_sequential_state_reg[1]_1\, + I1 => \wrap_second_len_r_reg[3]_0\(0), + I2 => \^axaddr_offset\(3), + I3 => \^axaddr_offset\(0), + I4 => \^axaddr_offset\(2), + I5 => \^axaddr_offset\(1), + O => \wrap_cnt_r[3]_i_2__0_n_0\ + ); +\wrap_second_len_r[0]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88BB88BB88BB88B8" + ) + port map ( + I0 => \wrap_second_len_r_reg[3]_0\(0), + I1 => \^fsm_sequential_state_reg[1]_1\, + I2 => \^axaddr_offset\(3), + I3 => \^axaddr_offset\(0), + I4 => \^axaddr_offset\(2), + I5 => \^axaddr_offset\(1), + O => \^wrap_second_len_r_reg[3]\(0) + ); +\wrap_second_len_r[1]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BB88BB8888BB88B8" + ) + port map ( + I0 => \wrap_second_len_r_reg[3]_0\(1), + I1 => \^fsm_sequential_state_reg[1]_1\, + I2 => \^axaddr_offset\(3), + I3 => \^axaddr_offset\(0), + I4 => \^axaddr_offset\(2), + I5 => \^axaddr_offset\(1), + O => \^wrap_second_len_r_reg[3]\(1) + ); +\wrap_second_len_r[2]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBB8888BB8888B8" + ) + port map ( + I0 => \wrap_second_len_r_reg[3]_0\(2), + I1 => \^fsm_sequential_state_reg[1]_1\, + I2 => \^axaddr_offset\(3), + I3 => \^axaddr_offset\(0), + I4 => \^axaddr_offset\(2), + I5 => \^axaddr_offset\(1), + O => \^wrap_second_len_r_reg[3]\(2) + ); +\wrap_second_len_r[3]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFF888888888" + ) + port map ( + I0 => \^fsm_sequential_state_reg[1]_1\, + I1 => \wrap_second_len_r_reg[3]_0\(3), + I2 => \^axaddr_offset\(0), + I3 => \^axaddr_offset\(1), + I4 => \^axaddr_offset\(2), + I5 => \wrap_second_len_r_reg[3]_1\, + O => \^wrap_second_len_r_reg[3]\(3) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_simple_fifo is + port ( + sel : out STD_LOGIC; + addr : out STD_LOGIC_VECTOR ( 1 downto 0 ); + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + \bresp_cnt_reg[1]\ : out STD_LOGIC; + \cnt_read_reg[1]_0\ : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 7 downto 0 ); + mhandshake_r : in STD_LOGIC; + areset_d1 : in STD_LOGIC; + b_push : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + aclk : in STD_LOGIC; + shandshake_r : in STD_LOGIC + ); +end NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_simple_fifo; + +architecture STRUCTURE of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_simple_fifo is + signal \^addr\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^bresp_cnt_reg[1]\ : STD_LOGIC; + signal \cnt_read[0]_i_1_n_0\ : STD_LOGIC; + signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC; + signal \cnt_read[1]_i_3_n_0\ : STD_LOGIC; + signal \cnt_read[1]_i_4_n_0\ : STD_LOGIC; + signal \memory_reg[3][0]_srl4_i_2_n_0\ : STD_LOGIC; + signal \memory_reg[3][0]_srl4_i_3_n_0\ : STD_LOGIC; + signal \memory_reg[3][0]_srl4_i_4_n_0\ : STD_LOGIC; + signal \memory_reg[3][0]_srl4_n_0\ : STD_LOGIC; + signal \memory_reg[3][1]_srl4_n_0\ : STD_LOGIC; + signal \memory_reg[3][2]_srl4_n_0\ : STD_LOGIC; + signal \memory_reg[3][3]_srl4_n_0\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of bvalid_i_i_3 : label is "soft_lutpair120"; + attribute SOFT_HLUTNM of \cnt_read[0]_i_1\ : label is "soft_lutpair121"; + attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair121"; + attribute SOFT_HLUTNM of \cnt_read[1]_i_4\ : label is "soft_lutpair120"; + attribute srl_bus_name : string; + attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; + attribute srl_name : string; + attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 "; + attribute srl_bus_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; + attribute srl_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 "; + attribute srl_bus_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; + attribute srl_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 "; + attribute srl_bus_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; + attribute srl_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 "; + attribute srl_bus_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; + attribute srl_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 "; + attribute srl_bus_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; + attribute srl_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 "; + attribute srl_bus_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; + attribute srl_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 "; + attribute srl_bus_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; + attribute srl_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 "; + attribute srl_bus_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; + attribute srl_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 "; + attribute srl_bus_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; + attribute srl_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 "; + attribute srl_bus_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; + attribute srl_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 "; + attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; + attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 "; + attribute srl_bus_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; + attribute srl_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 "; + attribute srl_bus_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; + attribute srl_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 "; + attribute srl_bus_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; + attribute srl_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 "; + attribute srl_bus_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; + attribute srl_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 "; +begin + addr(1 downto 0) <= \^addr\(1 downto 0); + \bresp_cnt_reg[1]\ <= \^bresp_cnt_reg[1]\; +\bresp_cnt[7]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => areset_d1, + I1 => \^bresp_cnt_reg[1]\, + O => SR(0) + ); +bvalid_i_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^addr\(1), + I1 => \^addr\(0), + O => \cnt_read_reg[1]_0\ + ); +\cnt_read[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"96" + ) + port map ( + I0 => b_push, + I1 => shandshake_r, + I2 => \^addr\(0), + O => \cnt_read[0]_i_1_n_0\ + ); +\cnt_read[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"DB24" + ) + port map ( + I0 => \^addr\(0), + I1 => shandshake_r, + I2 => b_push, + I3 => \^addr\(1), + O => \cnt_read[1]_i_1_n_0\ + ); +\cnt_read[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000041000041" + ) + port map ( + I0 => \cnt_read[1]_i_3_n_0\, + I1 => \memory_reg[3][1]_srl4_n_0\, + I2 => Q(1), + I3 => \memory_reg[3][2]_srl4_n_0\, + I4 => Q(2), + I5 => \cnt_read[1]_i_4_n_0\, + O => \^bresp_cnt_reg[1]\ + ); +\cnt_read[1]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EFFEFFFFFFFFEFFE" + ) + port map ( + I0 => Q(5), + I1 => Q(4), + I2 => Q(0), + I3 => \memory_reg[3][0]_srl4_n_0\, + I4 => Q(3), + I5 => \memory_reg[3][3]_srl4_n_0\, + O => \cnt_read[1]_i_3_n_0\ + ); +\cnt_read[1]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFF8FF" + ) + port map ( + I0 => \^addr\(0), + I1 => \^addr\(1), + I2 => Q(7), + I3 => mhandshake_r, + I4 => Q(6), + O => \cnt_read[1]_i_4_n_0\ + ); +\cnt_read_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => aclk, + CE => '1', + D => \cnt_read[0]_i_1_n_0\, + Q => \^addr\(0), + S => areset_d1 + ); +\cnt_read_reg[1]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => aclk, + CE => '1', + D => \cnt_read[1]_i_1_n_0\, + Q => \^addr\(1), + S => areset_d1 + ); +\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \^addr\(0), + A1 => \^addr\(1), + A2 => '0', + A3 => '0', + CE => b_push, + CLK => aclk, + D => \in\(0), + Q => \memory_reg[3][0]_srl4_n_0\ + ); +\memory_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000200" + ) + port map ( + I0 => \memory_reg[3][0]_srl4_i_2_n_0\, + I1 => Q(4), + I2 => Q(6), + I3 => mhandshake_r, + I4 => \memory_reg[3][0]_srl4_i_3_n_0\, + I5 => \memory_reg[3][0]_srl4_i_4_n_0\, + O => sel + ); +\memory_reg[3][0]_srl4_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"DD0D00000000DD0D" + ) + port map ( + I0 => \memory_reg[3][3]_srl4_n_0\, + I1 => Q(3), + I2 => \memory_reg[3][2]_srl4_n_0\, + I3 => Q(2), + I4 => \memory_reg[3][1]_srl4_n_0\, + I5 => Q(1), + O => \memory_reg[3][0]_srl4_i_2_n_0\ + ); +\memory_reg[3][0]_srl4_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFF8" + ) + port map ( + I0 => \^addr\(0), + I1 => \^addr\(1), + I2 => Q(7), + I3 => Q(5), + O => \memory_reg[3][0]_srl4_i_3_n_0\ + ); +\memory_reg[3][0]_srl4_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2FF22FF2FFFF2FF2" + ) + port map ( + I0 => Q(2), + I1 => \memory_reg[3][2]_srl4_n_0\, + I2 => \memory_reg[3][0]_srl4_n_0\, + I3 => Q(0), + I4 => Q(3), + I5 => \memory_reg[3][3]_srl4_n_0\, + O => \memory_reg[3][0]_srl4_i_4_n_0\ + ); +\memory_reg[3][10]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \^addr\(0), + A1 => \^addr\(1), + A2 => '0', + A3 => '0', + CE => b_push, + CLK => aclk, + D => \in\(6), + Q => \out\(2) + ); +\memory_reg[3][11]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \^addr\(0), + A1 => \^addr\(1), + A2 => '0', + A3 => '0', + CE => b_push, + CLK => aclk, + D => \in\(7), + Q => \out\(3) + ); +\memory_reg[3][12]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \^addr\(0), + A1 => \^addr\(1), + A2 => '0', + A3 => '0', + CE => b_push, + CLK => aclk, + D => \in\(8), + Q => \out\(4) + ); +\memory_reg[3][13]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \^addr\(0), + A1 => \^addr\(1), + A2 => '0', + A3 => '0', + CE => b_push, + CLK => aclk, + D => \in\(9), + Q => \out\(5) + ); +\memory_reg[3][14]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \^addr\(0), + A1 => \^addr\(1), + A2 => '0', + A3 => '0', + CE => b_push, + CLK => aclk, + D => \in\(10), + Q => \out\(6) + ); +\memory_reg[3][15]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \^addr\(0), + A1 => \^addr\(1), + A2 => '0', + A3 => '0', + CE => b_push, + CLK => aclk, + D => \in\(11), + Q => \out\(7) + ); +\memory_reg[3][16]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \^addr\(0), + A1 => \^addr\(1), + A2 => '0', + A3 => '0', + CE => b_push, + CLK => aclk, + D => \in\(12), + Q => \out\(8) + ); +\memory_reg[3][17]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \^addr\(0), + A1 => \^addr\(1), + A2 => '0', + A3 => '0', + CE => b_push, + CLK => aclk, + D => \in\(13), + Q => \out\(9) + ); +\memory_reg[3][18]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \^addr\(0), + A1 => \^addr\(1), + A2 => '0', + A3 => '0', + CE => b_push, + CLK => aclk, + D => \in\(14), + Q => \out\(10) + ); +\memory_reg[3][19]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \^addr\(0), + A1 => \^addr\(1), + A2 => '0', + A3 => '0', + CE => b_push, + CLK => aclk, + D => \in\(15), + Q => \out\(11) + ); +\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \^addr\(0), + A1 => \^addr\(1), + A2 => '0', + A3 => '0', + CE => b_push, + CLK => aclk, + D => \in\(1), + Q => \memory_reg[3][1]_srl4_n_0\ + ); +\memory_reg[3][2]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \^addr\(0), + A1 => \^addr\(1), + A2 => '0', + A3 => '0', + CE => b_push, + CLK => aclk, + D => \in\(2), + Q => \memory_reg[3][2]_srl4_n_0\ + ); +\memory_reg[3][3]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \^addr\(0), + A1 => \^addr\(1), + A2 => '0', + A3 => '0', + CE => b_push, + CLK => aclk, + D => \in\(3), + Q => \memory_reg[3][3]_srl4_n_0\ + ); +\memory_reg[3][8]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \^addr\(0), + A1 => \^addr\(1), + A2 => '0', + A3 => '0', + CE => b_push, + CLK => aclk, + D => \in\(4), + Q => \out\(0) + ); +\memory_reg[3][9]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \^addr\(0), + A1 => \^addr\(1), + A2 => '0', + A3 => '0', + CE => b_push, + CLK => aclk, + D => \in\(5), + Q => \out\(1) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized0\ is + port ( + areset_d1_reg : out STD_LOGIC; + mhandshake : out STD_LOGIC; + m_axi_bready : out STD_LOGIC; + \s_bresp_acc_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + areset_d1 : in STD_LOGIC; + shandshake_r : in STD_LOGIC; + bvalid_i_reg : in STD_LOGIC; + si_rs_bvalid : in STD_LOGIC; + si_rs_bready : in STD_LOGIC; + m_axi_bvalid : in STD_LOGIC; + mhandshake_r : in STD_LOGIC; + sel : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + aclk : in STD_LOGIC; + \cnt_read_reg[1]_0\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized0\ : entity is "axi_protocol_converter_v2_1_29_b2s_simple_fifo"; +end \NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized0\; + +architecture STRUCTURE of \NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized0\ is + signal bvalid_i_i_2_n_0 : STD_LOGIC; + signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \cnt_read[0]_i_1_n_0\ : STD_LOGIC; + signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \cnt_read[0]_i_1\ : label is "soft_lutpair122"; + attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair122"; + attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair123"; + attribute srl_bus_name : string; + attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] "; + attribute srl_name : string; + attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 "; + attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] "; + attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 "; + attribute SOFT_HLUTNM of mhandshake_r_i_1 : label is "soft_lutpair123"; +begin +bvalid_i_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000155550001" + ) + port map ( + I0 => areset_d1, + I1 => bvalid_i_i_2_n_0, + I2 => shandshake_r, + I3 => bvalid_i_reg, + I4 => si_rs_bvalid, + I5 => si_rs_bready, + O => areset_d1_reg + ); +bvalid_i_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => cnt_read(1), + I1 => cnt_read(0), + O => bvalid_i_i_2_n_0 + ); +\cnt_read[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"96" + ) + port map ( + I0 => \cnt_read_reg[1]_0\, + I1 => shandshake_r, + I2 => cnt_read(0), + O => \cnt_read[0]_i_1_n_0\ + ); +\cnt_read[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"DB24" + ) + port map ( + I0 => cnt_read(0), + I1 => shandshake_r, + I2 => \cnt_read_reg[1]_0\, + I3 => cnt_read(1), + O => \cnt_read[1]_i_1_n_0\ + ); +\cnt_read_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => aclk, + CE => '1', + D => \cnt_read[0]_i_1_n_0\, + Q => cnt_read(0), + S => areset_d1 + ); +\cnt_read_reg[1]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => aclk, + CE => '1', + D => \cnt_read[1]_i_1_n_0\, + Q => cnt_read(1), + S => areset_d1 + ); +m_axi_bready_INST_0: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => cnt_read(0), + I1 => cnt_read(1), + I2 => mhandshake_r, + O => m_axi_bready + ); +\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => cnt_read(0), + A1 => cnt_read(1), + A2 => '0', + A3 => '0', + CE => sel, + CLK => aclk, + D => \in\(0), + Q => \s_bresp_acc_reg[1]\(0) + ); +\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => cnt_read(0), + A1 => cnt_read(1), + A2 => '0', + A3 => '0', + CE => sel, + CLK => aclk, + D => \in\(1), + Q => \s_bresp_acc_reg[1]\(1) + ); +mhandshake_r_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2000" + ) + port map ( + I0 => m_axi_bvalid, + I1 => mhandshake_r, + I2 => cnt_read(1), + I3 => cnt_read(0), + O => mhandshake + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized1\ is + port ( + s_ready_i_reg : out STD_LOGIC; + \cnt_read_reg[2]_0\ : out STD_LOGIC; + m_axi_rready : out STD_LOGIC; + \cnt_read_reg[4]_0\ : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 33 downto 0 ); + \cnt_read_reg[4]_1\ : in STD_LOGIC; + si_rs_rready : in STD_LOGIC; + r_push_r : in STD_LOGIC; + m_valid_i_reg : in STD_LOGIC; + m_axi_rvalid : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); + aclk : in STD_LOGIC; + areset_d1 : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized1\ : entity is "axi_protocol_converter_v2_1_29_b2s_simple_fifo"; +end \NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized1\; + +architecture STRUCTURE of \NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized1\ is + signal \cnt_read[0]_i_1_n_0\ : STD_LOGIC; + signal \cnt_read[1]_i_1__0_n_0\ : STD_LOGIC; + signal \cnt_read[2]_i_1_n_0\ : STD_LOGIC; + signal \cnt_read[3]_i_1_n_0\ : STD_LOGIC; + signal \cnt_read[4]_i_1__0_n_0\ : STD_LOGIC; + signal \cnt_read[4]_i_2_n_0\ : STD_LOGIC; + signal \cnt_read[4]_i_4_n_0\ : STD_LOGIC; + signal cnt_read_reg : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \^cnt_read_reg[2]_0\ : STD_LOGIC; + signal wr_en0 : STD_LOGIC; + signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_state[1]_i_4\ : label is "soft_lutpair17"; + attribute SOFT_HLUTNM of \cnt_read[1]_i_1__0\ : label is "soft_lutpair16"; + attribute SOFT_HLUTNM of \cnt_read[2]_i_1\ : label is "soft_lutpair16"; + attribute SOFT_HLUTNM of \cnt_read[4]_i_3\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \cnt_read[4]_i_4\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair17"; + attribute srl_bus_name : string; + attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name : string; + attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 "; + attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 "; + attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 "; + attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 "; + attribute srl_bus_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 "; + attribute srl_bus_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 "; + attribute srl_bus_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 "; + attribute srl_bus_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 "; + attribute srl_bus_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 "; + attribute srl_bus_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 "; + attribute srl_bus_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 "; + attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 "; + attribute srl_bus_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 "; + attribute srl_bus_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 "; + attribute srl_bus_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 "; + attribute srl_bus_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 "; + attribute srl_bus_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 "; + attribute srl_bus_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 "; + attribute srl_bus_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 "; + attribute srl_bus_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 "; + attribute srl_bus_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 "; + attribute srl_bus_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 "; + attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 "; + attribute srl_bus_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 "; + attribute srl_bus_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 "; + attribute srl_bus_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 "; + attribute srl_bus_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 "; + attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 "; + attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 "; + attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 "; + attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 "; + attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 "; + attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 "; + attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 "; +begin + \cnt_read_reg[2]_0\ <= \^cnt_read_reg[2]_0\; +\FSM_sequential_state[1]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"08888800" + ) + port map ( + I0 => cnt_read_reg(4), + I1 => cnt_read_reg(3), + I2 => cnt_read_reg(0), + I3 => cnt_read_reg(1), + I4 => cnt_read_reg(2), + O => \cnt_read_reg[4]_0\ + ); +\cnt_read[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cnt_read_reg(0), + O => \cnt_read[0]_i_1_n_0\ + ); +\cnt_read[1]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"D22D" + ) + port map ( + I0 => wr_en0, + I1 => \cnt_read_reg[4]_1\, + I2 => cnt_read_reg(1), + I3 => cnt_read_reg(0), + O => \cnt_read[1]_i_1__0_n_0\ + ); +\cnt_read[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"A9A96AA9" + ) + port map ( + I0 => cnt_read_reg(2), + I1 => cnt_read_reg(1), + I2 => cnt_read_reg(0), + I3 => wr_en0, + I4 => \cnt_read_reg[4]_1\, + O => \cnt_read[2]_i_1_n_0\ + ); +\cnt_read[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BFFF4000FFF4000B" + ) + port map ( + I0 => \cnt_read_reg[4]_1\, + I1 => wr_en0, + I2 => cnt_read_reg(0), + I3 => cnt_read_reg(1), + I4 => cnt_read_reg(3), + I5 => cnt_read_reg(2), + O => \cnt_read[3]_i_1_n_0\ + ); +\cnt_read[4]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => wr_en0, + I1 => \cnt_read_reg[4]_1\, + O => \cnt_read[4]_i_1__0_n_0\ + ); +\cnt_read[4]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9AAAAAAAAAAAAAA6" + ) + port map ( + I0 => cnt_read_reg(4), + I1 => \cnt_read[4]_i_4_n_0\, + I2 => cnt_read_reg(0), + I3 => cnt_read_reg(1), + I4 => cnt_read_reg(3), + I5 => cnt_read_reg(2), + O => \cnt_read[4]_i_2_n_0\ + ); +\cnt_read[4]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"4F" + ) + port map ( + I0 => \^cnt_read_reg[2]_0\, + I1 => si_rs_rready, + I2 => r_push_r, + O => s_ready_i_reg + ); +\cnt_read[4]_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"4F" + ) + port map ( + I0 => \^cnt_read_reg[2]_0\, + I1 => si_rs_rready, + I2 => wr_en0, + O => \cnt_read[4]_i_4_n_0\ + ); +\cnt_read_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => aclk, + CE => \cnt_read[4]_i_1__0_n_0\, + D => \cnt_read[0]_i_1_n_0\, + Q => cnt_read_reg(0), + S => areset_d1 + ); +\cnt_read_reg[1]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => aclk, + CE => \cnt_read[4]_i_1__0_n_0\, + D => \cnt_read[1]_i_1__0_n_0\, + Q => cnt_read_reg(1), + S => areset_d1 + ); +\cnt_read_reg[2]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => aclk, + CE => \cnt_read[4]_i_1__0_n_0\, + D => \cnt_read[2]_i_1_n_0\, + Q => cnt_read_reg(2), + S => areset_d1 + ); +\cnt_read_reg[3]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => aclk, + CE => \cnt_read[4]_i_1__0_n_0\, + D => \cnt_read[3]_i_1_n_0\, + Q => cnt_read_reg(3), + S => areset_d1 + ); +\cnt_read_reg[4]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => aclk, + CE => \cnt_read[4]_i_1__0_n_0\, + D => \cnt_read[4]_i_2_n_0\, + Q => cnt_read_reg(4), + S => areset_d1 + ); +m_axi_rready_INST_0: unisim.vcomponents.LUT5 + generic map( + INIT => X"91FFFFFF" + ) + port map ( + I0 => cnt_read_reg(2), + I1 => cnt_read_reg(1), + I2 => cnt_read_reg(0), + I3 => cnt_read_reg(3), + I4 => cnt_read_reg(4), + O => m_axi_rready + ); +m_valid_i_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF80000000" + ) + port map ( + I0 => cnt_read_reg(2), + I1 => cnt_read_reg(1), + I2 => cnt_read_reg(0), + I3 => cnt_read_reg(4), + I4 => cnt_read_reg(3), + I5 => m_valid_i_reg, + O => \^cnt_read_reg[2]_0\ + ); +\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(0), + Q => \out\(0), + Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8202AAAAAAAAAAAA" + ) + port map ( + I0 => m_axi_rvalid, + I1 => cnt_read_reg(2), + I2 => cnt_read_reg(1), + I3 => cnt_read_reg(0), + I4 => cnt_read_reg(3), + I5 => cnt_read_reg(4), + O => wr_en0 + ); +\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(10), + Q => \out\(10), + Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(11), + Q => \out\(11), + Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(12), + Q => \out\(12), + Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(13), + Q => \out\(13), + Q31 => \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(14), + Q => \out\(14), + Q31 => \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][15]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(15), + Q => \out\(15), + Q31 => \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(16), + Q => \out\(16), + Q31 => \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(17), + Q => \out\(17), + Q31 => \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(18), + Q => \out\(18), + Q31 => \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(19), + Q => \out\(19), + Q31 => \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(1), + Q => \out\(1), + Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(20), + Q => \out\(20), + Q31 => \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(21), + Q => \out\(21), + Q31 => \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(22), + Q => \out\(22), + Q31 => \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(23), + Q => \out\(23), + Q31 => \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(24), + Q => \out\(24), + Q31 => \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(25), + Q => \out\(25), + Q31 => \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(26), + Q => \out\(26), + Q31 => \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(27), + Q => \out\(27), + Q31 => \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(28), + Q => \out\(28), + Q31 => \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(29), + Q => \out\(29), + Q31 => \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(2), + Q => \out\(2), + Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(30), + Q => \out\(30), + Q31 => \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(31), + Q => \out\(31), + Q31 => \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(32), + Q => \out\(32), + Q31 => \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(33), + Q => \out\(33), + Q31 => \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(3), + Q => \out\(3), + Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(4), + Q => \out\(4), + Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(5), + Q => \out\(5), + Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(6), + Q => \out\(6), + Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(7), + Q => \out\(7), + Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(8), + Q => \out\(8), + Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => wr_en0, + CLK => aclk, + D => \in\(9), + Q => \out\(9), + Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized2\ is + port ( + \cnt_read_reg[4]_0\ : out STD_LOGIC; + \cnt_read_reg[4]_1\ : out STD_LOGIC; + r_push_r_reg : out STD_LOGIC_VECTOR ( 12 downto 0 ); + r_push_r : in STD_LOGIC; + \cnt_read_reg[4]_2\ : in STD_LOGIC; + \cnt_read_reg[4]_3\ : in STD_LOGIC; + \FSM_sequential_state_reg[0]\ : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + aclk : in STD_LOGIC; + areset_d1 : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized2\ : entity is "axi_protocol_converter_v2_1_29_b2s_simple_fifo"; +end \NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized2\; + +architecture STRUCTURE of \NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized2\ is + signal \cnt_read[0]_i_1__0_n_0\ : STD_LOGIC; + signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC; + signal \cnt_read[2]_i_1__0_n_0\ : STD_LOGIC; + signal \cnt_read[3]_i_1__0_n_0\ : STD_LOGIC; + signal \cnt_read[4]_i_1_n_0\ : STD_LOGIC; + signal \cnt_read[4]_i_2__0_n_0\ : STD_LOGIC; + signal cnt_read_reg : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \cnt_read[0]_i_1__0\ : label is "soft_lutpair19"; + attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair20"; + attribute SOFT_HLUTNM of \cnt_read[2]_i_1__0\ : label is "soft_lutpair20"; + attribute SOFT_HLUTNM of m_valid_i_i_3 : label is "soft_lutpair19"; + attribute srl_bus_name : string; + attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; + attribute srl_name : string; + attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 "; + attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 "; + attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 "; + attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 "; + attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 "; + attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 "; + attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 "; + attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 "; + attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 "; + attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 "; + attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 "; + attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 "; + attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; + attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 "; +begin +\FSM_sequential_state[1]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAEAEAAAEAEAEAAA" + ) + port map ( + I0 => \FSM_sequential_state_reg[0]\, + I1 => cnt_read_reg(4), + I2 => cnt_read_reg(3), + I3 => cnt_read_reg(2), + I4 => cnt_read_reg(1), + I5 => cnt_read_reg(0), + O => \cnt_read_reg[4]_0\ + ); +\cnt_read[0]_i_1__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cnt_read_reg(0), + O => \cnt_read[0]_i_1__0_n_0\ + ); +\cnt_read[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"D22D" + ) + port map ( + I0 => r_push_r, + I1 => \cnt_read_reg[4]_2\, + I2 => cnt_read_reg(0), + I3 => cnt_read_reg(1), + O => \cnt_read[1]_i_1_n_0\ + ); +\cnt_read[2]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"A6AAAA59" + ) + port map ( + I0 => cnt_read_reg(2), + I1 => r_push_r, + I2 => \cnt_read_reg[4]_2\, + I3 => cnt_read_reg(0), + I4 => cnt_read_reg(1), + O => \cnt_read[2]_i_1__0_n_0\ + ); +\cnt_read[3]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F7FFEFEE08001011" + ) + port map ( + I0 => cnt_read_reg(1), + I1 => cnt_read_reg(0), + I2 => \cnt_read_reg[4]_2\, + I3 => r_push_r, + I4 => cnt_read_reg(2), + I5 => cnt_read_reg(3), + O => \cnt_read[3]_i_1__0_n_0\ + ); +\cnt_read[4]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => r_push_r, + I1 => \cnt_read_reg[4]_2\, + O => \cnt_read[4]_i_1_n_0\ + ); +\cnt_read[4]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AA6AAAAAAAAAA9AA" + ) + port map ( + I0 => cnt_read_reg(4), + I1 => cnt_read_reg(2), + I2 => cnt_read_reg(3), + I3 => \cnt_read_reg[4]_3\, + I4 => cnt_read_reg(1), + I5 => cnt_read_reg(0), + O => \cnt_read[4]_i_2__0_n_0\ + ); +\cnt_read_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => aclk, + CE => \cnt_read[4]_i_1_n_0\, + D => \cnt_read[0]_i_1__0_n_0\, + Q => cnt_read_reg(0), + S => areset_d1 + ); +\cnt_read_reg[1]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => aclk, + CE => \cnt_read[4]_i_1_n_0\, + D => \cnt_read[1]_i_1_n_0\, + Q => cnt_read_reg(1), + S => areset_d1 + ); +\cnt_read_reg[2]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => aclk, + CE => \cnt_read[4]_i_1_n_0\, + D => \cnt_read[2]_i_1__0_n_0\, + Q => cnt_read_reg(2), + S => areset_d1 + ); +\cnt_read_reg[3]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => aclk, + CE => \cnt_read[4]_i_1_n_0\, + D => \cnt_read[3]_i_1__0_n_0\, + Q => cnt_read_reg(3), + S => areset_d1 + ); +\cnt_read_reg[4]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => aclk, + CE => \cnt_read[4]_i_1_n_0\, + D => \cnt_read[4]_i_2__0_n_0\, + Q => cnt_read_reg(4), + S => areset_d1 + ); +m_valid_i_i_3: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => cnt_read_reg(4), + I1 => cnt_read_reg(3), + I2 => cnt_read_reg(2), + I3 => cnt_read_reg(1), + I4 => cnt_read_reg(0), + O => \cnt_read_reg[4]_1\ + ); +\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => r_push_r, + CLK => aclk, + D => \in\(0), + Q => r_push_r_reg(0), + Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => r_push_r, + CLK => aclk, + D => \in\(10), + Q => r_push_r_reg(10), + Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => r_push_r, + CLK => aclk, + D => \in\(11), + Q => r_push_r_reg(11), + Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => r_push_r, + CLK => aclk, + D => \in\(12), + Q => r_push_r_reg(12), + Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => r_push_r, + CLK => aclk, + D => \in\(1), + Q => r_push_r_reg(1), + Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => r_push_r, + CLK => aclk, + D => \in\(2), + Q => r_push_r_reg(2), + Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => r_push_r, + CLK => aclk, + D => \in\(3), + Q => r_push_r_reg(3), + Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => r_push_r, + CLK => aclk, + D => \in\(4), + Q => r_push_r_reg(4), + Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => r_push_r, + CLK => aclk, + D => \in\(5), + Q => r_push_r_reg(5), + Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => r_push_r, + CLK => aclk, + D => \in\(6), + Q => r_push_r_reg(6), + Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => r_push_r, + CLK => aclk, + D => \in\(7), + Q => r_push_r_reg(7), + Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => r_push_r, + CLK => aclk, + D => \in\(8), + Q => r_push_r_reg(8), + Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ + ); +\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => cnt_read_reg(4 downto 0), + CE => r_push_r, + CLK => aclk, + D => \in\(9), + Q => r_push_r_reg(9), + Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm is + port ( + D : out STD_LOGIC_VECTOR ( 3 downto 0 ); + axaddr_offset : out STD_LOGIC_VECTOR ( 3 downto 0 ); + Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \FSM_sequential_state_reg[0]_0\ : out STD_LOGIC; + \FSM_sequential_state_reg[0]_1\ : out STD_LOGIC; + \FSM_sequential_state_reg[0]_2\ : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awready_0 : out STD_LOGIC; + \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \axlen_cnt_reg[2]\ : out STD_LOGIC; + \next\ : out STD_LOGIC; + \axlen_cnt_reg[2]_0\ : out STD_LOGIC; + m_valid_i_reg : out STD_LOGIC_VECTOR ( 0 to 0 ); + sel_first_reg : out STD_LOGIC; + sel_first_reg_0 : out STD_LOGIC; + sel_first_i : out STD_LOGIC; + \wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_awvalid : out STD_LOGIC; + si_rs_awvalid : in STD_LOGIC; + \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axburst_eq0_reg : in STD_LOGIC; + \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC; + \axaddr_offset_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 14 downto 0 ); + \axaddr_offset_r_reg[0]\ : in STD_LOGIC; + \axaddr_offset_r_reg[2]\ : in STD_LOGIC; + \axaddr_offset_r_reg[2]_0\ : in STD_LOGIC; + s_axburst_eq0_reg_0 : in STD_LOGIC; + \FSM_sequential_state_reg[1]_0\ : in STD_LOGIC; + m_axi_awready : in STD_LOGIC; + s_axburst_eq1_reg : in STD_LOGIC; + next_pending_r : in STD_LOGIC; + next_pending_r_0 : in STD_LOGIC; + sel_first : in STD_LOGIC; + areset_d1 : in STD_LOGIC; + sel_first_reg_1 : in STD_LOGIC; + sel_first_reg_2 : in STD_LOGIC; + \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; + \axaddr_offset_r_reg[1]\ : in STD_LOGIC; + \axaddr_offset_r_reg[1]_0\ : in STD_LOGIC; + \axaddr_wrap_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); + axaddr_wrap0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \axaddr_wrap_reg[10]\ : in STD_LOGIC; + cnt_read : in STD_LOGIC_VECTOR ( 1 downto 0 ); + aclk : in STD_LOGIC + ); +end NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm; + +architecture STRUCTURE of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm is + signal \^fsm_sequential_state_reg[0]_1\ : STD_LOGIC; + signal \^fsm_sequential_state_reg[0]_2\ : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \axaddr_wrap[11]_i_2_n_0\ : STD_LOGIC; + signal \axaddr_wrap[11]_i_4_n_0\ : STD_LOGIC; + signal \^m_axi_awready_0\ : STD_LOGIC; + signal \^next\ : STD_LOGIC; + signal \next_state__0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s_axburst_eq0_i_2_n_0 : STD_LOGIC; + signal s_axburst_eq0_i_3_n_0 : STD_LOGIC; + signal s_axburst_eq0_i_4_n_0 : STD_LOGIC; + signal s_axburst_eq0_i_5_n_0 : STD_LOGIC; + signal s_axburst_eq1_i_2_n_0 : STD_LOGIC; + signal \wrap_cnt_r[2]_i_2_n_0\ : STD_LOGIC; + signal \wrap_cnt_r[3]_i_2_n_0\ : STD_LOGIC; + signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_state[1]_i_1\ : label is "soft_lutpair108"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_state_reg[0]\ : label is "SM_CMD_ACCEPTED:10,SM_CMD_EN:11,SM_IDLE:01,SM_DONE_WAIT:00"; + attribute FSM_ENCODED_STATES of \FSM_sequential_state_reg[1]\ : label is "SM_CMD_ACCEPTED:10,SM_CMD_EN:11,SM_IDLE:01,SM_DONE_WAIT:00"; + attribute SOFT_HLUTNM of \axaddr_wrap[11]_i_2\ : label is "soft_lutpair110"; + attribute SOFT_HLUTNM of \axaddr_wrap[11]_i_4\ : label is "soft_lutpair110"; + attribute SOFT_HLUTNM of \axlen_cnt[3]_i_1__0\ : label is "soft_lutpair109"; + attribute SOFT_HLUTNM of \axlen_cnt[3]_i_3__0\ : label is "soft_lutpair108"; + attribute SOFT_HLUTNM of next_pending_r_i_3 : label is "soft_lutpair111"; + attribute SOFT_HLUTNM of s_axburst_eq0_i_5 : label is "soft_lutpair111"; + attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1\ : label is "soft_lutpair109"; +begin + \FSM_sequential_state_reg[0]_1\ <= \^fsm_sequential_state_reg[0]_1\; + \FSM_sequential_state_reg[0]_2\ <= \^fsm_sequential_state_reg[0]_2\; + Q(1 downto 0) <= \^q\(1 downto 0); + axaddr_offset(3 downto 0) <= \^axaddr_offset\(3 downto 0); + m_axi_awready_0 <= \^m_axi_awready_0\; + \next\ <= \^next\; + \wrap_second_len_r_reg[3]\(3 downto 0) <= \^wrap_second_len_r_reg[3]\(3 downto 0); +\FSM_sequential_state[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7737FFFFFFFFFF0F" + ) + port map ( + I0 => \FSM_sequential_state_reg[1]_0\, + I1 => m_axi_awready, + I2 => cnt_read(1), + I3 => cnt_read(0), + I4 => \^q\(1), + I5 => \^q\(0), + O => \next_state__0\(0) + ); +\FSM_sequential_state[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACF0FCF0" + ) + port map ( + I0 => \FSM_sequential_state_reg[1]_0\, + I1 => si_rs_awvalid, + I2 => \^q\(1), + I3 => \^q\(0), + I4 => m_axi_awready, + O => \next_state__0\(1) + ); +\FSM_sequential_state_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => aclk, + CE => '1', + D => \next_state__0\(0), + Q => \^q\(0), + S => areset_d1 + ); +\FSM_sequential_state_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \next_state__0\(1), + Q => \^q\(1), + R => areset_d1 + ); +\axaddr_offset_r[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AEAAA2AAA2AAA2AA" + ) + port map ( + I0 => \axaddr_offset_r_reg[3]\(0), + I1 => si_rs_awvalid, + I2 => \^q\(1), + I3 => \^q\(0), + I4 => \axaddr_offset_r_reg[3]_0\(13), + I5 => \axaddr_offset_r_reg[0]\, + O => \^axaddr_offset\(0) + ); +\axaddr_offset_r[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AEAAAEAAAEAAA2AA" + ) + port map ( + I0 => \axaddr_offset_r_reg[3]\(1), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => si_rs_awvalid, + I4 => \axaddr_offset_r_reg[1]\, + I5 => \axaddr_offset_r_reg[1]_0\, + O => \^axaddr_offset\(1) + ); +\axaddr_offset_r[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AEAAA2AAAEAAAEAA" + ) + port map ( + I0 => \axaddr_offset_r_reg[3]\(2), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => si_rs_awvalid, + I4 => \axaddr_offset_r_reg[2]\, + I5 => \axaddr_offset_r_reg[2]_0\, + O => \^axaddr_offset\(2) + ); +\axaddr_offset_r[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAA30AAAAAAAAAA" + ) + port map ( + I0 => \axaddr_offset_r_reg[3]\(3), + I1 => \axaddr_offset_r_reg[3]_1\, + I2 => \axaddr_offset_r_reg[3]_0\(14), + I3 => si_rs_awvalid, + I4 => \^q\(1), + I5 => \^q\(0), + O => \^axaddr_offset\(3) + ); +\axaddr_wrap[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44F444F4FFFF44F4" + ) + port map ( + I0 => \axaddr_wrap[11]_i_2_n_0\, + I1 => \axaddr_wrap_reg[11]\(0), + I2 => axaddr_wrap0(0), + I3 => \axaddr_wrap[11]_i_4_n_0\, + I4 => \axaddr_offset_r_reg[3]_0\(0), + I5 => \^next\, + O => \wrap_boundary_axaddr_r_reg[11]\(0) + ); +\axaddr_wrap[10]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44F444F4FFFF44F4" + ) + port map ( + I0 => \axaddr_wrap[11]_i_4_n_0\, + I1 => axaddr_wrap0(10), + I2 => \axaddr_offset_r_reg[3]_0\(10), + I3 => \^next\, + I4 => \axaddr_wrap_reg[11]\(10), + I5 => \axaddr_wrap[11]_i_2_n_0\, + O => \wrap_boundary_axaddr_r_reg[11]\(10) + ); +\axaddr_wrap[11]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44F444F4FFFF44F4" + ) + port map ( + I0 => \axaddr_wrap[11]_i_2_n_0\, + I1 => \axaddr_wrap_reg[11]\(11), + I2 => \axaddr_offset_r_reg[3]_0\(11), + I3 => \^next\, + I4 => axaddr_wrap0(11), + I5 => \axaddr_wrap[11]_i_4_n_0\, + O => \wrap_boundary_axaddr_r_reg[11]\(11) + ); +\axaddr_wrap[11]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"51FF" + ) + port map ( + I0 => \^m_axi_awready_0\, + I1 => \^q\(1), + I2 => \^q\(0), + I3 => \axaddr_wrap_reg[10]\, + O => \axaddr_wrap[11]_i_2_n_0\ + ); +\axaddr_wrap[11]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBAB" + ) + port map ( + I0 => \axaddr_wrap_reg[10]\, + I1 => \^m_axi_awready_0\, + I2 => \^q\(1), + I3 => \^q\(0), + O => \axaddr_wrap[11]_i_4_n_0\ + ); +\axaddr_wrap[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44F444F4FFFF44F4" + ) + port map ( + I0 => \axaddr_wrap[11]_i_4_n_0\, + I1 => axaddr_wrap0(1), + I2 => \axaddr_wrap_reg[11]\(1), + I3 => \axaddr_wrap[11]_i_2_n_0\, + I4 => \axaddr_offset_r_reg[3]_0\(1), + I5 => \^next\, + O => \wrap_boundary_axaddr_r_reg[11]\(1) + ); +\axaddr_wrap[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44F444F4FFFF44F4" + ) + port map ( + I0 => \axaddr_wrap[11]_i_4_n_0\, + I1 => axaddr_wrap0(2), + I2 => \axaddr_wrap_reg[11]\(2), + I3 => \axaddr_wrap[11]_i_2_n_0\, + I4 => \axaddr_offset_r_reg[3]_0\(2), + I5 => \^next\, + O => \wrap_boundary_axaddr_r_reg[11]\(2) + ); +\axaddr_wrap[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44F444F4FFFF44F4" + ) + port map ( + I0 => \axaddr_wrap[11]_i_2_n_0\, + I1 => \axaddr_wrap_reg[11]\(3), + I2 => axaddr_wrap0(3), + I3 => \axaddr_wrap[11]_i_4_n_0\, + I4 => \axaddr_offset_r_reg[3]_0\(3), + I5 => \^next\, + O => \wrap_boundary_axaddr_r_reg[11]\(3) + ); +\axaddr_wrap[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44F444F4FFFF44F4" + ) + port map ( + I0 => \axaddr_wrap[11]_i_2_n_0\, + I1 => \axaddr_wrap_reg[11]\(4), + I2 => axaddr_wrap0(4), + I3 => \axaddr_wrap[11]_i_4_n_0\, + I4 => \axaddr_offset_r_reg[3]_0\(4), + I5 => \^next\, + O => \wrap_boundary_axaddr_r_reg[11]\(4) + ); +\axaddr_wrap[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44F444F4FFFF44F4" + ) + port map ( + I0 => \axaddr_wrap[11]_i_2_n_0\, + I1 => \axaddr_wrap_reg[11]\(5), + I2 => axaddr_wrap0(5), + I3 => \axaddr_wrap[11]_i_4_n_0\, + I4 => \axaddr_offset_r_reg[3]_0\(5), + I5 => \^next\, + O => \wrap_boundary_axaddr_r_reg[11]\(5) + ); +\axaddr_wrap[6]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44F444F4FFFF44F4" + ) + port map ( + I0 => \axaddr_wrap[11]_i_2_n_0\, + I1 => \axaddr_wrap_reg[11]\(6), + I2 => axaddr_wrap0(6), + I3 => \axaddr_wrap[11]_i_4_n_0\, + I4 => \axaddr_offset_r_reg[3]_0\(6), + I5 => \^next\, + O => \wrap_boundary_axaddr_r_reg[11]\(6) + ); +\axaddr_wrap[7]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44F444F4FFFF44F4" + ) + port map ( + I0 => \axaddr_wrap[11]_i_4_n_0\, + I1 => axaddr_wrap0(7), + I2 => \axaddr_wrap_reg[11]\(7), + I3 => \axaddr_wrap[11]_i_2_n_0\, + I4 => \axaddr_offset_r_reg[3]_0\(7), + I5 => \^next\, + O => \wrap_boundary_axaddr_r_reg[11]\(7) + ); +\axaddr_wrap[8]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44F444F4FFFF44F4" + ) + port map ( + I0 => \axaddr_wrap[11]_i_2_n_0\, + I1 => \axaddr_wrap_reg[11]\(8), + I2 => axaddr_wrap0(8), + I3 => \axaddr_wrap[11]_i_4_n_0\, + I4 => \axaddr_offset_r_reg[3]_0\(8), + I5 => \^next\, + O => \wrap_boundary_axaddr_r_reg[11]\(8) + ); +\axaddr_wrap[9]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44F444F4FFFF44F4" + ) + port map ( + I0 => \axaddr_wrap[11]_i_4_n_0\, + I1 => axaddr_wrap0(9), + I2 => \axaddr_wrap_reg[11]\(9), + I3 => \axaddr_wrap[11]_i_2_n_0\, + I4 => \axaddr_offset_r_reg[3]_0\(9), + I5 => \^next\, + O => \wrap_boundary_axaddr_r_reg[11]\(9) + ); +\axlen_cnt[3]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF64" + ) + port map ( + I0 => \^q\(0), + I1 => \^q\(1), + I2 => si_rs_awvalid, + I3 => \^m_axi_awready_0\, + O => \^fsm_sequential_state_reg[0]_1\ + ); +\axlen_cnt[3]_i_3__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"DF" + ) + port map ( + I0 => \^q\(0), + I1 => \^q\(1), + I2 => si_rs_awvalid, + O => \^fsm_sequential_state_reg[0]_2\ + ); +\axlen_cnt[5]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^fsm_sequential_state_reg[0]_1\, + I1 => s_axburst_eq0_reg, + O => \FSM_sequential_state_reg[0]_0\ + ); +m_axi_awvalid_INST_0: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^q\(1), + I1 => \^q\(0), + O => m_axi_awvalid + ); +\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^m_axi_awready_0\, + I1 => si_rs_awvalid, + O => E(0) + ); +\memory_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0383038300000383" + ) + port map ( + I0 => m_axi_awready, + I1 => \^q\(0), + I2 => \^q\(1), + I3 => \FSM_sequential_state_reg[1]_0\, + I4 => cnt_read(1), + I5 => cnt_read(0), + O => \^m_axi_awready_0\ + ); +next_pending_r_i_3: unisim.vcomponents.LUT3 + generic map( + INIT => X"F4" + ) + port map ( + I0 => \^q\(0), + I1 => \^q\(1), + I2 => \^m_axi_awready_0\, + O => \^next\ + ); +s_axburst_eq0_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"EFEFCFCFEFE0C0C0" + ) + port map ( + I0 => s_axburst_eq0_reg_0, + I1 => s_axburst_eq0_i_2_n_0, + I2 => s_axburst_eq0_i_3_n_0, + I3 => s_axburst_eq0_reg, + I4 => \^next\, + I5 => s_axburst_eq0_i_4_n_0, + O => \axlen_cnt_reg[2]\ + ); +s_axburst_eq0_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAEBEFAAAAAAAA" + ) + port map ( + I0 => s_axburst_eq1_reg, + I1 => \^q\(0), + I2 => \^q\(1), + I3 => si_rs_awvalid, + I4 => \^m_axi_awready_0\, + I5 => next_pending_r_0, + O => s_axburst_eq0_i_2_n_0 + ); +s_axburst_eq0_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000A2A2AAA2" + ) + port map ( + I0 => \axaddr_offset_r_reg[3]_0\(12), + I1 => sel_first_reg_2, + I2 => \^m_axi_awready_0\, + I3 => \^q\(1), + I4 => \^q\(0), + I5 => s_axburst_eq0_i_5_n_0, + O => s_axburst_eq0_i_3_n_0 + ); +s_axburst_eq0_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAEBEFAAAAAAAA" + ) + port map ( + I0 => s_axburst_eq1_reg, + I1 => \^q\(0), + I2 => \^q\(1), + I3 => si_rs_awvalid, + I4 => \^m_axi_awready_0\, + I5 => next_pending_r, + O => s_axburst_eq0_i_4_n_0 + ); +s_axburst_eq0_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"AEAA" + ) + port map ( + I0 => areset_d1, + I1 => si_rs_awvalid, + I2 => \^q\(1), + I3 => \^q\(0), + O => s_axburst_eq0_i_5_n_0 + ); +s_axburst_eq1_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"EFEFCFCFEFE0C0C0" + ) + port map ( + I0 => s_axburst_eq0_reg_0, + I1 => s_axburst_eq0_i_2_n_0, + I2 => s_axburst_eq1_i_2_n_0, + I3 => s_axburst_eq0_reg, + I4 => \^next\, + I5 => s_axburst_eq0_i_4_n_0, + O => \axlen_cnt_reg[2]_0\ + ); +s_axburst_eq1_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFAEAEAAAE" + ) + port map ( + I0 => \axaddr_offset_r_reg[3]_0\(12), + I1 => sel_first_reg_2, + I2 => \^m_axi_awready_0\, + I3 => \^q\(1), + I4 => \^q\(0), + I5 => s_axburst_eq0_i_5_n_0, + O => s_axburst_eq1_i_2_n_0 + ); +sel_first_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF44F44444" + ) + port map ( + I0 => \^next\, + I1 => sel_first, + I2 => \^q\(0), + I3 => \^q\(1), + I4 => si_rs_awvalid, + I5 => areset_d1, + O => sel_first_reg + ); +\sel_first_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF44F44444" + ) + port map ( + I0 => \^next\, + I1 => sel_first_reg_1, + I2 => \^q\(0), + I3 => \^q\(1), + I4 => si_rs_awvalid, + I5 => areset_d1, + O => sel_first_reg_0 + ); +\sel_first_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CCECFCFFCCECCCEC" + ) + port map ( + I0 => si_rs_awvalid, + I1 => areset_d1, + I2 => \^q\(0), + I3 => \^q\(1), + I4 => \^m_axi_awready_0\, + I5 => sel_first_reg_2, + O => sel_first_i + ); +\wrap_boundary_axaddr_r[11]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"20" + ) + port map ( + I0 => si_rs_awvalid, + I1 => \^q\(1), + I2 => \^q\(0), + O => m_valid_i_reg(0) + ); +\wrap_cnt_r[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"33833333CC8CCCCC" + ) + port map ( + I0 => \^axaddr_offset\(0), + I1 => \wrap_cnt_r[2]_i_2_n_0\, + I2 => \^q\(0), + I3 => \^q\(1), + I4 => si_rs_awvalid, + I5 => \wrap_second_len_r_reg[3]_0\(0), + O => D(0) + ); +\wrap_cnt_r[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"3CCCA0A0" + ) + port map ( + I0 => \^axaddr_offset\(1), + I1 => \wrap_second_len_r_reg[3]_0\(1), + I2 => \wrap_cnt_r[2]_i_2_n_0\, + I3 => \wrap_second_len_r_reg[3]_0\(0), + I4 => \^fsm_sequential_state_reg[0]_2\, + O => D(1) + ); +\wrap_cnt_r[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"59A9AAAAAAAAAAAA" + ) + port map ( + I0 => \^wrap_second_len_r_reg[3]\(2), + I1 => \^axaddr_offset\(0), + I2 => \^fsm_sequential_state_reg[0]_2\, + I3 => \wrap_second_len_r_reg[3]_0\(0), + I4 => \wrap_cnt_r[2]_i_2_n_0\, + I5 => \^wrap_second_len_r_reg[3]\(1), + O => D(2) + ); +\wrap_cnt_r[2]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \^axaddr_offset\(1), + I1 => \^axaddr_offset\(2), + I2 => \^axaddr_offset\(0), + I3 => \^axaddr_offset\(3), + O => \wrap_cnt_r[2]_i_2_n_0\ + ); +\wrap_cnt_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"A6AA" + ) + port map ( + I0 => \^wrap_second_len_r_reg[3]\(3), + I1 => \^wrap_second_len_r_reg[3]\(1), + I2 => \wrap_cnt_r[3]_i_2_n_0\, + I3 => \^wrap_second_len_r_reg[3]\(2), + O => D(3) + ); +\wrap_cnt_r[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"772277227722772F" + ) + port map ( + I0 => \^fsm_sequential_state_reg[0]_2\, + I1 => \wrap_second_len_r_reg[3]_0\(0), + I2 => \^axaddr_offset\(3), + I3 => \^axaddr_offset\(0), + I4 => \^axaddr_offset\(2), + I5 => \^axaddr_offset\(1), + O => \wrap_cnt_r[3]_i_2_n_0\ + ); +\wrap_second_len_r[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88BB88BB88BB88B8" + ) + port map ( + I0 => \wrap_second_len_r_reg[3]_0\(0), + I1 => \^fsm_sequential_state_reg[0]_2\, + I2 => \^axaddr_offset\(3), + I3 => \^axaddr_offset\(0), + I4 => \^axaddr_offset\(2), + I5 => \^axaddr_offset\(1), + O => \^wrap_second_len_r_reg[3]\(0) + ); +\wrap_second_len_r[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BB88BB8888BB88B8" + ) + port map ( + I0 => \wrap_second_len_r_reg[3]_0\(1), + I1 => \^fsm_sequential_state_reg[0]_2\, + I2 => \^axaddr_offset\(3), + I3 => \^axaddr_offset\(0), + I4 => \^axaddr_offset\(2), + I5 => \^axaddr_offset\(1), + O => \^wrap_second_len_r_reg[3]\(1) + ); +\wrap_second_len_r[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBB8888BB8888B8" + ) + port map ( + I0 => \wrap_second_len_r_reg[3]_0\(2), + I1 => \^fsm_sequential_state_reg[0]_2\, + I2 => \^axaddr_offset\(3), + I3 => \^axaddr_offset\(0), + I4 => \^axaddr_offset\(2), + I5 => \^axaddr_offset\(1), + O => \^wrap_second_len_r_reg[3]\(2) + ); +\wrap_second_len_r[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFF888888888" + ) + port map ( + I0 => \^fsm_sequential_state_reg[0]_2\, + I1 => \wrap_second_len_r_reg[3]_0\(3), + I2 => \^axaddr_offset\(0), + I3 => \^axaddr_offset\(1), + I4 => \^axaddr_offset\(2), + I5 => \wrap_second_len_r_reg[3]_1\, + O => \^wrap_second_len_r_reg[3]\(3) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_wrap_cmd is + port ( + next_pending_r_0 : out STD_LOGIC; + sel_first : out STD_LOGIC; + \axlen_cnt_reg[2]_0\ : out STD_LOGIC; + axaddr_wrap0 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + \axaddr_wrap_reg[11]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); + \axlen_cnt_reg[0]_0\ : out STD_LOGIC; + \axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \wrap_boundary_axaddr_r_reg[11]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); + aclk : in STD_LOGIC; + sel_first_reg_0 : in STD_LOGIC; + \axlen_cnt_reg[3]_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); + si_rs_awvalid : in STD_LOGIC; + \axaddr_wrap_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \axlen_cnt_reg[3]_1\ : in STD_LOGIC; + \next\ : in STD_LOGIC; + \axaddr_wrap_reg[0]_0\ : in STD_LOGIC; + next_pending_r_reg_0 : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \wrap_cnt_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + \wrap_boundary_axaddr_r_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); + \axaddr_wrap_reg[11]_1\ : in STD_LOGIC_VECTOR ( 11 downto 0 ) + ); +end NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_wrap_cmd; + +architecture STRUCTURE of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_wrap_cmd is + signal \axaddr_wrap[11]_i_6_n_0\ : STD_LOGIC; + signal \^axaddr_wrap_reg[11]_0\ : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \axaddr_wrap_reg[11]_i_3_n_1\ : STD_LOGIC; + signal \axaddr_wrap_reg[11]_i_3_n_2\ : STD_LOGIC; + signal \axaddr_wrap_reg[11]_i_3_n_3\ : STD_LOGIC; + signal \axaddr_wrap_reg[3]_i_2_n_0\ : STD_LOGIC; + signal \axaddr_wrap_reg[3]_i_2_n_1\ : STD_LOGIC; + signal \axaddr_wrap_reg[3]_i_2_n_2\ : STD_LOGIC; + signal \axaddr_wrap_reg[3]_i_2_n_3\ : STD_LOGIC; + signal \axaddr_wrap_reg[7]_i_2_n_0\ : STD_LOGIC; + signal \axaddr_wrap_reg[7]_i_2_n_1\ : STD_LOGIC; + signal \axaddr_wrap_reg[7]_i_2_n_2\ : STD_LOGIC; + signal \axaddr_wrap_reg[7]_i_2_n_3\ : STD_LOGIC; + signal \axlen_cnt[0]_i_1__0_n_0\ : STD_LOGIC; + signal \axlen_cnt[1]_i_1__0_n_0\ : STD_LOGIC; + signal \axlen_cnt[2]_i_1__0_n_0\ : STD_LOGIC; + signal \axlen_cnt[3]_i_1_n_0\ : STD_LOGIC; + signal \axlen_cnt[3]_i_2__2_n_0\ : STD_LOGIC; + signal \axlen_cnt[4]_i_1_n_0\ : STD_LOGIC; + signal \^axlen_cnt_reg[2]_0\ : STD_LOGIC; + signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC; + signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; + signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; + signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; + signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC; + signal \^next_pending_r_0\ : STD_LOGIC; + signal wrap_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal wrap_next_pending : STD_LOGIC; + signal \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute ADDER_THRESHOLD : integer; + attribute ADDER_THRESHOLD of \axaddr_wrap_reg[11]_i_3\ : label is 35; + attribute ADDER_THRESHOLD of \axaddr_wrap_reg[3]_i_2\ : label is 35; + attribute ADDER_THRESHOLD of \axaddr_wrap_reg[7]_i_2\ : label is 35; +begin + \axaddr_wrap_reg[11]_0\(11 downto 0) <= \^axaddr_wrap_reg[11]_0\(11 downto 0); + \axlen_cnt_reg[2]_0\ <= \^axlen_cnt_reg[2]_0\; + next_pending_r_0 <= \^next_pending_r_0\; +\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => D(0), + Q => \axaddr_offset_r_reg[3]_0\(0), + R => '0' + ); +\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => D(1), + Q => \axaddr_offset_r_reg[3]_0\(1), + R => '0' + ); +\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => D(2), + Q => \axaddr_offset_r_reg[3]_0\(2), + R => '0' + ); +\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => D(3), + Q => \axaddr_offset_r_reg[3]_0\(3), + R => '0' + ); +\axaddr_wrap[11]_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0009" + ) + port map ( + I0 => \axlen_cnt_reg_n_0_[0]\, + I1 => wrap_cnt_r(0), + I2 => \axlen_cnt_reg_n_0_[4]\, + I3 => \axaddr_wrap[11]_i_6_n_0\, + O => \axlen_cnt_reg[0]_0\ + ); +\axaddr_wrap[11]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"6FF6FFFFFFFF6FF6" + ) + port map ( + I0 => wrap_cnt_r(1), + I1 => \axlen_cnt_reg_n_0_[1]\, + I2 => \axlen_cnt_reg_n_0_[2]\, + I3 => wrap_cnt_r(2), + I4 => \axlen_cnt_reg_n_0_[3]\, + I5 => wrap_cnt_r(3), + O => \axaddr_wrap[11]_i_6_n_0\ + ); +\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axaddr_wrap_reg[11]_1\(0), + Q => \^axaddr_wrap_reg[11]_0\(0), + R => '0' + ); +\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axaddr_wrap_reg[11]_1\(10), + Q => \^axaddr_wrap_reg[11]_0\(10), + R => '0' + ); +\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axaddr_wrap_reg[11]_1\(11), + Q => \^axaddr_wrap_reg[11]_0\(11), + R => '0' + ); +\axaddr_wrap_reg[11]_i_3\: unisim.vcomponents.CARRY4 + port map ( + CI => \axaddr_wrap_reg[7]_i_2_n_0\, + CO(3) => \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\(3), + CO(2) => \axaddr_wrap_reg[11]_i_3_n_1\, + CO(1) => \axaddr_wrap_reg[11]_i_3_n_2\, + CO(0) => \axaddr_wrap_reg[11]_i_3_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => axaddr_wrap0(11 downto 8), + S(3 downto 0) => \^axaddr_wrap_reg[11]_0\(11 downto 8) + ); +\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axaddr_wrap_reg[11]_1\(1), + Q => \^axaddr_wrap_reg[11]_0\(1), + R => '0' + ); +\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axaddr_wrap_reg[11]_1\(2), + Q => \^axaddr_wrap_reg[11]_0\(2), + R => '0' + ); +\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axaddr_wrap_reg[11]_1\(3), + Q => \^axaddr_wrap_reg[11]_0\(3), + R => '0' + ); +\axaddr_wrap_reg[3]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \axaddr_wrap_reg[3]_i_2_n_0\, + CO(2) => \axaddr_wrap_reg[3]_i_2_n_1\, + CO(1) => \axaddr_wrap_reg[3]_i_2_n_2\, + CO(0) => \axaddr_wrap_reg[3]_i_2_n_3\, + CYINIT => '0', + DI(3 downto 0) => \^axaddr_wrap_reg[11]_0\(3 downto 0), + O(3 downto 0) => axaddr_wrap0(3 downto 0), + S(3 downto 0) => \axaddr_wrap_reg[3]_0\(3 downto 0) + ); +\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axaddr_wrap_reg[11]_1\(4), + Q => \^axaddr_wrap_reg[11]_0\(4), + R => '0' + ); +\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axaddr_wrap_reg[11]_1\(5), + Q => \^axaddr_wrap_reg[11]_0\(5), + R => '0' + ); +\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axaddr_wrap_reg[11]_1\(6), + Q => \^axaddr_wrap_reg[11]_0\(6), + R => '0' + ); +\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axaddr_wrap_reg[11]_1\(7), + Q => \^axaddr_wrap_reg[11]_0\(7), + R => '0' + ); +\axaddr_wrap_reg[7]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => \axaddr_wrap_reg[3]_i_2_n_0\, + CO(3) => \axaddr_wrap_reg[7]_i_2_n_0\, + CO(2) => \axaddr_wrap_reg[7]_i_2_n_1\, + CO(1) => \axaddr_wrap_reg[7]_i_2_n_2\, + CO(0) => \axaddr_wrap_reg[7]_i_2_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => axaddr_wrap0(7 downto 4), + S(3 downto 0) => \^axaddr_wrap_reg[11]_0\(7 downto 4) + ); +\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axaddr_wrap_reg[11]_1\(8), + Q => \^axaddr_wrap_reg[11]_0\(8), + R => '0' + ); +\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axaddr_wrap_reg[11]_1\(9), + Q => \^axaddr_wrap_reg[11]_0\(9), + R => '0' + ); +\axlen_cnt[0]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4444F44444444444" + ) + port map ( + I0 => \axlen_cnt_reg_n_0_[0]\, + I1 => \^axlen_cnt_reg[2]_0\, + I2 => \axlen_cnt_reg[3]_0\(5), + I3 => Q(0), + I4 => Q(1), + I5 => si_rs_awvalid, + O => \axlen_cnt[0]_i_1__0_n_0\ + ); +\axlen_cnt[1]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F44F4444" + ) + port map ( + I0 => \axlen_cnt_reg[3]_1\, + I1 => \axlen_cnt_reg[3]_0\(6), + I2 => \axlen_cnt_reg_n_0_[1]\, + I3 => \axlen_cnt_reg_n_0_[0]\, + I4 => \^axlen_cnt_reg[2]_0\, + O => \axlen_cnt[1]_i_1__0_n_0\ + ); +\axlen_cnt[2]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F4F4F44F44444444" + ) + port map ( + I0 => \axlen_cnt_reg[3]_1\, + I1 => \axlen_cnt_reg[3]_0\(7), + I2 => \axlen_cnt_reg_n_0_[2]\, + I3 => \axlen_cnt_reg_n_0_[0]\, + I4 => \axlen_cnt_reg_n_0_[1]\, + I5 => \^axlen_cnt_reg[2]_0\, + O => \axlen_cnt[2]_i_1__0_n_0\ + ); +\axlen_cnt[2]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAAAAAA8" + ) + port map ( + I0 => \axlen_cnt_reg[3]_1\, + I1 => \axlen_cnt_reg_n_0_[2]\, + I2 => \axlen_cnt_reg_n_0_[3]\, + I3 => \axlen_cnt_reg_n_0_[1]\, + I4 => \axlen_cnt_reg_n_0_[4]\, + O => \^axlen_cnt_reg[2]_0\ + ); +\axlen_cnt[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"38FF3800" + ) + port map ( + I0 => \axlen_cnt_reg_n_0_[4]\, + I1 => \axlen_cnt[3]_i_2__2_n_0\, + I2 => \axlen_cnt_reg_n_0_[3]\, + I3 => \axlen_cnt_reg[3]_1\, + I4 => \axlen_cnt_reg[3]_0\(8), + O => \axlen_cnt[3]_i_1_n_0\ + ); +\axlen_cnt[3]_i_2__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"01" + ) + port map ( + I0 => \axlen_cnt_reg_n_0_[0]\, + I1 => \axlen_cnt_reg_n_0_[1]\, + I2 => \axlen_cnt_reg_n_0_[2]\, + O => \axlen_cnt[3]_i_2__2_n_0\ + ); +\axlen_cnt[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAA800000000" + ) + port map ( + I0 => \axlen_cnt_reg[3]_1\, + I1 => \axlen_cnt_reg_n_0_[2]\, + I2 => \axlen_cnt_reg_n_0_[1]\, + I3 => \axlen_cnt_reg_n_0_[0]\, + I4 => \axlen_cnt_reg_n_0_[3]\, + I5 => \axlen_cnt_reg_n_0_[4]\, + O => \axlen_cnt[4]_i_1_n_0\ + ); +\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axlen_cnt[0]_i_1__0_n_0\, + Q => \axlen_cnt_reg_n_0_[0]\, + R => '0' + ); +\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axlen_cnt[1]_i_1__0_n_0\, + Q => \axlen_cnt_reg_n_0_[1]\, + R => '0' + ); +\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axlen_cnt[2]_i_1__0_n_0\, + Q => \axlen_cnt_reg_n_0_[2]\, + R => '0' + ); +\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axlen_cnt[3]_i_1_n_0\, + Q => \axlen_cnt_reg_n_0_[3]\, + R => '0' + ); +\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axlen_cnt[4]_i_1_n_0\, + Q => \axlen_cnt_reg_n_0_[4]\, + R => '0' + ); +\next_pending_r_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF88F8" + ) + port map ( + I0 => \^axlen_cnt_reg[2]_0\, + I1 => \next\, + I2 => \^next_pending_r_0\, + I3 => \axaddr_wrap_reg[0]_0\, + I4 => next_pending_r_reg_0, + O => wrap_next_pending + ); +next_pending_r_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => wrap_next_pending, + Q => \^next_pending_r_0\, + R => '0' + ); +sel_first_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => sel_first_reg_0, + Q => sel_first, + R => '0' + ); +\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => \wrap_boundary_axaddr_r_reg[6]_0\(0), + Q => \wrap_boundary_axaddr_r_reg[11]_0\(0), + R => '0' + ); +\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => \axlen_cnt_reg[3]_0\(3), + Q => \wrap_boundary_axaddr_r_reg[11]_0\(10), + R => '0' + ); +\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => \axlen_cnt_reg[3]_0\(4), + Q => \wrap_boundary_axaddr_r_reg[11]_0\(11), + R => '0' + ); +\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => \wrap_boundary_axaddr_r_reg[6]_0\(1), + Q => \wrap_boundary_axaddr_r_reg[11]_0\(1), + R => '0' + ); +\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => \wrap_boundary_axaddr_r_reg[6]_0\(2), + Q => \wrap_boundary_axaddr_r_reg[11]_0\(2), + R => '0' + ); +\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => \wrap_boundary_axaddr_r_reg[6]_0\(3), + Q => \wrap_boundary_axaddr_r_reg[11]_0\(3), + R => '0' + ); +\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => \wrap_boundary_axaddr_r_reg[6]_0\(4), + Q => \wrap_boundary_axaddr_r_reg[11]_0\(4), + R => '0' + ); +\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => \wrap_boundary_axaddr_r_reg[6]_0\(5), + Q => \wrap_boundary_axaddr_r_reg[11]_0\(5), + R => '0' + ); +\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => \wrap_boundary_axaddr_r_reg[6]_0\(6), + Q => \wrap_boundary_axaddr_r_reg[11]_0\(6), + R => '0' + ); +\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => \axlen_cnt_reg[3]_0\(0), + Q => \wrap_boundary_axaddr_r_reg[11]_0\(7), + R => '0' + ); +\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => \axlen_cnt_reg[3]_0\(1), + Q => \wrap_boundary_axaddr_r_reg[11]_0\(8), + R => '0' + ); +\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => \axlen_cnt_reg[3]_0\(2), + Q => \wrap_boundary_axaddr_r_reg[11]_0\(9), + R => '0' + ); +\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \wrap_cnt_r_reg[3]_0\(0), + Q => wrap_cnt_r(0), + R => '0' + ); +\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \wrap_cnt_r_reg[3]_0\(1), + Q => wrap_cnt_r(1), + R => '0' + ); +\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \wrap_cnt_r_reg[3]_0\(2), + Q => wrap_cnt_r(2), + R => '0' + ); +\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \wrap_cnt_r_reg[3]_0\(3), + Q => wrap_cnt_r(3), + R => '0' + ); +\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \wrap_second_len_r_reg[3]_1\(0), + Q => \wrap_second_len_r_reg[3]_0\(0), + R => '0' + ); +\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \wrap_second_len_r_reg[3]_1\(1), + Q => \wrap_second_len_r_reg[3]_0\(1), + R => '0' + ); +\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \wrap_second_len_r_reg[3]_1\(2), + Q => \wrap_second_len_r_reg[3]_0\(2), + R => '0' + ); +\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \wrap_second_len_r_reg[3]_1\(3), + Q => \wrap_second_len_r_reg[3]_0\(3), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_wrap_cmd_3 is + port ( + sel_first_reg_0 : out STD_LOGIC; + \axaddr_wrap_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \axaddr_wrap_reg[11]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); + \axaddr_wrap_reg[7]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + O : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \m_payload_i_reg[39]\ : out STD_LOGIC; + \m_payload_i_reg[39]_0\ : out STD_LOGIC; + \axlen_cnt_reg[0]_0\ : out STD_LOGIC; + \axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \wrap_boundary_axaddr_r_reg[11]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); + aclk : in STD_LOGIC; + sel_first_reg_1 : in STD_LOGIC; + \axlen_cnt_reg[2]_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + si_rs_arvalid : in STD_LOGIC; + S : in STD_LOGIC_VECTOR ( 3 downto 0 ); + sel_first_i : in STD_LOGIC; + incr_next_pending : in STD_LOGIC; + \axlen_cnt_reg[1]_0\ : in STD_LOGIC; + \axlen_cnt_reg[3]_0\ : in STD_LOGIC; + \axaddr_wrap_reg[0]_0\ : in STD_LOGIC; + next_pending_r_reg_0 : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \wrap_cnt_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + \wrap_boundary_axaddr_r_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); + \axaddr_wrap_reg[11]_1\ : in STD_LOGIC_VECTOR ( 11 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_wrap_cmd_3 : entity is "axi_protocol_converter_v2_1_29_b2s_wrap_cmd"; +end NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_wrap_cmd_3; + +architecture STRUCTURE of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_wrap_cmd_3 is + signal \axaddr_wrap[11]_i_6__0_n_0\ : STD_LOGIC; + signal \^axaddr_wrap_reg[11]_0\ : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \axaddr_wrap_reg[11]_i_3__0_n_1\ : STD_LOGIC; + signal \axaddr_wrap_reg[11]_i_3__0_n_2\ : STD_LOGIC; + signal \axaddr_wrap_reg[11]_i_3__0_n_3\ : STD_LOGIC; + signal \axaddr_wrap_reg[3]_i_2__0_n_0\ : STD_LOGIC; + signal \axaddr_wrap_reg[3]_i_2__0_n_1\ : STD_LOGIC; + signal \axaddr_wrap_reg[3]_i_2__0_n_2\ : STD_LOGIC; + signal \axaddr_wrap_reg[3]_i_2__0_n_3\ : STD_LOGIC; + signal \axaddr_wrap_reg[7]_i_2__0_n_0\ : STD_LOGIC; + signal \axaddr_wrap_reg[7]_i_2__0_n_1\ : STD_LOGIC; + signal \axaddr_wrap_reg[7]_i_2__0_n_2\ : STD_LOGIC; + signal \axaddr_wrap_reg[7]_i_2__0_n_3\ : STD_LOGIC; + signal \axlen_cnt[0]_i_1__2_n_0\ : STD_LOGIC; + signal \axlen_cnt[1]_i_1__2_n_0\ : STD_LOGIC; + signal \axlen_cnt[2]_i_1__2_n_0\ : STD_LOGIC; + signal \axlen_cnt[3]_i_1__1_n_0\ : STD_LOGIC; + signal \axlen_cnt[3]_i_2__1_n_0\ : STD_LOGIC; + signal \axlen_cnt[4]_i_1__0_n_0\ : STD_LOGIC; + signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC; + signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; + signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; + signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; + signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC; + signal next_pending_r : STD_LOGIC; + signal \wrap_cnt_r_reg_n_0_[0]\ : STD_LOGIC; + signal \wrap_cnt_r_reg_n_0_[1]\ : STD_LOGIC; + signal \wrap_cnt_r_reg_n_0_[2]\ : STD_LOGIC; + signal \wrap_cnt_r_reg_n_0_[3]\ : STD_LOGIC; + signal wrap_next_pending : STD_LOGIC; + signal \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute ADDER_THRESHOLD : integer; + attribute ADDER_THRESHOLD of \axaddr_wrap_reg[11]_i_3__0\ : label is 35; + attribute ADDER_THRESHOLD of \axaddr_wrap_reg[3]_i_2__0\ : label is 35; + attribute ADDER_THRESHOLD of \axaddr_wrap_reg[7]_i_2__0\ : label is 35; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \s_axburst_eq0_i_1__0\ : label is "soft_lutpair14"; + attribute SOFT_HLUTNM of \s_axburst_eq1_i_1__0\ : label is "soft_lutpair14"; +begin + \axaddr_wrap_reg[11]_0\(11 downto 0) <= \^axaddr_wrap_reg[11]_0\(11 downto 0); +\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => D(0), + Q => \axaddr_offset_r_reg[3]_0\(0), + R => '0' + ); +\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => D(1), + Q => \axaddr_offset_r_reg[3]_0\(1), + R => '0' + ); +\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => D(2), + Q => \axaddr_offset_r_reg[3]_0\(2), + R => '0' + ); +\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => D(3), + Q => \axaddr_offset_r_reg[3]_0\(3), + R => '0' + ); +\axaddr_wrap[11]_i_5__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0009" + ) + port map ( + I0 => \axlen_cnt_reg_n_0_[0]\, + I1 => \wrap_cnt_r_reg_n_0_[0]\, + I2 => \axlen_cnt_reg_n_0_[4]\, + I3 => \axaddr_wrap[11]_i_6__0_n_0\, + O => \axlen_cnt_reg[0]_0\ + ); +\axaddr_wrap[11]_i_6__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"6FF6FFFFFFFF6FF6" + ) + port map ( + I0 => \wrap_cnt_r_reg_n_0_[1]\, + I1 => \axlen_cnt_reg_n_0_[1]\, + I2 => \axlen_cnt_reg_n_0_[3]\, + I3 => \wrap_cnt_r_reg_n_0_[3]\, + I4 => \axlen_cnt_reg_n_0_[2]\, + I5 => \wrap_cnt_r_reg_n_0_[2]\, + O => \axaddr_wrap[11]_i_6__0_n_0\ + ); +\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axaddr_wrap_reg[11]_1\(0), + Q => \^axaddr_wrap_reg[11]_0\(0), + R => '0' + ); +\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axaddr_wrap_reg[11]_1\(10), + Q => \^axaddr_wrap_reg[11]_0\(10), + R => '0' + ); +\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axaddr_wrap_reg[11]_1\(11), + Q => \^axaddr_wrap_reg[11]_0\(11), + R => '0' + ); +\axaddr_wrap_reg[11]_i_3__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \axaddr_wrap_reg[7]_i_2__0_n_0\, + CO(3) => \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\(3), + CO(2) => \axaddr_wrap_reg[11]_i_3__0_n_1\, + CO(1) => \axaddr_wrap_reg[11]_i_3__0_n_2\, + CO(0) => \axaddr_wrap_reg[11]_i_3__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => O(3 downto 0), + S(3 downto 0) => \^axaddr_wrap_reg[11]_0\(11 downto 8) + ); +\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axaddr_wrap_reg[11]_1\(1), + Q => \^axaddr_wrap_reg[11]_0\(1), + R => '0' + ); +\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axaddr_wrap_reg[11]_1\(2), + Q => \^axaddr_wrap_reg[11]_0\(2), + R => '0' + ); +\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axaddr_wrap_reg[11]_1\(3), + Q => \^axaddr_wrap_reg[11]_0\(3), + R => '0' + ); +\axaddr_wrap_reg[3]_i_2__0\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \axaddr_wrap_reg[3]_i_2__0_n_0\, + CO(2) => \axaddr_wrap_reg[3]_i_2__0_n_1\, + CO(1) => \axaddr_wrap_reg[3]_i_2__0_n_2\, + CO(0) => \axaddr_wrap_reg[3]_i_2__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => \^axaddr_wrap_reg[11]_0\(3 downto 0), + O(3 downto 0) => \axaddr_wrap_reg[3]_0\(3 downto 0), + S(3 downto 0) => S(3 downto 0) + ); +\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axaddr_wrap_reg[11]_1\(4), + Q => \^axaddr_wrap_reg[11]_0\(4), + R => '0' + ); +\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axaddr_wrap_reg[11]_1\(5), + Q => \^axaddr_wrap_reg[11]_0\(5), + R => '0' + ); +\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axaddr_wrap_reg[11]_1\(6), + Q => \^axaddr_wrap_reg[11]_0\(6), + R => '0' + ); +\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axaddr_wrap_reg[11]_1\(7), + Q => \^axaddr_wrap_reg[11]_0\(7), + R => '0' + ); +\axaddr_wrap_reg[7]_i_2__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \axaddr_wrap_reg[3]_i_2__0_n_0\, + CO(3) => \axaddr_wrap_reg[7]_i_2__0_n_0\, + CO(2) => \axaddr_wrap_reg[7]_i_2__0_n_1\, + CO(1) => \axaddr_wrap_reg[7]_i_2__0_n_2\, + CO(0) => \axaddr_wrap_reg[7]_i_2__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => \axaddr_wrap_reg[7]_0\(3 downto 0), + S(3 downto 0) => \^axaddr_wrap_reg[11]_0\(7 downto 4) + ); +\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axaddr_wrap_reg[11]_1\(8), + Q => \^axaddr_wrap_reg[11]_0\(8), + R => '0' + ); +\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axaddr_wrap_reg[11]_1\(9), + Q => \^axaddr_wrap_reg[11]_0\(9), + R => '0' + ); +\axlen_cnt[0]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"44F44444" + ) + port map ( + I0 => \axlen_cnt_reg_n_0_[0]\, + I1 => \axlen_cnt[3]_i_2__1_n_0\, + I2 => \axlen_cnt_reg[2]_0\(6), + I3 => Q(0), + I4 => si_rs_arvalid, + O => \axlen_cnt[0]_i_1__2_n_0\ + ); +\axlen_cnt[1]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F44F4444" + ) + port map ( + I0 => \axlen_cnt_reg[1]_0\, + I1 => \axlen_cnt_reg[2]_0\(7), + I2 => \axlen_cnt_reg_n_0_[1]\, + I3 => \axlen_cnt_reg_n_0_[0]\, + I4 => \axlen_cnt[3]_i_2__1_n_0\, + O => \axlen_cnt[1]_i_1__2_n_0\ + ); +\axlen_cnt[2]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F4F4F44F44444444" + ) + port map ( + I0 => \axlen_cnt_reg[1]_0\, + I1 => \axlen_cnt_reg[2]_0\(8), + I2 => \axlen_cnt_reg_n_0_[2]\, + I3 => \axlen_cnt_reg_n_0_[0]\, + I4 => \axlen_cnt_reg_n_0_[1]\, + I5 => \axlen_cnt[3]_i_2__1_n_0\, + O => \axlen_cnt[2]_i_1__2_n_0\ + ); +\axlen_cnt[3]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EAEAEAEAEAEAEAAE" + ) + port map ( + I0 => \axlen_cnt_reg[3]_0\, + I1 => \axlen_cnt[3]_i_2__1_n_0\, + I2 => \axlen_cnt_reg_n_0_[3]\, + I3 => \axlen_cnt_reg_n_0_[0]\, + I4 => \axlen_cnt_reg_n_0_[1]\, + I5 => \axlen_cnt_reg_n_0_[2]\, + O => \axlen_cnt[3]_i_1__1_n_0\ + ); +\axlen_cnt[3]_i_2__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAAAAAA8" + ) + port map ( + I0 => \axlen_cnt_reg[1]_0\, + I1 => \axlen_cnt_reg_n_0_[2]\, + I2 => \axlen_cnt_reg_n_0_[3]\, + I3 => \axlen_cnt_reg_n_0_[1]\, + I4 => \axlen_cnt_reg_n_0_[4]\, + O => \axlen_cnt[3]_i_2__1_n_0\ + ); +\axlen_cnt[4]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAA800000000" + ) + port map ( + I0 => \axlen_cnt_reg[1]_0\, + I1 => \axlen_cnt_reg_n_0_[2]\, + I2 => \axlen_cnt_reg_n_0_[1]\, + I3 => \axlen_cnt_reg_n_0_[0]\, + I4 => \axlen_cnt_reg_n_0_[3]\, + I5 => \axlen_cnt_reg_n_0_[4]\, + O => \axlen_cnt[4]_i_1__0_n_0\ + ); +\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axlen_cnt[0]_i_1__2_n_0\, + Q => \axlen_cnt_reg_n_0_[0]\, + R => '0' + ); +\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axlen_cnt[1]_i_1__2_n_0\, + Q => \axlen_cnt_reg_n_0_[1]\, + R => '0' + ); +\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axlen_cnt[2]_i_1__2_n_0\, + Q => \axlen_cnt_reg_n_0_[2]\, + R => '0' + ); +\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axlen_cnt[3]_i_1__1_n_0\, + Q => \axlen_cnt_reg_n_0_[3]\, + R => '0' + ); +\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \axaddr_wrap_reg[0]_0\, + D => \axlen_cnt[4]_i_1__0_n_0\, + Q => \axlen_cnt_reg_n_0_[4]\, + R => '0' + ); +\next_pending_r_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFAC" + ) + port map ( + I0 => \axlen_cnt[3]_i_2__1_n_0\, + I1 => next_pending_r, + I2 => \axaddr_wrap_reg[0]_0\, + I3 => next_pending_r_reg_0, + O => wrap_next_pending + ); +next_pending_r_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => wrap_next_pending, + Q => next_pending_r, + R => '0' + ); +\s_axburst_eq0_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => wrap_next_pending, + I1 => \axlen_cnt_reg[2]_0\(5), + I2 => sel_first_i, + I3 => incr_next_pending, + O => \m_payload_i_reg[39]\ + ); +\s_axburst_eq1_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"ABA8" + ) + port map ( + I0 => wrap_next_pending, + I1 => \axlen_cnt_reg[2]_0\(5), + I2 => sel_first_i, + I3 => incr_next_pending, + O => \m_payload_i_reg[39]_0\ + ); +sel_first_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => sel_first_reg_1, + Q => sel_first_reg_0, + R => '0' + ); +\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => \wrap_boundary_axaddr_r_reg[6]_0\(0), + Q => \wrap_boundary_axaddr_r_reg[11]_0\(0), + R => '0' + ); +\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => \axlen_cnt_reg[2]_0\(3), + Q => \wrap_boundary_axaddr_r_reg[11]_0\(10), + R => '0' + ); +\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => \axlen_cnt_reg[2]_0\(4), + Q => \wrap_boundary_axaddr_r_reg[11]_0\(11), + R => '0' + ); +\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => \wrap_boundary_axaddr_r_reg[6]_0\(1), + Q => \wrap_boundary_axaddr_r_reg[11]_0\(1), + R => '0' + ); +\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => \wrap_boundary_axaddr_r_reg[6]_0\(2), + Q => \wrap_boundary_axaddr_r_reg[11]_0\(2), + R => '0' + ); +\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => \wrap_boundary_axaddr_r_reg[6]_0\(3), + Q => \wrap_boundary_axaddr_r_reg[11]_0\(3), + R => '0' + ); +\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => \wrap_boundary_axaddr_r_reg[6]_0\(4), + Q => \wrap_boundary_axaddr_r_reg[11]_0\(4), + R => '0' + ); +\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => \wrap_boundary_axaddr_r_reg[6]_0\(5), + Q => \wrap_boundary_axaddr_r_reg[11]_0\(5), + R => '0' + ); +\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => \wrap_boundary_axaddr_r_reg[6]_0\(6), + Q => \wrap_boundary_axaddr_r_reg[11]_0\(6), + R => '0' + ); +\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => \axlen_cnt_reg[2]_0\(0), + Q => \wrap_boundary_axaddr_r_reg[11]_0\(7), + R => '0' + ); +\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => \axlen_cnt_reg[2]_0\(1), + Q => \wrap_boundary_axaddr_r_reg[11]_0\(8), + R => '0' + ); +\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => \axlen_cnt_reg[2]_0\(2), + Q => \wrap_boundary_axaddr_r_reg[11]_0\(9), + R => '0' + ); +\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \wrap_cnt_r_reg[3]_0\(0), + Q => \wrap_cnt_r_reg_n_0_[0]\, + R => '0' + ); +\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \wrap_cnt_r_reg[3]_0\(1), + Q => \wrap_cnt_r_reg_n_0_[1]\, + R => '0' + ); +\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \wrap_cnt_r_reg[3]_0\(2), + Q => \wrap_cnt_r_reg_n_0_[2]\, + R => '0' + ); +\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \wrap_cnt_r_reg[3]_0\(3), + Q => \wrap_cnt_r_reg_n_0_[3]\, + R => '0' + ); +\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \wrap_second_len_r_reg[3]_1\(0), + Q => \wrap_second_len_r_reg[3]_0\(0), + R => '0' + ); +\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \wrap_second_len_r_reg[3]_1\(1), + Q => \wrap_second_len_r_reg[3]_0\(1), + R => '0' + ); +\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \wrap_second_len_r_reg[3]_1\(2), + Q => \wrap_second_len_r_reg[3]_0\(2), + R => '0' + ); +\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \wrap_second_len_r_reg[3]_1\(3), + Q => \wrap_second_len_r_reg[3]_0\(3), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axic_register_slice is + port ( + s_ready_i_reg_0 : out STD_LOGIC; + si_rs_arvalid : out STD_LOGIC; + \aresetn_d_reg[1]_inv_0\ : out STD_LOGIC; + \axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + Q : out STD_LOGIC_VECTOR ( 53 downto 0 ); + \axaddr_wrap_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \m_payload_i_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \m_payload_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + O : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \FSM_sequential_state_reg[1]\ : out STD_LOGIC; + \m_payload_i_reg[6]_0\ : out STD_LOGIC; + \m_payload_i_reg[47]_0\ : out STD_LOGIC; + \m_payload_i_reg[45]_0\ : out STD_LOGIC; + \m_payload_i_reg[6]_1\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); + \m_payload_i_reg[2]_0\ : out STD_LOGIC; + \m_payload_i_reg[1]_0\ : out STD_LOGIC; + \m_payload_i_reg[1]_1\ : out STD_LOGIC; + \m_payload_i_reg[2]_1\ : out STD_LOGIC; + \m_payload_i_reg[4]_0\ : out STD_LOGIC; + m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); + s_ready_i_reg_1 : in STD_LOGIC; + s_ready_i0 : in STD_LOGIC; + aclk : in STD_LOGIC; + m_valid_i0 : in STD_LOGIC; + \aresetn_d_reg[1]_inv_1\ : in STD_LOGIC; + \m_axi_araddr[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \m_axi_araddr[11]_0\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \axlen_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + next_pending_r_reg : in STD_LOGIC; + s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \m_axi_araddr[11]_1\ : in STD_LOGIC; + sel_first_1 : in STD_LOGIC; + \m_payload_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); +end NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axic_register_slice; + +architecture STRUCTURE of NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axic_register_slice is + signal \^q\ : STD_LOGIC_VECTOR ( 53 downto 0 ); + signal \^aresetn_d_reg[1]_inv_0\ : STD_LOGIC; + signal \axaddr_incr[3]_i_4__0_n_0\ : STD_LOGIC; + signal \axaddr_incr[3]_i_5__0_n_0\ : STD_LOGIC; + signal \axaddr_incr[3]_i_6__0_n_0\ : STD_LOGIC; + signal \axaddr_incr_reg[11]_i_3__0_n_1\ : STD_LOGIC; + signal \axaddr_incr_reg[11]_i_3__0_n_2\ : STD_LOGIC; + signal \axaddr_incr_reg[11]_i_3__0_n_3\ : STD_LOGIC; + signal \axaddr_incr_reg[3]_i_2__0_n_0\ : STD_LOGIC; + signal \axaddr_incr_reg[3]_i_2__0_n_1\ : STD_LOGIC; + signal \axaddr_incr_reg[3]_i_2__0_n_2\ : STD_LOGIC; + signal \axaddr_incr_reg[3]_i_2__0_n_3\ : STD_LOGIC; + signal \axaddr_incr_reg[7]_i_2__0_n_0\ : STD_LOGIC; + signal \axaddr_incr_reg[7]_i_2__0_n_1\ : STD_LOGIC; + signal \axaddr_incr_reg[7]_i_2__0_n_2\ : STD_LOGIC; + signal \axaddr_incr_reg[7]_i_2__0_n_3\ : STD_LOGIC; + signal \m_axi_araddr[11]_INST_0_i_1_n_0\ : STD_LOGIC; + signal \m_payload_i[0]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[10]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[11]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[12]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[14]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[15]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[16]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[17]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[18]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[19]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[1]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[20]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[21]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[22]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[23]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[24]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[25]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[26]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[27]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[28]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[29]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[30]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[31]_i_2__0_n_0\ : STD_LOGIC; + signal \m_payload_i[32]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[33]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[34]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[35]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[36]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[38]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[39]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[3]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[44]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[45]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[46]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[47]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[4]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[50]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[51]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[52]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[53]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[54]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[55]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[56]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[57]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[58]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[59]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[5]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[60]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[61]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[6]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[7]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[8]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[9]_i_1__0_n_0\ : STD_LOGIC; + signal \^m_payload_i_reg[6]_0\ : STD_LOGIC; + signal \m_payload_i_reg_n_0_[38]\ : STD_LOGIC; + signal \^s_ready_i_reg_0\ : STD_LOGIC; + signal \^si_rs_arvalid\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; + signal \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ : STD_LOGIC; + signal \NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute inverted : string; + attribute inverted of \aresetn_d_reg[1]_inv\ : label is "yes"; + attribute ADDER_THRESHOLD : integer; + attribute ADDER_THRESHOLD of \axaddr_incr_reg[11]_i_3__0\ : label is 35; + attribute ADDER_THRESHOLD of \axaddr_incr_reg[3]_i_2__0\ : label is 35; + attribute ADDER_THRESHOLD of \axaddr_incr_reg[7]_i_2__0\ : label is 35; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \axlen_cnt[3]_i_3\ : label is "soft_lutpair21"; + attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair44"; + attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair43"; + attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair43"; + attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__1\ : label is "soft_lutpair42"; + attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair42"; + attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair41"; + attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair41"; + attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair40"; + attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair40"; + attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair39"; + attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair48"; + attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair39"; + attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair38"; + attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair38"; + attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair37"; + attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair37"; + attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair36"; + attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair36"; + attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair35"; + attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair35"; + attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair34"; + attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair48"; + attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair34"; + attribute SOFT_HLUTNM of \m_payload_i[31]_i_2__0\ : label is "soft_lutpair33"; + attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair33"; + attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair32"; + attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair32"; + attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair31"; + attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair31"; + attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair30"; + attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair30"; + attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair47"; + attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair29"; + attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair29"; + attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair28"; + attribute SOFT_HLUTNM of \m_payload_i[47]_i_1__0\ : label is "soft_lutpair28"; + attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair47"; + attribute SOFT_HLUTNM of \m_payload_i[50]_i_1__0\ : label is "soft_lutpair27"; + attribute SOFT_HLUTNM of \m_payload_i[51]_i_1__0\ : label is "soft_lutpair27"; + attribute SOFT_HLUTNM of \m_payload_i[52]_i_1__0\ : label is "soft_lutpair26"; + attribute SOFT_HLUTNM of \m_payload_i[53]_i_1__0\ : label is "soft_lutpair26"; + attribute SOFT_HLUTNM of \m_payload_i[54]_i_1__0\ : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of \m_payload_i[55]_i_1__0\ : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of \m_payload_i[56]_i_1__0\ : label is "soft_lutpair24"; + attribute SOFT_HLUTNM of \m_payload_i[57]_i_1__0\ : label is "soft_lutpair24"; + attribute SOFT_HLUTNM of \m_payload_i[58]_i_1__0\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \m_payload_i[59]_i_1__0\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair46"; + attribute SOFT_HLUTNM of \m_payload_i[60]_i_1__0\ : label is "soft_lutpair22"; + attribute SOFT_HLUTNM of \m_payload_i[61]_i_1__0\ : label is "soft_lutpair22"; + attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair46"; + attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair45"; + attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair45"; + attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair44"; + attribute SOFT_HLUTNM of \wrap_second_len_r[3]_i_2__0\ : label is "soft_lutpair21"; +begin + Q(53 downto 0) <= \^q\(53 downto 0); + \aresetn_d_reg[1]_inv_0\ <= \^aresetn_d_reg[1]_inv_0\; + \m_payload_i_reg[6]_0\ <= \^m_payload_i_reg[6]_0\; + s_ready_i_reg_0 <= \^s_ready_i_reg_0\; + si_rs_arvalid <= \^si_rs_arvalid\; +\aresetn_d_reg[1]_inv\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => aclk, + CE => '1', + D => \aresetn_d_reg[1]_inv_1\, + Q => \^aresetn_d_reg[1]_inv_0\, + R => '0' + ); +\axaddr_incr[3]_i_11__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => \m_axi_araddr[11]\(3), + I1 => \^q\(35), + I2 => \^q\(36), + O => \axaddr_incr_reg[3]\(3) + ); +\axaddr_incr[3]_i_12__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A6" + ) + port map ( + I0 => \m_axi_araddr[11]\(2), + I1 => \^q\(36), + I2 => \^q\(35), + O => \axaddr_incr_reg[3]\(2) + ); +\axaddr_incr[3]_i_13__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A6" + ) + port map ( + I0 => \m_axi_araddr[11]\(1), + I1 => \^q\(35), + I2 => \^q\(36), + O => \axaddr_incr_reg[3]\(1) + ); +\axaddr_incr[3]_i_14__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A9" + ) + port map ( + I0 => \m_axi_araddr[11]\(0), + I1 => \^q\(35), + I2 => \^q\(36), + O => \axaddr_incr_reg[3]\(0) + ); +\axaddr_incr[3]_i_4__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"2A" + ) + port map ( + I0 => \^q\(2), + I1 => \^q\(35), + I2 => \^q\(36), + O => \axaddr_incr[3]_i_4__0_n_0\ + ); +\axaddr_incr[3]_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^q\(1), + I1 => \^q\(36), + O => \axaddr_incr[3]_i_5__0_n_0\ + ); +\axaddr_incr[3]_i_6__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"02" + ) + port map ( + I0 => \^q\(0), + I1 => \^q\(35), + I2 => \^q\(36), + O => \axaddr_incr[3]_i_6__0_n_0\ + ); +\axaddr_incr_reg[11]_i_3__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \axaddr_incr_reg[7]_i_2__0_n_0\, + CO(3) => \NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED\(3), + CO(2) => \axaddr_incr_reg[11]_i_3__0_n_1\, + CO(1) => \axaddr_incr_reg[11]_i_3__0_n_2\, + CO(0) => \axaddr_incr_reg[11]_i_3__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => O(3 downto 0), + S(3 downto 0) => \^q\(11 downto 8) + ); +\axaddr_incr_reg[3]_i_2__0\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \axaddr_incr_reg[3]_i_2__0_n_0\, + CO(2) => \axaddr_incr_reg[3]_i_2__0_n_1\, + CO(1) => \axaddr_incr_reg[3]_i_2__0_n_2\, + CO(0) => \axaddr_incr_reg[3]_i_2__0_n_3\, + CYINIT => '0', + DI(3) => \^q\(3), + DI(2) => \axaddr_incr[3]_i_4__0_n_0\, + DI(1) => \axaddr_incr[3]_i_5__0_n_0\, + DI(0) => \axaddr_incr[3]_i_6__0_n_0\, + O(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0), + S(3 downto 0) => \axaddr_incr_reg[3]_0\(3 downto 0) + ); +\axaddr_incr_reg[7]_i_2__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \axaddr_incr_reg[3]_i_2__0_n_0\, + CO(3) => \axaddr_incr_reg[7]_i_2__0_n_0\, + CO(2) => \axaddr_incr_reg[7]_i_2__0_n_1\, + CO(1) => \axaddr_incr_reg[7]_i_2__0_n_2\, + CO(0) => \axaddr_incr_reg[7]_i_2__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => \m_payload_i_reg[7]_0\(3 downto 0), + S(3 downto 0) => \^q\(7 downto 4) + ); +\axaddr_offset_r[0]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CCAAF0FFCCAAF000" + ) + port map ( + I0 => \^q\(1), + I1 => \^q\(3), + I2 => \^q\(2), + I3 => \^q\(36), + I4 => \^q\(35), + I5 => \^q\(0), + O => \m_payload_i_reg[1]_0\ + ); +\axaddr_offset_r[1]_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30800080" + ) + port map ( + I0 => \^q\(2), + I1 => \^q\(35), + I2 => \^q\(39), + I3 => \^q\(36), + I4 => \^q\(3), + O => \m_payload_i_reg[2]_1\ + ); +\axaddr_offset_r[1]_i_3__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"C0000088" + ) + port map ( + I0 => \^q\(1), + I1 => \^q\(39), + I2 => \^q\(4), + I3 => \^q\(36), + I4 => \^q\(35), + O => \m_payload_i_reg[1]_1\ + ); +\axaddr_offset_r[2]_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"C0008800" + ) + port map ( + I0 => \^q\(4), + I1 => \^q\(40), + I2 => \^q\(5), + I3 => \^q\(36), + I4 => \^q\(35), + O => \m_payload_i_reg[4]_0\ + ); +\axaddr_offset_r[2]_i_3__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FF3FFF77" + ) + port map ( + I0 => \^q\(2), + I1 => \^q\(40), + I2 => \^q\(3), + I3 => \^q\(36), + I4 => \^q\(35), + O => \m_payload_i_reg[2]_0\ + ); +\axaddr_offset_r[3]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5533000F5533FF0F" + ) + port map ( + I0 => \^q\(6), + I1 => \^q\(5), + I2 => \^q\(3), + I3 => \^q\(35), + I4 => \^q\(36), + I5 => \^q\(4), + O => \^m_payload_i_reg[6]_0\ + ); +\axaddr_wrap[3]_i_3__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => \m_axi_araddr[11]_0\(3), + I1 => \^q\(35), + I2 => \^q\(36), + O => \axaddr_wrap_reg[3]\(3) + ); +\axaddr_wrap[3]_i_4__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A6" + ) + port map ( + I0 => \m_axi_araddr[11]_0\(2), + I1 => \^q\(36), + I2 => \^q\(35), + O => \axaddr_wrap_reg[3]\(2) + ); +\axaddr_wrap[3]_i_5__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A6" + ) + port map ( + I0 => \m_axi_araddr[11]_0\(1), + I1 => \^q\(35), + I2 => \^q\(36), + O => \axaddr_wrap_reg[3]\(1) + ); +\axaddr_wrap[3]_i_6__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A9" + ) + port map ( + I0 => \m_axi_araddr[11]_0\(0), + I1 => \^q\(35), + I2 => \^q\(36), + O => \axaddr_wrap_reg[3]\(0) + ); +\axlen_cnt[3]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0080" + ) + port map ( + I0 => \^q\(41), + I1 => \^si_rs_arvalid\, + I2 => \axlen_cnt_reg[3]\(0), + I3 => \axlen_cnt_reg[3]\(1), + O => \m_payload_i_reg[47]_0\ + ); +\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACAFFC0CACACACA" + ) + port map ( + I0 => \^q\(0), + I1 => \m_axi_araddr[11]\(0), + I2 => \m_axi_araddr[11]_INST_0_i_1_n_0\, + I3 => \m_axi_araddr[11]_0\(0), + I4 => \m_axi_araddr[11]_1\, + I5 => \^q\(37), + O => m_axi_araddr(0) + ); +\m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACAFFC0CACACACA" + ) + port map ( + I0 => \^q\(10), + I1 => \m_axi_araddr[11]\(10), + I2 => \m_axi_araddr[11]_INST_0_i_1_n_0\, + I3 => \m_axi_araddr[11]_0\(10), + I4 => \m_axi_araddr[11]_1\, + I5 => \^q\(37), + O => m_axi_araddr(10) + ); +\m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACAFFC0CACACACA" + ) + port map ( + I0 => \^q\(11), + I1 => \m_axi_araddr[11]\(11), + I2 => \m_axi_araddr[11]_INST_0_i_1_n_0\, + I3 => \m_axi_araddr[11]_0\(11), + I4 => \m_axi_araddr[11]_1\, + I5 => \^q\(37), + O => m_axi_araddr(11) + ); +\m_axi_araddr[11]_INST_0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => \^q\(37), + I1 => \m_payload_i_reg_n_0_[38]\, + I2 => sel_first_1, + O => \m_axi_araddr[11]_INST_0_i_1_n_0\ + ); +\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACAFFC0CACACACA" + ) + port map ( + I0 => \^q\(1), + I1 => \m_axi_araddr[11]\(1), + I2 => \m_axi_araddr[11]_INST_0_i_1_n_0\, + I3 => \m_axi_araddr[11]_0\(1), + I4 => \m_axi_araddr[11]_1\, + I5 => \^q\(37), + O => m_axi_araddr(1) + ); +\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF0C00ACAAACAA" + ) + port map ( + I0 => \^q\(2), + I1 => \m_axi_araddr[11]_0\(2), + I2 => \m_axi_araddr[11]_1\, + I3 => \^q\(37), + I4 => \m_axi_araddr[11]\(2), + I5 => \m_axi_araddr[11]_INST_0_i_1_n_0\, + O => m_axi_araddr(2) + ); +\m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACAFFC0CACACACA" + ) + port map ( + I0 => \^q\(3), + I1 => \m_axi_araddr[11]\(3), + I2 => \m_axi_araddr[11]_INST_0_i_1_n_0\, + I3 => \m_axi_araddr[11]_0\(3), + I4 => \m_axi_araddr[11]_1\, + I5 => \^q\(37), + O => m_axi_araddr(3) + ); +\m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACAFFC0CACACACA" + ) + port map ( + I0 => \^q\(4), + I1 => \m_axi_araddr[11]\(4), + I2 => \m_axi_araddr[11]_INST_0_i_1_n_0\, + I3 => \m_axi_araddr[11]_0\(4), + I4 => \m_axi_araddr[11]_1\, + I5 => \^q\(37), + O => m_axi_araddr(4) + ); +\m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACAFFC0CACACACA" + ) + port map ( + I0 => \^q\(5), + I1 => \m_axi_araddr[11]\(5), + I2 => \m_axi_araddr[11]_INST_0_i_1_n_0\, + I3 => \m_axi_araddr[11]_0\(5), + I4 => \m_axi_araddr[11]_1\, + I5 => \^q\(37), + O => m_axi_araddr(5) + ); +\m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF0C00ACAAACAA" + ) + port map ( + I0 => \^q\(6), + I1 => \m_axi_araddr[11]_0\(6), + I2 => \m_axi_araddr[11]_1\, + I3 => \^q\(37), + I4 => \m_axi_araddr[11]\(6), + I5 => \m_axi_araddr[11]_INST_0_i_1_n_0\, + O => m_axi_araddr(6) + ); +\m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACAFFC0CACACACA" + ) + port map ( + I0 => \^q\(7), + I1 => \m_axi_araddr[11]\(7), + I2 => \m_axi_araddr[11]_INST_0_i_1_n_0\, + I3 => \m_axi_araddr[11]_0\(7), + I4 => \m_axi_araddr[11]_1\, + I5 => \^q\(37), + O => m_axi_araddr(7) + ); +\m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF0C00ACAAACAA" + ) + port map ( + I0 => \^q\(8), + I1 => \m_axi_araddr[11]_0\(8), + I2 => \m_axi_araddr[11]_1\, + I3 => \^q\(37), + I4 => \m_axi_araddr[11]\(8), + I5 => \m_axi_araddr[11]_INST_0_i_1_n_0\, + O => m_axi_araddr(8) + ); +\m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACAFFC0CACACACA" + ) + port map ( + I0 => \^q\(9), + I1 => \m_axi_araddr[11]\(9), + I2 => \m_axi_araddr[11]_INST_0_i_1_n_0\, + I3 => \m_axi_araddr[11]_0\(9), + I4 => \m_axi_araddr[11]_1\, + I5 => \^q\(37), + O => m_axi_araddr(9) + ); +\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(0), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[0]\, + O => \m_payload_i[0]_i_1__0_n_0\ + ); +\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(10), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[10]\, + O => \m_payload_i[10]_i_1__0_n_0\ + ); +\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(11), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[11]\, + O => \m_payload_i[11]_i_1__0_n_0\ + ); +\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(12), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[12]\, + O => \m_payload_i[12]_i_1__0_n_0\ + ); +\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(13), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[13]\, + O => \m_payload_i[13]_i_1__1_n_0\ + ); +\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(14), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[14]\, + O => \m_payload_i[14]_i_1__0_n_0\ + ); +\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(15), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[15]\, + O => \m_payload_i[15]_i_1__0_n_0\ + ); +\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(16), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[16]\, + O => \m_payload_i[16]_i_1__0_n_0\ + ); +\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(17), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[17]\, + O => \m_payload_i[17]_i_1__0_n_0\ + ); +\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(18), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[18]\, + O => \m_payload_i[18]_i_1__0_n_0\ + ); +\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(19), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[19]\, + O => \m_payload_i[19]_i_1__0_n_0\ + ); +\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(1), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[1]\, + O => \m_payload_i[1]_i_1__0_n_0\ + ); +\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(20), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[20]\, + O => \m_payload_i[20]_i_1__0_n_0\ + ); +\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(21), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[21]\, + O => \m_payload_i[21]_i_1__0_n_0\ + ); +\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(22), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[22]\, + O => \m_payload_i[22]_i_1__0_n_0\ + ); +\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(23), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[23]\, + O => \m_payload_i[23]_i_1__0_n_0\ + ); +\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(24), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[24]\, + O => \m_payload_i[24]_i_1__0_n_0\ + ); +\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(25), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[25]\, + O => \m_payload_i[25]_i_1__0_n_0\ + ); +\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(26), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[26]\, + O => \m_payload_i[26]_i_1__0_n_0\ + ); +\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(27), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[27]\, + O => \m_payload_i[27]_i_1__0_n_0\ + ); +\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(28), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[28]\, + O => \m_payload_i[28]_i_1__0_n_0\ + ); +\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(29), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[29]\, + O => \m_payload_i[29]_i_1__0_n_0\ + ); +\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(2), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[2]\, + O => \m_payload_i[2]_i_1__0_n_0\ + ); +\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(30), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[30]\, + O => \m_payload_i[30]_i_1__0_n_0\ + ); +\m_payload_i[31]_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(31), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[31]\, + O => \m_payload_i[31]_i_2__0_n_0\ + ); +\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_arprot(0), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[32]\, + O => \m_payload_i[32]_i_1__0_n_0\ + ); +\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_arprot(1), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[33]\, + O => \m_payload_i[33]_i_1__0_n_0\ + ); +\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_arprot(2), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[34]\, + O => \m_payload_i[34]_i_1__0_n_0\ + ); +\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_arsize(0), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[35]\, + O => \m_payload_i[35]_i_1__0_n_0\ + ); +\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_arsize(1), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[36]\, + O => \m_payload_i[36]_i_1__0_n_0\ + ); +\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_arburst(0), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[38]\, + O => \m_payload_i[38]_i_1__0_n_0\ + ); +\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_arburst(1), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[39]\, + O => \m_payload_i[39]_i_1__0_n_0\ + ); +\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(3), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[3]\, + O => \m_payload_i[3]_i_1__0_n_0\ + ); +\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_arlen(0), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[44]\, + O => \m_payload_i[44]_i_1__0_n_0\ + ); +\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_arlen(1), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[45]\, + O => \m_payload_i[45]_i_1__0_n_0\ + ); +\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_arlen(2), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[46]\, + O => \m_payload_i[46]_i_1__1_n_0\ + ); +\m_payload_i[47]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_arlen(3), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[47]\, + O => \m_payload_i[47]_i_1__0_n_0\ + ); +\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(4), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[4]\, + O => \m_payload_i[4]_i_1__0_n_0\ + ); +\m_payload_i[50]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_arid(0), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[50]\, + O => \m_payload_i[50]_i_1__0_n_0\ + ); +\m_payload_i[51]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_arid(1), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[51]\, + O => \m_payload_i[51]_i_1__0_n_0\ + ); +\m_payload_i[52]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_arid(2), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[52]\, + O => \m_payload_i[52]_i_1__0_n_0\ + ); +\m_payload_i[53]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_arid(3), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[53]\, + O => \m_payload_i[53]_i_1__0_n_0\ + ); +\m_payload_i[54]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_arid(4), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[54]\, + O => \m_payload_i[54]_i_1__0_n_0\ + ); +\m_payload_i[55]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_arid(5), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[55]\, + O => \m_payload_i[55]_i_1__0_n_0\ + ); +\m_payload_i[56]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_arid(6), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[56]\, + O => \m_payload_i[56]_i_1__0_n_0\ + ); +\m_payload_i[57]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_arid(7), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[57]\, + O => \m_payload_i[57]_i_1__0_n_0\ + ); +\m_payload_i[58]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_arid(8), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[58]\, + O => \m_payload_i[58]_i_1__0_n_0\ + ); +\m_payload_i[59]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_arid(9), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[59]\, + O => \m_payload_i[59]_i_1__0_n_0\ + ); +\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(5), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[5]\, + O => \m_payload_i[5]_i_1__0_n_0\ + ); +\m_payload_i[60]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_arid(10), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[60]\, + O => \m_payload_i[60]_i_1__0_n_0\ + ); +\m_payload_i[61]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_arid(11), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[61]\, + O => \m_payload_i[61]_i_1__0_n_0\ + ); +\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(6), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[6]\, + O => \m_payload_i[6]_i_1__0_n_0\ + ); +\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(7), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[7]\, + O => \m_payload_i[7]_i_1__0_n_0\ + ); +\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(8), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[8]\, + O => \m_payload_i[8]_i_1__0_n_0\ + ); +\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_araddr(9), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[9]\, + O => \m_payload_i[9]_i_1__0_n_0\ + ); +\m_payload_i_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[0]_i_1__0_n_0\, + Q => \^q\(0), + R => '0' + ); +\m_payload_i_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[10]_i_1__0_n_0\, + Q => \^q\(10), + R => '0' + ); +\m_payload_i_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[11]_i_1__0_n_0\, + Q => \^q\(11), + R => '0' + ); +\m_payload_i_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[12]_i_1__0_n_0\, + Q => \^q\(12), + R => '0' + ); +\m_payload_i_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[13]_i_1__1_n_0\, + Q => \^q\(13), + R => '0' + ); +\m_payload_i_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[14]_i_1__0_n_0\, + Q => \^q\(14), + R => '0' + ); +\m_payload_i_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[15]_i_1__0_n_0\, + Q => \^q\(15), + R => '0' + ); +\m_payload_i_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[16]_i_1__0_n_0\, + Q => \^q\(16), + R => '0' + ); +\m_payload_i_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[17]_i_1__0_n_0\, + Q => \^q\(17), + R => '0' + ); +\m_payload_i_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[18]_i_1__0_n_0\, + Q => \^q\(18), + R => '0' + ); +\m_payload_i_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[19]_i_1__0_n_0\, + Q => \^q\(19), + R => '0' + ); +\m_payload_i_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[1]_i_1__0_n_0\, + Q => \^q\(1), + R => '0' + ); +\m_payload_i_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[20]_i_1__0_n_0\, + Q => \^q\(20), + R => '0' + ); +\m_payload_i_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[21]_i_1__0_n_0\, + Q => \^q\(21), + R => '0' + ); +\m_payload_i_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[22]_i_1__0_n_0\, + Q => \^q\(22), + R => '0' + ); +\m_payload_i_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[23]_i_1__0_n_0\, + Q => \^q\(23), + R => '0' + ); +\m_payload_i_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[24]_i_1__0_n_0\, + Q => \^q\(24), + R => '0' + ); +\m_payload_i_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[25]_i_1__0_n_0\, + Q => \^q\(25), + R => '0' + ); +\m_payload_i_reg[26]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[26]_i_1__0_n_0\, + Q => \^q\(26), + R => '0' + ); +\m_payload_i_reg[27]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[27]_i_1__0_n_0\, + Q => \^q\(27), + R => '0' + ); +\m_payload_i_reg[28]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[28]_i_1__0_n_0\, + Q => \^q\(28), + R => '0' + ); +\m_payload_i_reg[29]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[29]_i_1__0_n_0\, + Q => \^q\(29), + R => '0' + ); +\m_payload_i_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[2]_i_1__0_n_0\, + Q => \^q\(2), + R => '0' + ); +\m_payload_i_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[30]_i_1__0_n_0\, + Q => \^q\(30), + R => '0' + ); +\m_payload_i_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[31]_i_2__0_n_0\, + Q => \^q\(31), + R => '0' + ); +\m_payload_i_reg[32]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[32]_i_1__0_n_0\, + Q => \^q\(32), + R => '0' + ); +\m_payload_i_reg[33]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[33]_i_1__0_n_0\, + Q => \^q\(33), + R => '0' + ); +\m_payload_i_reg[34]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[34]_i_1__0_n_0\, + Q => \^q\(34), + R => '0' + ); +\m_payload_i_reg[35]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[35]_i_1__0_n_0\, + Q => \^q\(35), + R => '0' + ); +\m_payload_i_reg[36]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[36]_i_1__0_n_0\, + Q => \^q\(36), + R => '0' + ); +\m_payload_i_reg[38]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[38]_i_1__0_n_0\, + Q => \m_payload_i_reg_n_0_[38]\, + R => '0' + ); +\m_payload_i_reg[39]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[39]_i_1__0_n_0\, + Q => \^q\(37), + R => '0' + ); +\m_payload_i_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[3]_i_1__0_n_0\, + Q => \^q\(3), + R => '0' + ); +\m_payload_i_reg[44]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[44]_i_1__0_n_0\, + Q => \^q\(38), + R => '0' + ); +\m_payload_i_reg[45]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[45]_i_1__0_n_0\, + Q => \^q\(39), + R => '0' + ); +\m_payload_i_reg[46]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[46]_i_1__1_n_0\, + Q => \^q\(40), + R => '0' + ); +\m_payload_i_reg[47]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[47]_i_1__0_n_0\, + Q => \^q\(41), + R => '0' + ); +\m_payload_i_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[4]_i_1__0_n_0\, + Q => \^q\(4), + R => '0' + ); +\m_payload_i_reg[50]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[50]_i_1__0_n_0\, + Q => \^q\(42), + R => '0' + ); +\m_payload_i_reg[51]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[51]_i_1__0_n_0\, + Q => \^q\(43), + R => '0' + ); +\m_payload_i_reg[52]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[52]_i_1__0_n_0\, + Q => \^q\(44), + R => '0' + ); +\m_payload_i_reg[53]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[53]_i_1__0_n_0\, + Q => \^q\(45), + R => '0' + ); +\m_payload_i_reg[54]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[54]_i_1__0_n_0\, + Q => \^q\(46), + R => '0' + ); +\m_payload_i_reg[55]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[55]_i_1__0_n_0\, + Q => \^q\(47), + R => '0' + ); +\m_payload_i_reg[56]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[56]_i_1__0_n_0\, + Q => \^q\(48), + R => '0' + ); +\m_payload_i_reg[57]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[57]_i_1__0_n_0\, + Q => \^q\(49), + R => '0' + ); +\m_payload_i_reg[58]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[58]_i_1__0_n_0\, + Q => \^q\(50), + R => '0' + ); +\m_payload_i_reg[59]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[59]_i_1__0_n_0\, + Q => \^q\(51), + R => '0' + ); +\m_payload_i_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[5]_i_1__0_n_0\, + Q => \^q\(5), + R => '0' + ); +\m_payload_i_reg[60]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[60]_i_1__0_n_0\, + Q => \^q\(52), + R => '0' + ); +\m_payload_i_reg[61]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[61]_i_1__0_n_0\, + Q => \^q\(53), + R => '0' + ); +\m_payload_i_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[6]_i_1__0_n_0\, + Q => \^q\(6), + R => '0' + ); +\m_payload_i_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[7]_i_1__0_n_0\, + Q => \^q\(7), + R => '0' + ); +\m_payload_i_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[8]_i_1__0_n_0\, + Q => \^q\(8), + R => '0' + ); +\m_payload_i_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \m_payload_i_reg[0]_0\(0), + D => \m_payload_i[9]_i_1__0_n_0\, + Q => \^q\(9), + R => '0' + ); +m_valid_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => m_valid_i0, + Q => \^si_rs_arvalid\, + R => \^aresetn_d_reg[1]_inv_0\ + ); +\next_pending_r_i_3__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000FFFE" + ) + port map ( + I0 => \^q\(39), + I1 => \^q\(38), + I2 => \^q\(40), + I3 => \^q\(41), + I4 => next_pending_r_reg, + O => \m_payload_i_reg[45]_0\ + ); +s_ready_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_ready_i0, + Q => \^s_ready_i_reg_0\, + R => s_ready_i_reg_1 + ); +\skid_buffer_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(0), + Q => \skid_buffer_reg_n_0_[0]\, + R => '0' + ); +\skid_buffer_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(10), + Q => \skid_buffer_reg_n_0_[10]\, + R => '0' + ); +\skid_buffer_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(11), + Q => \skid_buffer_reg_n_0_[11]\, + R => '0' + ); +\skid_buffer_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(12), + Q => \skid_buffer_reg_n_0_[12]\, + R => '0' + ); +\skid_buffer_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(13), + Q => \skid_buffer_reg_n_0_[13]\, + R => '0' + ); +\skid_buffer_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(14), + Q => \skid_buffer_reg_n_0_[14]\, + R => '0' + ); +\skid_buffer_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(15), + Q => \skid_buffer_reg_n_0_[15]\, + R => '0' + ); +\skid_buffer_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(16), + Q => \skid_buffer_reg_n_0_[16]\, + R => '0' + ); +\skid_buffer_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(17), + Q => \skid_buffer_reg_n_0_[17]\, + R => '0' + ); +\skid_buffer_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(18), + Q => \skid_buffer_reg_n_0_[18]\, + R => '0' + ); +\skid_buffer_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(19), + Q => \skid_buffer_reg_n_0_[19]\, + R => '0' + ); +\skid_buffer_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(1), + Q => \skid_buffer_reg_n_0_[1]\, + R => '0' + ); +\skid_buffer_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(20), + Q => \skid_buffer_reg_n_0_[20]\, + R => '0' + ); +\skid_buffer_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(21), + Q => \skid_buffer_reg_n_0_[21]\, + R => '0' + ); +\skid_buffer_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(22), + Q => \skid_buffer_reg_n_0_[22]\, + R => '0' + ); +\skid_buffer_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(23), + Q => \skid_buffer_reg_n_0_[23]\, + R => '0' + ); +\skid_buffer_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(24), + Q => \skid_buffer_reg_n_0_[24]\, + R => '0' + ); +\skid_buffer_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(25), + Q => \skid_buffer_reg_n_0_[25]\, + R => '0' + ); +\skid_buffer_reg[26]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(26), + Q => \skid_buffer_reg_n_0_[26]\, + R => '0' + ); +\skid_buffer_reg[27]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(27), + Q => \skid_buffer_reg_n_0_[27]\, + R => '0' + ); +\skid_buffer_reg[28]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(28), + Q => \skid_buffer_reg_n_0_[28]\, + R => '0' + ); +\skid_buffer_reg[29]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(29), + Q => \skid_buffer_reg_n_0_[29]\, + R => '0' + ); +\skid_buffer_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(2), + Q => \skid_buffer_reg_n_0_[2]\, + R => '0' + ); +\skid_buffer_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(30), + Q => \skid_buffer_reg_n_0_[30]\, + R => '0' + ); +\skid_buffer_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(31), + Q => \skid_buffer_reg_n_0_[31]\, + R => '0' + ); +\skid_buffer_reg[32]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_arprot(0), + Q => \skid_buffer_reg_n_0_[32]\, + R => '0' + ); +\skid_buffer_reg[33]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_arprot(1), + Q => \skid_buffer_reg_n_0_[33]\, + R => '0' + ); +\skid_buffer_reg[34]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_arprot(2), + Q => \skid_buffer_reg_n_0_[34]\, + R => '0' + ); +\skid_buffer_reg[35]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_arsize(0), + Q => \skid_buffer_reg_n_0_[35]\, + R => '0' + ); +\skid_buffer_reg[36]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_arsize(1), + Q => \skid_buffer_reg_n_0_[36]\, + R => '0' + ); +\skid_buffer_reg[38]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_arburst(0), + Q => \skid_buffer_reg_n_0_[38]\, + R => '0' + ); +\skid_buffer_reg[39]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_arburst(1), + Q => \skid_buffer_reg_n_0_[39]\, + R => '0' + ); +\skid_buffer_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(3), + Q => \skid_buffer_reg_n_0_[3]\, + R => '0' + ); +\skid_buffer_reg[44]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_arlen(0), + Q => \skid_buffer_reg_n_0_[44]\, + R => '0' + ); +\skid_buffer_reg[45]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_arlen(1), + Q => \skid_buffer_reg_n_0_[45]\, + R => '0' + ); +\skid_buffer_reg[46]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_arlen(2), + Q => \skid_buffer_reg_n_0_[46]\, + R => '0' + ); +\skid_buffer_reg[47]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_arlen(3), + Q => \skid_buffer_reg_n_0_[47]\, + R => '0' + ); +\skid_buffer_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(4), + Q => \skid_buffer_reg_n_0_[4]\, + R => '0' + ); +\skid_buffer_reg[50]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_arid(0), + Q => \skid_buffer_reg_n_0_[50]\, + R => '0' + ); +\skid_buffer_reg[51]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_arid(1), + Q => \skid_buffer_reg_n_0_[51]\, + R => '0' + ); +\skid_buffer_reg[52]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_arid(2), + Q => \skid_buffer_reg_n_0_[52]\, + R => '0' + ); +\skid_buffer_reg[53]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_arid(3), + Q => \skid_buffer_reg_n_0_[53]\, + R => '0' + ); +\skid_buffer_reg[54]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_arid(4), + Q => \skid_buffer_reg_n_0_[54]\, + R => '0' + ); +\skid_buffer_reg[55]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_arid(5), + Q => \skid_buffer_reg_n_0_[55]\, + R => '0' + ); +\skid_buffer_reg[56]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_arid(6), + Q => \skid_buffer_reg_n_0_[56]\, + R => '0' + ); +\skid_buffer_reg[57]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_arid(7), + Q => \skid_buffer_reg_n_0_[57]\, + R => '0' + ); +\skid_buffer_reg[58]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_arid(8), + Q => \skid_buffer_reg_n_0_[58]\, + R => '0' + ); +\skid_buffer_reg[59]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_arid(9), + Q => \skid_buffer_reg_n_0_[59]\, + R => '0' + ); +\skid_buffer_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(5), + Q => \skid_buffer_reg_n_0_[5]\, + R => '0' + ); +\skid_buffer_reg[60]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_arid(10), + Q => \skid_buffer_reg_n_0_[60]\, + R => '0' + ); +\skid_buffer_reg[61]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_arid(11), + Q => \skid_buffer_reg_n_0_[61]\, + R => '0' + ); +\skid_buffer_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(6), + Q => \skid_buffer_reg_n_0_[6]\, + R => '0' + ); +\skid_buffer_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(7), + Q => \skid_buffer_reg_n_0_[7]\, + R => '0' + ); +\skid_buffer_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(8), + Q => \skid_buffer_reg_n_0_[8]\, + R => '0' + ); +\skid_buffer_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_araddr(9), + Q => \skid_buffer_reg_n_0_[9]\, + R => '0' + ); +\wrap_boundary_axaddr_r[0]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"A8AA" + ) + port map ( + I0 => \^q\(0), + I1 => \^q\(36), + I2 => \^q\(35), + I3 => \^q\(38), + O => \m_payload_i_reg[6]_1\(0) + ); +\wrap_boundary_axaddr_r[1]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"DDCF0000" + ) + port map ( + I0 => \^q\(38), + I1 => \^q\(36), + I2 => \^q\(39), + I3 => \^q\(35), + I4 => \^q\(1), + O => \m_payload_i_reg[6]_1\(1) + ); +\wrap_boundary_axaddr_r[2]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"A0A0202AAAAA202A" + ) + port map ( + I0 => \^q\(2), + I1 => \^q\(38), + I2 => \^q\(36), + I3 => \^q\(40), + I4 => \^q\(35), + I5 => \^q\(39), + O => \m_payload_i_reg[6]_1\(2) + ); +\wrap_boundary_axaddr_r[3]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF00201030" + ) + port map ( + I0 => \^q\(36), + I1 => \^q\(35), + I2 => \^q\(3), + I3 => \^q\(39), + I4 => \^q\(41), + I5 => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\, + O => \m_payload_i_reg[6]_1\(3) + ); +\wrap_boundary_axaddr_r[3]_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30500000" + ) + port map ( + I0 => \^q\(40), + I1 => \^q\(38), + I2 => \^q\(35), + I3 => \^q\(36), + I4 => \^q\(3), + O => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ + ); +\wrap_boundary_axaddr_r[4]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000A22AAAA0A22AA" + ) + port map ( + I0 => \^q\(4), + I1 => \^q\(40), + I2 => \^q\(41), + I3 => \^q\(36), + I4 => \^q\(35), + I5 => \^q\(39), + O => \m_payload_i_reg[6]_1\(4) + ); +\wrap_boundary_axaddr_r[5]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"44CC0CCC" + ) + port map ( + I0 => \^q\(40), + I1 => \^q\(5), + I2 => \^q\(41), + I3 => \^q\(36), + I4 => \^q\(35), + O => \m_payload_i_reg[6]_1\(5) + ); +\wrap_boundary_axaddr_r[6]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2AAA" + ) + port map ( + I0 => \^q\(6), + I1 => \^q\(36), + I2 => \^q\(35), + I3 => \^q\(41), + O => \m_payload_i_reg[6]_1\(6) + ); +\wrap_second_len_r[3]_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00004000" + ) + port map ( + I0 => \axlen_cnt_reg[3]\(1), + I1 => \axlen_cnt_reg[3]\(0), + I2 => \^si_rs_arvalid\, + I3 => \^q\(41), + I4 => \^m_payload_i_reg[6]_0\, + O => \FSM_sequential_state_reg[1]\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axic_register_slice_0 is + port ( + s_ready_i_reg_0 : out STD_LOGIC; + \aresetn_d_reg[0]_0\ : out STD_LOGIC; + m_valid_i_reg_0 : out STD_LOGIC; + S : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \m_payload_i_reg[61]_0\ : out STD_LOGIC_VECTOR ( 53 downto 0 ); + \axaddr_wrap_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + axaddr_incr : out STD_LOGIC_VECTOR ( 11 downto 0 ); + \m_payload_i_reg[45]_0\ : out STD_LOGIC; + \FSM_sequential_state_reg[0]\ : out STD_LOGIC; + \m_payload_i_reg[5]_0\ : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 6 downto 0 ); + \m_payload_i_reg[4]_0\ : out STD_LOGIC; + \m_payload_i_reg[1]_0\ : out STD_LOGIC; + \m_payload_i_reg[2]_0\ : out STD_LOGIC; + \m_payload_i_reg[1]_1\ : out STD_LOGIC; + \m_payload_i_reg[2]_1\ : out STD_LOGIC; + m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); + \aresetn_d_reg[0]_1\ : out STD_LOGIC; + aclk : in STD_LOGIC; + m_valid_i_reg_1 : in STD_LOGIC; + aresetn : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \m_axi_awaddr[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); + b_push : in STD_LOGIC; + s_axi_awvalid : in STD_LOGIC; + \axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + next_pending_r_reg : in STD_LOGIC; + \wrap_second_len_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + sel_first : in STD_LOGIC; + sel_first_0 : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axic_register_slice_0 : entity is "axi_register_slice_v2_1_29_axic_register_slice"; +end NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axic_register_slice_0; + +architecture STRUCTURE of NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axic_register_slice_0 is + signal \^aresetn_d_reg[0]_0\ : STD_LOGIC; + signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC; + signal \axaddr_incr[3]_i_4_n_0\ : STD_LOGIC; + signal \axaddr_incr[3]_i_5_n_0\ : STD_LOGIC; + signal \axaddr_incr[3]_i_6_n_0\ : STD_LOGIC; + signal \axaddr_incr_reg[11]_i_3_n_1\ : STD_LOGIC; + signal \axaddr_incr_reg[11]_i_3_n_2\ : STD_LOGIC; + signal \axaddr_incr_reg[11]_i_3_n_3\ : STD_LOGIC; + signal \axaddr_incr_reg[3]_i_2_n_0\ : STD_LOGIC; + signal \axaddr_incr_reg[3]_i_2_n_1\ : STD_LOGIC; + signal \axaddr_incr_reg[3]_i_2_n_2\ : STD_LOGIC; + signal \axaddr_incr_reg[3]_i_2_n_3\ : STD_LOGIC; + signal \axaddr_incr_reg[7]_i_2_n_0\ : STD_LOGIC; + signal \axaddr_incr_reg[7]_i_2_n_1\ : STD_LOGIC; + signal \axaddr_incr_reg[7]_i_2_n_2\ : STD_LOGIC; + signal \axaddr_incr_reg[7]_i_2_n_3\ : STD_LOGIC; + signal \m_axi_awaddr[11]_INST_0_i_1_n_0\ : STD_LOGIC; + signal \^m_payload_i_reg[5]_0\ : STD_LOGIC; + signal \^m_payload_i_reg[61]_0\ : STD_LOGIC_VECTOR ( 53 downto 0 ); + signal \m_payload_i_reg_n_0_[38]\ : STD_LOGIC; + signal m_valid_i0 : STD_LOGIC; + signal \^m_valid_i_reg_0\ : STD_LOGIC; + signal s_ready_i0 : STD_LOGIC; + signal \^s_ready_i_reg_0\ : STD_LOGIC; + signal skid_buffer : STD_LOGIC_VECTOR ( 61 downto 0 ); + signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; + signal \wrap_boundary_axaddr_r[3]_i_2_n_0\ : STD_LOGIC; + signal \NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute ADDER_THRESHOLD : integer; + attribute ADDER_THRESHOLD of \axaddr_incr_reg[11]_i_3\ : label is 35; + attribute ADDER_THRESHOLD of \axaddr_incr_reg[3]_i_2\ : label is 35; + attribute ADDER_THRESHOLD of \axaddr_incr_reg[7]_i_2\ : label is 35; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair71"; + attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair70"; + attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair70"; + attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__0\ : label is "soft_lutpair69"; + attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair69"; + attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair68"; + attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair68"; + attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair67"; + attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair67"; + attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair66"; + attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair75"; + attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair66"; + attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair65"; + attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair65"; + attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair64"; + attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair64"; + attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair63"; + attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair63"; + attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair62"; + attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair62"; + attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair61"; + attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair75"; + attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair61"; + attribute SOFT_HLUTNM of \m_payload_i[31]_i_2\ : label is "soft_lutpair60"; + attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair60"; + attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair59"; + attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair59"; + attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair58"; + attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair58"; + attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair57"; + attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair57"; + attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair74"; + attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair56"; + attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair56"; + attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair55"; + attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair55"; + attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair74"; + attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair54"; + attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair54"; + attribute SOFT_HLUTNM of \m_payload_i[52]_i_1\ : label is "soft_lutpair53"; + attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair53"; + attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair52"; + attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair52"; + attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair51"; + attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair51"; + attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair50"; + attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair50"; + attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair73"; + attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair49"; + attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair49"; + attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair73"; + attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair72"; + attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair72"; + attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair71"; +begin + \aresetn_d_reg[0]_0\ <= \^aresetn_d_reg[0]_0\; + \m_payload_i_reg[5]_0\ <= \^m_payload_i_reg[5]_0\; + \m_payload_i_reg[61]_0\(53 downto 0) <= \^m_payload_i_reg[61]_0\(53 downto 0); + m_valid_i_reg_0 <= \^m_valid_i_reg_0\; + s_ready_i_reg_0 <= \^s_ready_i_reg_0\; +\aresetn_d[1]_inv_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"7" + ) + port map ( + I0 => \aresetn_d_reg_n_0_[0]\, + I1 => aresetn, + O => \aresetn_d_reg[0]_1\ + ); +\aresetn_d_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => aresetn, + Q => \aresetn_d_reg_n_0_[0]\, + R => '0' + ); +\axaddr_incr[3]_i_11\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => Q(3), + I1 => \^m_payload_i_reg[61]_0\(35), + I2 => \^m_payload_i_reg[61]_0\(36), + O => S(3) + ); +\axaddr_incr[3]_i_12\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A6" + ) + port map ( + I0 => Q(2), + I1 => \^m_payload_i_reg[61]_0\(36), + I2 => \^m_payload_i_reg[61]_0\(35), + O => S(2) + ); +\axaddr_incr[3]_i_13\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A6" + ) + port map ( + I0 => Q(1), + I1 => \^m_payload_i_reg[61]_0\(35), + I2 => \^m_payload_i_reg[61]_0\(36), + O => S(1) + ); +\axaddr_incr[3]_i_14\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A9" + ) + port map ( + I0 => Q(0), + I1 => \^m_payload_i_reg[61]_0\(35), + I2 => \^m_payload_i_reg[61]_0\(36), + O => S(0) + ); +\axaddr_incr[3]_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"2A" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(2), + I1 => \^m_payload_i_reg[61]_0\(35), + I2 => \^m_payload_i_reg[61]_0\(36), + O => \axaddr_incr[3]_i_4_n_0\ + ); +\axaddr_incr[3]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(1), + I1 => \^m_payload_i_reg[61]_0\(36), + O => \axaddr_incr[3]_i_5_n_0\ + ); +\axaddr_incr[3]_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"02" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(0), + I1 => \^m_payload_i_reg[61]_0\(35), + I2 => \^m_payload_i_reg[61]_0\(36), + O => \axaddr_incr[3]_i_6_n_0\ + ); +\axaddr_incr_reg[11]_i_3\: unisim.vcomponents.CARRY4 + port map ( + CI => \axaddr_incr_reg[7]_i_2_n_0\, + CO(3) => \NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED\(3), + CO(2) => \axaddr_incr_reg[11]_i_3_n_1\, + CO(1) => \axaddr_incr_reg[11]_i_3_n_2\, + CO(0) => \axaddr_incr_reg[11]_i_3_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => axaddr_incr(11 downto 8), + S(3 downto 0) => \^m_payload_i_reg[61]_0\(11 downto 8) + ); +\axaddr_incr_reg[3]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \axaddr_incr_reg[3]_i_2_n_0\, + CO(2) => \axaddr_incr_reg[3]_i_2_n_1\, + CO(1) => \axaddr_incr_reg[3]_i_2_n_2\, + CO(0) => \axaddr_incr_reg[3]_i_2_n_3\, + CYINIT => '0', + DI(3) => \^m_payload_i_reg[61]_0\(3), + DI(2) => \axaddr_incr[3]_i_4_n_0\, + DI(1) => \axaddr_incr[3]_i_5_n_0\, + DI(0) => \axaddr_incr[3]_i_6_n_0\, + O(3 downto 0) => axaddr_incr(3 downto 0), + S(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0) + ); +\axaddr_incr_reg[7]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => \axaddr_incr_reg[3]_i_2_n_0\, + CO(3) => \axaddr_incr_reg[7]_i_2_n_0\, + CO(2) => \axaddr_incr_reg[7]_i_2_n_1\, + CO(1) => \axaddr_incr_reg[7]_i_2_n_2\, + CO(0) => \axaddr_incr_reg[7]_i_2_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => axaddr_incr(7 downto 4), + S(3 downto 0) => \^m_payload_i_reg[61]_0\(7 downto 4) + ); +\axaddr_offset_r[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CCAAF0FFCCAAF000" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(1), + I1 => \^m_payload_i_reg[61]_0\(3), + I2 => \^m_payload_i_reg[61]_0\(2), + I3 => \^m_payload_i_reg[61]_0\(36), + I4 => \^m_payload_i_reg[61]_0\(35), + I5 => \^m_payload_i_reg[61]_0\(0), + O => \m_payload_i_reg[1]_1\ + ); +\axaddr_offset_r[1]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30800080" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(2), + I1 => \^m_payload_i_reg[61]_0\(35), + I2 => \^m_payload_i_reg[61]_0\(39), + I3 => \^m_payload_i_reg[61]_0\(36), + I4 => \^m_payload_i_reg[61]_0\(3), + O => \m_payload_i_reg[2]_1\ + ); +\axaddr_offset_r[1]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"C0000088" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(1), + I1 => \^m_payload_i_reg[61]_0\(39), + I2 => \^m_payload_i_reg[61]_0\(4), + I3 => \^m_payload_i_reg[61]_0\(36), + I4 => \^m_payload_i_reg[61]_0\(35), + O => \m_payload_i_reg[1]_0\ + ); +\axaddr_offset_r[2]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"C0008800" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(4), + I1 => \^m_payload_i_reg[61]_0\(40), + I2 => \^m_payload_i_reg[61]_0\(5), + I3 => \^m_payload_i_reg[61]_0\(36), + I4 => \^m_payload_i_reg[61]_0\(35), + O => \m_payload_i_reg[4]_0\ + ); +\axaddr_offset_r[2]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FF3FFF77" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(2), + I1 => \^m_payload_i_reg[61]_0\(40), + I2 => \^m_payload_i_reg[61]_0\(3), + I3 => \^m_payload_i_reg[61]_0\(36), + I4 => \^m_payload_i_reg[61]_0\(35), + O => \m_payload_i_reg[2]_0\ + ); +\axaddr_offset_r[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"33550F0033550FFF" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(5), + I1 => \^m_payload_i_reg[61]_0\(6), + I2 => \^m_payload_i_reg[61]_0\(4), + I3 => \^m_payload_i_reg[61]_0\(35), + I4 => \^m_payload_i_reg[61]_0\(36), + I5 => \^m_payload_i_reg[61]_0\(3), + O => \^m_payload_i_reg[5]_0\ + ); +\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => \m_axi_awaddr[11]\(3), + I1 => \^m_payload_i_reg[61]_0\(35), + I2 => \^m_payload_i_reg[61]_0\(36), + O => \axaddr_wrap_reg[3]\(3) + ); +\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A6" + ) + port map ( + I0 => \m_axi_awaddr[11]\(2), + I1 => \^m_payload_i_reg[61]_0\(36), + I2 => \^m_payload_i_reg[61]_0\(35), + O => \axaddr_wrap_reg[3]\(2) + ); +\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A6" + ) + port map ( + I0 => \m_axi_awaddr[11]\(1), + I1 => \^m_payload_i_reg[61]_0\(35), + I2 => \^m_payload_i_reg[61]_0\(36), + O => \axaddr_wrap_reg[3]\(1) + ); +\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A9" + ) + port map ( + I0 => \m_axi_awaddr[11]\(0), + I1 => \^m_payload_i_reg[61]_0\(35), + I2 => \^m_payload_i_reg[61]_0\(36), + O => \axaddr_wrap_reg[3]\(0) + ); +\m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACAFFC0CACACACA" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(0), + I1 => Q(0), + I2 => \m_axi_awaddr[11]_INST_0_i_1_n_0\, + I3 => \m_axi_awaddr[11]\(0), + I4 => sel_first, + I5 => \^m_payload_i_reg[61]_0\(37), + O => m_axi_awaddr(0) + ); +\m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACAFFC0CACACACA" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(10), + I1 => Q(10), + I2 => \m_axi_awaddr[11]_INST_0_i_1_n_0\, + I3 => \m_axi_awaddr[11]\(10), + I4 => sel_first, + I5 => \^m_payload_i_reg[61]_0\(37), + O => m_axi_awaddr(10) + ); +\m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACAFFC0CACACACA" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(11), + I1 => Q(11), + I2 => \m_axi_awaddr[11]_INST_0_i_1_n_0\, + I3 => \m_axi_awaddr[11]\(11), + I4 => sel_first, + I5 => \^m_payload_i_reg[61]_0\(37), + O => m_axi_awaddr(11) + ); +\m_axi_awaddr[11]_INST_0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(37), + I1 => \m_payload_i_reg_n_0_[38]\, + I2 => sel_first_0, + O => \m_axi_awaddr[11]_INST_0_i_1_n_0\ + ); +\m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACAFFC0CACACACA" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(1), + I1 => Q(1), + I2 => \m_axi_awaddr[11]_INST_0_i_1_n_0\, + I3 => \m_axi_awaddr[11]\(1), + I4 => sel_first, + I5 => \^m_payload_i_reg[61]_0\(37), + O => m_axi_awaddr(1) + ); +\m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACAFFC0CACACACA" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(2), + I1 => Q(2), + I2 => \m_axi_awaddr[11]_INST_0_i_1_n_0\, + I3 => \m_axi_awaddr[11]\(2), + I4 => sel_first, + I5 => \^m_payload_i_reg[61]_0\(37), + O => m_axi_awaddr(2) + ); +\m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACAFFC0CACACACA" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(3), + I1 => Q(3), + I2 => \m_axi_awaddr[11]_INST_0_i_1_n_0\, + I3 => \m_axi_awaddr[11]\(3), + I4 => sel_first, + I5 => \^m_payload_i_reg[61]_0\(37), + O => m_axi_awaddr(3) + ); +\m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACAFFC0CACACACA" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(4), + I1 => Q(4), + I2 => \m_axi_awaddr[11]_INST_0_i_1_n_0\, + I3 => \m_axi_awaddr[11]\(4), + I4 => sel_first, + I5 => \^m_payload_i_reg[61]_0\(37), + O => m_axi_awaddr(4) + ); +\m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACAFFC0CACACACA" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(5), + I1 => Q(5), + I2 => \m_axi_awaddr[11]_INST_0_i_1_n_0\, + I3 => \m_axi_awaddr[11]\(5), + I4 => sel_first, + I5 => \^m_payload_i_reg[61]_0\(37), + O => m_axi_awaddr(5) + ); +\m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACAFFC0CACACACA" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(6), + I1 => Q(6), + I2 => \m_axi_awaddr[11]_INST_0_i_1_n_0\, + I3 => \m_axi_awaddr[11]\(6), + I4 => sel_first, + I5 => \^m_payload_i_reg[61]_0\(37), + O => m_axi_awaddr(6) + ); +\m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACAFFC0CACACACA" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(7), + I1 => Q(7), + I2 => \m_axi_awaddr[11]_INST_0_i_1_n_0\, + I3 => \m_axi_awaddr[11]\(7), + I4 => sel_first, + I5 => \^m_payload_i_reg[61]_0\(37), + O => m_axi_awaddr(7) + ); +\m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACAFFC0CACACACA" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(8), + I1 => Q(8), + I2 => \m_axi_awaddr[11]_INST_0_i_1_n_0\, + I3 => \m_axi_awaddr[11]\(8), + I4 => sel_first, + I5 => \^m_payload_i_reg[61]_0\(37), + O => m_axi_awaddr(8) + ); +\m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACAFFC0CACACACA" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(9), + I1 => Q(9), + I2 => \m_axi_awaddr[11]_INST_0_i_1_n_0\, + I3 => \m_axi_awaddr[11]\(9), + I4 => sel_first, + I5 => \^m_payload_i_reg[61]_0\(37), + O => m_axi_awaddr(9) + ); +\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(0), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[0]\, + O => skid_buffer(0) + ); +\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(10), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[10]\, + O => skid_buffer(10) + ); +\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(11), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[11]\, + O => skid_buffer(11) + ); +\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(12), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[12]\, + O => skid_buffer(12) + ); +\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(13), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[13]\, + O => skid_buffer(13) + ); +\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(14), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[14]\, + O => skid_buffer(14) + ); +\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(15), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[15]\, + O => skid_buffer(15) + ); +\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(16), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[16]\, + O => skid_buffer(16) + ); +\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(17), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[17]\, + O => skid_buffer(17) + ); +\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(18), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[18]\, + O => skid_buffer(18) + ); +\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(19), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[19]\, + O => skid_buffer(19) + ); +\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(1), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[1]\, + O => skid_buffer(1) + ); +\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(20), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[20]\, + O => skid_buffer(20) + ); +\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(21), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[21]\, + O => skid_buffer(21) + ); +\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(22), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[22]\, + O => skid_buffer(22) + ); +\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(23), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[23]\, + O => skid_buffer(23) + ); +\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(24), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[24]\, + O => skid_buffer(24) + ); +\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(25), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[25]\, + O => skid_buffer(25) + ); +\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(26), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[26]\, + O => skid_buffer(26) + ); +\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(27), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[27]\, + O => skid_buffer(27) + ); +\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(28), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[28]\, + O => skid_buffer(28) + ); +\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(29), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[29]\, + O => skid_buffer(29) + ); +\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(2), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[2]\, + O => skid_buffer(2) + ); +\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(30), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[30]\, + O => skid_buffer(30) + ); +\m_payload_i[31]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(31), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[31]\, + O => skid_buffer(31) + ); +\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awprot(0), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[32]\, + O => skid_buffer(32) + ); +\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awprot(1), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[33]\, + O => skid_buffer(33) + ); +\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awprot(2), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[34]\, + O => skid_buffer(34) + ); +\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awsize(0), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[35]\, + O => skid_buffer(35) + ); +\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awsize(1), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[36]\, + O => skid_buffer(36) + ); +\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awburst(0), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[38]\, + O => skid_buffer(38) + ); +\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awburst(1), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[39]\, + O => skid_buffer(39) + ); +\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(3), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[3]\, + O => skid_buffer(3) + ); +\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awlen(0), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[44]\, + O => skid_buffer(44) + ); +\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awlen(1), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[45]\, + O => skid_buffer(45) + ); +\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awlen(2), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[46]\, + O => skid_buffer(46) + ); +\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awlen(3), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[47]\, + O => skid_buffer(47) + ); +\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(4), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[4]\, + O => skid_buffer(4) + ); +\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awid(0), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[50]\, + O => skid_buffer(50) + ); +\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awid(1), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[51]\, + O => skid_buffer(51) + ); +\m_payload_i[52]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awid(2), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[52]\, + O => skid_buffer(52) + ); +\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awid(3), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[53]\, + O => skid_buffer(53) + ); +\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awid(4), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[54]\, + O => skid_buffer(54) + ); +\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awid(5), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[55]\, + O => skid_buffer(55) + ); +\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awid(6), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[56]\, + O => skid_buffer(56) + ); +\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awid(7), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[57]\, + O => skid_buffer(57) + ); +\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awid(8), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[58]\, + O => skid_buffer(58) + ); +\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awid(9), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[59]\, + O => skid_buffer(59) + ); +\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(5), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[5]\, + O => skid_buffer(5) + ); +\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awid(10), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[60]\, + O => skid_buffer(60) + ); +\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awid(11), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[61]\, + O => skid_buffer(61) + ); +\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(6), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[6]\, + O => skid_buffer(6) + ); +\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(7), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[7]\, + O => skid_buffer(7) + ); +\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(8), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[8]\, + O => skid_buffer(8) + ); +\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axi_awaddr(9), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[9]\, + O => skid_buffer(9) + ); +\m_payload_i_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(0), + Q => \^m_payload_i_reg[61]_0\(0), + R => '0' + ); +\m_payload_i_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(10), + Q => \^m_payload_i_reg[61]_0\(10), + R => '0' + ); +\m_payload_i_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(11), + Q => \^m_payload_i_reg[61]_0\(11), + R => '0' + ); +\m_payload_i_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(12), + Q => \^m_payload_i_reg[61]_0\(12), + R => '0' + ); +\m_payload_i_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(13), + Q => \^m_payload_i_reg[61]_0\(13), + R => '0' + ); +\m_payload_i_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(14), + Q => \^m_payload_i_reg[61]_0\(14), + R => '0' + ); +\m_payload_i_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(15), + Q => \^m_payload_i_reg[61]_0\(15), + R => '0' + ); +\m_payload_i_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(16), + Q => \^m_payload_i_reg[61]_0\(16), + R => '0' + ); +\m_payload_i_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(17), + Q => \^m_payload_i_reg[61]_0\(17), + R => '0' + ); +\m_payload_i_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(18), + Q => \^m_payload_i_reg[61]_0\(18), + R => '0' + ); +\m_payload_i_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(19), + Q => \^m_payload_i_reg[61]_0\(19), + R => '0' + ); +\m_payload_i_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(1), + Q => \^m_payload_i_reg[61]_0\(1), + R => '0' + ); +\m_payload_i_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(20), + Q => \^m_payload_i_reg[61]_0\(20), + R => '0' + ); +\m_payload_i_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(21), + Q => \^m_payload_i_reg[61]_0\(21), + R => '0' + ); +\m_payload_i_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(22), + Q => \^m_payload_i_reg[61]_0\(22), + R => '0' + ); +\m_payload_i_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(23), + Q => \^m_payload_i_reg[61]_0\(23), + R => '0' + ); +\m_payload_i_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(24), + Q => \^m_payload_i_reg[61]_0\(24), + R => '0' + ); +\m_payload_i_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(25), + Q => \^m_payload_i_reg[61]_0\(25), + R => '0' + ); +\m_payload_i_reg[26]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(26), + Q => \^m_payload_i_reg[61]_0\(26), + R => '0' + ); +\m_payload_i_reg[27]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(27), + Q => \^m_payload_i_reg[61]_0\(27), + R => '0' + ); +\m_payload_i_reg[28]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(28), + Q => \^m_payload_i_reg[61]_0\(28), + R => '0' + ); +\m_payload_i_reg[29]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(29), + Q => \^m_payload_i_reg[61]_0\(29), + R => '0' + ); +\m_payload_i_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(2), + Q => \^m_payload_i_reg[61]_0\(2), + R => '0' + ); +\m_payload_i_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(30), + Q => \^m_payload_i_reg[61]_0\(30), + R => '0' + ); +\m_payload_i_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(31), + Q => \^m_payload_i_reg[61]_0\(31), + R => '0' + ); +\m_payload_i_reg[32]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(32), + Q => \^m_payload_i_reg[61]_0\(32), + R => '0' + ); +\m_payload_i_reg[33]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(33), + Q => \^m_payload_i_reg[61]_0\(33), + R => '0' + ); +\m_payload_i_reg[34]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(34), + Q => \^m_payload_i_reg[61]_0\(34), + R => '0' + ); +\m_payload_i_reg[35]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(35), + Q => \^m_payload_i_reg[61]_0\(35), + R => '0' + ); +\m_payload_i_reg[36]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(36), + Q => \^m_payload_i_reg[61]_0\(36), + R => '0' + ); +\m_payload_i_reg[38]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(38), + Q => \m_payload_i_reg_n_0_[38]\, + R => '0' + ); +\m_payload_i_reg[39]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(39), + Q => \^m_payload_i_reg[61]_0\(37), + R => '0' + ); +\m_payload_i_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(3), + Q => \^m_payload_i_reg[61]_0\(3), + R => '0' + ); +\m_payload_i_reg[44]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(44), + Q => \^m_payload_i_reg[61]_0\(38), + R => '0' + ); +\m_payload_i_reg[45]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(45), + Q => \^m_payload_i_reg[61]_0\(39), + R => '0' + ); +\m_payload_i_reg[46]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(46), + Q => \^m_payload_i_reg[61]_0\(40), + R => '0' + ); +\m_payload_i_reg[47]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(47), + Q => \^m_payload_i_reg[61]_0\(41), + R => '0' + ); +\m_payload_i_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(4), + Q => \^m_payload_i_reg[61]_0\(4), + R => '0' + ); +\m_payload_i_reg[50]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(50), + Q => \^m_payload_i_reg[61]_0\(42), + R => '0' + ); +\m_payload_i_reg[51]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(51), + Q => \^m_payload_i_reg[61]_0\(43), + R => '0' + ); +\m_payload_i_reg[52]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(52), + Q => \^m_payload_i_reg[61]_0\(44), + R => '0' + ); +\m_payload_i_reg[53]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(53), + Q => \^m_payload_i_reg[61]_0\(45), + R => '0' + ); +\m_payload_i_reg[54]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(54), + Q => \^m_payload_i_reg[61]_0\(46), + R => '0' + ); +\m_payload_i_reg[55]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(55), + Q => \^m_payload_i_reg[61]_0\(47), + R => '0' + ); +\m_payload_i_reg[56]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(56), + Q => \^m_payload_i_reg[61]_0\(48), + R => '0' + ); +\m_payload_i_reg[57]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(57), + Q => \^m_payload_i_reg[61]_0\(49), + R => '0' + ); +\m_payload_i_reg[58]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(58), + Q => \^m_payload_i_reg[61]_0\(50), + R => '0' + ); +\m_payload_i_reg[59]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(59), + Q => \^m_payload_i_reg[61]_0\(51), + R => '0' + ); +\m_payload_i_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(5), + Q => \^m_payload_i_reg[61]_0\(5), + R => '0' + ); +\m_payload_i_reg[60]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(60), + Q => \^m_payload_i_reg[61]_0\(52), + R => '0' + ); +\m_payload_i_reg[61]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(61), + Q => \^m_payload_i_reg[61]_0\(53), + R => '0' + ); +\m_payload_i_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(6), + Q => \^m_payload_i_reg[61]_0\(6), + R => '0' + ); +\m_payload_i_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(7), + Q => \^m_payload_i_reg[61]_0\(7), + R => '0' + ); +\m_payload_i_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(8), + Q => \^m_payload_i_reg[61]_0\(8), + R => '0' + ); +\m_payload_i_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(9), + Q => \^m_payload_i_reg[61]_0\(9), + R => '0' + ); +\m_valid_i_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F4FF" + ) + port map ( + I0 => b_push, + I1 => \^m_valid_i_reg_0\, + I2 => s_axi_awvalid, + I3 => \^s_ready_i_reg_0\, + O => m_valid_i0 + ); +m_valid_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => m_valid_i0, + Q => \^m_valid_i_reg_0\, + R => m_valid_i_reg_1 + ); +next_pending_r_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000FFFE" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(39), + I1 => \^m_payload_i_reg[61]_0\(38), + I2 => \^m_payload_i_reg[61]_0\(40), + I3 => \^m_payload_i_reg[61]_0\(41), + I4 => next_pending_r_reg, + O => \m_payload_i_reg[45]_0\ + ); +\s_ready_i_i_1__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \aresetn_d_reg_n_0_[0]\, + O => \^aresetn_d_reg[0]_0\ + ); +s_ready_i_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"BFBB" + ) + port map ( + I0 => b_push, + I1 => \^m_valid_i_reg_0\, + I2 => s_axi_awvalid, + I3 => \^s_ready_i_reg_0\, + O => s_ready_i0 + ); +s_ready_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_ready_i0, + Q => \^s_ready_i_reg_0\, + R => \^aresetn_d_reg[0]_0\ + ); +\skid_buffer_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(0), + Q => \skid_buffer_reg_n_0_[0]\, + R => '0' + ); +\skid_buffer_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(10), + Q => \skid_buffer_reg_n_0_[10]\, + R => '0' + ); +\skid_buffer_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(11), + Q => \skid_buffer_reg_n_0_[11]\, + R => '0' + ); +\skid_buffer_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(12), + Q => \skid_buffer_reg_n_0_[12]\, + R => '0' + ); +\skid_buffer_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(13), + Q => \skid_buffer_reg_n_0_[13]\, + R => '0' + ); +\skid_buffer_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(14), + Q => \skid_buffer_reg_n_0_[14]\, + R => '0' + ); +\skid_buffer_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(15), + Q => \skid_buffer_reg_n_0_[15]\, + R => '0' + ); +\skid_buffer_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(16), + Q => \skid_buffer_reg_n_0_[16]\, + R => '0' + ); +\skid_buffer_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(17), + Q => \skid_buffer_reg_n_0_[17]\, + R => '0' + ); +\skid_buffer_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(18), + Q => \skid_buffer_reg_n_0_[18]\, + R => '0' + ); +\skid_buffer_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(19), + Q => \skid_buffer_reg_n_0_[19]\, + R => '0' + ); +\skid_buffer_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(1), + Q => \skid_buffer_reg_n_0_[1]\, + R => '0' + ); +\skid_buffer_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(20), + Q => \skid_buffer_reg_n_0_[20]\, + R => '0' + ); +\skid_buffer_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(21), + Q => \skid_buffer_reg_n_0_[21]\, + R => '0' + ); +\skid_buffer_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(22), + Q => \skid_buffer_reg_n_0_[22]\, + R => '0' + ); +\skid_buffer_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(23), + Q => \skid_buffer_reg_n_0_[23]\, + R => '0' + ); +\skid_buffer_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(24), + Q => \skid_buffer_reg_n_0_[24]\, + R => '0' + ); +\skid_buffer_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(25), + Q => \skid_buffer_reg_n_0_[25]\, + R => '0' + ); +\skid_buffer_reg[26]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(26), + Q => \skid_buffer_reg_n_0_[26]\, + R => '0' + ); +\skid_buffer_reg[27]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(27), + Q => \skid_buffer_reg_n_0_[27]\, + R => '0' + ); +\skid_buffer_reg[28]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(28), + Q => \skid_buffer_reg_n_0_[28]\, + R => '0' + ); +\skid_buffer_reg[29]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(29), + Q => \skid_buffer_reg_n_0_[29]\, + R => '0' + ); +\skid_buffer_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(2), + Q => \skid_buffer_reg_n_0_[2]\, + R => '0' + ); +\skid_buffer_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(30), + Q => \skid_buffer_reg_n_0_[30]\, + R => '0' + ); +\skid_buffer_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(31), + Q => \skid_buffer_reg_n_0_[31]\, + R => '0' + ); +\skid_buffer_reg[32]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awprot(0), + Q => \skid_buffer_reg_n_0_[32]\, + R => '0' + ); +\skid_buffer_reg[33]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awprot(1), + Q => \skid_buffer_reg_n_0_[33]\, + R => '0' + ); +\skid_buffer_reg[34]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awprot(2), + Q => \skid_buffer_reg_n_0_[34]\, + R => '0' + ); +\skid_buffer_reg[35]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awsize(0), + Q => \skid_buffer_reg_n_0_[35]\, + R => '0' + ); +\skid_buffer_reg[36]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awsize(1), + Q => \skid_buffer_reg_n_0_[36]\, + R => '0' + ); +\skid_buffer_reg[38]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awburst(0), + Q => \skid_buffer_reg_n_0_[38]\, + R => '0' + ); +\skid_buffer_reg[39]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awburst(1), + Q => \skid_buffer_reg_n_0_[39]\, + R => '0' + ); +\skid_buffer_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(3), + Q => \skid_buffer_reg_n_0_[3]\, + R => '0' + ); +\skid_buffer_reg[44]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awlen(0), + Q => \skid_buffer_reg_n_0_[44]\, + R => '0' + ); +\skid_buffer_reg[45]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awlen(1), + Q => \skid_buffer_reg_n_0_[45]\, + R => '0' + ); +\skid_buffer_reg[46]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awlen(2), + Q => \skid_buffer_reg_n_0_[46]\, + R => '0' + ); +\skid_buffer_reg[47]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awlen(3), + Q => \skid_buffer_reg_n_0_[47]\, + R => '0' + ); +\skid_buffer_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(4), + Q => \skid_buffer_reg_n_0_[4]\, + R => '0' + ); +\skid_buffer_reg[50]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awid(0), + Q => \skid_buffer_reg_n_0_[50]\, + R => '0' + ); +\skid_buffer_reg[51]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awid(1), + Q => \skid_buffer_reg_n_0_[51]\, + R => '0' + ); +\skid_buffer_reg[52]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awid(2), + Q => \skid_buffer_reg_n_0_[52]\, + R => '0' + ); +\skid_buffer_reg[53]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awid(3), + Q => \skid_buffer_reg_n_0_[53]\, + R => '0' + ); +\skid_buffer_reg[54]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awid(4), + Q => \skid_buffer_reg_n_0_[54]\, + R => '0' + ); +\skid_buffer_reg[55]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awid(5), + Q => \skid_buffer_reg_n_0_[55]\, + R => '0' + ); +\skid_buffer_reg[56]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awid(6), + Q => \skid_buffer_reg_n_0_[56]\, + R => '0' + ); +\skid_buffer_reg[57]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awid(7), + Q => \skid_buffer_reg_n_0_[57]\, + R => '0' + ); +\skid_buffer_reg[58]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awid(8), + Q => \skid_buffer_reg_n_0_[58]\, + R => '0' + ); +\skid_buffer_reg[59]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awid(9), + Q => \skid_buffer_reg_n_0_[59]\, + R => '0' + ); +\skid_buffer_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(5), + Q => \skid_buffer_reg_n_0_[5]\, + R => '0' + ); +\skid_buffer_reg[60]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awid(10), + Q => \skid_buffer_reg_n_0_[60]\, + R => '0' + ); +\skid_buffer_reg[61]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awid(11), + Q => \skid_buffer_reg_n_0_[61]\, + R => '0' + ); +\skid_buffer_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(6), + Q => \skid_buffer_reg_n_0_[6]\, + R => '0' + ); +\skid_buffer_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(7), + Q => \skid_buffer_reg_n_0_[7]\, + R => '0' + ); +\skid_buffer_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(8), + Q => \skid_buffer_reg_n_0_[8]\, + R => '0' + ); +\skid_buffer_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => s_axi_awaddr(9), + Q => \skid_buffer_reg_n_0_[9]\, + R => '0' + ); +\wrap_boundary_axaddr_r[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"A8AA" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(0), + I1 => \^m_payload_i_reg[61]_0\(36), + I2 => \^m_payload_i_reg[61]_0\(35), + I3 => \^m_payload_i_reg[61]_0\(38), + O => D(0) + ); +\wrap_boundary_axaddr_r[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"DDCF0000" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(38), + I1 => \^m_payload_i_reg[61]_0\(36), + I2 => \^m_payload_i_reg[61]_0\(39), + I3 => \^m_payload_i_reg[61]_0\(35), + I4 => \^m_payload_i_reg[61]_0\(1), + O => D(1) + ); +\wrap_boundary_axaddr_r[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"A0A0202AAAAA202A" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(2), + I1 => \^m_payload_i_reg[61]_0\(38), + I2 => \^m_payload_i_reg[61]_0\(36), + I3 => \^m_payload_i_reg[61]_0\(40), + I4 => \^m_payload_i_reg[61]_0\(35), + I5 => \^m_payload_i_reg[61]_0\(39), + O => D(2) + ); +\wrap_boundary_axaddr_r[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF008020A0" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(3), + I1 => \^m_payload_i_reg[61]_0\(36), + I2 => \^m_payload_i_reg[61]_0\(35), + I3 => \^m_payload_i_reg[61]_0\(38), + I4 => \^m_payload_i_reg[61]_0\(40), + I5 => \wrap_boundary_axaddr_r[3]_i_2_n_0\, + O => D(3) + ); +\wrap_boundary_axaddr_r[3]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00300050" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(41), + I1 => \^m_payload_i_reg[61]_0\(39), + I2 => \^m_payload_i_reg[61]_0\(3), + I3 => \^m_payload_i_reg[61]_0\(35), + I4 => \^m_payload_i_reg[61]_0\(36), + O => \wrap_boundary_axaddr_r[3]_i_2_n_0\ + ); +\wrap_boundary_axaddr_r[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000A22AAAA0A22AA" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(4), + I1 => \^m_payload_i_reg[61]_0\(40), + I2 => \^m_payload_i_reg[61]_0\(41), + I3 => \^m_payload_i_reg[61]_0\(36), + I4 => \^m_payload_i_reg[61]_0\(35), + I5 => \^m_payload_i_reg[61]_0\(39), + O => D(4) + ); +\wrap_boundary_axaddr_r[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"737F0000" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(40), + I1 => \^m_payload_i_reg[61]_0\(36), + I2 => \^m_payload_i_reg[61]_0\(35), + I3 => \^m_payload_i_reg[61]_0\(41), + I4 => \^m_payload_i_reg[61]_0\(5), + O => D(5) + ); +\wrap_boundary_axaddr_r[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2AAA" + ) + port map ( + I0 => \^m_payload_i_reg[61]_0\(6), + I1 => \^m_payload_i_reg[61]_0\(41), + I2 => \^m_payload_i_reg[61]_0\(36), + I3 => \^m_payload_i_reg[61]_0\(35), + O => D(6) + ); +\wrap_second_len_r[3]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00002000" + ) + port map ( + I0 => \wrap_second_len_r_reg[3]\(0), + I1 => \wrap_second_len_r_reg[3]\(1), + I2 => \^m_valid_i_reg_0\, + I3 => \^m_payload_i_reg[61]_0\(41), + I4 => \^m_payload_i_reg[5]_0\, + O => \FSM_sequential_state_reg[0]\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axic_register_slice__parameterized1\ is + port ( + m_valid_i_reg_0 : out STD_LOGIC; + s_ready_i_reg_0 : out STD_LOGIC; + shandshake : out STD_LOGIC; + \m_payload_i_reg[13]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 ); + m_valid_i_reg_1 : in STD_LOGIC; + aclk : in STD_LOGIC; + s_ready_i_reg_1 : in STD_LOGIC; + si_rs_bvalid : in STD_LOGIC; + s_axi_bready : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \skid_buffer_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_29_axic_register_slice"; +end \NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axic_register_slice__parameterized1\; + +architecture STRUCTURE of \NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axic_register_slice__parameterized1\ is + signal \m_payload_i[0]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[10]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[11]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[12]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC; + signal \m_payload_i[1]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[2]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[4]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[5]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[6]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[7]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[8]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[9]_i_1__1_n_0\ : STD_LOGIC; + signal m_valid_i0 : STD_LOGIC; + signal \^m_valid_i_reg_0\ : STD_LOGIC; + signal p_1_in : STD_LOGIC; + signal s_ready_i0 : STD_LOGIC; + signal \^s_ready_i_reg_0\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__1\ : label is "soft_lutpair83"; + attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair78"; + attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair78"; + attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair77"; + attribute SOFT_HLUTNM of \m_payload_i[13]_i_2\ : label is "soft_lutpair77"; + attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair83"; + attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair82"; + attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair82"; + attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair81"; + attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair81"; + attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair80"; + attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair80"; + attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair79"; + attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair79"; + attribute SOFT_HLUTNM of s_ready_i_i_1 : label is "soft_lutpair76"; + attribute SOFT_HLUTNM of shandshake_r_i_1 : label is "soft_lutpair76"; +begin + m_valid_i_reg_0 <= \^m_valid_i_reg_0\; + s_ready_i_reg_0 <= \^s_ready_i_reg_0\; +\m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[1]_0\(0), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[0]\, + O => \m_payload_i[0]_i_1__1_n_0\ + ); +\m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \out\(8), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[10]\, + O => \m_payload_i[10]_i_1__1_n_0\ + ); +\m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \out\(9), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[11]\, + O => \m_payload_i[11]_i_1__1_n_0\ + ); +\m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \out\(10), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[12]\, + O => \m_payload_i[12]_i_1__1_n_0\ + ); +\m_payload_i[13]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => s_axi_bready, + I1 => \^m_valid_i_reg_0\, + O => p_1_in + ); +\m_payload_i[13]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \out\(11), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[13]\, + O => \m_payload_i[13]_i_2_n_0\ + ); +\m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[1]_0\(1), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[1]\, + O => \m_payload_i[1]_i_1__1_n_0\ + ); +\m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \out\(0), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[2]\, + O => \m_payload_i[2]_i_1__1_n_0\ + ); +\m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \out\(1), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[3]\, + O => \m_payload_i[3]_i_1__1_n_0\ + ); +\m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \out\(2), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[4]\, + O => \m_payload_i[4]_i_1__1_n_0\ + ); +\m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \out\(3), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[5]\, + O => \m_payload_i[5]_i_1__1_n_0\ + ); +\m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \out\(4), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[6]\, + O => \m_payload_i[6]_i_1__1_n_0\ + ); +\m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \out\(5), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[7]\, + O => \m_payload_i[7]_i_1__1_n_0\ + ); +\m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \out\(6), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[8]\, + O => \m_payload_i[8]_i_1__1_n_0\ + ); +\m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \out\(7), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[9]\, + O => \m_payload_i[9]_i_1__1_n_0\ + ); +\m_payload_i_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[0]_i_1__1_n_0\, + Q => \m_payload_i_reg[13]_0\(0), + R => '0' + ); +\m_payload_i_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[10]_i_1__1_n_0\, + Q => \m_payload_i_reg[13]_0\(10), + R => '0' + ); +\m_payload_i_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[11]_i_1__1_n_0\, + Q => \m_payload_i_reg[13]_0\(11), + R => '0' + ); +\m_payload_i_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[12]_i_1__1_n_0\, + Q => \m_payload_i_reg[13]_0\(12), + R => '0' + ); +\m_payload_i_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[13]_i_2_n_0\, + Q => \m_payload_i_reg[13]_0\(13), + R => '0' + ); +\m_payload_i_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[1]_i_1__1_n_0\, + Q => \m_payload_i_reg[13]_0\(1), + R => '0' + ); +\m_payload_i_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[2]_i_1__1_n_0\, + Q => \m_payload_i_reg[13]_0\(2), + R => '0' + ); +\m_payload_i_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[3]_i_1__1_n_0\, + Q => \m_payload_i_reg[13]_0\(3), + R => '0' + ); +\m_payload_i_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[4]_i_1__1_n_0\, + Q => \m_payload_i_reg[13]_0\(4), + R => '0' + ); +\m_payload_i_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[5]_i_1__1_n_0\, + Q => \m_payload_i_reg[13]_0\(5), + R => '0' + ); +\m_payload_i_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[6]_i_1__1_n_0\, + Q => \m_payload_i_reg[13]_0\(6), + R => '0' + ); +\m_payload_i_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[7]_i_1__1_n_0\, + Q => \m_payload_i_reg[13]_0\(7), + R => '0' + ); +\m_payload_i_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[8]_i_1__1_n_0\, + Q => \m_payload_i_reg[13]_0\(8), + R => '0' + ); +\m_payload_i_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[9]_i_1__1_n_0\, + Q => \m_payload_i_reg[13]_0\(9), + R => '0' + ); +m_valid_i_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"F4FF" + ) + port map ( + I0 => s_axi_bready, + I1 => \^m_valid_i_reg_0\, + I2 => si_rs_bvalid, + I3 => \^s_ready_i_reg_0\, + O => m_valid_i0 + ); +m_valid_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => m_valid_i0, + Q => \^m_valid_i_reg_0\, + R => m_valid_i_reg_1 + ); +s_ready_i_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"F4FF" + ) + port map ( + I0 => si_rs_bvalid, + I1 => \^s_ready_i_reg_0\, + I2 => s_axi_bready, + I3 => \^m_valid_i_reg_0\, + O => s_ready_i0 + ); +s_ready_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_ready_i0, + Q => \^s_ready_i_reg_0\, + R => s_ready_i_reg_1 + ); +shandshake_r_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_ready_i_reg_0\, + I1 => si_rs_bvalid, + O => shandshake + ); +\skid_buffer_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[1]_0\(0), + Q => \skid_buffer_reg_n_0_[0]\, + R => '0' + ); +\skid_buffer_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \out\(8), + Q => \skid_buffer_reg_n_0_[10]\, + R => '0' + ); +\skid_buffer_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \out\(9), + Q => \skid_buffer_reg_n_0_[11]\, + R => '0' + ); +\skid_buffer_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \out\(10), + Q => \skid_buffer_reg_n_0_[12]\, + R => '0' + ); +\skid_buffer_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \out\(11), + Q => \skid_buffer_reg_n_0_[13]\, + R => '0' + ); +\skid_buffer_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[1]_0\(1), + Q => \skid_buffer_reg_n_0_[1]\, + R => '0' + ); +\skid_buffer_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \out\(0), + Q => \skid_buffer_reg_n_0_[2]\, + R => '0' + ); +\skid_buffer_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \out\(1), + Q => \skid_buffer_reg_n_0_[3]\, + R => '0' + ); +\skid_buffer_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \out\(2), + Q => \skid_buffer_reg_n_0_[4]\, + R => '0' + ); +\skid_buffer_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \out\(3), + Q => \skid_buffer_reg_n_0_[5]\, + R => '0' + ); +\skid_buffer_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \out\(4), + Q => \skid_buffer_reg_n_0_[6]\, + R => '0' + ); +\skid_buffer_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \out\(5), + Q => \skid_buffer_reg_n_0_[7]\, + R => '0' + ); +\skid_buffer_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \out\(6), + Q => \skid_buffer_reg_n_0_[8]\, + R => '0' + ); +\skid_buffer_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \out\(7), + Q => \skid_buffer_reg_n_0_[9]\, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axic_register_slice__parameterized2\ is + port ( + m_valid_i_reg_0 : out STD_LOGIC; + s_ready_i_reg_0 : out STD_LOGIC; + s_ready_i_reg_1 : out STD_LOGIC; + \m_payload_i_reg[46]_0\ : out STD_LOGIC_VECTOR ( 46 downto 0 ); + m_valid_i_reg_1 : in STD_LOGIC; + aclk : in STD_LOGIC; + s_ready_i_reg_2 : in STD_LOGIC; + m_valid_i_reg_2 : in STD_LOGIC; + s_axi_rready : in STD_LOGIC; + \skid_buffer_reg[46]_0\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + \skid_buffer_reg[33]_0\ : in STD_LOGIC_VECTOR ( 33 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_29_axic_register_slice"; +end \NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axic_register_slice__parameterized2\; + +architecture STRUCTURE of \NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axic_register_slice__parameterized2\ is + signal \m_payload_i[0]_i_1__2_n_0\ : STD_LOGIC; + signal \m_payload_i[10]_i_1__2_n_0\ : STD_LOGIC; + signal \m_payload_i[11]_i_1__2_n_0\ : STD_LOGIC; + signal \m_payload_i[12]_i_1__2_n_0\ : STD_LOGIC; + signal \m_payload_i[13]_i_1__2_n_0\ : STD_LOGIC; + signal \m_payload_i[14]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[15]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[16]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[17]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[18]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[19]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[1]_i_1__2_n_0\ : STD_LOGIC; + signal \m_payload_i[20]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[21]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[22]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[23]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[24]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[25]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[26]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[27]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[28]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[29]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[2]_i_1__2_n_0\ : STD_LOGIC; + signal \m_payload_i[30]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[31]_i_1__0_n_0\ : STD_LOGIC; + signal \m_payload_i[32]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[33]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[34]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[35]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[36]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[37]_i_1_n_0\ : STD_LOGIC; + signal \m_payload_i[38]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[39]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[3]_i_1__2_n_0\ : STD_LOGIC; + signal \m_payload_i[40]_i_1_n_0\ : STD_LOGIC; + signal \m_payload_i[41]_i_1_n_0\ : STD_LOGIC; + signal \m_payload_i[42]_i_1_n_0\ : STD_LOGIC; + signal \m_payload_i[43]_i_1_n_0\ : STD_LOGIC; + signal \m_payload_i[44]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[45]_i_1__1_n_0\ : STD_LOGIC; + signal \m_payload_i[46]_i_2_n_0\ : STD_LOGIC; + signal \m_payload_i[4]_i_1__2_n_0\ : STD_LOGIC; + signal \m_payload_i[5]_i_1__2_n_0\ : STD_LOGIC; + signal \m_payload_i[6]_i_1__2_n_0\ : STD_LOGIC; + signal \m_payload_i[7]_i_1__2_n_0\ : STD_LOGIC; + signal \m_payload_i[8]_i_1__2_n_0\ : STD_LOGIC; + signal \m_payload_i[9]_i_1__2_n_0\ : STD_LOGIC; + signal \m_valid_i_i_1__1_n_0\ : STD_LOGIC; + signal \^m_valid_i_reg_0\ : STD_LOGIC; + signal p_1_in : STD_LOGIC; + signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC; + signal \^s_ready_i_reg_0\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \cnt_read[4]_i_3__0\ : label is "soft_lutpair84"; + attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair103"; + attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair102"; + attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair102"; + attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair101"; + attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair101"; + attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair100"; + attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair100"; + attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair99"; + attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair99"; + attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair98"; + attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair107"; + attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair98"; + attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair97"; + attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair97"; + attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair96"; + attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair96"; + attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair95"; + attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair95"; + attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair94"; + attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair94"; + attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair93"; + attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair107"; + attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair93"; + attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair92"; + attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair92"; + attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair91"; + attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair91"; + attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair90"; + attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair90"; + attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair89"; + attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair89"; + attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair88"; + attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair106"; + attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair88"; + attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair87"; + attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair87"; + attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair86"; + attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair86"; + attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair85"; + attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair85"; + attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair106"; + attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair105"; + attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair105"; + attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair104"; + attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair104"; + attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair103"; + attribute SOFT_HLUTNM of \s_ready_i_i_1__2\ : label is "soft_lutpair84"; +begin + m_valid_i_reg_0 <= \^m_valid_i_reg_0\; + s_ready_i_reg_0 <= \^s_ready_i_reg_0\; +\cnt_read[4]_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^s_ready_i_reg_0\, + I1 => m_valid_i_reg_2, + O => s_ready_i_reg_1 + ); +\m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(0), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[0]\, + O => \m_payload_i[0]_i_1__2_n_0\ + ); +\m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(10), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[10]\, + O => \m_payload_i[10]_i_1__2_n_0\ + ); +\m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(11), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[11]\, + O => \m_payload_i[11]_i_1__2_n_0\ + ); +\m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(12), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[12]\, + O => \m_payload_i[12]_i_1__2_n_0\ + ); +\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(13), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[13]\, + O => \m_payload_i[13]_i_1__2_n_0\ + ); +\m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(14), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[14]\, + O => \m_payload_i[14]_i_1__1_n_0\ + ); +\m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(15), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[15]\, + O => \m_payload_i[15]_i_1__1_n_0\ + ); +\m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(16), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[16]\, + O => \m_payload_i[16]_i_1__1_n_0\ + ); +\m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(17), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[17]\, + O => \m_payload_i[17]_i_1__1_n_0\ + ); +\m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(18), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[18]\, + O => \m_payload_i[18]_i_1__1_n_0\ + ); +\m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(19), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[19]\, + O => \m_payload_i[19]_i_1__1_n_0\ + ); +\m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(1), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[1]\, + O => \m_payload_i[1]_i_1__2_n_0\ + ); +\m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(20), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[20]\, + O => \m_payload_i[20]_i_1__1_n_0\ + ); +\m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(21), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[21]\, + O => \m_payload_i[21]_i_1__1_n_0\ + ); +\m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(22), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[22]\, + O => \m_payload_i[22]_i_1__1_n_0\ + ); +\m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(23), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[23]\, + O => \m_payload_i[23]_i_1__1_n_0\ + ); +\m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(24), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[24]\, + O => \m_payload_i[24]_i_1__1_n_0\ + ); +\m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(25), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[25]\, + O => \m_payload_i[25]_i_1__1_n_0\ + ); +\m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(26), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[26]\, + O => \m_payload_i[26]_i_1__1_n_0\ + ); +\m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(27), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[27]\, + O => \m_payload_i[27]_i_1__1_n_0\ + ); +\m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(28), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[28]\, + O => \m_payload_i[28]_i_1__1_n_0\ + ); +\m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(29), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[29]\, + O => \m_payload_i[29]_i_1__1_n_0\ + ); +\m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(2), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[2]\, + O => \m_payload_i[2]_i_1__2_n_0\ + ); +\m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(30), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[30]\, + O => \m_payload_i[30]_i_1__1_n_0\ + ); +\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(31), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[31]\, + O => \m_payload_i[31]_i_1__0_n_0\ + ); +\m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(32), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[32]\, + O => \m_payload_i[32]_i_1__1_n_0\ + ); +\m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(33), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[33]\, + O => \m_payload_i[33]_i_1__1_n_0\ + ); +\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[46]_0\(0), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[34]\, + O => \m_payload_i[34]_i_1__1_n_0\ + ); +\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[46]_0\(1), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[35]\, + O => \m_payload_i[35]_i_1__1_n_0\ + ); +\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[46]_0\(2), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[36]\, + O => \m_payload_i[36]_i_1__1_n_0\ + ); +\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[46]_0\(3), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[37]\, + O => \m_payload_i[37]_i_1_n_0\ + ); +\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[46]_0\(4), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[38]\, + O => \m_payload_i[38]_i_1__1_n_0\ + ); +\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[46]_0\(5), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[39]\, + O => \m_payload_i[39]_i_1__1_n_0\ + ); +\m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(3), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[3]\, + O => \m_payload_i[3]_i_1__2_n_0\ + ); +\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[46]_0\(6), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[40]\, + O => \m_payload_i[40]_i_1_n_0\ + ); +\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[46]_0\(7), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[41]\, + O => \m_payload_i[41]_i_1_n_0\ + ); +\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[46]_0\(8), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[42]\, + O => \m_payload_i[42]_i_1_n_0\ + ); +\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[46]_0\(9), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[43]\, + O => \m_payload_i[43]_i_1_n_0\ + ); +\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[46]_0\(10), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[44]\, + O => \m_payload_i[44]_i_1__1_n_0\ + ); +\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[46]_0\(11), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[45]\, + O => \m_payload_i[45]_i_1__1_n_0\ + ); +\m_payload_i[46]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => s_axi_rready, + I1 => \^m_valid_i_reg_0\, + O => p_1_in + ); +\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[46]_0\(12), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[46]\, + O => \m_payload_i[46]_i_2_n_0\ + ); +\m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(4), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[4]\, + O => \m_payload_i[4]_i_1__2_n_0\ + ); +\m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(5), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[5]\, + O => \m_payload_i[5]_i_1__2_n_0\ + ); +\m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(6), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[6]\, + O => \m_payload_i[6]_i_1__2_n_0\ + ); +\m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(7), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[7]\, + O => \m_payload_i[7]_i_1__2_n_0\ + ); +\m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(8), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[8]\, + O => \m_payload_i[8]_i_1__2_n_0\ + ); +\m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer_reg[33]_0\(9), + I1 => \^s_ready_i_reg_0\, + I2 => \skid_buffer_reg_n_0_[9]\, + O => \m_payload_i[9]_i_1__2_n_0\ + ); +\m_payload_i_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[0]_i_1__2_n_0\, + Q => \m_payload_i_reg[46]_0\(0), + R => '0' + ); +\m_payload_i_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[10]_i_1__2_n_0\, + Q => \m_payload_i_reg[46]_0\(10), + R => '0' + ); +\m_payload_i_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[11]_i_1__2_n_0\, + Q => \m_payload_i_reg[46]_0\(11), + R => '0' + ); +\m_payload_i_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[12]_i_1__2_n_0\, + Q => \m_payload_i_reg[46]_0\(12), + R => '0' + ); +\m_payload_i_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[13]_i_1__2_n_0\, + Q => \m_payload_i_reg[46]_0\(13), + R => '0' + ); +\m_payload_i_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[14]_i_1__1_n_0\, + Q => \m_payload_i_reg[46]_0\(14), + R => '0' + ); +\m_payload_i_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[15]_i_1__1_n_0\, + Q => \m_payload_i_reg[46]_0\(15), + R => '0' + ); +\m_payload_i_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[16]_i_1__1_n_0\, + Q => \m_payload_i_reg[46]_0\(16), + R => '0' + ); +\m_payload_i_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[17]_i_1__1_n_0\, + Q => \m_payload_i_reg[46]_0\(17), + R => '0' + ); +\m_payload_i_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[18]_i_1__1_n_0\, + Q => \m_payload_i_reg[46]_0\(18), + R => '0' + ); +\m_payload_i_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[19]_i_1__1_n_0\, + Q => \m_payload_i_reg[46]_0\(19), + R => '0' + ); +\m_payload_i_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[1]_i_1__2_n_0\, + Q => \m_payload_i_reg[46]_0\(1), + R => '0' + ); +\m_payload_i_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[20]_i_1__1_n_0\, + Q => \m_payload_i_reg[46]_0\(20), + R => '0' + ); +\m_payload_i_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[21]_i_1__1_n_0\, + Q => \m_payload_i_reg[46]_0\(21), + R => '0' + ); +\m_payload_i_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[22]_i_1__1_n_0\, + Q => \m_payload_i_reg[46]_0\(22), + R => '0' + ); +\m_payload_i_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[23]_i_1__1_n_0\, + Q => \m_payload_i_reg[46]_0\(23), + R => '0' + ); +\m_payload_i_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[24]_i_1__1_n_0\, + Q => \m_payload_i_reg[46]_0\(24), + R => '0' + ); +\m_payload_i_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[25]_i_1__1_n_0\, + Q => \m_payload_i_reg[46]_0\(25), + R => '0' + ); +\m_payload_i_reg[26]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[26]_i_1__1_n_0\, + Q => \m_payload_i_reg[46]_0\(26), + R => '0' + ); +\m_payload_i_reg[27]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[27]_i_1__1_n_0\, + Q => \m_payload_i_reg[46]_0\(27), + R => '0' + ); +\m_payload_i_reg[28]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[28]_i_1__1_n_0\, + Q => \m_payload_i_reg[46]_0\(28), + R => '0' + ); +\m_payload_i_reg[29]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[29]_i_1__1_n_0\, + Q => \m_payload_i_reg[46]_0\(29), + R => '0' + ); +\m_payload_i_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[2]_i_1__2_n_0\, + Q => \m_payload_i_reg[46]_0\(2), + R => '0' + ); +\m_payload_i_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[30]_i_1__1_n_0\, + Q => \m_payload_i_reg[46]_0\(30), + R => '0' + ); +\m_payload_i_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[31]_i_1__0_n_0\, + Q => \m_payload_i_reg[46]_0\(31), + R => '0' + ); +\m_payload_i_reg[32]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[32]_i_1__1_n_0\, + Q => \m_payload_i_reg[46]_0\(32), + R => '0' + ); +\m_payload_i_reg[33]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[33]_i_1__1_n_0\, + Q => \m_payload_i_reg[46]_0\(33), + R => '0' + ); +\m_payload_i_reg[34]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[34]_i_1__1_n_0\, + Q => \m_payload_i_reg[46]_0\(34), + R => '0' + ); +\m_payload_i_reg[35]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[35]_i_1__1_n_0\, + Q => \m_payload_i_reg[46]_0\(35), + R => '0' + ); +\m_payload_i_reg[36]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[36]_i_1__1_n_0\, + Q => \m_payload_i_reg[46]_0\(36), + R => '0' + ); +\m_payload_i_reg[37]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[37]_i_1_n_0\, + Q => \m_payload_i_reg[46]_0\(37), + R => '0' + ); +\m_payload_i_reg[38]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[38]_i_1__1_n_0\, + Q => \m_payload_i_reg[46]_0\(38), + R => '0' + ); +\m_payload_i_reg[39]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[39]_i_1__1_n_0\, + Q => \m_payload_i_reg[46]_0\(39), + R => '0' + ); +\m_payload_i_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[3]_i_1__2_n_0\, + Q => \m_payload_i_reg[46]_0\(3), + R => '0' + ); +\m_payload_i_reg[40]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[40]_i_1_n_0\, + Q => \m_payload_i_reg[46]_0\(40), + R => '0' + ); +\m_payload_i_reg[41]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[41]_i_1_n_0\, + Q => \m_payload_i_reg[46]_0\(41), + R => '0' + ); +\m_payload_i_reg[42]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[42]_i_1_n_0\, + Q => \m_payload_i_reg[46]_0\(42), + R => '0' + ); +\m_payload_i_reg[43]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[43]_i_1_n_0\, + Q => \m_payload_i_reg[46]_0\(43), + R => '0' + ); +\m_payload_i_reg[44]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[44]_i_1__1_n_0\, + Q => \m_payload_i_reg[46]_0\(44), + R => '0' + ); +\m_payload_i_reg[45]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[45]_i_1__1_n_0\, + Q => \m_payload_i_reg[46]_0\(45), + R => '0' + ); +\m_payload_i_reg[46]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[46]_i_2_n_0\, + Q => \m_payload_i_reg[46]_0\(46), + R => '0' + ); +\m_payload_i_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[4]_i_1__2_n_0\, + Q => \m_payload_i_reg[46]_0\(4), + R => '0' + ); +\m_payload_i_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[5]_i_1__2_n_0\, + Q => \m_payload_i_reg[46]_0\(5), + R => '0' + ); +\m_payload_i_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[6]_i_1__2_n_0\, + Q => \m_payload_i_reg[46]_0\(6), + R => '0' + ); +\m_payload_i_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[7]_i_1__2_n_0\, + Q => \m_payload_i_reg[46]_0\(7), + R => '0' + ); +\m_payload_i_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[8]_i_1__2_n_0\, + Q => \m_payload_i_reg[46]_0\(8), + R => '0' + ); +\m_payload_i_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \m_payload_i[9]_i_1__2_n_0\, + Q => \m_payload_i_reg[46]_0\(9), + R => '0' + ); +\m_valid_i_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4FFF" + ) + port map ( + I0 => s_axi_rready, + I1 => \^m_valid_i_reg_0\, + I2 => m_valid_i_reg_2, + I3 => \^s_ready_i_reg_0\, + O => \m_valid_i_i_1__1_n_0\ + ); +m_valid_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \m_valid_i_i_1__1_n_0\, + Q => \^m_valid_i_reg_0\, + R => m_valid_i_reg_1 + ); +\s_ready_i_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F8FF" + ) + port map ( + I0 => m_valid_i_reg_2, + I1 => \^s_ready_i_reg_0\, + I2 => s_axi_rready, + I3 => \^m_valid_i_reg_0\, + O => \s_ready_i_i_1__2_n_0\ + ); +s_ready_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \s_ready_i_i_1__2_n_0\, + Q => \^s_ready_i_reg_0\, + R => s_ready_i_reg_2 + ); +\skid_buffer_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(0), + Q => \skid_buffer_reg_n_0_[0]\, + R => '0' + ); +\skid_buffer_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(10), + Q => \skid_buffer_reg_n_0_[10]\, + R => '0' + ); +\skid_buffer_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(11), + Q => \skid_buffer_reg_n_0_[11]\, + R => '0' + ); +\skid_buffer_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(12), + Q => \skid_buffer_reg_n_0_[12]\, + R => '0' + ); +\skid_buffer_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(13), + Q => \skid_buffer_reg_n_0_[13]\, + R => '0' + ); +\skid_buffer_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(14), + Q => \skid_buffer_reg_n_0_[14]\, + R => '0' + ); +\skid_buffer_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(15), + Q => \skid_buffer_reg_n_0_[15]\, + R => '0' + ); +\skid_buffer_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(16), + Q => \skid_buffer_reg_n_0_[16]\, + R => '0' + ); +\skid_buffer_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(17), + Q => \skid_buffer_reg_n_0_[17]\, + R => '0' + ); +\skid_buffer_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(18), + Q => \skid_buffer_reg_n_0_[18]\, + R => '0' + ); +\skid_buffer_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(19), + Q => \skid_buffer_reg_n_0_[19]\, + R => '0' + ); +\skid_buffer_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(1), + Q => \skid_buffer_reg_n_0_[1]\, + R => '0' + ); +\skid_buffer_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(20), + Q => \skid_buffer_reg_n_0_[20]\, + R => '0' + ); +\skid_buffer_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(21), + Q => \skid_buffer_reg_n_0_[21]\, + R => '0' + ); +\skid_buffer_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(22), + Q => \skid_buffer_reg_n_0_[22]\, + R => '0' + ); +\skid_buffer_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(23), + Q => \skid_buffer_reg_n_0_[23]\, + R => '0' + ); +\skid_buffer_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(24), + Q => \skid_buffer_reg_n_0_[24]\, + R => '0' + ); +\skid_buffer_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(25), + Q => \skid_buffer_reg_n_0_[25]\, + R => '0' + ); +\skid_buffer_reg[26]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(26), + Q => \skid_buffer_reg_n_0_[26]\, + R => '0' + ); +\skid_buffer_reg[27]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(27), + Q => \skid_buffer_reg_n_0_[27]\, + R => '0' + ); +\skid_buffer_reg[28]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(28), + Q => \skid_buffer_reg_n_0_[28]\, + R => '0' + ); +\skid_buffer_reg[29]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(29), + Q => \skid_buffer_reg_n_0_[29]\, + R => '0' + ); +\skid_buffer_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(2), + Q => \skid_buffer_reg_n_0_[2]\, + R => '0' + ); +\skid_buffer_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(30), + Q => \skid_buffer_reg_n_0_[30]\, + R => '0' + ); +\skid_buffer_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(31), + Q => \skid_buffer_reg_n_0_[31]\, + R => '0' + ); +\skid_buffer_reg[32]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(32), + Q => \skid_buffer_reg_n_0_[32]\, + R => '0' + ); +\skid_buffer_reg[33]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(33), + Q => \skid_buffer_reg_n_0_[33]\, + R => '0' + ); +\skid_buffer_reg[34]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[46]_0\(0), + Q => \skid_buffer_reg_n_0_[34]\, + R => '0' + ); +\skid_buffer_reg[35]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[46]_0\(1), + Q => \skid_buffer_reg_n_0_[35]\, + R => '0' + ); +\skid_buffer_reg[36]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[46]_0\(2), + Q => \skid_buffer_reg_n_0_[36]\, + R => '0' + ); +\skid_buffer_reg[37]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[46]_0\(3), + Q => \skid_buffer_reg_n_0_[37]\, + R => '0' + ); +\skid_buffer_reg[38]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[46]_0\(4), + Q => \skid_buffer_reg_n_0_[38]\, + R => '0' + ); +\skid_buffer_reg[39]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[46]_0\(5), + Q => \skid_buffer_reg_n_0_[39]\, + R => '0' + ); +\skid_buffer_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(3), + Q => \skid_buffer_reg_n_0_[3]\, + R => '0' + ); +\skid_buffer_reg[40]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[46]_0\(6), + Q => \skid_buffer_reg_n_0_[40]\, + R => '0' + ); +\skid_buffer_reg[41]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[46]_0\(7), + Q => \skid_buffer_reg_n_0_[41]\, + R => '0' + ); +\skid_buffer_reg[42]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[46]_0\(8), + Q => \skid_buffer_reg_n_0_[42]\, + R => '0' + ); +\skid_buffer_reg[43]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[46]_0\(9), + Q => \skid_buffer_reg_n_0_[43]\, + R => '0' + ); +\skid_buffer_reg[44]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[46]_0\(10), + Q => \skid_buffer_reg_n_0_[44]\, + R => '0' + ); +\skid_buffer_reg[45]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[46]_0\(11), + Q => \skid_buffer_reg_n_0_[45]\, + R => '0' + ); +\skid_buffer_reg[46]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[46]_0\(12), + Q => \skid_buffer_reg_n_0_[46]\, + R => '0' + ); +\skid_buffer_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(4), + Q => \skid_buffer_reg_n_0_[4]\, + R => '0' + ); +\skid_buffer_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(5), + Q => \skid_buffer_reg_n_0_[5]\, + R => '0' + ); +\skid_buffer_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(6), + Q => \skid_buffer_reg_n_0_[6]\, + R => '0' + ); +\skid_buffer_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(7), + Q => \skid_buffer_reg_n_0_[7]\, + R => '0' + ); +\skid_buffer_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(8), + Q => \skid_buffer_reg_n_0_[8]\, + R => '0' + ); +\skid_buffer_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^s_ready_i_reg_0\, + D => \skid_buffer_reg[33]_0\(9), + Q => \skid_buffer_reg_n_0_[9]\, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_b_channel is + port ( + si_rs_bvalid : out STD_LOGIC; + cnt_read : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_bready : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); + \s_bresp_acc_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + areset_d1 : in STD_LOGIC; + shandshake : in STD_LOGIC; + aclk : in STD_LOGIC; + si_rs_bready : in STD_LOGIC; + m_axi_bvalid : in STD_LOGIC; + b_push : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); +end NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_b_channel; + +architecture STRUCTURE of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_b_channel is + signal bid_fifo_0_n_4 : STD_LOGIC; + signal bid_fifo_0_n_5 : STD_LOGIC; + signal \bresp_cnt[7]_i_3_n_0\ : STD_LOGIC; + signal bresp_cnt_reg : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal bresp_fifo_0_n_0 : STD_LOGIC; + signal bresp_push : STD_LOGIC; + signal mhandshake : STD_LOGIC; + signal mhandshake_r : STD_LOGIC; + signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal s_bresp_acc0 : STD_LOGIC; + signal \s_bresp_acc[0]_i_1_n_0\ : STD_LOGIC; + signal \s_bresp_acc[1]_i_1_n_0\ : STD_LOGIC; + signal \s_bresp_acc_reg_n_0_[0]\ : STD_LOGIC; + signal \s_bresp_acc_reg_n_0_[1]\ : STD_LOGIC; + signal shandshake_r : STD_LOGIC; + signal \^si_rs_bvalid\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \bresp_cnt[1]_i_1\ : label is "soft_lutpair126"; + attribute SOFT_HLUTNM of \bresp_cnt[2]_i_1\ : label is "soft_lutpair126"; + attribute SOFT_HLUTNM of \bresp_cnt[3]_i_1\ : label is "soft_lutpair124"; + attribute SOFT_HLUTNM of \bresp_cnt[4]_i_1\ : label is "soft_lutpair124"; + attribute SOFT_HLUTNM of \bresp_cnt[6]_i_1\ : label is "soft_lutpair125"; + attribute SOFT_HLUTNM of \bresp_cnt[7]_i_2\ : label is "soft_lutpair125"; +begin + si_rs_bvalid <= \^si_rs_bvalid\; +bid_fifo_0: entity work.NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_simple_fifo + port map ( + Q(7 downto 0) => bresp_cnt_reg(7 downto 0), + SR(0) => s_bresp_acc0, + aclk => aclk, + addr(1 downto 0) => cnt_read(1 downto 0), + areset_d1 => areset_d1, + b_push => b_push, + \bresp_cnt_reg[1]\ => bid_fifo_0_n_4, + \cnt_read_reg[1]_0\ => bid_fifo_0_n_5, + \in\(15 downto 0) => \in\(15 downto 0), + mhandshake_r => mhandshake_r, + \out\(11 downto 0) => \out\(11 downto 0), + sel => bresp_push, + shandshake_r => shandshake_r + ); +\bresp_cnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => bresp_cnt_reg(0), + O => p_0_in(0) + ); +\bresp_cnt[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => bresp_cnt_reg(1), + I1 => bresp_cnt_reg(0), + O => p_0_in(1) + ); +\bresp_cnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => bresp_cnt_reg(2), + I1 => bresp_cnt_reg(0), + I2 => bresp_cnt_reg(1), + O => p_0_in(2) + ); +\bresp_cnt[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => bresp_cnt_reg(3), + I1 => bresp_cnt_reg(1), + I2 => bresp_cnt_reg(0), + I3 => bresp_cnt_reg(2), + O => p_0_in(3) + ); +\bresp_cnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAAAAAA" + ) + port map ( + I0 => bresp_cnt_reg(4), + I1 => bresp_cnt_reg(2), + I2 => bresp_cnt_reg(0), + I3 => bresp_cnt_reg(1), + I4 => bresp_cnt_reg(3), + O => p_0_in(4) + ); +\bresp_cnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"6AAAAAAAAAAAAAAA" + ) + port map ( + I0 => bresp_cnt_reg(5), + I1 => bresp_cnt_reg(3), + I2 => bresp_cnt_reg(1), + I3 => bresp_cnt_reg(0), + I4 => bresp_cnt_reg(2), + I5 => bresp_cnt_reg(4), + O => p_0_in(5) + ); +\bresp_cnt[6]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => bresp_cnt_reg(6), + I1 => \bresp_cnt[7]_i_3_n_0\, + O => p_0_in(6) + ); +\bresp_cnt[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => bresp_cnt_reg(7), + I1 => \bresp_cnt[7]_i_3_n_0\, + I2 => bresp_cnt_reg(6), + O => p_0_in(7) + ); +\bresp_cnt[7]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => bresp_cnt_reg(5), + I1 => bresp_cnt_reg(3), + I2 => bresp_cnt_reg(1), + I3 => bresp_cnt_reg(0), + I4 => bresp_cnt_reg(2), + I5 => bresp_cnt_reg(4), + O => \bresp_cnt[7]_i_3_n_0\ + ); +\bresp_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => mhandshake_r, + D => p_0_in(0), + Q => bresp_cnt_reg(0), + R => s_bresp_acc0 + ); +\bresp_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => mhandshake_r, + D => p_0_in(1), + Q => bresp_cnt_reg(1), + R => s_bresp_acc0 + ); +\bresp_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => mhandshake_r, + D => p_0_in(2), + Q => bresp_cnt_reg(2), + R => s_bresp_acc0 + ); +\bresp_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => mhandshake_r, + D => p_0_in(3), + Q => bresp_cnt_reg(3), + R => s_bresp_acc0 + ); +\bresp_cnt_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => mhandshake_r, + D => p_0_in(4), + Q => bresp_cnt_reg(4), + R => s_bresp_acc0 + ); +\bresp_cnt_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => mhandshake_r, + D => p_0_in(5), + Q => bresp_cnt_reg(5), + R => s_bresp_acc0 + ); +\bresp_cnt_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => mhandshake_r, + D => p_0_in(6), + Q => bresp_cnt_reg(6), + R => s_bresp_acc0 + ); +\bresp_cnt_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => mhandshake_r, + D => p_0_in(7), + Q => bresp_cnt_reg(7), + R => s_bresp_acc0 + ); +bresp_fifo_0: entity work.\NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized0\ + port map ( + aclk => aclk, + areset_d1 => areset_d1, + areset_d1_reg => bresp_fifo_0_n_0, + bvalid_i_reg => bid_fifo_0_n_5, + \cnt_read_reg[1]_0\ => bid_fifo_0_n_4, + \in\(1) => \s_bresp_acc_reg_n_0_[1]\, + \in\(0) => \s_bresp_acc_reg_n_0_[0]\, + m_axi_bready => m_axi_bready, + m_axi_bvalid => m_axi_bvalid, + mhandshake => mhandshake, + mhandshake_r => mhandshake_r, + \s_bresp_acc_reg[1]\(1 downto 0) => \s_bresp_acc_reg[1]_0\(1 downto 0), + sel => bresp_push, + shandshake_r => shandshake_r, + si_rs_bready => si_rs_bready, + si_rs_bvalid => \^si_rs_bvalid\ + ); +bvalid_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => bresp_fifo_0_n_0, + Q => \^si_rs_bvalid\, + R => '0' + ); +mhandshake_r_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => mhandshake, + Q => mhandshake_r, + R => areset_d1 + ); +\s_bresp_acc[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000EACECCCC" + ) + port map ( + I0 => m_axi_bresp(0), + I1 => \s_bresp_acc_reg_n_0_[0]\, + I2 => \s_bresp_acc_reg_n_0_[1]\, + I3 => m_axi_bresp(1), + I4 => mhandshake, + I5 => s_bresp_acc0, + O => \s_bresp_acc[0]_i_1_n_0\ + ); +\s_bresp_acc[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00EA" + ) + port map ( + I0 => \s_bresp_acc_reg_n_0_[1]\, + I1 => m_axi_bresp(1), + I2 => mhandshake, + I3 => s_bresp_acc0, + O => \s_bresp_acc[1]_i_1_n_0\ + ); +\s_bresp_acc_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_bresp_acc[0]_i_1_n_0\, + Q => \s_bresp_acc_reg_n_0_[0]\, + R => '0' + ); +\s_bresp_acc_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_bresp_acc[1]_i_1_n_0\, + Q => \s_bresp_acc_reg_n_0_[1]\, + R => '0' + ); +shandshake_r_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => shandshake, + Q => shandshake_r, + R => areset_d1 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_cmd_translator is + port ( + next_pending_r : out STD_LOGIC; + next_pending_r_0 : out STD_LOGIC; + sel_first_reg_0 : out STD_LOGIC; + sel_first_reg_1 : out STD_LOGIC; + sel_first : out STD_LOGIC; + \axlen_cnt_reg[5]\ : out STD_LOGIC; + \axlen_cnt_reg[2]\ : out STD_LOGIC; + axaddr_wrap0 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + \axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); + \axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axburst_eq1_reg_0 : out STD_LOGIC; + \axlen_cnt_reg[0]\ : out STD_LOGIC; + \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); + \m_payload_i_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + aclk : in STD_LOGIC; + sel_first_i : in STD_LOGIC; + s_axburst_eq0_reg_0 : in STD_LOGIC; + s_axburst_eq1_reg_1 : in STD_LOGIC; + sel_first_reg_2 : in STD_LOGIC; + sel_first_reg_3 : in STD_LOGIC; + \axlen_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); + si_rs_awvalid : in STD_LOGIC; + \axlen_cnt_reg[3]_0\ : in STD_LOGIC; + \axaddr_wrap_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \next\ : in STD_LOGIC; + \axaddr_wrap_reg[0]\ : in STD_LOGIC; + next_pending_r_reg : in STD_LOGIC; + axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \axlen_cnt_reg[5]_0\ : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \wrap_cnt_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + \wrap_boundary_axaddr_r_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); + \axaddr_wrap_reg[11]_0\ : in STD_LOGIC_VECTOR ( 11 downto 0 ) + ); +end NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_cmd_translator; + +architecture STRUCTURE of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_cmd_translator is + signal s_axburst_eq0 : STD_LOGIC; + signal s_axburst_eq1 : STD_LOGIC; +begin +\FSM_sequential_state[1]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => s_axburst_eq1, + I1 => \axlen_cnt_reg[3]\(11), + I2 => s_axburst_eq0, + O => s_axburst_eq1_reg_0 + ); +incr_cmd_0: entity work.NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_incr_cmd + port map ( + Q(1 downto 0) => Q(1 downto 0), + S(3 downto 0) => S(3 downto 0), + aclk => aclk, + axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), + \axaddr_incr_reg[11]_0\(11 downto 0) => \axaddr_incr_reg[11]\(11 downto 0), + \axlen_cnt_reg[3]_0\(9 downto 6) => \axlen_cnt_reg[3]\(15 downto 12), + \axlen_cnt_reg[3]_0\(5 downto 4) => \axlen_cnt_reg[3]\(10 downto 9), + \axlen_cnt_reg[3]_0\(3 downto 0) => \axlen_cnt_reg[3]\(3 downto 0), + \axlen_cnt_reg[3]_1\ => \axlen_cnt_reg[3]_0\, + \axlen_cnt_reg[4]_0\ => \axaddr_wrap_reg[0]\, + \axlen_cnt_reg[5]_0\ => \axlen_cnt_reg[5]\, + \axlen_cnt_reg[5]_1\ => \axlen_cnt_reg[5]_0\, + \m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0), + \next\ => \next\, + next_pending_r => next_pending_r, + next_pending_r_reg_0 => next_pending_r_reg, + sel_first_reg_0 => sel_first_reg_1, + sel_first_reg_1 => sel_first_reg_2, + si_rs_awvalid => si_rs_awvalid + ); +s_axburst_eq0_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => s_axburst_eq0_reg_0, + Q => s_axburst_eq0, + R => '0' + ); +s_axburst_eq1_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => s_axburst_eq1_reg_1, + Q => s_axburst_eq1, + R => '0' + ); +sel_first_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => sel_first_i, + Q => sel_first_reg_0, + R => '0' + ); +wrap_cmd_0: entity work.NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_wrap_cmd + port map ( + D(3 downto 0) => D(3 downto 0), + E(0) => E(0), + Q(1 downto 0) => Q(1 downto 0), + aclk => aclk, + \axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0), + axaddr_wrap0(11 downto 0) => axaddr_wrap0(11 downto 0), + \axaddr_wrap_reg[0]_0\ => \axaddr_wrap_reg[0]\, + \axaddr_wrap_reg[11]_0\(11 downto 0) => \axaddr_wrap_reg[11]\(11 downto 0), + \axaddr_wrap_reg[11]_1\(11 downto 0) => \axaddr_wrap_reg[11]_0\(11 downto 0), + \axaddr_wrap_reg[3]_0\(3 downto 0) => \axaddr_wrap_reg[3]\(3 downto 0), + \axlen_cnt_reg[0]_0\ => \axlen_cnt_reg[0]\, + \axlen_cnt_reg[2]_0\ => \axlen_cnt_reg[2]\, + \axlen_cnt_reg[3]_0\(8 downto 5) => \axlen_cnt_reg[3]\(15 downto 12), + \axlen_cnt_reg[3]_0\(4 downto 0) => \axlen_cnt_reg[3]\(8 downto 4), + \axlen_cnt_reg[3]_1\ => \axlen_cnt_reg[3]_0\, + \next\ => \next\, + next_pending_r_0 => next_pending_r_0, + next_pending_r_reg_0 => next_pending_r_reg, + sel_first => sel_first, + sel_first_reg_0 => sel_first_reg_3, + si_rs_awvalid => si_rs_awvalid, + \wrap_boundary_axaddr_r_reg[11]_0\(11 downto 0) => \wrap_boundary_axaddr_r_reg[11]\(11 downto 0), + \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0), + \wrap_cnt_r_reg[3]_0\(3 downto 0) => \wrap_cnt_r_reg[3]\(3 downto 0), + \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0), + \wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_cmd_translator_1 is + port ( + sel_first_reg_0 : out STD_LOGIC; + sel_first_reg_1 : out STD_LOGIC; + sel_first_reg_2 : out STD_LOGIC; + \axlen_cnt_reg[7]\ : out STD_LOGIC; + \axaddr_wrap_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); + \axaddr_wrap_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + O : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_arready_0 : out STD_LOGIC; + r_rlast : out STD_LOGIC; + \axlen_cnt_reg[0]\ : out STD_LOGIC; + \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); + \m_payload_i_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + aclk : in STD_LOGIC; + sel_first_i : in STD_LOGIC; + sel_first_reg_3 : in STD_LOGIC; + sel_first_reg_4 : in STD_LOGIC; + \axlen_cnt_reg[1]\ : in STD_LOGIC; + \axlen_cnt_reg[2]\ : in STD_LOGIC_VECTOR ( 14 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); + si_rs_arvalid : in STD_LOGIC; + S : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + r_push : in STD_LOGIC; + \axaddr_wrap_reg[0]\ : in STD_LOGIC; + next_pending_r_reg : in STD_LOGIC; + \axlen_cnt_reg[3]\ : in STD_LOGIC; + m_axi_arready : in STD_LOGIC; + \axaddr_incr_reg[11]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \axaddr_incr_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \axlen_cnt_reg[7]_0\ : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \wrap_cnt_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + \wrap_boundary_axaddr_r_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); + \axaddr_wrap_reg[11]_0\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \axaddr_incr_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_cmd_translator_1 : entity is "axi_protocol_converter_v2_1_29_b2s_cmd_translator"; +end NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_cmd_translator_1; + +architecture STRUCTURE of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_cmd_translator_1 is + signal incr_next_pending : STD_LOGIC; + signal s_axburst_eq0 : STD_LOGIC; + signal s_axburst_eq1 : STD_LOGIC; + signal wrap_cmd_0_n_25 : STD_LOGIC; + signal wrap_cmd_0_n_26 : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_state[1]_i_3\ : label is "soft_lutpair15"; + attribute SOFT_HLUTNM of r_rlast_r_i_1 : label is "soft_lutpair15"; +begin +\FSM_sequential_state[1]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00088808" + ) + port map ( + I0 => m_axi_arready, + I1 => Q(0), + I2 => s_axburst_eq0, + I3 => \axlen_cnt_reg[2]\(11), + I4 => s_axburst_eq1, + O => m_axi_arready_0 + ); +incr_cmd_0: entity work.NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_incr_cmd_2 + port map ( + Q(1 downto 0) => Q(1 downto 0), + aclk => aclk, + \axaddr_incr_reg[0]_0\(0) => \axaddr_incr_reg[0]\(0), + \axaddr_incr_reg[11]_0\(11 downto 0) => \axaddr_incr_reg[11]\(11 downto 0), + \axaddr_incr_reg[11]_1\(3 downto 0) => \axaddr_incr_reg[11]_0\(3 downto 0), + \axaddr_incr_reg[3]_0\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0), + \axaddr_incr_reg[3]_1\(3 downto 0) => \axaddr_incr_reg[3]_0\(3 downto 0), + \axaddr_incr_reg[7]_0\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0), + \axlen_cnt_reg[2]_0\ => \axlen_cnt_reg[1]\, + \axlen_cnt_reg[2]_1\(8 downto 6) => \axlen_cnt_reg[2]\(14 downto 12), + \axlen_cnt_reg[2]_1\(5 downto 4) => \axlen_cnt_reg[2]\(10 downto 9), + \axlen_cnt_reg[2]_1\(3 downto 0) => \axlen_cnt_reg[2]\(3 downto 0), + \axlen_cnt_reg[3]_0\ => \axlen_cnt_reg[3]\, + \axlen_cnt_reg[4]_0\ => \axaddr_wrap_reg[0]\, + \axlen_cnt_reg[7]_0\ => \axlen_cnt_reg[7]\, + \axlen_cnt_reg[7]_1\ => \axlen_cnt_reg[7]_0\, + incr_next_pending => incr_next_pending, + m_axi_arready => m_axi_arready, + \m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0), + next_pending_r_reg_0 => next_pending_r_reg, + r_push => r_push, + sel_first_reg_0 => sel_first_reg_1, + sel_first_reg_1 => sel_first_reg_3, + si_rs_arvalid => si_rs_arvalid + ); +r_rlast_r_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"1D" + ) + port map ( + I0 => s_axburst_eq0, + I1 => \axlen_cnt_reg[2]\(11), + I2 => s_axburst_eq1, + O => r_rlast + ); +s_axburst_eq0_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => wrap_cmd_0_n_25, + Q => s_axburst_eq0, + R => '0' + ); +s_axburst_eq1_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => wrap_cmd_0_n_26, + Q => s_axburst_eq1, + R => '0' + ); +sel_first_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => sel_first_i, + Q => sel_first_reg_0, + R => '0' + ); +wrap_cmd_0: entity work.NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_wrap_cmd_3 + port map ( + D(3 downto 0) => D(3 downto 0), + E(0) => E(0), + O(3 downto 0) => O(3 downto 0), + Q(0) => Q(1), + S(3 downto 0) => S(3 downto 0), + aclk => aclk, + \axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0), + \axaddr_wrap_reg[0]_0\ => \axaddr_wrap_reg[0]\, + \axaddr_wrap_reg[11]_0\(11 downto 0) => \axaddr_wrap_reg[11]\(11 downto 0), + \axaddr_wrap_reg[11]_1\(11 downto 0) => \axaddr_wrap_reg[11]_0\(11 downto 0), + \axaddr_wrap_reg[3]_0\(3 downto 0) => \axaddr_wrap_reg[3]\(3 downto 0), + \axaddr_wrap_reg[7]_0\(3 downto 0) => \axaddr_wrap_reg[7]\(3 downto 0), + \axlen_cnt_reg[0]_0\ => \axlen_cnt_reg[0]\, + \axlen_cnt_reg[1]_0\ => \axlen_cnt_reg[1]\, + \axlen_cnt_reg[2]_0\(8 downto 5) => \axlen_cnt_reg[2]\(14 downto 11), + \axlen_cnt_reg[2]_0\(4 downto 0) => \axlen_cnt_reg[2]\(8 downto 4), + \axlen_cnt_reg[3]_0\ => \axlen_cnt_reg[3]\, + incr_next_pending => incr_next_pending, + \m_payload_i_reg[39]\ => wrap_cmd_0_n_25, + \m_payload_i_reg[39]_0\ => wrap_cmd_0_n_26, + next_pending_r_reg_0 => next_pending_r_reg, + sel_first_i => sel_first_i, + sel_first_reg_0 => sel_first_reg_2, + sel_first_reg_1 => sel_first_reg_4, + si_rs_arvalid => si_rs_arvalid, + \wrap_boundary_axaddr_r_reg[11]_0\(11 downto 0) => \wrap_boundary_axaddr_r_reg[11]\(11 downto 0), + \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0), + \wrap_cnt_r_reg[3]_0\(3 downto 0) => \wrap_cnt_r_reg[3]\(3 downto 0), + \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0), + \wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_r_channel is + port ( + \cnt_read_reg[2]\ : out STD_LOGIC; + \cnt_read_reg[4]\ : out STD_LOGIC; + m_axi_rready : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 33 downto 0 ); + r_push_r_reg_0 : out STD_LOGIC_VECTOR ( 12 downto 0 ); + r_push : in STD_LOGIC; + aclk : in STD_LOGIC; + r_rlast : in STD_LOGIC; + \cnt_read_reg[4]_0\ : in STD_LOGIC; + si_rs_rready : in STD_LOGIC; + m_axi_rvalid : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); + D : in STD_LOGIC_VECTOR ( 11 downto 0 ); + areset_d1 : in STD_LOGIC + ); +end NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_r_channel; + +architecture STRUCTURE of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_r_channel is + signal r_push_r : STD_LOGIC; + signal rd_data_fifo_0_n_0 : STD_LOGIC; + signal rd_data_fifo_0_n_3 : STD_LOGIC; + signal trans_in : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal transaction_fifo_0_n_1 : STD_LOGIC; +begin +\r_arid_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => D(0), + Q => trans_in(1), + R => '0' + ); +\r_arid_r_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => D(10), + Q => trans_in(11), + R => '0' + ); +\r_arid_r_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => D(11), + Q => trans_in(12), + R => '0' + ); +\r_arid_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => D(1), + Q => trans_in(2), + R => '0' + ); +\r_arid_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => D(2), + Q => trans_in(3), + R => '0' + ); +\r_arid_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => D(3), + Q => trans_in(4), + R => '0' + ); +\r_arid_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => D(4), + Q => trans_in(5), + R => '0' + ); +\r_arid_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => D(5), + Q => trans_in(6), + R => '0' + ); +\r_arid_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => D(6), + Q => trans_in(7), + R => '0' + ); +\r_arid_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => D(7), + Q => trans_in(8), + R => '0' + ); +\r_arid_r_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => D(8), + Q => trans_in(9), + R => '0' + ); +\r_arid_r_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => D(9), + Q => trans_in(10), + R => '0' + ); +r_push_r_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => r_push, + Q => r_push_r, + R => '0' + ); +r_rlast_r_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => r_rlast, + Q => trans_in(0), + R => '0' + ); +rd_data_fifo_0: entity work.\NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized1\ + port map ( + aclk => aclk, + areset_d1 => areset_d1, + \cnt_read_reg[2]_0\ => \cnt_read_reg[2]\, + \cnt_read_reg[4]_0\ => rd_data_fifo_0_n_3, + \cnt_read_reg[4]_1\ => \cnt_read_reg[4]_0\, + \in\(33 downto 0) => \in\(33 downto 0), + m_axi_rready => m_axi_rready, + m_axi_rvalid => m_axi_rvalid, + m_valid_i_reg => transaction_fifo_0_n_1, + \out\(33 downto 0) => \out\(33 downto 0), + r_push_r => r_push_r, + s_ready_i_reg => rd_data_fifo_0_n_0, + si_rs_rready => si_rs_rready + ); +transaction_fifo_0: entity work.\NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized2\ + port map ( + \FSM_sequential_state_reg[0]\ => rd_data_fifo_0_n_3, + aclk => aclk, + areset_d1 => areset_d1, + \cnt_read_reg[4]_0\ => \cnt_read_reg[4]\, + \cnt_read_reg[4]_1\ => transaction_fifo_0_n_1, + \cnt_read_reg[4]_2\ => \cnt_read_reg[4]_0\, + \cnt_read_reg[4]_3\ => rd_data_fifo_0_n_0, + \in\(12 downto 0) => trans_in(12 downto 0), + r_push_r => r_push_r, + r_push_r_reg(12 downto 0) => r_push_r_reg_0(12 downto 0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axi_register_slice is + port ( + s_ready_i_reg : out STD_LOGIC; + s_ready_i_reg_0 : out STD_LOGIC; + si_rs_awvalid : out STD_LOGIC; + m_valid_i_reg : out STD_LOGIC; + si_rs_bready : out STD_LOGIC; + si_rs_arvalid : out STD_LOGIC; + m_valid_i_reg_0 : out STD_LOGIC; + si_rs_rready : out STD_LOGIC; + S : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \m_payload_i_reg[61]\ : out STD_LOGIC_VECTOR ( 53 downto 0 ); + \axaddr_wrap_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \m_payload_i_reg[61]_0\ : out STD_LOGIC_VECTOR ( 53 downto 0 ); + \axaddr_wrap_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + axaddr_incr : out STD_LOGIC_VECTOR ( 11 downto 0 ); + \m_payload_i_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \m_payload_i_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + O : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \m_payload_i_reg[45]\ : out STD_LOGIC; + \FSM_sequential_state_reg[0]\ : out STD_LOGIC; + \m_payload_i_reg[5]\ : out STD_LOGIC; + shandshake : out STD_LOGIC; + \FSM_sequential_state_reg[1]\ : out STD_LOGIC; + \m_payload_i_reg[6]\ : out STD_LOGIC; + \m_payload_i_reg[47]\ : out STD_LOGIC; + \m_payload_i_reg[45]_0\ : out STD_LOGIC; + s_ready_i_reg_1 : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 6 downto 0 ); + \m_payload_i_reg[4]\ : out STD_LOGIC; + \m_payload_i_reg[1]\ : out STD_LOGIC; + \m_payload_i_reg[2]\ : out STD_LOGIC; + \m_payload_i_reg[1]_0\ : out STD_LOGIC; + \m_payload_i_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); + \m_payload_i_reg[2]_0\ : out STD_LOGIC; + \m_payload_i_reg[1]_1\ : out STD_LOGIC; + \m_payload_i_reg[2]_1\ : out STD_LOGIC; + \m_payload_i_reg[1]_2\ : out STD_LOGIC; + \m_payload_i_reg[2]_2\ : out STD_LOGIC; + \m_payload_i_reg[4]_0\ : out STD_LOGIC; + m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); + \m_payload_i_reg[13]\ : out STD_LOGIC_VECTOR ( 13 downto 0 ); + \m_payload_i_reg[46]\ : out STD_LOGIC_VECTOR ( 46 downto 0 ); + aclk : in STD_LOGIC; + s_ready_i0 : in STD_LOGIC; + m_valid_i0 : in STD_LOGIC; + aresetn : in STD_LOGIC; + m_valid_i_reg_1 : in STD_LOGIC; + s_axi_rready : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \m_axi_awaddr[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \m_axi_araddr[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \m_axi_araddr[11]_0\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); + b_push : in STD_LOGIC; + s_axi_awvalid : in STD_LOGIC; + \axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \axaddr_incr_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + next_pending_r_reg : in STD_LOGIC; + \wrap_second_len_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + si_rs_bvalid : in STD_LOGIC; + \axlen_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + next_pending_r_reg_0 : in STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + sel_first : in STD_LOGIC; + sel_first_0 : in STD_LOGIC; + s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \m_axi_araddr[11]_1\ : in STD_LOGIC; + sel_first_1 : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \skid_buffer_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \skid_buffer_reg[46]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + \skid_buffer_reg[33]\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + \m_payload_i_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); +end NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axi_register_slice; + +architecture STRUCTURE of NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axi_register_slice is + signal \ar.ar_pipe_n_2\ : STD_LOGIC; + signal \aw.aw_pipe_n_1\ : STD_LOGIC; + signal \aw.aw_pipe_n_104\ : STD_LOGIC; +begin +\ar.ar_pipe\: entity work.NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axic_register_slice + port map ( + \FSM_sequential_state_reg[1]\ => \FSM_sequential_state_reg[1]\, + O(3 downto 0) => O(3 downto 0), + Q(53 downto 0) => \m_payload_i_reg[61]_0\(53 downto 0), + aclk => aclk, + \aresetn_d_reg[1]_inv_0\ => \ar.ar_pipe_n_2\, + \aresetn_d_reg[1]_inv_1\ => \aw.aw_pipe_n_104\, + \axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0), + \axaddr_incr_reg[3]_0\(3 downto 0) => \axaddr_incr_reg[3]_1\(3 downto 0), + \axaddr_wrap_reg[3]\(3 downto 0) => \axaddr_wrap_reg[3]_0\(3 downto 0), + \axlen_cnt_reg[3]\(1 downto 0) => \axlen_cnt_reg[3]\(1 downto 0), + m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), + \m_axi_araddr[11]\(11 downto 0) => \m_axi_araddr[11]\(11 downto 0), + \m_axi_araddr[11]_0\(11 downto 0) => \m_axi_araddr[11]_0\(11 downto 0), + \m_axi_araddr[11]_1\ => \m_axi_araddr[11]_1\, + \m_payload_i_reg[0]_0\(0) => \m_payload_i_reg[0]\(0), + \m_payload_i_reg[1]_0\ => \m_payload_i_reg[1]_1\, + \m_payload_i_reg[1]_1\ => \m_payload_i_reg[1]_2\, + \m_payload_i_reg[2]_0\ => \m_payload_i_reg[2]_0\, + \m_payload_i_reg[2]_1\ => \m_payload_i_reg[2]_2\, + \m_payload_i_reg[3]_0\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0), + \m_payload_i_reg[45]_0\ => \m_payload_i_reg[45]_0\, + \m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]\, + \m_payload_i_reg[4]_0\ => \m_payload_i_reg[4]_0\, + \m_payload_i_reg[6]_0\ => \m_payload_i_reg[6]\, + \m_payload_i_reg[6]_1\(6 downto 0) => \m_payload_i_reg[6]_0\(6 downto 0), + \m_payload_i_reg[7]_0\(3 downto 0) => \m_payload_i_reg[7]\(3 downto 0), + m_valid_i0 => m_valid_i0, + next_pending_r_reg => next_pending_r_reg_0, + s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), + s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), + s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), + s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), + s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), + s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0), + s_ready_i0 => s_ready_i0, + s_ready_i_reg_0 => s_ready_i_reg_0, + s_ready_i_reg_1 => \aw.aw_pipe_n_1\, + sel_first_1 => sel_first_1, + si_rs_arvalid => si_rs_arvalid + ); +\aw.aw_pipe\: entity work.NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axic_register_slice_0 + port map ( + D(6 downto 0) => D(6 downto 0), + E(0) => E(0), + \FSM_sequential_state_reg[0]\ => \FSM_sequential_state_reg[0]\, + Q(11 downto 0) => Q(11 downto 0), + S(3 downto 0) => S(3 downto 0), + aclk => aclk, + aresetn => aresetn, + \aresetn_d_reg[0]_0\ => \aw.aw_pipe_n_1\, + \aresetn_d_reg[0]_1\ => \aw.aw_pipe_n_104\, + axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), + \axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]_0\(3 downto 0), + \axaddr_wrap_reg[3]\(3 downto 0) => \axaddr_wrap_reg[3]\(3 downto 0), + b_push => b_push, + m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), + \m_axi_awaddr[11]\(11 downto 0) => \m_axi_awaddr[11]\(11 downto 0), + \m_payload_i_reg[1]_0\ => \m_payload_i_reg[1]\, + \m_payload_i_reg[1]_1\ => \m_payload_i_reg[1]_0\, + \m_payload_i_reg[2]_0\ => \m_payload_i_reg[2]\, + \m_payload_i_reg[2]_1\ => \m_payload_i_reg[2]_1\, + \m_payload_i_reg[45]_0\ => \m_payload_i_reg[45]\, + \m_payload_i_reg[4]_0\ => \m_payload_i_reg[4]\, + \m_payload_i_reg[5]_0\ => \m_payload_i_reg[5]\, + \m_payload_i_reg[61]_0\(53 downto 0) => \m_payload_i_reg[61]\(53 downto 0), + m_valid_i_reg_0 => si_rs_awvalid, + m_valid_i_reg_1 => \ar.ar_pipe_n_2\, + next_pending_r_reg => next_pending_r_reg, + s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), + s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), + s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), + s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), + s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), + s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0), + s_axi_awvalid => s_axi_awvalid, + s_ready_i_reg_0 => s_ready_i_reg, + sel_first => sel_first, + sel_first_0 => sel_first_0, + \wrap_second_len_r_reg[3]\(1 downto 0) => \wrap_second_len_r_reg[3]\(1 downto 0) + ); +\b.b_pipe\: entity work.\NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axic_register_slice__parameterized1\ + port map ( + aclk => aclk, + \m_payload_i_reg[13]_0\(13 downto 0) => \m_payload_i_reg[13]\(13 downto 0), + m_valid_i_reg_0 => m_valid_i_reg, + m_valid_i_reg_1 => \ar.ar_pipe_n_2\, + \out\(11 downto 0) => \out\(11 downto 0), + s_axi_bready => s_axi_bready, + s_ready_i_reg_0 => si_rs_bready, + s_ready_i_reg_1 => \aw.aw_pipe_n_1\, + shandshake => shandshake, + si_rs_bvalid => si_rs_bvalid, + \skid_buffer_reg[1]_0\(1 downto 0) => \skid_buffer_reg[1]\(1 downto 0) + ); +\r.r_pipe\: entity work.\NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axic_register_slice__parameterized2\ + port map ( + aclk => aclk, + \m_payload_i_reg[46]_0\(46 downto 0) => \m_payload_i_reg[46]\(46 downto 0), + m_valid_i_reg_0 => m_valid_i_reg_0, + m_valid_i_reg_1 => \ar.ar_pipe_n_2\, + m_valid_i_reg_2 => m_valid_i_reg_1, + s_axi_rready => s_axi_rready, + s_ready_i_reg_0 => si_rs_rready, + s_ready_i_reg_1 => s_ready_i_reg_1, + s_ready_i_reg_2 => \aw.aw_pipe_n_1\, + \skid_buffer_reg[33]_0\(33 downto 0) => \skid_buffer_reg[33]\(33 downto 0), + \skid_buffer_reg[46]_0\(12 downto 0) => \skid_buffer_reg[46]\(12 downto 0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_ar_channel is + port ( + sel_first : out STD_LOGIC; + sel_first_reg : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \FSM_sequential_state_reg[1]\ : out STD_LOGIC; + \axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); + \axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); + r_push : out STD_LOGIC; + m_axi_arvalid : out STD_LOGIC; + m_valid_i0 : out STD_LOGIC; + s_ready_i0 : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + r_rlast : out STD_LOGIC; + \s_arid_r_reg[11]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); + \m_payload_i_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + aclk : in STD_LOGIC; + si_rs_arvalid : in STD_LOGIC; + m_axi_arready : in STD_LOGIC; + \s_arid_r_reg[11]_1\ : in STD_LOGIC_VECTOR ( 30 downto 0 ); + S : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \wrap_second_len_r_reg[3]\ : in STD_LOGIC; + \axaddr_offset_r_reg[0]\ : in STD_LOGIC; + \FSM_sequential_state_reg[0]\ : in STD_LOGIC; + \axaddr_offset_r_reg[2]\ : in STD_LOGIC; + \axaddr_offset_r_reg[2]_0\ : in STD_LOGIC; + next_pending_r_reg : in STD_LOGIC; + \axlen_cnt_reg[3]\ : in STD_LOGIC; + \axaddr_offset_r_reg[1]\ : in STD_LOGIC; + \axaddr_offset_r_reg[1]_0\ : in STD_LOGIC; + \axaddr_offset_r_reg[3]\ : in STD_LOGIC; + areset_d1 : in STD_LOGIC; + s_axi_arvalid : in STD_LOGIC; + m_valid_i_reg : in STD_LOGIC; + O : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \axaddr_incr_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + D : in STD_LOGIC_VECTOR ( 6 downto 0 ) + ); +end NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_ar_channel; + +architecture STRUCTURE of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_ar_channel is + signal \^fsm_sequential_state_reg[1]\ : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ar_cmd_fsm_0_n_0 : STD_LOGIC; + signal ar_cmd_fsm_0_n_1 : STD_LOGIC; + signal ar_cmd_fsm_0_n_10 : STD_LOGIC; + signal ar_cmd_fsm_0_n_16 : STD_LOGIC; + signal ar_cmd_fsm_0_n_17 : STD_LOGIC; + signal ar_cmd_fsm_0_n_19 : STD_LOGIC; + signal ar_cmd_fsm_0_n_2 : STD_LOGIC; + signal ar_cmd_fsm_0_n_20 : STD_LOGIC; + signal ar_cmd_fsm_0_n_21 : STD_LOGIC; + signal ar_cmd_fsm_0_n_22 : STD_LOGIC; + signal ar_cmd_fsm_0_n_23 : STD_LOGIC; + signal ar_cmd_fsm_0_n_24 : STD_LOGIC; + signal ar_cmd_fsm_0_n_25 : STD_LOGIC; + signal ar_cmd_fsm_0_n_26 : STD_LOGIC; + signal ar_cmd_fsm_0_n_27 : STD_LOGIC; + signal ar_cmd_fsm_0_n_28 : STD_LOGIC; + signal ar_cmd_fsm_0_n_29 : STD_LOGIC; + signal ar_cmd_fsm_0_n_3 : STD_LOGIC; + signal ar_cmd_fsm_0_n_30 : STD_LOGIC; + signal ar_cmd_fsm_0_n_31 : STD_LOGIC; + signal ar_cmd_fsm_0_n_32 : STD_LOGIC; + signal ar_cmd_fsm_0_n_33 : STD_LOGIC; + signal cmd_translator_0_n_0 : STD_LOGIC; + signal cmd_translator_0_n_20 : STD_LOGIC; + signal cmd_translator_0_n_21 : STD_LOGIC; + signal cmd_translator_0_n_22 : STD_LOGIC; + signal cmd_translator_0_n_23 : STD_LOGIC; + signal cmd_translator_0_n_24 : STD_LOGIC; + signal cmd_translator_0_n_25 : STD_LOGIC; + signal cmd_translator_0_n_26 : STD_LOGIC; + signal cmd_translator_0_n_27 : STD_LOGIC; + signal cmd_translator_0_n_3 : STD_LOGIC; + signal cmd_translator_0_n_4 : STD_LOGIC; + signal cmd_translator_0_n_40 : STD_LOGIC; + signal cmd_translator_0_n_42 : STD_LOGIC; + signal cmd_translator_0_n_5 : STD_LOGIC; + signal cmd_translator_0_n_51 : STD_LOGIC; + signal cmd_translator_0_n_52 : STD_LOGIC; + signal cmd_translator_0_n_53 : STD_LOGIC; + signal cmd_translator_0_n_54 : STD_LOGIC; + signal cmd_translator_0_n_55 : STD_LOGIC; + signal cmd_translator_0_n_56 : STD_LOGIC; + signal cmd_translator_0_n_57 : STD_LOGIC; + signal cmd_translator_0_n_58 : STD_LOGIC; + signal cmd_translator_0_n_59 : STD_LOGIC; + signal cmd_translator_0_n_6 : STD_LOGIC; + signal cmd_translator_0_n_60 : STD_LOGIC; + signal cmd_translator_0_n_61 : STD_LOGIC; + signal cmd_translator_0_n_62 : STD_LOGIC; + signal cmd_translator_0_n_7 : STD_LOGIC; + signal \^r_push\ : STD_LOGIC; + signal \^sel_first\ : STD_LOGIC; + signal sel_first_i : STD_LOGIC; + signal \^sel_first_reg\ : STD_LOGIC; + signal \wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 ); +begin + \FSM_sequential_state_reg[1]\ <= \^fsm_sequential_state_reg[1]\; + Q(1 downto 0) <= \^q\(1 downto 0); + r_push <= \^r_push\; + sel_first <= \^sel_first\; + sel_first_reg <= \^sel_first_reg\; +ar_cmd_fsm_0: entity work.NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm + port map ( + D(3) => ar_cmd_fsm_0_n_0, + D(2) => ar_cmd_fsm_0_n_1, + D(1) => ar_cmd_fsm_0_n_2, + D(0) => ar_cmd_fsm_0_n_3, + E(0) => ar_cmd_fsm_0_n_20, + \FSM_sequential_state_reg[0]_0\ => \FSM_sequential_state_reg[0]\, + \FSM_sequential_state_reg[1]_0\ => ar_cmd_fsm_0_n_10, + \FSM_sequential_state_reg[1]_1\ => \^fsm_sequential_state_reg[1]\, + \FSM_sequential_state_reg[1]_2\ => \^r_push\, + \FSM_sequential_state_reg[1]_3\ => cmd_translator_0_n_40, + O(3) => cmd_translator_0_n_24, + O(2) => cmd_translator_0_n_25, + O(1) => cmd_translator_0_n_26, + O(0) => cmd_translator_0_n_27, + Q(1 downto 0) => \^q\(1 downto 0), + aclk => aclk, + areset_d1 => areset_d1, + \axaddr_incr_reg[0]\ => \^sel_first\, + axaddr_offset(3 downto 0) => \wrap_cmd_0/axaddr_offset\(3 downto 0), + \axaddr_offset_r_reg[0]\ => \axaddr_offset_r_reg[0]\, + \axaddr_offset_r_reg[1]\ => \axaddr_offset_r_reg[1]\, + \axaddr_offset_r_reg[1]_0\ => \axaddr_offset_r_reg[1]_0\, + \axaddr_offset_r_reg[2]\ => \axaddr_offset_r_reg[2]\, + \axaddr_offset_r_reg[2]_0\ => \axaddr_offset_r_reg[2]_0\, + \axaddr_offset_r_reg[3]\(3 downto 0) => \wrap_cmd_0/axaddr_offset_r\(3 downto 0), + \axaddr_offset_r_reg[3]_0\(13) => \s_arid_r_reg[11]_1\(18), + \axaddr_offset_r_reg[3]_0\(12) => \s_arid_r_reg[11]_1\(15), + \axaddr_offset_r_reg[3]_0\(11 downto 0) => \s_arid_r_reg[11]_1\(11 downto 0), + \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]\, + \axaddr_wrap_reg[10]\ => cmd_translator_0_n_42, + \axaddr_wrap_reg[11]\(11) => cmd_translator_0_n_51, + \axaddr_wrap_reg[11]\(10) => cmd_translator_0_n_52, + \axaddr_wrap_reg[11]\(9) => cmd_translator_0_n_53, + \axaddr_wrap_reg[11]\(8) => cmd_translator_0_n_54, + \axaddr_wrap_reg[11]\(7) => cmd_translator_0_n_55, + \axaddr_wrap_reg[11]\(6) => cmd_translator_0_n_56, + \axaddr_wrap_reg[11]\(5) => cmd_translator_0_n_57, + \axaddr_wrap_reg[11]\(4) => cmd_translator_0_n_58, + \axaddr_wrap_reg[11]\(3) => cmd_translator_0_n_59, + \axaddr_wrap_reg[11]\(2) => cmd_translator_0_n_60, + \axaddr_wrap_reg[11]\(1) => cmd_translator_0_n_61, + \axaddr_wrap_reg[11]\(0) => cmd_translator_0_n_62, + \axaddr_wrap_reg[3]\(3) => cmd_translator_0_n_4, + \axaddr_wrap_reg[3]\(2) => cmd_translator_0_n_5, + \axaddr_wrap_reg[3]\(1) => cmd_translator_0_n_6, + \axaddr_wrap_reg[3]\(0) => cmd_translator_0_n_7, + \axaddr_wrap_reg[7]\(3) => cmd_translator_0_n_20, + \axaddr_wrap_reg[7]\(2) => cmd_translator_0_n_21, + \axaddr_wrap_reg[7]\(1) => cmd_translator_0_n_22, + \axaddr_wrap_reg[7]\(0) => cmd_translator_0_n_23, + \axlen_cnt_reg[7]\ => cmd_translator_0_n_3, + m_axi_arready => m_axi_arready, + m_axi_arready_0 => ar_cmd_fsm_0_n_16, + m_axi_arready_1 => ar_cmd_fsm_0_n_17, + m_axi_arready_2 => ar_cmd_fsm_0_n_19, + m_axi_arvalid => m_axi_arvalid, + \m_payload_i_reg[11]\(11) => ar_cmd_fsm_0_n_22, + \m_payload_i_reg[11]\(10) => ar_cmd_fsm_0_n_23, + \m_payload_i_reg[11]\(9) => ar_cmd_fsm_0_n_24, + \m_payload_i_reg[11]\(8) => ar_cmd_fsm_0_n_25, + \m_payload_i_reg[11]\(7) => ar_cmd_fsm_0_n_26, + \m_payload_i_reg[11]\(6) => ar_cmd_fsm_0_n_27, + \m_payload_i_reg[11]\(5) => ar_cmd_fsm_0_n_28, + \m_payload_i_reg[11]\(4) => ar_cmd_fsm_0_n_29, + \m_payload_i_reg[11]\(3) => ar_cmd_fsm_0_n_30, + \m_payload_i_reg[11]\(2) => ar_cmd_fsm_0_n_31, + \m_payload_i_reg[11]\(1) => ar_cmd_fsm_0_n_32, + \m_payload_i_reg[11]\(0) => ar_cmd_fsm_0_n_33, + m_valid_i0 => m_valid_i0, + m_valid_i_reg(0) => E(0), + m_valid_i_reg_0 => m_valid_i_reg, + s_axi_arvalid => s_axi_arvalid, + s_ready_i0 => s_ready_i0, + sel_first_i => sel_first_i, + sel_first_reg(0) => ar_cmd_fsm_0_n_21, + sel_first_reg_0 => \^sel_first_reg\, + sel_first_reg_1 => cmd_translator_0_n_0, + si_rs_arvalid => si_rs_arvalid, + \wrap_second_len_r_reg[3]\(3 downto 0) => \wrap_cmd_0/wrap_second_len\(3 downto 0), + \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_cmd_0/wrap_second_len_r\(3 downto 0), + \wrap_second_len_r_reg[3]_1\ => \wrap_second_len_r_reg[3]\ + ); +cmd_translator_0: entity work.NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_cmd_translator_1 + port map ( + D(3 downto 0) => \wrap_cmd_0/axaddr_offset\(3 downto 0), + E(0) => ar_cmd_fsm_0_n_20, + O(3) => cmd_translator_0_n_24, + O(2) => cmd_translator_0_n_25, + O(1) => cmd_translator_0_n_26, + O(0) => cmd_translator_0_n_27, + Q(1 downto 0) => \^q\(1 downto 0), + S(3 downto 0) => S(3 downto 0), + aclk => aclk, + \axaddr_incr_reg[0]\(0) => ar_cmd_fsm_0_n_21, + \axaddr_incr_reg[11]\(11 downto 0) => \axaddr_incr_reg[11]\(11 downto 0), + \axaddr_incr_reg[11]_0\(3 downto 0) => O(3 downto 0), + \axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0), + \axaddr_incr_reg[3]_0\(3 downto 0) => \axaddr_incr_reg[3]_0\(3 downto 0), + \axaddr_incr_reg[7]\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0), + \axaddr_offset_r_reg[3]\(3 downto 0) => \wrap_cmd_0/axaddr_offset_r\(3 downto 0), + \axaddr_wrap_reg[0]\ => ar_cmd_fsm_0_n_19, + \axaddr_wrap_reg[11]\(11 downto 0) => \axaddr_wrap_reg[11]\(11 downto 0), + \axaddr_wrap_reg[11]_0\(11) => ar_cmd_fsm_0_n_22, + \axaddr_wrap_reg[11]_0\(10) => ar_cmd_fsm_0_n_23, + \axaddr_wrap_reg[11]_0\(9) => ar_cmd_fsm_0_n_24, + \axaddr_wrap_reg[11]_0\(8) => ar_cmd_fsm_0_n_25, + \axaddr_wrap_reg[11]_0\(7) => ar_cmd_fsm_0_n_26, + \axaddr_wrap_reg[11]_0\(6) => ar_cmd_fsm_0_n_27, + \axaddr_wrap_reg[11]_0\(5) => ar_cmd_fsm_0_n_28, + \axaddr_wrap_reg[11]_0\(4) => ar_cmd_fsm_0_n_29, + \axaddr_wrap_reg[11]_0\(3) => ar_cmd_fsm_0_n_30, + \axaddr_wrap_reg[11]_0\(2) => ar_cmd_fsm_0_n_31, + \axaddr_wrap_reg[11]_0\(1) => ar_cmd_fsm_0_n_32, + \axaddr_wrap_reg[11]_0\(0) => ar_cmd_fsm_0_n_33, + \axaddr_wrap_reg[3]\(3) => cmd_translator_0_n_4, + \axaddr_wrap_reg[3]\(2) => cmd_translator_0_n_5, + \axaddr_wrap_reg[3]\(1) => cmd_translator_0_n_6, + \axaddr_wrap_reg[3]\(0) => cmd_translator_0_n_7, + \axaddr_wrap_reg[7]\(3) => cmd_translator_0_n_20, + \axaddr_wrap_reg[7]\(2) => cmd_translator_0_n_21, + \axaddr_wrap_reg[7]\(1) => cmd_translator_0_n_22, + \axaddr_wrap_reg[7]\(0) => cmd_translator_0_n_23, + \axlen_cnt_reg[0]\ => cmd_translator_0_n_42, + \axlen_cnt_reg[1]\ => \^fsm_sequential_state_reg[1]\, + \axlen_cnt_reg[2]\(14 downto 4) => \s_arid_r_reg[11]_1\(17 downto 7), + \axlen_cnt_reg[2]\(3 downto 0) => \s_arid_r_reg[11]_1\(3 downto 0), + \axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]\, + \axlen_cnt_reg[7]\ => cmd_translator_0_n_3, + \axlen_cnt_reg[7]_0\ => ar_cmd_fsm_0_n_10, + m_axi_arready => m_axi_arready, + m_axi_arready_0 => cmd_translator_0_n_40, + \m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0), + next_pending_r_reg => next_pending_r_reg, + r_push => \^r_push\, + r_rlast => r_rlast, + sel_first_i => sel_first_i, + sel_first_reg_0 => cmd_translator_0_n_0, + sel_first_reg_1 => \^sel_first\, + sel_first_reg_2 => \^sel_first_reg\, + sel_first_reg_3 => ar_cmd_fsm_0_n_17, + sel_first_reg_4 => ar_cmd_fsm_0_n_16, + si_rs_arvalid => si_rs_arvalid, + \wrap_boundary_axaddr_r_reg[11]\(11) => cmd_translator_0_n_51, + \wrap_boundary_axaddr_r_reg[11]\(10) => cmd_translator_0_n_52, + \wrap_boundary_axaddr_r_reg[11]\(9) => cmd_translator_0_n_53, + \wrap_boundary_axaddr_r_reg[11]\(8) => cmd_translator_0_n_54, + \wrap_boundary_axaddr_r_reg[11]\(7) => cmd_translator_0_n_55, + \wrap_boundary_axaddr_r_reg[11]\(6) => cmd_translator_0_n_56, + \wrap_boundary_axaddr_r_reg[11]\(5) => cmd_translator_0_n_57, + \wrap_boundary_axaddr_r_reg[11]\(4) => cmd_translator_0_n_58, + \wrap_boundary_axaddr_r_reg[11]\(3) => cmd_translator_0_n_59, + \wrap_boundary_axaddr_r_reg[11]\(2) => cmd_translator_0_n_60, + \wrap_boundary_axaddr_r_reg[11]\(1) => cmd_translator_0_n_61, + \wrap_boundary_axaddr_r_reg[11]\(0) => cmd_translator_0_n_62, + \wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => D(6 downto 0), + \wrap_cnt_r_reg[3]\(3) => ar_cmd_fsm_0_n_0, + \wrap_cnt_r_reg[3]\(2) => ar_cmd_fsm_0_n_1, + \wrap_cnt_r_reg[3]\(1) => ar_cmd_fsm_0_n_2, + \wrap_cnt_r_reg[3]\(0) => ar_cmd_fsm_0_n_3, + \wrap_second_len_r_reg[3]\(3 downto 0) => \wrap_cmd_0/wrap_second_len_r\(3 downto 0), + \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_cmd_0/wrap_second_len\(3 downto 0) + ); +\s_arid_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_arid_r_reg[11]_1\(19), + Q => \s_arid_r_reg[11]_0\(0), + R => '0' + ); +\s_arid_r_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_arid_r_reg[11]_1\(29), + Q => \s_arid_r_reg[11]_0\(10), + R => '0' + ); +\s_arid_r_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_arid_r_reg[11]_1\(30), + Q => \s_arid_r_reg[11]_0\(11), + R => '0' + ); +\s_arid_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_arid_r_reg[11]_1\(20), + Q => \s_arid_r_reg[11]_0\(1), + R => '0' + ); +\s_arid_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_arid_r_reg[11]_1\(21), + Q => \s_arid_r_reg[11]_0\(2), + R => '0' + ); +\s_arid_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_arid_r_reg[11]_1\(22), + Q => \s_arid_r_reg[11]_0\(3), + R => '0' + ); +\s_arid_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_arid_r_reg[11]_1\(23), + Q => \s_arid_r_reg[11]_0\(4), + R => '0' + ); +\s_arid_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_arid_r_reg[11]_1\(24), + Q => \s_arid_r_reg[11]_0\(5), + R => '0' + ); +\s_arid_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_arid_r_reg[11]_1\(25), + Q => \s_arid_r_reg[11]_0\(6), + R => '0' + ); +\s_arid_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_arid_r_reg[11]_1\(26), + Q => \s_arid_r_reg[11]_0\(7), + R => '0' + ); +\s_arid_r_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_arid_r_reg[11]_1\(27), + Q => \s_arid_r_reg[11]_0\(8), + R => '0' + ); +\s_arid_r_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_arid_r_reg[11]_1\(28), + Q => \s_arid_r_reg[11]_0\(9), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_aw_channel is + port ( + sel_first_0 : out STD_LOGIC; + sel_first : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \FSM_sequential_state_reg[0]\ : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + b_push : out STD_LOGIC; + \axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); + \axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_awvalid : out STD_LOGIC; + \in\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + \m_payload_i_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + aclk : in STD_LOGIC; + \s_awid_r_reg[11]_0\ : in STD_LOGIC_VECTOR ( 30 downto 0 ); + si_rs_awvalid : in STD_LOGIC; + \axaddr_wrap_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \wrap_second_len_r_reg[3]\ : in STD_LOGIC; + \axaddr_offset_r_reg[0]\ : in STD_LOGIC; + \axaddr_offset_r_reg[2]\ : in STD_LOGIC; + \axaddr_offset_r_reg[2]_0\ : in STD_LOGIC; + next_pending_r_reg : in STD_LOGIC; + m_axi_awready : in STD_LOGIC; + areset_d1 : in STD_LOGIC; + \axaddr_offset_r_reg[3]\ : in STD_LOGIC; + \axaddr_offset_r_reg[1]\ : in STD_LOGIC; + \axaddr_offset_r_reg[1]_0\ : in STD_LOGIC; + cnt_read : in STD_LOGIC_VECTOR ( 1 downto 0 ); + axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 ); + D : in STD_LOGIC_VECTOR ( 6 downto 0 ) + ); +end NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_aw_channel; + +architecture STRUCTURE of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_aw_channel is + signal \^fsm_sequential_state_reg[0]\ : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal aw_cmd_fsm_0_n_10 : STD_LOGIC; + signal aw_cmd_fsm_0_n_11 : STD_LOGIC; + signal aw_cmd_fsm_0_n_19 : STD_LOGIC; + signal aw_cmd_fsm_0_n_2 : STD_LOGIC; + signal aw_cmd_fsm_0_n_21 : STD_LOGIC; + signal aw_cmd_fsm_0_n_22 : STD_LOGIC; + signal aw_cmd_fsm_0_n_23 : STD_LOGIC; + signal aw_cmd_fsm_0_n_24 : STD_LOGIC; + signal aw_cmd_fsm_0_n_26 : STD_LOGIC; + signal aw_cmd_fsm_0_n_27 : STD_LOGIC; + signal aw_cmd_fsm_0_n_28 : STD_LOGIC; + signal aw_cmd_fsm_0_n_29 : STD_LOGIC; + signal aw_cmd_fsm_0_n_3 : STD_LOGIC; + signal aw_cmd_fsm_0_n_30 : STD_LOGIC; + signal aw_cmd_fsm_0_n_31 : STD_LOGIC; + signal aw_cmd_fsm_0_n_32 : STD_LOGIC; + signal aw_cmd_fsm_0_n_33 : STD_LOGIC; + signal aw_cmd_fsm_0_n_34 : STD_LOGIC; + signal aw_cmd_fsm_0_n_35 : STD_LOGIC; + signal aw_cmd_fsm_0_n_36 : STD_LOGIC; + signal aw_cmd_fsm_0_n_37 : STD_LOGIC; + signal axaddr_wrap0 : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal cmd_translator_0_n_2 : STD_LOGIC; + signal cmd_translator_0_n_43 : STD_LOGIC; + signal cmd_translator_0_n_44 : STD_LOGIC; + signal cmd_translator_0_n_5 : STD_LOGIC; + signal cmd_translator_0_n_6 : STD_LOGIC; + signal \incr_cmd_0/next_pending_r\ : STD_LOGIC; + signal \next\ : STD_LOGIC; + signal \^sel_first\ : STD_LOGIC; + signal \^sel_first_0\ : STD_LOGIC; + signal sel_first_i : STD_LOGIC; + signal wrap_boundary_axaddr_r : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \wrap_cmd_0/next_pending_r\ : STD_LOGIC; + signal \wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal wrap_cnt : STD_LOGIC_VECTOR ( 3 downto 2 ); +begin + \FSM_sequential_state_reg[0]\ <= \^fsm_sequential_state_reg[0]\; + Q(1 downto 0) <= \^q\(1 downto 0); + sel_first <= \^sel_first\; + sel_first_0 <= \^sel_first_0\; +aw_cmd_fsm_0: entity work.NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm + port map ( + D(3 downto 2) => wrap_cnt(3 downto 2), + D(1) => aw_cmd_fsm_0_n_2, + D(0) => aw_cmd_fsm_0_n_3, + E(0) => E(0), + \FSM_sequential_state_reg[0]_0\ => aw_cmd_fsm_0_n_10, + \FSM_sequential_state_reg[0]_1\ => aw_cmd_fsm_0_n_11, + \FSM_sequential_state_reg[0]_2\ => \^fsm_sequential_state_reg[0]\, + \FSM_sequential_state_reg[1]_0\ => cmd_translator_0_n_43, + Q(1 downto 0) => \^q\(1 downto 0), + aclk => aclk, + areset_d1 => areset_d1, + axaddr_offset(3 downto 0) => \wrap_cmd_0/axaddr_offset\(3 downto 0), + \axaddr_offset_r_reg[0]\ => \axaddr_offset_r_reg[0]\, + \axaddr_offset_r_reg[1]\ => \axaddr_offset_r_reg[1]\, + \axaddr_offset_r_reg[1]_0\ => \axaddr_offset_r_reg[1]_0\, + \axaddr_offset_r_reg[2]\ => \axaddr_offset_r_reg[2]\, + \axaddr_offset_r_reg[2]_0\ => \axaddr_offset_r_reg[2]_0\, + \axaddr_offset_r_reg[3]\(3 downto 0) => \wrap_cmd_0/axaddr_offset_r\(3 downto 0), + \axaddr_offset_r_reg[3]_0\(14) => \s_awid_r_reg[11]_0\(18), + \axaddr_offset_r_reg[3]_0\(13 downto 12) => \s_awid_r_reg[11]_0\(15 downto 14), + \axaddr_offset_r_reg[3]_0\(11 downto 0) => \s_awid_r_reg[11]_0\(11 downto 0), + \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]\, + axaddr_wrap0(11 downto 0) => axaddr_wrap0(11 downto 0), + \axaddr_wrap_reg[10]\ => cmd_translator_0_n_44, + \axaddr_wrap_reg[11]\(11 downto 0) => wrap_boundary_axaddr_r(11 downto 0), + \axlen_cnt_reg[2]\ => aw_cmd_fsm_0_n_19, + \axlen_cnt_reg[2]_0\ => aw_cmd_fsm_0_n_21, + cnt_read(1 downto 0) => cnt_read(1 downto 0), + m_axi_awready => m_axi_awready, + m_axi_awready_0 => b_push, + m_axi_awvalid => m_axi_awvalid, + m_valid_i_reg(0) => aw_cmd_fsm_0_n_22, + \next\ => \next\, + next_pending_r => \incr_cmd_0/next_pending_r\, + next_pending_r_0 => \wrap_cmd_0/next_pending_r\, + s_axburst_eq0_reg => cmd_translator_0_n_5, + s_axburst_eq0_reg_0 => cmd_translator_0_n_6, + s_axburst_eq1_reg => next_pending_r_reg, + sel_first => \^sel_first\, + sel_first_i => sel_first_i, + sel_first_reg => aw_cmd_fsm_0_n_23, + sel_first_reg_0 => aw_cmd_fsm_0_n_24, + sel_first_reg_1 => \^sel_first_0\, + sel_first_reg_2 => cmd_translator_0_n_2, + si_rs_awvalid => si_rs_awvalid, + \wrap_boundary_axaddr_r_reg[11]\(11) => aw_cmd_fsm_0_n_26, + \wrap_boundary_axaddr_r_reg[11]\(10) => aw_cmd_fsm_0_n_27, + \wrap_boundary_axaddr_r_reg[11]\(9) => aw_cmd_fsm_0_n_28, + \wrap_boundary_axaddr_r_reg[11]\(8) => aw_cmd_fsm_0_n_29, + \wrap_boundary_axaddr_r_reg[11]\(7) => aw_cmd_fsm_0_n_30, + \wrap_boundary_axaddr_r_reg[11]\(6) => aw_cmd_fsm_0_n_31, + \wrap_boundary_axaddr_r_reg[11]\(5) => aw_cmd_fsm_0_n_32, + \wrap_boundary_axaddr_r_reg[11]\(4) => aw_cmd_fsm_0_n_33, + \wrap_boundary_axaddr_r_reg[11]\(3) => aw_cmd_fsm_0_n_34, + \wrap_boundary_axaddr_r_reg[11]\(2) => aw_cmd_fsm_0_n_35, + \wrap_boundary_axaddr_r_reg[11]\(1) => aw_cmd_fsm_0_n_36, + \wrap_boundary_axaddr_r_reg[11]\(0) => aw_cmd_fsm_0_n_37, + \wrap_second_len_r_reg[3]\(3 downto 0) => \wrap_cmd_0/wrap_second_len\(3 downto 0), + \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_cmd_0/wrap_second_len_r\(3 downto 0), + \wrap_second_len_r_reg[3]_1\ => \wrap_second_len_r_reg[3]\ + ); +cmd_translator_0: entity work.NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_cmd_translator + port map ( + D(3 downto 0) => \wrap_cmd_0/axaddr_offset\(3 downto 0), + E(0) => aw_cmd_fsm_0_n_22, + Q(1 downto 0) => \^q\(1 downto 0), + S(3 downto 0) => S(3 downto 0), + aclk => aclk, + axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), + \axaddr_incr_reg[11]\(11 downto 0) => \axaddr_incr_reg[11]\(11 downto 0), + \axaddr_offset_r_reg[3]\(3 downto 0) => \wrap_cmd_0/axaddr_offset_r\(3 downto 0), + axaddr_wrap0(11 downto 0) => axaddr_wrap0(11 downto 0), + \axaddr_wrap_reg[0]\ => aw_cmd_fsm_0_n_11, + \axaddr_wrap_reg[11]\(11 downto 0) => \axaddr_wrap_reg[11]\(11 downto 0), + \axaddr_wrap_reg[11]_0\(11) => aw_cmd_fsm_0_n_26, + \axaddr_wrap_reg[11]_0\(10) => aw_cmd_fsm_0_n_27, + \axaddr_wrap_reg[11]_0\(9) => aw_cmd_fsm_0_n_28, + \axaddr_wrap_reg[11]_0\(8) => aw_cmd_fsm_0_n_29, + \axaddr_wrap_reg[11]_0\(7) => aw_cmd_fsm_0_n_30, + \axaddr_wrap_reg[11]_0\(6) => aw_cmd_fsm_0_n_31, + \axaddr_wrap_reg[11]_0\(5) => aw_cmd_fsm_0_n_32, + \axaddr_wrap_reg[11]_0\(4) => aw_cmd_fsm_0_n_33, + \axaddr_wrap_reg[11]_0\(3) => aw_cmd_fsm_0_n_34, + \axaddr_wrap_reg[11]_0\(2) => aw_cmd_fsm_0_n_35, + \axaddr_wrap_reg[11]_0\(1) => aw_cmd_fsm_0_n_36, + \axaddr_wrap_reg[11]_0\(0) => aw_cmd_fsm_0_n_37, + \axaddr_wrap_reg[3]\(3 downto 0) => \axaddr_wrap_reg[3]\(3 downto 0), + \axlen_cnt_reg[0]\ => cmd_translator_0_n_44, + \axlen_cnt_reg[2]\ => cmd_translator_0_n_6, + \axlen_cnt_reg[3]\(15 downto 4) => \s_awid_r_reg[11]_0\(18 downto 7), + \axlen_cnt_reg[3]\(3 downto 0) => \s_awid_r_reg[11]_0\(3 downto 0), + \axlen_cnt_reg[3]_0\ => \^fsm_sequential_state_reg[0]\, + \axlen_cnt_reg[5]\ => cmd_translator_0_n_5, + \axlen_cnt_reg[5]_0\ => aw_cmd_fsm_0_n_10, + \m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0), + \next\ => \next\, + next_pending_r => \incr_cmd_0/next_pending_r\, + next_pending_r_0 => \wrap_cmd_0/next_pending_r\, + next_pending_r_reg => next_pending_r_reg, + s_axburst_eq0_reg_0 => aw_cmd_fsm_0_n_19, + s_axburst_eq1_reg_0 => cmd_translator_0_n_43, + s_axburst_eq1_reg_1 => aw_cmd_fsm_0_n_21, + sel_first => \^sel_first\, + sel_first_i => sel_first_i, + sel_first_reg_0 => cmd_translator_0_n_2, + sel_first_reg_1 => \^sel_first_0\, + sel_first_reg_2 => aw_cmd_fsm_0_n_24, + sel_first_reg_3 => aw_cmd_fsm_0_n_23, + si_rs_awvalid => si_rs_awvalid, + \wrap_boundary_axaddr_r_reg[11]\(11 downto 0) => wrap_boundary_axaddr_r(11 downto 0), + \wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => D(6 downto 0), + \wrap_cnt_r_reg[3]\(3 downto 2) => wrap_cnt(3 downto 2), + \wrap_cnt_r_reg[3]\(1) => aw_cmd_fsm_0_n_2, + \wrap_cnt_r_reg[3]\(0) => aw_cmd_fsm_0_n_3, + \wrap_second_len_r_reg[3]\(3 downto 0) => \wrap_cmd_0/wrap_second_len_r\(3 downto 0), + \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_cmd_0/wrap_second_len\(3 downto 0) + ); +\s_awid_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_awid_r_reg[11]_0\(19), + Q => \in\(4), + R => '0' + ); +\s_awid_r_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_awid_r_reg[11]_0\(29), + Q => \in\(14), + R => '0' + ); +\s_awid_r_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_awid_r_reg[11]_0\(30), + Q => \in\(15), + R => '0' + ); +\s_awid_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_awid_r_reg[11]_0\(20), + Q => \in\(5), + R => '0' + ); +\s_awid_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_awid_r_reg[11]_0\(21), + Q => \in\(6), + R => '0' + ); +\s_awid_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_awid_r_reg[11]_0\(22), + Q => \in\(7), + R => '0' + ); +\s_awid_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_awid_r_reg[11]_0\(23), + Q => \in\(8), + R => '0' + ); +\s_awid_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_awid_r_reg[11]_0\(24), + Q => \in\(9), + R => '0' + ); +\s_awid_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_awid_r_reg[11]_0\(25), + Q => \in\(10), + R => '0' + ); +\s_awid_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_awid_r_reg[11]_0\(26), + Q => \in\(11), + R => '0' + ); +\s_awid_r_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_awid_r_reg[11]_0\(27), + Q => \in\(12), + R => '0' + ); +\s_awid_r_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_awid_r_reg[11]_0\(28), + Q => \in\(13), + R => '0' + ); +\s_awlen_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_awid_r_reg[11]_0\(15), + Q => \in\(0), + R => '0' + ); +\s_awlen_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_awid_r_reg[11]_0\(16), + Q => \in\(1), + R => '0' + ); +\s_awlen_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_awid_r_reg[11]_0\(17), + Q => \in\(2), + R => '0' + ); +\s_awlen_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_awid_r_reg[11]_0\(18), + Q => \in\(3), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s is + port ( + s_axi_rvalid : out STD_LOGIC; + s_axi_awready : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 22 downto 0 ); + s_axi_arready : out STD_LOGIC; + \m_payload_i_reg[34]\ : out STD_LOGIC_VECTOR ( 22 downto 0 ); + s_axi_bvalid : out STD_LOGIC; + \m_payload_i_reg[13]\ : out STD_LOGIC_VECTOR ( 13 downto 0 ); + \m_payload_i_reg[46]\ : out STD_LOGIC_VECTOR ( 46 downto 0 ); + m_axi_awvalid : out STD_LOGIC; + m_axi_bready : out STD_LOGIC; + m_axi_arvalid : out STD_LOGIC; + m_axi_rready : out STD_LOGIC; + m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_arready : in STD_LOGIC; + s_axi_rready : in STD_LOGIC; + s_axi_awvalid : in STD_LOGIC; + aclk : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); + s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_awready : in STD_LOGIC; + m_axi_bvalid : in STD_LOGIC; + m_axi_rvalid : in STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_arvalid : in STD_LOGIC; + aresetn : in STD_LOGIC + ); +end NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s; + +architecture STRUCTURE of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s is + signal \RD.ar_channel_0_n_1\ : STD_LOGIC; + signal \RD.ar_channel_0_n_10\ : STD_LOGIC; + signal \RD.ar_channel_0_n_11\ : STD_LOGIC; + signal \RD.ar_channel_0_n_12\ : STD_LOGIC; + signal \RD.ar_channel_0_n_13\ : STD_LOGIC; + signal \RD.ar_channel_0_n_14\ : STD_LOGIC; + signal \RD.ar_channel_0_n_15\ : STD_LOGIC; + signal \RD.ar_channel_0_n_16\ : STD_LOGIC; + signal \RD.ar_channel_0_n_17\ : STD_LOGIC; + signal \RD.ar_channel_0_n_18\ : STD_LOGIC; + signal \RD.ar_channel_0_n_19\ : STD_LOGIC; + signal \RD.ar_channel_0_n_20\ : STD_LOGIC; + signal \RD.ar_channel_0_n_21\ : STD_LOGIC; + signal \RD.ar_channel_0_n_22\ : STD_LOGIC; + signal \RD.ar_channel_0_n_23\ : STD_LOGIC; + signal \RD.ar_channel_0_n_24\ : STD_LOGIC; + signal \RD.ar_channel_0_n_25\ : STD_LOGIC; + signal \RD.ar_channel_0_n_26\ : STD_LOGIC; + signal \RD.ar_channel_0_n_27\ : STD_LOGIC; + signal \RD.ar_channel_0_n_28\ : STD_LOGIC; + signal \RD.ar_channel_0_n_4\ : STD_LOGIC; + signal \RD.ar_channel_0_n_47\ : STD_LOGIC; + signal \RD.ar_channel_0_n_48\ : STD_LOGIC; + signal \RD.ar_channel_0_n_49\ : STD_LOGIC; + signal \RD.ar_channel_0_n_5\ : STD_LOGIC; + signal \RD.ar_channel_0_n_50\ : STD_LOGIC; + signal \RD.ar_channel_0_n_6\ : STD_LOGIC; + signal \RD.ar_channel_0_n_7\ : STD_LOGIC; + signal \RD.ar_channel_0_n_8\ : STD_LOGIC; + signal \RD.ar_channel_0_n_9\ : STD_LOGIC; + signal \RD.r_channel_0_n_0\ : STD_LOGIC; + signal \RD.r_channel_0_n_1\ : STD_LOGIC; + signal SI_REG_n_10 : STD_LOGIC; + signal SI_REG_n_11 : STD_LOGIC; + signal SI_REG_n_128 : STD_LOGIC; + signal SI_REG_n_129 : STD_LOGIC; + signal SI_REG_n_130 : STD_LOGIC; + signal SI_REG_n_131 : STD_LOGIC; + signal SI_REG_n_144 : STD_LOGIC; + signal SI_REG_n_145 : STD_LOGIC; + signal SI_REG_n_146 : STD_LOGIC; + signal SI_REG_n_147 : STD_LOGIC; + signal SI_REG_n_148 : STD_LOGIC; + signal SI_REG_n_149 : STD_LOGIC; + signal SI_REG_n_150 : STD_LOGIC; + signal SI_REG_n_151 : STD_LOGIC; + signal SI_REG_n_152 : STD_LOGIC; + signal SI_REG_n_153 : STD_LOGIC; + signal SI_REG_n_154 : STD_LOGIC; + signal SI_REG_n_155 : STD_LOGIC; + signal SI_REG_n_156 : STD_LOGIC; + signal SI_REG_n_157 : STD_LOGIC; + signal SI_REG_n_158 : STD_LOGIC; + signal SI_REG_n_160 : STD_LOGIC; + signal SI_REG_n_161 : STD_LOGIC; + signal SI_REG_n_162 : STD_LOGIC; + signal SI_REG_n_163 : STD_LOGIC; + signal SI_REG_n_164 : STD_LOGIC; + signal SI_REG_n_165 : STD_LOGIC; + signal SI_REG_n_166 : STD_LOGIC; + signal SI_REG_n_167 : STD_LOGIC; + signal SI_REG_n_168 : STD_LOGIC; + signal SI_REG_n_169 : STD_LOGIC; + signal SI_REG_n_170 : STD_LOGIC; + signal SI_REG_n_171 : STD_LOGIC; + signal SI_REG_n_172 : STD_LOGIC; + signal SI_REG_n_173 : STD_LOGIC; + signal SI_REG_n_174 : STD_LOGIC; + signal SI_REG_n_175 : STD_LOGIC; + signal SI_REG_n_176 : STD_LOGIC; + signal SI_REG_n_177 : STD_LOGIC; + signal SI_REG_n_178 : STD_LOGIC; + signal SI_REG_n_179 : STD_LOGIC; + signal SI_REG_n_180 : STD_LOGIC; + signal SI_REG_n_181 : STD_LOGIC; + signal SI_REG_n_182 : STD_LOGIC; + signal SI_REG_n_183 : STD_LOGIC; + signal SI_REG_n_184 : STD_LOGIC; + signal SI_REG_n_185 : STD_LOGIC; + signal SI_REG_n_186 : STD_LOGIC; + signal SI_REG_n_187 : STD_LOGIC; + signal SI_REG_n_188 : STD_LOGIC; + signal SI_REG_n_66 : STD_LOGIC; + signal SI_REG_n_67 : STD_LOGIC; + signal SI_REG_n_68 : STD_LOGIC; + signal SI_REG_n_69 : STD_LOGIC; + signal SI_REG_n_70 : STD_LOGIC; + signal SI_REG_n_71 : STD_LOGIC; + signal SI_REG_n_72 : STD_LOGIC; + signal SI_REG_n_73 : STD_LOGIC; + signal SI_REG_n_8 : STD_LOGIC; + signal SI_REG_n_9 : STD_LOGIC; + signal SI_REG_n_91 : STD_LOGIC; + signal SI_REG_n_92 : STD_LOGIC; + signal \WR.aw_channel_0_n_19\ : STD_LOGIC; + signal \WR.aw_channel_0_n_20\ : STD_LOGIC; + signal \WR.aw_channel_0_n_21\ : STD_LOGIC; + signal \WR.aw_channel_0_n_22\ : STD_LOGIC; + signal \WR.aw_channel_0_n_23\ : STD_LOGIC; + signal \WR.aw_channel_0_n_24\ : STD_LOGIC; + signal \WR.aw_channel_0_n_25\ : STD_LOGIC; + signal \WR.aw_channel_0_n_26\ : STD_LOGIC; + signal \WR.aw_channel_0_n_27\ : STD_LOGIC; + signal \WR.aw_channel_0_n_28\ : STD_LOGIC; + signal \WR.aw_channel_0_n_29\ : STD_LOGIC; + signal \WR.aw_channel_0_n_30\ : STD_LOGIC; + signal \WR.aw_channel_0_n_4\ : STD_LOGIC; + signal \WR.aw_channel_0_n_48\ : STD_LOGIC; + signal \WR.aw_channel_0_n_49\ : STD_LOGIC; + signal \WR.aw_channel_0_n_5\ : STD_LOGIC; + signal \WR.aw_channel_0_n_50\ : STD_LOGIC; + signal \WR.aw_channel_0_n_51\ : STD_LOGIC; + signal \ar.ar_pipe/m_valid_i0\ : STD_LOGIC; + signal \ar.ar_pipe/p_1_in\ : STD_LOGIC; + signal \ar.ar_pipe/s_ready_i0\ : STD_LOGIC; + signal \ar_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal areset_d1 : STD_LOGIC; + signal areset_d1_i_1_n_0 : STD_LOGIC; + signal \aw_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axaddr_incr : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal axaddr_wrap : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal axsize : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal b_awid : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal b_awlen : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal b_push : STD_LOGIC; + signal \bid_fifo_0/cnt_read\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \cmd_translator_0/incr_cmd_0/sel_first\ : STD_LOGIC; + signal \cmd_translator_0/incr_cmd_0/sel_first_0\ : STD_LOGIC; + signal r_push : STD_LOGIC; + signal r_rlast : STD_LOGIC; + signal s_arid : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal s_arid_r : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal s_awid : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \^s_axi_arready\ : STD_LOGIC; + signal sel_first : STD_LOGIC; + signal shandshake : STD_LOGIC; + signal si_rs_araddr : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal si_rs_arburst : STD_LOGIC_VECTOR ( 1 to 1 ); + signal si_rs_arlen : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal si_rs_arvalid : STD_LOGIC; + signal si_rs_awaddr : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal si_rs_awburst : STD_LOGIC_VECTOR ( 1 to 1 ); + signal si_rs_awlen : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal si_rs_awvalid : STD_LOGIC; + signal si_rs_bid : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal si_rs_bready : STD_LOGIC; + signal si_rs_bresp : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal si_rs_bvalid : STD_LOGIC; + signal si_rs_rdata : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal si_rs_rid : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal si_rs_rlast : STD_LOGIC; + signal si_rs_rready : STD_LOGIC; + signal si_rs_rresp : STD_LOGIC_VECTOR ( 1 downto 0 ); +begin + s_axi_arready <= \^s_axi_arready\; +\RD.ar_channel_0\: entity work.NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_ar_channel + port map ( + D(6) => SI_REG_n_176, + D(5) => SI_REG_n_177, + D(4) => SI_REG_n_178, + D(3) => SI_REG_n_179, + D(2) => SI_REG_n_180, + D(1) => SI_REG_n_181, + D(0) => SI_REG_n_182, + E(0) => \ar.ar_pipe/p_1_in\, + \FSM_sequential_state_reg[0]\ => \RD.r_channel_0_n_1\, + \FSM_sequential_state_reg[1]\ => \RD.ar_channel_0_n_4\, + O(3) => SI_REG_n_152, + O(2) => SI_REG_n_153, + O(1) => SI_REG_n_154, + O(0) => SI_REG_n_155, + Q(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0), + S(3) => SI_REG_n_128, + S(2) => SI_REG_n_129, + S(1) => SI_REG_n_130, + S(0) => SI_REG_n_131, + aclk => aclk, + areset_d1 => areset_d1, + \axaddr_incr_reg[11]\(11) => \RD.ar_channel_0_n_17\, + \axaddr_incr_reg[11]\(10) => \RD.ar_channel_0_n_18\, + \axaddr_incr_reg[11]\(9) => \RD.ar_channel_0_n_19\, + \axaddr_incr_reg[11]\(8) => \RD.ar_channel_0_n_20\, + \axaddr_incr_reg[11]\(7) => \RD.ar_channel_0_n_21\, + \axaddr_incr_reg[11]\(6) => \RD.ar_channel_0_n_22\, + \axaddr_incr_reg[11]\(5) => \RD.ar_channel_0_n_23\, + \axaddr_incr_reg[11]\(4) => \RD.ar_channel_0_n_24\, + \axaddr_incr_reg[11]\(3) => \RD.ar_channel_0_n_25\, + \axaddr_incr_reg[11]\(2) => \RD.ar_channel_0_n_26\, + \axaddr_incr_reg[11]\(1) => \RD.ar_channel_0_n_27\, + \axaddr_incr_reg[11]\(0) => \RD.ar_channel_0_n_28\, + \axaddr_incr_reg[3]\(3) => SI_REG_n_70, + \axaddr_incr_reg[3]\(2) => SI_REG_n_71, + \axaddr_incr_reg[3]\(1) => SI_REG_n_72, + \axaddr_incr_reg[3]\(0) => SI_REG_n_73, + \axaddr_incr_reg[3]_0\(3) => SI_REG_n_144, + \axaddr_incr_reg[3]_0\(2) => SI_REG_n_145, + \axaddr_incr_reg[3]_0\(1) => SI_REG_n_146, + \axaddr_incr_reg[3]_0\(0) => SI_REG_n_147, + \axaddr_incr_reg[7]\(3) => SI_REG_n_148, + \axaddr_incr_reg[7]\(2) => SI_REG_n_149, + \axaddr_incr_reg[7]\(1) => SI_REG_n_150, + \axaddr_incr_reg[7]\(0) => SI_REG_n_151, + \axaddr_offset_r_reg[0]\ => SI_REG_n_184, + \axaddr_offset_r_reg[1]\ => SI_REG_n_187, + \axaddr_offset_r_reg[1]_0\ => SI_REG_n_186, + \axaddr_offset_r_reg[2]\ => SI_REG_n_188, + \axaddr_offset_r_reg[2]_0\ => SI_REG_n_183, + \axaddr_offset_r_reg[3]\ => SI_REG_n_161, + \axaddr_wrap_reg[11]\(11) => \RD.ar_channel_0_n_5\, + \axaddr_wrap_reg[11]\(10) => \RD.ar_channel_0_n_6\, + \axaddr_wrap_reg[11]\(9) => \RD.ar_channel_0_n_7\, + \axaddr_wrap_reg[11]\(8) => \RD.ar_channel_0_n_8\, + \axaddr_wrap_reg[11]\(7) => \RD.ar_channel_0_n_9\, + \axaddr_wrap_reg[11]\(6) => \RD.ar_channel_0_n_10\, + \axaddr_wrap_reg[11]\(5) => \RD.ar_channel_0_n_11\, + \axaddr_wrap_reg[11]\(4) => \RD.ar_channel_0_n_12\, + \axaddr_wrap_reg[11]\(3) => \RD.ar_channel_0_n_13\, + \axaddr_wrap_reg[11]\(2) => \RD.ar_channel_0_n_14\, + \axaddr_wrap_reg[11]\(1) => \RD.ar_channel_0_n_15\, + \axaddr_wrap_reg[11]\(0) => \RD.ar_channel_0_n_16\, + \axlen_cnt_reg[3]\ => SI_REG_n_162, + m_axi_arready => m_axi_arready, + m_axi_arvalid => m_axi_arvalid, + \m_payload_i_reg[3]\(3) => \RD.ar_channel_0_n_47\, + \m_payload_i_reg[3]\(2) => \RD.ar_channel_0_n_48\, + \m_payload_i_reg[3]\(1) => \RD.ar_channel_0_n_49\, + \m_payload_i_reg[3]\(0) => \RD.ar_channel_0_n_50\, + m_valid_i0 => \ar.ar_pipe/m_valid_i0\, + m_valid_i_reg => \^s_axi_arready\, + next_pending_r_reg => SI_REG_n_163, + r_push => r_push, + r_rlast => r_rlast, + \s_arid_r_reg[11]_0\(11 downto 0) => s_arid_r(11 downto 0), + \s_arid_r_reg[11]_1\(30 downto 19) => s_arid(11 downto 0), + \s_arid_r_reg[11]_1\(18 downto 15) => si_rs_arlen(3 downto 0), + \s_arid_r_reg[11]_1\(14) => si_rs_arburst(1), + \s_arid_r_reg[11]_1\(13) => SI_REG_n_91, + \s_arid_r_reg[11]_1\(12) => SI_REG_n_92, + \s_arid_r_reg[11]_1\(11 downto 0) => si_rs_araddr(11 downto 0), + s_axi_arvalid => s_axi_arvalid, + s_ready_i0 => \ar.ar_pipe/s_ready_i0\, + sel_first => \cmd_translator_0/incr_cmd_0/sel_first\, + sel_first_reg => \RD.ar_channel_0_n_1\, + si_rs_arvalid => si_rs_arvalid, + \wrap_second_len_r_reg[3]\ => SI_REG_n_160 + ); +\RD.r_channel_0\: entity work.NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_r_channel + port map ( + D(11 downto 0) => s_arid_r(11 downto 0), + aclk => aclk, + areset_d1 => areset_d1, + \cnt_read_reg[2]\ => \RD.r_channel_0_n_0\, + \cnt_read_reg[4]\ => \RD.r_channel_0_n_1\, + \cnt_read_reg[4]_0\ => SI_REG_n_164, + \in\(33 downto 0) => \in\(33 downto 0), + m_axi_rready => m_axi_rready, + m_axi_rvalid => m_axi_rvalid, + \out\(33 downto 32) => si_rs_rresp(1 downto 0), + \out\(31 downto 0) => si_rs_rdata(31 downto 0), + r_push => r_push, + r_push_r_reg_0(12 downto 1) => si_rs_rid(11 downto 0), + r_push_r_reg_0(0) => si_rs_rlast, + r_rlast => r_rlast, + si_rs_rready => si_rs_rready + ); +SI_REG: entity work.NewExtInst_TOP_auto_pc_0_axi_register_slice_v2_1_29_axi_register_slice + port map ( + D(6) => SI_REG_n_165, + D(5) => SI_REG_n_166, + D(4) => SI_REG_n_167, + D(3) => SI_REG_n_168, + D(2) => SI_REG_n_169, + D(1) => SI_REG_n_170, + D(0) => SI_REG_n_171, + E(0) => \WR.aw_channel_0_n_5\, + \FSM_sequential_state_reg[0]\ => SI_REG_n_157, + \FSM_sequential_state_reg[1]\ => SI_REG_n_160, + O(3) => SI_REG_n_152, + O(2) => SI_REG_n_153, + O(1) => SI_REG_n_154, + O(0) => SI_REG_n_155, + Q(11) => \WR.aw_channel_0_n_19\, + Q(10) => \WR.aw_channel_0_n_20\, + Q(9) => \WR.aw_channel_0_n_21\, + Q(8) => \WR.aw_channel_0_n_22\, + Q(7) => \WR.aw_channel_0_n_23\, + Q(6) => \WR.aw_channel_0_n_24\, + Q(5) => \WR.aw_channel_0_n_25\, + Q(4) => \WR.aw_channel_0_n_26\, + Q(3) => \WR.aw_channel_0_n_27\, + Q(2) => \WR.aw_channel_0_n_28\, + Q(1) => \WR.aw_channel_0_n_29\, + Q(0) => \WR.aw_channel_0_n_30\, + S(3) => SI_REG_n_8, + S(2) => SI_REG_n_9, + S(1) => SI_REG_n_10, + S(0) => SI_REG_n_11, + aclk => aclk, + aresetn => aresetn, + axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), + \axaddr_incr_reg[3]\(3) => SI_REG_n_70, + \axaddr_incr_reg[3]\(2) => SI_REG_n_71, + \axaddr_incr_reg[3]\(1) => SI_REG_n_72, + \axaddr_incr_reg[3]\(0) => SI_REG_n_73, + \axaddr_incr_reg[3]_0\(3) => \WR.aw_channel_0_n_48\, + \axaddr_incr_reg[3]_0\(2) => \WR.aw_channel_0_n_49\, + \axaddr_incr_reg[3]_0\(1) => \WR.aw_channel_0_n_50\, + \axaddr_incr_reg[3]_0\(0) => \WR.aw_channel_0_n_51\, + \axaddr_incr_reg[3]_1\(3) => \RD.ar_channel_0_n_47\, + \axaddr_incr_reg[3]_1\(2) => \RD.ar_channel_0_n_48\, + \axaddr_incr_reg[3]_1\(1) => \RD.ar_channel_0_n_49\, + \axaddr_incr_reg[3]_1\(0) => \RD.ar_channel_0_n_50\, + \axaddr_wrap_reg[3]\(3) => SI_REG_n_66, + \axaddr_wrap_reg[3]\(2) => SI_REG_n_67, + \axaddr_wrap_reg[3]\(1) => SI_REG_n_68, + \axaddr_wrap_reg[3]\(0) => SI_REG_n_69, + \axaddr_wrap_reg[3]_0\(3) => SI_REG_n_128, + \axaddr_wrap_reg[3]_0\(2) => SI_REG_n_129, + \axaddr_wrap_reg[3]_0\(1) => SI_REG_n_130, + \axaddr_wrap_reg[3]_0\(0) => SI_REG_n_131, + \axlen_cnt_reg[3]\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0), + b_push => b_push, + m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), + \m_axi_araddr[11]\(11) => \RD.ar_channel_0_n_17\, + \m_axi_araddr[11]\(10) => \RD.ar_channel_0_n_18\, + \m_axi_araddr[11]\(9) => \RD.ar_channel_0_n_19\, + \m_axi_araddr[11]\(8) => \RD.ar_channel_0_n_20\, + \m_axi_araddr[11]\(7) => \RD.ar_channel_0_n_21\, + \m_axi_araddr[11]\(6) => \RD.ar_channel_0_n_22\, + \m_axi_araddr[11]\(5) => \RD.ar_channel_0_n_23\, + \m_axi_araddr[11]\(4) => \RD.ar_channel_0_n_24\, + \m_axi_araddr[11]\(3) => \RD.ar_channel_0_n_25\, + \m_axi_araddr[11]\(2) => \RD.ar_channel_0_n_26\, + \m_axi_araddr[11]\(1) => \RD.ar_channel_0_n_27\, + \m_axi_araddr[11]\(0) => \RD.ar_channel_0_n_28\, + \m_axi_araddr[11]_0\(11) => \RD.ar_channel_0_n_5\, + \m_axi_araddr[11]_0\(10) => \RD.ar_channel_0_n_6\, + \m_axi_araddr[11]_0\(9) => \RD.ar_channel_0_n_7\, + \m_axi_araddr[11]_0\(8) => \RD.ar_channel_0_n_8\, + \m_axi_araddr[11]_0\(7) => \RD.ar_channel_0_n_9\, + \m_axi_araddr[11]_0\(6) => \RD.ar_channel_0_n_10\, + \m_axi_araddr[11]_0\(5) => \RD.ar_channel_0_n_11\, + \m_axi_araddr[11]_0\(4) => \RD.ar_channel_0_n_12\, + \m_axi_araddr[11]_0\(3) => \RD.ar_channel_0_n_13\, + \m_axi_araddr[11]_0\(2) => \RD.ar_channel_0_n_14\, + \m_axi_araddr[11]_0\(1) => \RD.ar_channel_0_n_15\, + \m_axi_araddr[11]_0\(0) => \RD.ar_channel_0_n_16\, + \m_axi_araddr[11]_1\ => \RD.ar_channel_0_n_1\, + m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), + \m_axi_awaddr[11]\(11 downto 0) => axaddr_wrap(11 downto 0), + \m_payload_i_reg[0]\(0) => \ar.ar_pipe/p_1_in\, + \m_payload_i_reg[13]\(13 downto 0) => \m_payload_i_reg[13]\(13 downto 0), + \m_payload_i_reg[1]\ => SI_REG_n_173, + \m_payload_i_reg[1]_0\ => SI_REG_n_175, + \m_payload_i_reg[1]_1\ => SI_REG_n_184, + \m_payload_i_reg[1]_2\ => SI_REG_n_186, + \m_payload_i_reg[2]\ => SI_REG_n_174, + \m_payload_i_reg[2]_0\ => SI_REG_n_183, + \m_payload_i_reg[2]_1\ => SI_REG_n_185, + \m_payload_i_reg[2]_2\ => SI_REG_n_187, + \m_payload_i_reg[3]\(3) => SI_REG_n_144, + \m_payload_i_reg[3]\(2) => SI_REG_n_145, + \m_payload_i_reg[3]\(1) => SI_REG_n_146, + \m_payload_i_reg[3]\(0) => SI_REG_n_147, + \m_payload_i_reg[45]\ => SI_REG_n_156, + \m_payload_i_reg[45]_0\ => SI_REG_n_163, + \m_payload_i_reg[46]\(46 downto 0) => \m_payload_i_reg[46]\(46 downto 0), + \m_payload_i_reg[47]\ => SI_REG_n_162, + \m_payload_i_reg[4]\ => SI_REG_n_172, + \m_payload_i_reg[4]_0\ => SI_REG_n_188, + \m_payload_i_reg[5]\ => SI_REG_n_158, + \m_payload_i_reg[61]\(53 downto 42) => s_awid(11 downto 0), + \m_payload_i_reg[61]\(41 downto 38) => si_rs_awlen(3 downto 0), + \m_payload_i_reg[61]\(37) => si_rs_awburst(1), + \m_payload_i_reg[61]\(36 downto 35) => axsize(1 downto 0), + \m_payload_i_reg[61]\(34 downto 12) => Q(22 downto 0), + \m_payload_i_reg[61]\(11 downto 0) => si_rs_awaddr(11 downto 0), + \m_payload_i_reg[61]_0\(53 downto 42) => s_arid(11 downto 0), + \m_payload_i_reg[61]_0\(41 downto 38) => si_rs_arlen(3 downto 0), + \m_payload_i_reg[61]_0\(37) => si_rs_arburst(1), + \m_payload_i_reg[61]_0\(36) => SI_REG_n_91, + \m_payload_i_reg[61]_0\(35) => SI_REG_n_92, + \m_payload_i_reg[61]_0\(34 downto 12) => \m_payload_i_reg[34]\(22 downto 0), + \m_payload_i_reg[61]_0\(11 downto 0) => si_rs_araddr(11 downto 0), + \m_payload_i_reg[6]\ => SI_REG_n_161, + \m_payload_i_reg[6]_0\(6) => SI_REG_n_176, + \m_payload_i_reg[6]_0\(5) => SI_REG_n_177, + \m_payload_i_reg[6]_0\(4) => SI_REG_n_178, + \m_payload_i_reg[6]_0\(3) => SI_REG_n_179, + \m_payload_i_reg[6]_0\(2) => SI_REG_n_180, + \m_payload_i_reg[6]_0\(1) => SI_REG_n_181, + \m_payload_i_reg[6]_0\(0) => SI_REG_n_182, + \m_payload_i_reg[7]\(3) => SI_REG_n_148, + \m_payload_i_reg[7]\(2) => SI_REG_n_149, + \m_payload_i_reg[7]\(1) => SI_REG_n_150, + \m_payload_i_reg[7]\(0) => SI_REG_n_151, + m_valid_i0 => \ar.ar_pipe/m_valid_i0\, + m_valid_i_reg => s_axi_bvalid, + m_valid_i_reg_0 => s_axi_rvalid, + m_valid_i_reg_1 => \RD.r_channel_0_n_0\, + next_pending_r_reg => \WR.aw_channel_0_n_4\, + next_pending_r_reg_0 => \RD.ar_channel_0_n_4\, + \out\(11 downto 0) => si_rs_bid(11 downto 0), + s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), + s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), + s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), + s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), + s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), + s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0), + s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), + s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), + s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), + s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), + s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), + s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0), + s_axi_awvalid => s_axi_awvalid, + s_axi_bready => s_axi_bready, + s_axi_rready => s_axi_rready, + s_ready_i0 => \ar.ar_pipe/s_ready_i0\, + s_ready_i_reg => s_axi_awready, + s_ready_i_reg_0 => \^s_axi_arready\, + s_ready_i_reg_1 => SI_REG_n_164, + sel_first => sel_first, + sel_first_0 => \cmd_translator_0/incr_cmd_0/sel_first_0\, + sel_first_1 => \cmd_translator_0/incr_cmd_0/sel_first\, + shandshake => shandshake, + si_rs_arvalid => si_rs_arvalid, + si_rs_awvalid => si_rs_awvalid, + si_rs_bready => si_rs_bready, + si_rs_bvalid => si_rs_bvalid, + si_rs_rready => si_rs_rready, + \skid_buffer_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0), + \skid_buffer_reg[33]\(33 downto 32) => si_rs_rresp(1 downto 0), + \skid_buffer_reg[33]\(31 downto 0) => si_rs_rdata(31 downto 0), + \skid_buffer_reg[46]\(12 downto 1) => si_rs_rid(11 downto 0), + \skid_buffer_reg[46]\(0) => si_rs_rlast, + \wrap_second_len_r_reg[3]\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0) + ); +\WR.aw_channel_0\: entity work.NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_aw_channel + port map ( + D(6) => SI_REG_n_165, + D(5) => SI_REG_n_166, + D(4) => SI_REG_n_167, + D(3) => SI_REG_n_168, + D(2) => SI_REG_n_169, + D(1) => SI_REG_n_170, + D(0) => SI_REG_n_171, + E(0) => \WR.aw_channel_0_n_5\, + \FSM_sequential_state_reg[0]\ => \WR.aw_channel_0_n_4\, + Q(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0), + S(3) => SI_REG_n_8, + S(2) => SI_REG_n_9, + S(1) => SI_REG_n_10, + S(0) => SI_REG_n_11, + aclk => aclk, + areset_d1 => areset_d1, + axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), + \axaddr_incr_reg[11]\(11) => \WR.aw_channel_0_n_19\, + \axaddr_incr_reg[11]\(10) => \WR.aw_channel_0_n_20\, + \axaddr_incr_reg[11]\(9) => \WR.aw_channel_0_n_21\, + \axaddr_incr_reg[11]\(8) => \WR.aw_channel_0_n_22\, + \axaddr_incr_reg[11]\(7) => \WR.aw_channel_0_n_23\, + \axaddr_incr_reg[11]\(6) => \WR.aw_channel_0_n_24\, + \axaddr_incr_reg[11]\(5) => \WR.aw_channel_0_n_25\, + \axaddr_incr_reg[11]\(4) => \WR.aw_channel_0_n_26\, + \axaddr_incr_reg[11]\(3) => \WR.aw_channel_0_n_27\, + \axaddr_incr_reg[11]\(2) => \WR.aw_channel_0_n_28\, + \axaddr_incr_reg[11]\(1) => \WR.aw_channel_0_n_29\, + \axaddr_incr_reg[11]\(0) => \WR.aw_channel_0_n_30\, + \axaddr_offset_r_reg[0]\ => SI_REG_n_175, + \axaddr_offset_r_reg[1]\ => SI_REG_n_185, + \axaddr_offset_r_reg[1]_0\ => SI_REG_n_173, + \axaddr_offset_r_reg[2]\ => SI_REG_n_172, + \axaddr_offset_r_reg[2]_0\ => SI_REG_n_174, + \axaddr_offset_r_reg[3]\ => SI_REG_n_158, + \axaddr_wrap_reg[11]\(11 downto 0) => axaddr_wrap(11 downto 0), + \axaddr_wrap_reg[3]\(3) => SI_REG_n_66, + \axaddr_wrap_reg[3]\(2) => SI_REG_n_67, + \axaddr_wrap_reg[3]\(1) => SI_REG_n_68, + \axaddr_wrap_reg[3]\(0) => SI_REG_n_69, + b_push => b_push, + cnt_read(1 downto 0) => \bid_fifo_0/cnt_read\(1 downto 0), + \in\(15 downto 4) => b_awid(11 downto 0), + \in\(3 downto 0) => b_awlen(3 downto 0), + m_axi_awready => m_axi_awready, + m_axi_awvalid => m_axi_awvalid, + \m_payload_i_reg[3]\(3) => \WR.aw_channel_0_n_48\, + \m_payload_i_reg[3]\(2) => \WR.aw_channel_0_n_49\, + \m_payload_i_reg[3]\(1) => \WR.aw_channel_0_n_50\, + \m_payload_i_reg[3]\(0) => \WR.aw_channel_0_n_51\, + next_pending_r_reg => SI_REG_n_156, + \s_awid_r_reg[11]_0\(30 downto 19) => s_awid(11 downto 0), + \s_awid_r_reg[11]_0\(18 downto 15) => si_rs_awlen(3 downto 0), + \s_awid_r_reg[11]_0\(14) => si_rs_awburst(1), + \s_awid_r_reg[11]_0\(13 downto 12) => axsize(1 downto 0), + \s_awid_r_reg[11]_0\(11 downto 0) => si_rs_awaddr(11 downto 0), + sel_first => sel_first, + sel_first_0 => \cmd_translator_0/incr_cmd_0/sel_first_0\, + si_rs_awvalid => si_rs_awvalid, + \wrap_second_len_r_reg[3]\ => SI_REG_n_157 + ); +\WR.b_channel_0\: entity work.NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s_b_channel + port map ( + aclk => aclk, + areset_d1 => areset_d1, + b_push => b_push, + cnt_read(1 downto 0) => \bid_fifo_0/cnt_read\(1 downto 0), + \in\(15 downto 4) => b_awid(11 downto 0), + \in\(3 downto 0) => b_awlen(3 downto 0), + m_axi_bready => m_axi_bready, + m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), + m_axi_bvalid => m_axi_bvalid, + \out\(11 downto 0) => si_rs_bid(11 downto 0), + \s_bresp_acc_reg[1]_0\(1 downto 0) => si_rs_bresp(1 downto 0), + shandshake => shandshake, + si_rs_bready => si_rs_bready, + si_rs_bvalid => si_rs_bvalid + ); +areset_d1_i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => aresetn, + O => areset_d1_i_1_n_0 + ); +areset_d1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => areset_d1_i_1_n_0, + Q => areset_d1, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter is + port ( + aclk : in STD_LOGIC; + aresetn : in STD_LOGIC; + s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wlast : in STD_LOGIC; + s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_arvalid : in STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rlast : out STD_LOGIC; + s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rvalid : out STD_LOGIC; + s_axi_rready : in STD_LOGIC; + m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awvalid : out STD_LOGIC; + m_axi_awready : in STD_LOGIC; + m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_wlast : out STD_LOGIC; + m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_wvalid : out STD_LOGIC; + m_axi_wready : in STD_LOGIC; + m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_bvalid : in STD_LOGIC; + m_axi_bready : out STD_LOGIC; + m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_arvalid : out STD_LOGIC; + m_axi_arready : in STD_LOGIC; + m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_rlast : in STD_LOGIC; + m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rvalid : in STD_LOGIC; + m_axi_rready : out STD_LOGIC + ); + attribute C_AXI_ADDR_WIDTH : integer; + attribute C_AXI_ADDR_WIDTH of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter : entity is 32; + attribute C_AXI_ARUSER_WIDTH : integer; + attribute C_AXI_ARUSER_WIDTH of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter : entity is 1; + attribute C_AXI_AWUSER_WIDTH : integer; + attribute C_AXI_AWUSER_WIDTH of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter : entity is 1; + attribute C_AXI_BUSER_WIDTH : integer; + attribute C_AXI_BUSER_WIDTH of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter : entity is 1; + attribute C_AXI_DATA_WIDTH : integer; + attribute C_AXI_DATA_WIDTH of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter : entity is 32; + attribute C_AXI_ID_WIDTH : integer; + attribute C_AXI_ID_WIDTH of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter : entity is 12; + attribute C_AXI_RUSER_WIDTH : integer; + attribute C_AXI_RUSER_WIDTH of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter : entity is 1; + attribute C_AXI_SUPPORTS_READ : integer; + attribute C_AXI_SUPPORTS_READ of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter : entity is 1; + attribute C_AXI_SUPPORTS_USER_SIGNALS : integer; + attribute C_AXI_SUPPORTS_USER_SIGNALS of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter : entity is 0; + attribute C_AXI_SUPPORTS_WRITE : integer; + attribute C_AXI_SUPPORTS_WRITE of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter : entity is 1; + attribute C_AXI_WUSER_WIDTH : integer; + attribute C_AXI_WUSER_WIDTH of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter : entity is 1; + attribute C_FAMILY : string; + attribute C_FAMILY of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter : entity is "zynq"; + attribute C_IGNORE_ID : integer; + attribute C_IGNORE_ID of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter : entity is 0; + attribute C_M_AXI_PROTOCOL : integer; + attribute C_M_AXI_PROTOCOL of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter : entity is 2; + attribute C_S_AXI_PROTOCOL : integer; + attribute C_S_AXI_PROTOCOL of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter : entity is 1; + attribute C_TRANSLATION_MODE : integer; + attribute C_TRANSLATION_MODE of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter : entity is 2; + attribute DowngradeIPIdentifiedWarnings : string; + attribute DowngradeIPIdentifiedWarnings of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter : entity is "yes"; + attribute P_AXI3 : integer; + attribute P_AXI3 of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter : entity is 1; + attribute P_AXI4 : integer; + attribute P_AXI4 of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter : entity is 0; + attribute P_AXILITE : integer; + attribute P_AXILITE of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter : entity is 2; + attribute P_AXILITE_SIZE : string; + attribute P_AXILITE_SIZE of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter : entity is "3'b010"; + attribute P_CONVERSION : integer; + attribute P_CONVERSION of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter : entity is 2; + attribute P_DECERR : string; + attribute P_DECERR of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter : entity is "2'b11"; + attribute P_INCR : string; + attribute P_INCR of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter : entity is "2'b01"; + attribute P_PROTECTION : integer; + attribute P_PROTECTION of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter : entity is 1; + attribute P_SLVERR : string; + attribute P_SLVERR of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter : entity is "2'b10"; +end NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter; + +architecture STRUCTURE of NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter is + signal \\ : STD_LOGIC; + signal \^m_axi_wready\ : STD_LOGIC; + signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^s_axi_wvalid\ : STD_LOGIC; +begin + \^m_axi_wready\ <= m_axi_wready; + \^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0); + \^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0); + \^s_axi_wvalid\ <= s_axi_wvalid; + m_axi_arburst(1) <= \\; + m_axi_arburst(0) <= \\; + m_axi_arcache(3) <= \\; + m_axi_arcache(2) <= \\; + m_axi_arcache(1) <= \\; + m_axi_arcache(0) <= \\; + m_axi_arid(11) <= \\; + m_axi_arid(10) <= \\; + m_axi_arid(9) <= \\; + m_axi_arid(8) <= \\; + m_axi_arid(7) <= \\; + m_axi_arid(6) <= \\; + m_axi_arid(5) <= \\; + m_axi_arid(4) <= \\; + m_axi_arid(3) <= \\; + m_axi_arid(2) <= \\; + m_axi_arid(1) <= \\; + m_axi_arid(0) <= \\; + m_axi_arlen(7) <= \\; + m_axi_arlen(6) <= \\; + m_axi_arlen(5) <= \\; + m_axi_arlen(4) <= \\; + m_axi_arlen(3) <= \\; + m_axi_arlen(2) <= \\; + m_axi_arlen(1) <= \\; + m_axi_arlen(0) <= \\; + m_axi_arlock(0) <= \\; + m_axi_arqos(3) <= \\; + m_axi_arqos(2) <= \\; + m_axi_arqos(1) <= \\; + m_axi_arqos(0) <= \\; + m_axi_arregion(3) <= \\; + m_axi_arregion(2) <= \\; + m_axi_arregion(1) <= \\; + m_axi_arregion(0) <= \\; + m_axi_arsize(2) <= \\; + m_axi_arsize(1) <= \\; + m_axi_arsize(0) <= \\; + m_axi_aruser(0) <= \\; + m_axi_awburst(1) <= \\; + m_axi_awburst(0) <= \\; + m_axi_awcache(3) <= \\; + m_axi_awcache(2) <= \\; + m_axi_awcache(1) <= \\; + m_axi_awcache(0) <= \\; + m_axi_awid(11) <= \\; + m_axi_awid(10) <= \\; + m_axi_awid(9) <= \\; + m_axi_awid(8) <= \\; + m_axi_awid(7) <= \\; + m_axi_awid(6) <= \\; + m_axi_awid(5) <= \\; + m_axi_awid(4) <= \\; + m_axi_awid(3) <= \\; + m_axi_awid(2) <= \\; + m_axi_awid(1) <= \\; + m_axi_awid(0) <= \\; + m_axi_awlen(7) <= \\; + m_axi_awlen(6) <= \\; + m_axi_awlen(5) <= \\; + m_axi_awlen(4) <= \\; + m_axi_awlen(3) <= \\; + m_axi_awlen(2) <= \\; + m_axi_awlen(1) <= \\; + m_axi_awlen(0) <= \\; + m_axi_awlock(0) <= \\; + m_axi_awqos(3) <= \\; + m_axi_awqos(2) <= \\; + m_axi_awqos(1) <= \\; + m_axi_awqos(0) <= \\; + m_axi_awregion(3) <= \\; + m_axi_awregion(2) <= \\; + m_axi_awregion(1) <= \\; + m_axi_awregion(0) <= \\; + m_axi_awsize(2) <= \\; + m_axi_awsize(1) <= \\; + m_axi_awsize(0) <= \\; + m_axi_awuser(0) <= \\; + m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0); + m_axi_wid(11) <= \\; + m_axi_wid(10) <= \\; + m_axi_wid(9) <= \\; + m_axi_wid(8) <= \\; + m_axi_wid(7) <= \\; + m_axi_wid(6) <= \\; + m_axi_wid(5) <= \\; + m_axi_wid(4) <= \\; + m_axi_wid(3) <= \\; + m_axi_wid(2) <= \\; + m_axi_wid(1) <= \\; + m_axi_wid(0) <= \\; + m_axi_wlast <= \\; + m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0); + m_axi_wuser(0) <= \\; + m_axi_wvalid <= \^s_axi_wvalid\; + s_axi_buser(0) <= \\; + s_axi_ruser(0) <= \\; + s_axi_wready <= \^m_axi_wready\; +GND: unisim.vcomponents.GND + port map ( + G => \\ + ); +\gen_axilite.gen_b2s_conv.axilite_b2s\: entity work.NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_b2s + port map ( + Q(22 downto 20) => m_axi_awprot(2 downto 0), + Q(19 downto 0) => m_axi_awaddr(31 downto 12), + aclk => aclk, + aresetn => aresetn, + \in\(33 downto 32) => m_axi_rresp(1 downto 0), + \in\(31 downto 0) => m_axi_rdata(31 downto 0), + m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), + m_axi_arready => m_axi_arready, + m_axi_arvalid => m_axi_arvalid, + m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), + m_axi_awready => m_axi_awready, + m_axi_awvalid => m_axi_awvalid, + m_axi_bready => m_axi_bready, + m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), + m_axi_bvalid => m_axi_bvalid, + m_axi_rready => m_axi_rready, + m_axi_rvalid => m_axi_rvalid, + \m_payload_i_reg[13]\(13 downto 2) => s_axi_bid(11 downto 0), + \m_payload_i_reg[13]\(1 downto 0) => s_axi_bresp(1 downto 0), + \m_payload_i_reg[34]\(22 downto 20) => m_axi_arprot(2 downto 0), + \m_payload_i_reg[34]\(19 downto 0) => m_axi_araddr(31 downto 12), + \m_payload_i_reg[46]\(46 downto 35) => s_axi_rid(11 downto 0), + \m_payload_i_reg[46]\(34) => s_axi_rlast, + \m_payload_i_reg[46]\(33 downto 32) => s_axi_rresp(1 downto 0), + \m_payload_i_reg[46]\(31 downto 0) => s_axi_rdata(31 downto 0), + s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), + s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), + s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), + s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), + s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), + s_axi_arready => s_axi_arready, + s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0), + s_axi_arvalid => s_axi_arvalid, + s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), + s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), + s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), + s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), + s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), + s_axi_awready => s_axi_awready, + s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0), + s_axi_awvalid => s_axi_awvalid, + s_axi_bready => s_axi_bready, + s_axi_bvalid => s_axi_bvalid, + s_axi_rready => s_axi_rready, + s_axi_rvalid => s_axi_rvalid + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_auto_pc_0 is + port ( + aclk : in STD_LOGIC; + aresetn : in STD_LOGIC; + s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wlast : in STD_LOGIC; + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arvalid : in STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rlast : out STD_LOGIC; + s_axi_rvalid : out STD_LOGIC; + s_axi_rready : in STD_LOGIC; + m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awvalid : out STD_LOGIC; + m_axi_awready : in STD_LOGIC; + m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_wvalid : out STD_LOGIC; + m_axi_wready : in STD_LOGIC; + m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_bvalid : in STD_LOGIC; + m_axi_bready : out STD_LOGIC; + m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arvalid : out STD_LOGIC; + m_axi_arready : in STD_LOGIC; + m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_rvalid : in STD_LOGIC; + m_axi_rready : out STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of NewExtInst_TOP_auto_pc_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of NewExtInst_TOP_auto_pc_0 : entity is "NewExtInst_TOP_auto_pc_0,axi_protocol_converter_v2_1_29_axi_protocol_converter,{}"; + attribute DowngradeIPIdentifiedWarnings : string; + attribute DowngradeIPIdentifiedWarnings of NewExtInst_TOP_auto_pc_0 : entity is "yes"; + attribute X_CORE_INFO : string; + attribute X_CORE_INFO of NewExtInst_TOP_auto_pc_0 : entity is "axi_protocol_converter_v2_1_29_axi_protocol_converter,Vivado 2023.2"; +end NewExtInst_TOP_auto_pc_0; + +architecture STRUCTURE of NewExtInst_TOP_auto_pc_0 is + signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC; + signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + attribute C_AXI_ADDR_WIDTH : integer; + attribute C_AXI_ADDR_WIDTH of inst : label is 32; + attribute C_AXI_ARUSER_WIDTH : integer; + attribute C_AXI_ARUSER_WIDTH of inst : label is 1; + attribute C_AXI_AWUSER_WIDTH : integer; + attribute C_AXI_AWUSER_WIDTH of inst : label is 1; + attribute C_AXI_BUSER_WIDTH : integer; + attribute C_AXI_BUSER_WIDTH of inst : label is 1; + attribute C_AXI_DATA_WIDTH : integer; + attribute C_AXI_DATA_WIDTH of inst : label is 32; + attribute C_AXI_ID_WIDTH : integer; + attribute C_AXI_ID_WIDTH of inst : label is 12; + attribute C_AXI_RUSER_WIDTH : integer; + attribute C_AXI_RUSER_WIDTH of inst : label is 1; + attribute C_AXI_SUPPORTS_READ : integer; + attribute C_AXI_SUPPORTS_READ of inst : label is 1; + attribute C_AXI_SUPPORTS_USER_SIGNALS : integer; + attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0; + attribute C_AXI_SUPPORTS_WRITE : integer; + attribute C_AXI_SUPPORTS_WRITE of inst : label is 1; + attribute C_AXI_WUSER_WIDTH : integer; + attribute C_AXI_WUSER_WIDTH of inst : label is 1; + attribute C_FAMILY : string; + attribute C_FAMILY of inst : label is "zynq"; + attribute C_IGNORE_ID : integer; + attribute C_IGNORE_ID of inst : label is 0; + attribute C_M_AXI_PROTOCOL : integer; + attribute C_M_AXI_PROTOCOL of inst : label is 2; + attribute C_S_AXI_PROTOCOL : integer; + attribute C_S_AXI_PROTOCOL of inst : label is 1; + attribute C_TRANSLATION_MODE : integer; + attribute C_TRANSLATION_MODE of inst : label is 2; + attribute DowngradeIPIdentifiedWarnings of inst : label is "yes"; + attribute P_AXI3 : integer; + attribute P_AXI3 of inst : label is 1; + attribute P_AXI4 : integer; + attribute P_AXI4 of inst : label is 0; + attribute P_AXILITE : integer; + attribute P_AXILITE of inst : label is 2; + attribute P_AXILITE_SIZE : string; + attribute P_AXILITE_SIZE of inst : label is "3'b010"; + attribute P_CONVERSION : integer; + attribute P_CONVERSION of inst : label is 2; + attribute P_DECERR : string; + attribute P_DECERR of inst : label is "2'b11"; + attribute P_INCR : string; + attribute P_INCR of inst : label is "2'b01"; + attribute P_PROTECTION : integer; + attribute P_PROTECTION of inst : label is 1; + attribute P_SLVERR : string; + attribute P_SLVERR of inst : label is "2'b10"; + attribute X_INTERFACE_INFO : string; + attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK CLK"; + attribute X_INTERFACE_PARAMETER : string; + attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0"; + attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST RST"; + attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT"; + attribute X_INTERFACE_INFO of m_axi_arready : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARREADY"; + attribute X_INTERFACE_INFO of m_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARVALID"; + attribute X_INTERFACE_INFO of m_axi_awready : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWREADY"; + attribute X_INTERFACE_INFO of m_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWVALID"; + attribute X_INTERFACE_INFO of m_axi_bready : signal is "xilinx.com:interface:aximm:1.0 M_AXI BREADY"; + attribute X_INTERFACE_INFO of m_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI BVALID"; + attribute X_INTERFACE_INFO of m_axi_rready : signal is "xilinx.com:interface:aximm:1.0 M_AXI RREADY"; + attribute X_INTERFACE_PARAMETER of m_axi_rready : signal is "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0"; + attribute X_INTERFACE_INFO of m_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI RVALID"; + attribute X_INTERFACE_INFO of m_axi_wready : signal is "xilinx.com:interface:aximm:1.0 M_AXI WREADY"; + attribute X_INTERFACE_INFO of m_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI WVALID"; + attribute X_INTERFACE_INFO of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY"; + attribute X_INTERFACE_INFO of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID"; + attribute X_INTERFACE_INFO of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY"; + attribute X_INTERFACE_INFO of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID"; + attribute X_INTERFACE_INFO of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY"; + attribute X_INTERFACE_INFO of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID"; + attribute X_INTERFACE_INFO of s_axi_rlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI RLAST"; + attribute X_INTERFACE_INFO of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; + attribute X_INTERFACE_PARAMETER of s_axi_rready : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0"; + attribute X_INTERFACE_INFO of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; + attribute X_INTERFACE_INFO of s_axi_wlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI WLAST"; + attribute X_INTERFACE_INFO of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY"; + attribute X_INTERFACE_INFO of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID"; + attribute X_INTERFACE_INFO of m_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARADDR"; + attribute X_INTERFACE_INFO of m_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARPROT"; + attribute X_INTERFACE_INFO of m_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWADDR"; + attribute X_INTERFACE_INFO of m_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWPROT"; + attribute X_INTERFACE_INFO of m_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI BRESP"; + attribute X_INTERFACE_INFO of m_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI RDATA"; + attribute X_INTERFACE_INFO of m_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI RRESP"; + attribute X_INTERFACE_INFO of m_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI WDATA"; + attribute X_INTERFACE_INFO of m_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 M_AXI WSTRB"; + attribute X_INTERFACE_INFO of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR"; + attribute X_INTERFACE_INFO of s_axi_arburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARBURST"; + attribute X_INTERFACE_INFO of s_axi_arcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE"; + attribute X_INTERFACE_INFO of s_axi_arid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARID"; + attribute X_INTERFACE_INFO of s_axi_arlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLEN"; + attribute X_INTERFACE_INFO of s_axi_arlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK"; + attribute X_INTERFACE_INFO of s_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARPROT"; + attribute X_INTERFACE_INFO of s_axi_arqos : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARQOS"; + attribute X_INTERFACE_INFO of s_axi_arsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE"; + attribute X_INTERFACE_INFO of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR"; + attribute X_INTERFACE_INFO of s_axi_awburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWBURST"; + attribute X_INTERFACE_INFO of s_axi_awcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE"; + attribute X_INTERFACE_INFO of s_axi_awid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWID"; + attribute X_INTERFACE_INFO of s_axi_awlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLEN"; + attribute X_INTERFACE_INFO of s_axi_awlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK"; + attribute X_INTERFACE_INFO of s_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWPROT"; + attribute X_INTERFACE_INFO of s_axi_awqos : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWQOS"; + attribute X_INTERFACE_INFO of s_axi_awsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE"; + attribute X_INTERFACE_INFO of s_axi_bid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BID"; + attribute X_INTERFACE_INFO of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP"; + attribute X_INTERFACE_INFO of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA"; + attribute X_INTERFACE_INFO of s_axi_rid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RID"; + attribute X_INTERFACE_INFO of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; + attribute X_INTERFACE_INFO of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA"; + attribute X_INTERFACE_INFO of s_axi_wid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WID"; + attribute X_INTERFACE_INFO of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB"; +begin +inst: entity work.NewExtInst_TOP_auto_pc_0_axi_protocol_converter_v2_1_29_axi_protocol_converter + port map ( + aclk => aclk, + aresetn => aresetn, + m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0), + m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0), + m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0), + m_axi_arid(11 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(11 downto 0), + m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0), + m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0), + m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0), + m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0), + m_axi_arready => m_axi_arready, + m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0), + m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0), + m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0), + m_axi_arvalid => m_axi_arvalid, + m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0), + m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0), + m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0), + m_axi_awid(11 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(11 downto 0), + m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0), + m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0), + m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0), + m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0), + m_axi_awready => m_axi_awready, + m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0), + m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0), + m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0), + m_axi_awvalid => m_axi_awvalid, + m_axi_bid(11 downto 0) => B"000000000000", + m_axi_bready => m_axi_bready, + m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), + m_axi_buser(0) => '0', + m_axi_bvalid => m_axi_bvalid, + m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0), + m_axi_rid(11 downto 0) => B"000000000000", + m_axi_rlast => '1', + m_axi_rready => m_axi_rready, + m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0), + m_axi_ruser(0) => '0', + m_axi_rvalid => m_axi_rvalid, + m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0), + m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0), + m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED, + m_axi_wready => m_axi_wready, + m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0), + m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0), + m_axi_wvalid => m_axi_wvalid, + s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), + s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), + s_axi_arcache(3 downto 0) => B"0000", + s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), + s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), + s_axi_arlock(1 downto 0) => B"00", + s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), + s_axi_arqos(3 downto 0) => B"0000", + s_axi_arready => s_axi_arready, + s_axi_arregion(3 downto 0) => B"0000", + s_axi_arsize(2) => '0', + s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0), + s_axi_aruser(0) => '0', + s_axi_arvalid => s_axi_arvalid, + s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), + s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), + s_axi_awcache(3 downto 0) => B"0000", + s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), + s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), + s_axi_awlock(1 downto 0) => B"00", + s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), + s_axi_awqos(3 downto 0) => B"0000", + s_axi_awready => s_axi_awready, + s_axi_awregion(3 downto 0) => B"0000", + s_axi_awsize(2) => '0', + s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0), + s_axi_awuser(0) => '0', + s_axi_awvalid => s_axi_awvalid, + s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0), + s_axi_bready => s_axi_bready, + s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0), + s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0), + s_axi_bvalid => s_axi_bvalid, + s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), + s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0), + s_axi_rlast => s_axi_rlast, + s_axi_rready => s_axi_rready, + s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0), + s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0), + s_axi_rvalid => s_axi_rvalid, + s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), + s_axi_wid(11 downto 0) => B"000000000000", + s_axi_wlast => '0', + s_axi_wready => s_axi_wready, + s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0), + s_axi_wuser(0) => '0', + s_axi_wvalid => s_axi_wvalid + ); +end STRUCTURE; diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_auto_pc_0/sim/NewExtInst_TOP_auto_pc_0.v b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_auto_pc_0/sim/NewExtInst_TOP_auto_pc_0.v new file mode 100644 index 0000000..3a0d3dc --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_auto_pc_0/sim/NewExtInst_TOP_auto_pc_0.v @@ -0,0 +1,354 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1 +// IP Revision: 29 + +`timescale 1ns/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module NewExtInst_TOP_auto_pc_0 ( + aclk, + aresetn, + s_axi_awid, + s_axi_awaddr, + s_axi_awlen, + s_axi_awsize, + s_axi_awburst, + s_axi_awlock, + s_axi_awcache, + s_axi_awprot, + s_axi_awqos, + s_axi_awvalid, + s_axi_awready, + s_axi_wid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wlast, + s_axi_wvalid, + s_axi_wready, + s_axi_bid, + s_axi_bresp, + s_axi_bvalid, + s_axi_bready, + s_axi_arid, + s_axi_araddr, + s_axi_arlen, + s_axi_arsize, + s_axi_arburst, + s_axi_arlock, + s_axi_arcache, + s_axi_arprot, + s_axi_arqos, + s_axi_arvalid, + s_axi_arready, + s_axi_rid, + s_axi_rdata, + s_axi_rresp, + s_axi_rlast, + s_axi_rvalid, + s_axi_rready, + m_axi_awaddr, + m_axi_awprot, + m_axi_awvalid, + m_axi_awready, + m_axi_wdata, + m_axi_wstrb, + m_axi_wvalid, + m_axi_wready, + m_axi_bresp, + m_axi_bvalid, + m_axi_bready, + m_axi_araddr, + m_axi_arprot, + m_axi_arvalid, + m_axi_arready, + m_axi_rdata, + m_axi_rresp, + m_axi_rvalid, + m_axi_rready +); + +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *) +input wire aclk; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *) +input wire aresetn; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) +input wire [11 : 0] s_axi_awid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) +input wire [31 : 0] s_axi_awaddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) +input wire [3 : 0] s_axi_awlen; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) +input wire [2 : 0] s_axi_awsize; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) +input wire [1 : 0] s_axi_awburst; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) +input wire [1 : 0] s_axi_awlock; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) +input wire [3 : 0] s_axi_awcache; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) +input wire [2 : 0] s_axi_awprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *) +input wire [3 : 0] s_axi_awqos; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) +input wire s_axi_awvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) +output wire s_axi_awready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *) +input wire [11 : 0] s_axi_wid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) +input wire [31 : 0] s_axi_wdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) +input wire [3 : 0] s_axi_wstrb; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) +input wire s_axi_wlast; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) +input wire s_axi_wvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) +output wire s_axi_wready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) +output wire [11 : 0] s_axi_bid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) +output wire [1 : 0] s_axi_bresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) +output wire s_axi_bvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) +input wire s_axi_bready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) +input wire [11 : 0] s_axi_arid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) +input wire [31 : 0] s_axi_araddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) +input wire [3 : 0] s_axi_arlen; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) +input wire [2 : 0] s_axi_arsize; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) +input wire [1 : 0] s_axi_arburst; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) +input wire [1 : 0] s_axi_arlock; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) +input wire [3 : 0] s_axi_arcache; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) +input wire [2 : 0] s_axi_arprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) +input wire [3 : 0] s_axi_arqos; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) +input wire s_axi_arvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) +output wire s_axi_arready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) +output wire [11 : 0] s_axi_rid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) +output wire [31 : 0] s_axi_rdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) +output wire [1 : 0] s_axi_rresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) +output wire s_axi_rlast; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) +output wire s_axi_rvalid; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, \ +RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) +input wire s_axi_rready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) +output wire [31 : 0] m_axi_awaddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) +output wire [2 : 0] m_axi_awprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) +output wire m_axi_awvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) +input wire m_axi_awready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) +output wire [31 : 0] m_axi_wdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) +output wire [3 : 0] m_axi_wstrb; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) +output wire m_axi_wvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) +input wire m_axi_wready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) +input wire [1 : 0] m_axi_bresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) +input wire m_axi_bvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) +output wire m_axi_bready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) +output wire [31 : 0] m_axi_araddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) +output wire [2 : 0] m_axi_arprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) +output wire m_axi_arvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) +input wire m_axi_arready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) +input wire [31 : 0] m_axi_rdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) +input wire [1 : 0] m_axi_rresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) +input wire m_axi_rvalid; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4\ +, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) +output wire m_axi_rready; + + axi_protocol_converter_v2_1_29_axi_protocol_converter #( + .C_FAMILY("zynq"), + .C_M_AXI_PROTOCOL(2), + .C_S_AXI_PROTOCOL(1), + .C_IGNORE_ID(0), + .C_AXI_ID_WIDTH(12), + .C_AXI_ADDR_WIDTH(32), + .C_AXI_DATA_WIDTH(32), + .C_AXI_SUPPORTS_WRITE(1), + .C_AXI_SUPPORTS_READ(1), + .C_AXI_SUPPORTS_USER_SIGNALS(0), + .C_AXI_AWUSER_WIDTH(1), + .C_AXI_ARUSER_WIDTH(1), + .C_AXI_WUSER_WIDTH(1), + .C_AXI_RUSER_WIDTH(1), + .C_AXI_BUSER_WIDTH(1), + .C_TRANSLATION_MODE(2) + ) inst ( + .aclk(aclk), + .aresetn(aresetn), + .s_axi_awid(s_axi_awid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awlen(s_axi_awlen), + .s_axi_awsize(s_axi_awsize), + .s_axi_awburst(s_axi_awburst), + .s_axi_awlock(s_axi_awlock), + .s_axi_awcache(s_axi_awcache), + .s_axi_awprot(s_axi_awprot), + .s_axi_awregion(4'H0), + .s_axi_awqos(s_axi_awqos), + .s_axi_awuser(1'H0), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_awready(s_axi_awready), + .s_axi_wid(s_axi_wid), + .s_axi_wdata(s_axi_wdata), + .s_axi_wstrb(s_axi_wstrb), + .s_axi_wlast(s_axi_wlast), + .s_axi_wuser(1'H0), + .s_axi_wvalid(s_axi_wvalid), + .s_axi_wready(s_axi_wready), + .s_axi_bid(s_axi_bid), + .s_axi_bresp(s_axi_bresp), + .s_axi_buser(), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_bready(s_axi_bready), + .s_axi_arid(s_axi_arid), + .s_axi_araddr(s_axi_araddr), + .s_axi_arlen(s_axi_arlen), + .s_axi_arsize(s_axi_arsize), + .s_axi_arburst(s_axi_arburst), + .s_axi_arlock(s_axi_arlock), + .s_axi_arcache(s_axi_arcache), + .s_axi_arprot(s_axi_arprot), + .s_axi_arregion(4'H0), + .s_axi_arqos(s_axi_arqos), + .s_axi_aruser(1'H0), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_arready(s_axi_arready), + .s_axi_rid(s_axi_rid), + .s_axi_rdata(s_axi_rdata), + .s_axi_rresp(s_axi_rresp), + .s_axi_rlast(s_axi_rlast), + .s_axi_ruser(), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_rready(s_axi_rready), + .m_axi_awid(), + .m_axi_awaddr(m_axi_awaddr), + .m_axi_awlen(), + .m_axi_awsize(), + .m_axi_awburst(), + .m_axi_awlock(), + .m_axi_awcache(), + .m_axi_awprot(m_axi_awprot), + .m_axi_awregion(), + .m_axi_awqos(), + .m_axi_awuser(), + .m_axi_awvalid(m_axi_awvalid), + .m_axi_awready(m_axi_awready), + .m_axi_wid(), + .m_axi_wdata(m_axi_wdata), + .m_axi_wstrb(m_axi_wstrb), + .m_axi_wlast(), + .m_axi_wuser(), + .m_axi_wvalid(m_axi_wvalid), + .m_axi_wready(m_axi_wready), + .m_axi_bid(12'H000), + .m_axi_bresp(m_axi_bresp), + .m_axi_buser(1'H0), + .m_axi_bvalid(m_axi_bvalid), + .m_axi_bready(m_axi_bready), + .m_axi_arid(), + .m_axi_araddr(m_axi_araddr), + .m_axi_arlen(), + .m_axi_arsize(), + .m_axi_arburst(), + .m_axi_arlock(), + .m_axi_arcache(), + .m_axi_arprot(m_axi_arprot), + .m_axi_arregion(), + .m_axi_arqos(), + .m_axi_aruser(), + .m_axi_arvalid(m_axi_arvalid), + .m_axi_arready(m_axi_arready), + .m_axi_rid(12'H000), + .m_axi_rdata(m_axi_rdata), + .m_axi_rresp(m_axi_rresp), + .m_axi_rlast(1'H1), + .m_axi_ruser(1'H0), + .m_axi_rvalid(m_axi_rvalid), + .m_axi_rready(m_axi_rready) + ); +endmodule diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.v b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.v new file mode 100644 index 0000000..cd376db --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.v @@ -0,0 +1,89 @@ + +// file: NewExtInst_TOP_clk_wiz_0_0.v +// (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// clk_out1__100.00000______0.000______50.0______226.965____237.727 +// +//---------------------------------------------------------------------------- +// Input Clock Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// __primary__________25.000____________0.010 + +`timescale 1ps/1ps + +(* CORE_GENERATION_INFO = "NewExtInst_TOP_clk_wiz_0_0,clk_wiz_v6_0_13_0_0,{component_name=NewExtInst_TOP_clk_wiz_0_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=40.000,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) + +module NewExtInst_TOP_clk_wiz_0_0 + ( + // Clock out ports + output clk_out1, + // Status and control signals + input reset, + output locked, + // Clock in ports + input clk_in1 + ); + + NewExtInst_TOP_clk_wiz_0_0_clk_wiz inst + ( + // Clock out ports + .clk_out1(clk_out1), + // Status and control signals + .reset(reset), + .locked(locked), + // Clock in ports + .clk_in1(clk_in1) + ); + +endmodule diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_clk_wiz.v b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_clk_wiz.v new file mode 100644 index 0000000..19dfa41 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_clk_wiz.v @@ -0,0 +1,201 @@ + +// file: NewExtInst_TOP_clk_wiz_0_0.v +// (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// clk_out1__100.00000______0.000______50.0______226.965____237.727 +// +//---------------------------------------------------------------------------- +// Input Clock Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// __primary__________25.000____________0.010 + +`timescale 1ps/1ps + +module NewExtInst_TOP_clk_wiz_0_0_clk_wiz + + (// Clock in ports + // Clock out ports + output clk_out1, + // Status and control signals + input reset, + output locked, + input clk_in1 + ); + // Input buffering + //------------------------------------ +wire clk_in1_NewExtInst_TOP_clk_wiz_0_0; +wire clk_in2_NewExtInst_TOP_clk_wiz_0_0; + IBUF clkin1_ibufg + (.O (clk_in1_NewExtInst_TOP_clk_wiz_0_0), + .I (clk_in1)); + + + + + // Clocking PRIMITIVE + //------------------------------------ + + // Instantiation of the MMCM PRIMITIVE + // * Unused inputs are tied off + // * Unused outputs are labeled unused + + wire clk_out1_NewExtInst_TOP_clk_wiz_0_0; + wire clk_out2_NewExtInst_TOP_clk_wiz_0_0; + wire clk_out3_NewExtInst_TOP_clk_wiz_0_0; + wire clk_out4_NewExtInst_TOP_clk_wiz_0_0; + wire clk_out5_NewExtInst_TOP_clk_wiz_0_0; + wire clk_out6_NewExtInst_TOP_clk_wiz_0_0; + wire clk_out7_NewExtInst_TOP_clk_wiz_0_0; + + wire [15:0] do_unused; + wire drdy_unused; + wire psdone_unused; + wire locked_int; + wire clkfbout_NewExtInst_TOP_clk_wiz_0_0; + wire clkfbout_buf_NewExtInst_TOP_clk_wiz_0_0; + wire clkfboutb_unused; + wire clkout0b_unused; + wire clkout1_unused; + wire clkout1b_unused; + wire clkout2_unused; + wire clkout2b_unused; + wire clkout3_unused; + wire clkout3b_unused; + wire clkout4_unused; + wire clkout5_unused; + wire clkout6_unused; + wire clkfbstopped_unused; + wire clkinstopped_unused; + wire reset_high; + + MMCME2_ADV + #(.BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (1), + .CLKFBOUT_MULT_F (40.000), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (10.000), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (40.000)) + mmcm_adv_inst + // Output clocks + ( + .CLKFBOUT (clkfbout_NewExtInst_TOP_clk_wiz_0_0), + .CLKFBOUTB (clkfboutb_unused), + .CLKOUT0 (clk_out1_NewExtInst_TOP_clk_wiz_0_0), + .CLKOUT0B (clkout0b_unused), + .CLKOUT1 (clkout1_unused), + .CLKOUT1B (clkout1b_unused), + .CLKOUT2 (clkout2_unused), + .CLKOUT2B (clkout2b_unused), + .CLKOUT3 (clkout3_unused), + .CLKOUT3B (clkout3b_unused), + .CLKOUT4 (clkout4_unused), + .CLKOUT5 (clkout5_unused), + .CLKOUT6 (clkout6_unused), + // Input clock control + .CLKFBIN (clkfbout_buf_NewExtInst_TOP_clk_wiz_0_0), + .CLKIN1 (clk_in1_NewExtInst_TOP_clk_wiz_0_0), + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (do_unused), + .DRDY (drdy_unused), + .DWE (1'b0), + // Ports for dynamic phase shift + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (psdone_unused), + // Other control and status signals + .LOCKED (locked_int), + .CLKINSTOPPED (clkinstopped_unused), + .CLKFBSTOPPED (clkfbstopped_unused), + .PWRDWN (1'b0), + .RST (reset_high)); + assign reset_high = reset; + + assign locked = locked_int; +// Clock Monitor clock assigning +//-------------------------------------- + // Output buffering + //----------------------------------- + + BUFG clkf_buf + (.O (clkfbout_buf_NewExtInst_TOP_clk_wiz_0_0), + .I (clkfbout_NewExtInst_TOP_clk_wiz_0_0)); + + + + + + + BUFG clkout1_buf + (.O (clk_out1), + .I (clk_out1_NewExtInst_TOP_clk_wiz_0_0)); + + + + +endmodule diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_sim_netlist.v b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_sim_netlist.v new file mode 100644 index 0000000..bdb99f2 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_sim_netlist.v @@ -0,0 +1,258 @@ +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +// Date : Fri May 15 15:26:59 2026 +// Host : mkb running 64-bit unknown +// Command : write_verilog -force -mode funcsim +// /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_sim_netlist.v +// Design : NewExtInst_TOP_clk_wiz_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z035ffg676-2 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* NotValidForBitStream *) +module NewExtInst_TOP_clk_wiz_0_0 + (clk_out1, + reset, + locked, + clk_in1); + output clk_out1; + input reset; + output locked; + input clk_in1; + + (* IBUF_LOW_PWR *) wire clk_in1; + wire clk_out1; + wire locked; + wire reset; + + NewExtInst_TOP_clk_wiz_0_0_clk_wiz inst + (.clk_in1(clk_in1), + .clk_out1(clk_out1), + .locked(locked), + .reset(reset)); +endmodule + +module NewExtInst_TOP_clk_wiz_0_0_clk_wiz + (clk_out1, + reset, + locked, + clk_in1); + output clk_out1; + input reset; + output locked; + input clk_in1; + + wire clk_in1; + wire clk_in1_NewExtInst_TOP_clk_wiz_0_0; + wire clk_out1; + wire clk_out1_NewExtInst_TOP_clk_wiz_0_0; + wire clkfbout_NewExtInst_TOP_clk_wiz_0_0; + wire clkfbout_buf_NewExtInst_TOP_clk_wiz_0_0; + wire locked; + wire reset; + wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED; + wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED; + wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED; + wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED; + + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkf_buf + (.I(clkfbout_NewExtInst_TOP_clk_wiz_0_0), + .O(clkfbout_buf_NewExtInst_TOP_clk_wiz_0_0)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + IBUF #( + .IOSTANDARD("DEFAULT")) + clkin1_ibufg + (.I(clk_in1), + .O(clk_in1_NewExtInst_TOP_clk_wiz_0_0)); + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkout1_buf + (.I(clk_out1_NewExtInst_TOP_clk_wiz_0_0), + .O(clk_out1)); + (* BOX_TYPE = "PRIMITIVE" *) + MMCME2_ADV #( + .BANDWIDTH("OPTIMIZED"), + .CLKFBOUT_MULT_F(40.000000), + .CLKFBOUT_PHASE(0.000000), + .CLKFBOUT_USE_FINE_PS("FALSE"), + .CLKIN1_PERIOD(40.000000), + .CLKIN2_PERIOD(0.000000), + .CLKOUT0_DIVIDE_F(10.000000), + .CLKOUT0_DUTY_CYCLE(0.500000), + .CLKOUT0_PHASE(0.000000), + .CLKOUT0_USE_FINE_PS("FALSE"), + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.500000), + .CLKOUT1_PHASE(0.000000), + .CLKOUT1_USE_FINE_PS("FALSE"), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.500000), + .CLKOUT2_PHASE(0.000000), + .CLKOUT2_USE_FINE_PS("FALSE"), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.500000), + .CLKOUT3_PHASE(0.000000), + .CLKOUT3_USE_FINE_PS("FALSE"), + .CLKOUT4_CASCADE("FALSE"), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.500000), + .CLKOUT4_PHASE(0.000000), + .CLKOUT4_USE_FINE_PS("FALSE"), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.500000), + .CLKOUT5_PHASE(0.000000), + .CLKOUT5_USE_FINE_PS("FALSE"), + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.500000), + .CLKOUT6_PHASE(0.000000), + .CLKOUT6_USE_FINE_PS("FALSE"), + .COMPENSATION("ZHOLD"), + .DIVCLK_DIVIDE(1), + .IS_CLKINSEL_INVERTED(1'b0), + .IS_PSEN_INVERTED(1'b0), + .IS_PSINCDEC_INVERTED(1'b0), + .IS_PWRDWN_INVERTED(1'b0), + .IS_RST_INVERTED(1'b0), + .REF_JITTER1(0.010000), + .REF_JITTER2(0.010000), + .SS_EN("FALSE"), + .SS_MODE("CENTER_HIGH"), + .SS_MOD_PERIOD(10000), + .STARTUP_WAIT("FALSE")) + mmcm_adv_inst + (.CLKFBIN(clkfbout_buf_NewExtInst_TOP_clk_wiz_0_0), + .CLKFBOUT(clkfbout_NewExtInst_TOP_clk_wiz_0_0), + .CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED), + .CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED), + .CLKIN1(clk_in1_NewExtInst_TOP_clk_wiz_0_0), + .CLKIN2(1'b0), + .CLKINSEL(1'b1), + .CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED), + .CLKOUT0(clk_out1_NewExtInst_TOP_clk_wiz_0_0), + .CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED), + .CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED), + .CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED), + .CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED), + .CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED), + .CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED), + .CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED), + .CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED), + .CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED), + .CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED), + .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DCLK(1'b0), + .DEN(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]), + .DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED), + .DWE(1'b0), + .LOCKED(locked), + .PSCLK(1'b0), + .PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED), + .PSEN(1'b0), + .PSINCDEC(1'b0), + .PWRDWN(1'b0), + .RST(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_sim_netlist.vhdl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_sim_netlist.vhdl new file mode 100644 index 0000000..c77c08b --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_sim_netlist.vhdl @@ -0,0 +1,189 @@ +-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +-- Date : Fri May 15 15:26:59 2026 +-- Host : mkb running 64-bit unknown +-- Command : write_vhdl -force -mode funcsim +-- /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_sim_netlist.vhdl +-- Design : NewExtInst_TOP_clk_wiz_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z035ffg676-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_clk_wiz_0_0_clk_wiz is + port ( + clk_out1 : out STD_LOGIC; + reset : in STD_LOGIC; + locked : out STD_LOGIC; + clk_in1 : in STD_LOGIC + ); +end NewExtInst_TOP_clk_wiz_0_0_clk_wiz; + +architecture STRUCTURE of NewExtInst_TOP_clk_wiz_0_0_clk_wiz is + signal clk_in1_NewExtInst_TOP_clk_wiz_0_0 : STD_LOGIC; + signal clk_out1_NewExtInst_TOP_clk_wiz_0_0 : STD_LOGIC; + signal clkfbout_NewExtInst_TOP_clk_wiz_0_0 : STD_LOGIC; + signal clkfbout_buf_NewExtInst_TOP_clk_wiz_0_0 : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE"; + attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE"; + attribute CAPACITANCE : string; + attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE"; + attribute IBUF_DELAY_VALUE : string; + attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0"; + attribute IFD_DELAY_VALUE : string; + attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO"; + attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE"; + attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE"; +begin +clkf_buf: unisim.vcomponents.BUFG + port map ( + I => clkfbout_NewExtInst_TOP_clk_wiz_0_0, + O => clkfbout_buf_NewExtInst_TOP_clk_wiz_0_0 + ); +clkin1_ibufg: unisim.vcomponents.IBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => clk_in1, + O => clk_in1_NewExtInst_TOP_clk_wiz_0_0 + ); +clkout1_buf: unisim.vcomponents.BUFG + port map ( + I => clk_out1_NewExtInst_TOP_clk_wiz_0_0, + O => clk_out1 + ); +mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV + generic map( + BANDWIDTH => "OPTIMIZED", + CLKFBOUT_MULT_F => 40.000000, + CLKFBOUT_PHASE => 0.000000, + CLKFBOUT_USE_FINE_PS => false, + CLKIN1_PERIOD => 40.000000, + CLKIN2_PERIOD => 0.000000, + CLKOUT0_DIVIDE_F => 10.000000, + CLKOUT0_DUTY_CYCLE => 0.500000, + CLKOUT0_PHASE => 0.000000, + CLKOUT0_USE_FINE_PS => false, + CLKOUT1_DIVIDE => 1, + CLKOUT1_DUTY_CYCLE => 0.500000, + CLKOUT1_PHASE => 0.000000, + CLKOUT1_USE_FINE_PS => false, + CLKOUT2_DIVIDE => 1, + CLKOUT2_DUTY_CYCLE => 0.500000, + CLKOUT2_PHASE => 0.000000, + CLKOUT2_USE_FINE_PS => false, + CLKOUT3_DIVIDE => 1, + CLKOUT3_DUTY_CYCLE => 0.500000, + CLKOUT3_PHASE => 0.000000, + CLKOUT3_USE_FINE_PS => false, + CLKOUT4_CASCADE => false, + CLKOUT4_DIVIDE => 1, + CLKOUT4_DUTY_CYCLE => 0.500000, + CLKOUT4_PHASE => 0.000000, + CLKOUT4_USE_FINE_PS => false, + CLKOUT5_DIVIDE => 1, + CLKOUT5_DUTY_CYCLE => 0.500000, + CLKOUT5_PHASE => 0.000000, + CLKOUT5_USE_FINE_PS => false, + CLKOUT6_DIVIDE => 1, + CLKOUT6_DUTY_CYCLE => 0.500000, + CLKOUT6_PHASE => 0.000000, + CLKOUT6_USE_FINE_PS => false, + COMPENSATION => "ZHOLD", + DIVCLK_DIVIDE => 1, + IS_CLKINSEL_INVERTED => '0', + IS_PSEN_INVERTED => '0', + IS_PSINCDEC_INVERTED => '0', + IS_PWRDWN_INVERTED => '0', + IS_RST_INVERTED => '0', + REF_JITTER1 => 0.010000, + REF_JITTER2 => 0.010000, + SS_EN => "FALSE", + SS_MODE => "CENTER_HIGH", + SS_MOD_PERIOD => 10000, + STARTUP_WAIT => false + ) + port map ( + CLKFBIN => clkfbout_buf_NewExtInst_TOP_clk_wiz_0_0, + CLKFBOUT => clkfbout_NewExtInst_TOP_clk_wiz_0_0, + CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED, + CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED, + CLKIN1 => clk_in1_NewExtInst_TOP_clk_wiz_0_0, + CLKIN2 => '0', + CLKINSEL => '1', + CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED, + CLKOUT0 => clk_out1_NewExtInst_TOP_clk_wiz_0_0, + CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED, + CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED, + CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED, + CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED, + CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED, + CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED, + CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED, + CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED, + CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED, + CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED, + DADDR(6 downto 0) => B"0000000", + DCLK => '0', + DEN => '0', + DI(15 downto 0) => B"0000000000000000", + DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0), + DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED, + DWE => '0', + LOCKED => locked, + PSCLK => '0', + PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED, + PSEN => '0', + PSINCDEC => '0', + PWRDWN => '0', + RST => reset + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_clk_wiz_0_0 is + port ( + clk_out1 : out STD_LOGIC; + reset : in STD_LOGIC; + locked : out STD_LOGIC; + clk_in1 : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of NewExtInst_TOP_clk_wiz_0_0 : entity is true; +end NewExtInst_TOP_clk_wiz_0_0; + +architecture STRUCTURE of NewExtInst_TOP_clk_wiz_0_0 is +begin +inst: entity work.NewExtInst_TOP_clk_wiz_0_0_clk_wiz + port map ( + clk_in1 => clk_in1, + clk_out1 => clk_out1, + locked => locked, + reset => reset + ); +end STRUCTURE; diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_sim_netlist.v b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_sim_netlist.v new file mode 100644 index 0000000..cd6f033 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_sim_netlist.v @@ -0,0 +1,985 @@ +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +// Date : Fri May 15 15:26:59 2026 +// Host : mkb running 64-bit unknown +// Command : write_verilog -force -mode funcsim +// /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_sim_netlist.v +// Design : NewExtInst_TOP_proc_sys_reset_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z035ffg676-2 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "NewExtInst_TOP_proc_sys_reset_0_0,proc_sys_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "proc_sys_reset,Vivado 2023.2" *) +(* NotValidForBitStream *) +module NewExtInst_TOP_proc_sys_reset_0_0 + (slowest_sync_clk, + ext_reset_in, + aux_reset_in, + mb_debug_sys_rst, + dcm_locked, + mb_reset, + bus_struct_reset, + peripheral_reset, + interconnect_aresetn, + peripheral_aresetn); + (* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 25000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN NewExtInst_TOP_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) input slowest_sync_clk; + (* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input ext_reset_in; + (* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input aux_reset_in; + (* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input mb_debug_sys_rst; + input dcm_locked; + (* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0" *) output mb_reset; + (* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]bus_struct_reset; + (* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_reset; + (* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]interconnect_aresetn; + (* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_aresetn; + + wire aux_reset_in; + wire [0:0]bus_struct_reset; + wire dcm_locked; + wire ext_reset_in; + wire [0:0]interconnect_aresetn; + wire mb_debug_sys_rst; + wire mb_reset; + wire [0:0]peripheral_aresetn; + wire [0:0]peripheral_reset; + wire slowest_sync_clk; + + (* C_AUX_RESET_HIGH = "1'b0" *) + (* C_AUX_RST_WIDTH = "4" *) + (* C_EXT_RESET_HIGH = "1'b0" *) + (* C_EXT_RST_WIDTH = "4" *) + (* C_FAMILY = "zynq" *) + (* C_NUM_BUS_RST = "1" *) + (* C_NUM_INTERCONNECT_ARESETN = "1" *) + (* C_NUM_PERP_ARESETN = "1" *) + (* C_NUM_PERP_RST = "1" *) + NewExtInst_TOP_proc_sys_reset_0_0_proc_sys_reset U0 + (.aux_reset_in(aux_reset_in), + .bus_struct_reset(bus_struct_reset), + .dcm_locked(dcm_locked), + .ext_reset_in(ext_reset_in), + .interconnect_aresetn(interconnect_aresetn), + .mb_debug_sys_rst(mb_debug_sys_rst), + .mb_reset(mb_reset), + .peripheral_aresetn(peripheral_aresetn), + .peripheral_reset(peripheral_reset), + .slowest_sync_clk(slowest_sync_clk)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module NewExtInst_TOP_proc_sys_reset_0_0_cdc_sync + (lpf_asr_reg, + scndry_out, + lpf_asr, + p_1_in, + p_2_in, + asr_lpf, + aux_reset_in, + slowest_sync_clk); + output lpf_asr_reg; + output scndry_out; + input lpf_asr; + input p_1_in; + input p_2_in; + input [0:0]asr_lpf; + input aux_reset_in; + input slowest_sync_clk; + + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ; + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ; + wire Q; + wire asr_d1; + wire [0:0]asr_lpf; + wire aux_reset_in; + wire lpf_asr; + wire lpf_asr_reg; + wire p_1_in; + wire p_2_in; + wire scndry_out; + wire slowest_sync_clk; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(slowest_sync_clk), + .CE(1'b1), + .D(asr_d1), + .Q(Q), + .R(1'b0)); + LUT1 #( + .INIT(2'h1)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0 + (.I0(aux_reset_in), + .O(asr_d1)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 + (.C(slowest_sync_clk), + .CE(1'b1), + .D(Q), + .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 + (.C(slowest_sync_clk), + .CE(1'b1), + .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ), + .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 + (.C(slowest_sync_clk), + .CE(1'b1), + .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ), + .Q(scndry_out), + .R(1'b0)); + LUT5 #( + .INIT(32'hEAAAAAA8)) + lpf_asr_i_1 + (.I0(lpf_asr), + .I1(p_1_in), + .I2(p_2_in), + .I3(scndry_out), + .I4(asr_lpf), + .O(lpf_asr_reg)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module NewExtInst_TOP_proc_sys_reset_0_0_cdc_sync_0 + (lpf_exr_reg, + scndry_out, + lpf_exr, + p_1_in4_in, + p_2_in3_in, + exr_lpf, + mb_debug_sys_rst, + ext_reset_in, + slowest_sync_clk); + output lpf_exr_reg; + output scndry_out; + input lpf_exr; + input p_1_in4_in; + input p_2_in3_in; + input [0:0]exr_lpf; + input mb_debug_sys_rst; + input ext_reset_in; + input slowest_sync_clk; + + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ; + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ; + wire Q; + wire exr_d1; + wire [0:0]exr_lpf; + wire ext_reset_in; + wire lpf_exr; + wire lpf_exr_reg; + wire mb_debug_sys_rst; + wire p_1_in4_in; + wire p_2_in3_in; + wire scndry_out; + wire slowest_sync_clk; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(slowest_sync_clk), + .CE(1'b1), + .D(exr_d1), + .Q(Q), + .R(1'b0)); + LUT2 #( + .INIT(4'hB)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1 + (.I0(mb_debug_sys_rst), + .I1(ext_reset_in), + .O(exr_d1)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 + (.C(slowest_sync_clk), + .CE(1'b1), + .D(Q), + .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 + (.C(slowest_sync_clk), + .CE(1'b1), + .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ), + .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 + (.C(slowest_sync_clk), + .CE(1'b1), + .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ), + .Q(scndry_out), + .R(1'b0)); + LUT5 #( + .INIT(32'hEAAAAAA8)) + lpf_exr_i_1 + (.I0(lpf_exr), + .I1(p_1_in4_in), + .I2(p_2_in3_in), + .I3(scndry_out), + .I4(exr_lpf), + .O(lpf_exr_reg)); +endmodule + +(* ORIG_REF_NAME = "lpf" *) +module NewExtInst_TOP_proc_sys_reset_0_0_lpf + (lpf_int, + slowest_sync_clk, + dcm_locked, + mb_debug_sys_rst, + ext_reset_in, + aux_reset_in); + output lpf_int; + input slowest_sync_clk; + input dcm_locked; + input mb_debug_sys_rst; + input ext_reset_in; + input aux_reset_in; + + wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ; + wire \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ; + wire Q; + wire [0:0]asr_lpf; + wire aux_reset_in; + wire dcm_locked; + wire [0:0]exr_lpf; + wire ext_reset_in; + wire lpf_asr; + wire lpf_exr; + wire lpf_int; + wire lpf_int0__0; + wire mb_debug_sys_rst; + wire p_1_in; + wire p_1_in4_in; + wire p_2_in; + wire p_2_in3_in; + wire p_3_in1_in; + wire p_3_in6_in; + wire slowest_sync_clk; + + NewExtInst_TOP_proc_sys_reset_0_0_cdc_sync \ACTIVE_LOW_AUX.ACT_LO_AUX + (.asr_lpf(asr_lpf), + .aux_reset_in(aux_reset_in), + .lpf_asr(lpf_asr), + .lpf_asr_reg(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ), + .p_1_in(p_1_in), + .p_2_in(p_2_in), + .scndry_out(p_3_in1_in), + .slowest_sync_clk(slowest_sync_clk)); + NewExtInst_TOP_proc_sys_reset_0_0_cdc_sync_0 \ACTIVE_LOW_EXT.ACT_LO_EXT + (.exr_lpf(exr_lpf), + .ext_reset_in(ext_reset_in), + .lpf_exr(lpf_exr), + .lpf_exr_reg(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ), + .mb_debug_sys_rst(mb_debug_sys_rst), + .p_1_in4_in(p_1_in4_in), + .p_2_in3_in(p_2_in3_in), + .scndry_out(p_3_in6_in), + .slowest_sync_clk(slowest_sync_clk)); + FDRE #( + .INIT(1'b0)) + \AUX_LPF[1].asr_lpf_reg[1] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(p_3_in1_in), + .Q(p_2_in), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AUX_LPF[2].asr_lpf_reg[2] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(p_2_in), + .Q(p_1_in), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AUX_LPF[3].asr_lpf_reg[3] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(p_1_in), + .Q(asr_lpf), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \EXT_LPF[1].exr_lpf_reg[1] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(p_3_in6_in), + .Q(p_2_in3_in), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \EXT_LPF[2].exr_lpf_reg[2] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(p_2_in3_in), + .Q(p_1_in4_in), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \EXT_LPF[3].exr_lpf_reg[3] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(p_1_in4_in), + .Q(exr_lpf), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "SRL16" *) + (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) + (* box_type = "PRIMITIVE" *) + (* srl_name = "U0/\\EXT_LPF/POR_SRL_I " *) + SRL16E #( + .INIT(16'hFFFF)) + POR_SRL_I + (.A0(1'b1), + .A1(1'b1), + .A2(1'b1), + .A3(1'b1), + .CE(1'b1), + .CLK(slowest_sync_clk), + .D(1'b0), + .Q(Q)); + FDRE #( + .INIT(1'b0)) + lpf_asr_reg + (.C(slowest_sync_clk), + .CE(1'b1), + .D(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ), + .Q(lpf_asr), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + lpf_exr_reg + (.C(slowest_sync_clk), + .CE(1'b1), + .D(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ), + .Q(lpf_exr), + .R(1'b0)); + LUT4 #( + .INIT(16'hFFFD)) + lpf_int0 + (.I0(dcm_locked), + .I1(lpf_exr), + .I2(lpf_asr), + .I3(Q), + .O(lpf_int0__0)); + FDRE #( + .INIT(1'b0)) + lpf_int_reg + (.C(slowest_sync_clk), + .CE(1'b1), + .D(lpf_int0__0), + .Q(lpf_int), + .R(1'b0)); +endmodule + +(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b0" *) +(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "zynq" *) (* C_NUM_BUS_RST = "1" *) +(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *) (* C_NUM_PERP_RST = "1" *) +(* ORIG_REF_NAME = "proc_sys_reset" *) +module NewExtInst_TOP_proc_sys_reset_0_0_proc_sys_reset + (slowest_sync_clk, + ext_reset_in, + aux_reset_in, + mb_debug_sys_rst, + dcm_locked, + mb_reset, + bus_struct_reset, + peripheral_reset, + interconnect_aresetn, + peripheral_aresetn); + input slowest_sync_clk; + input ext_reset_in; + input aux_reset_in; + input mb_debug_sys_rst; + input dcm_locked; + output mb_reset; + output [0:0]bus_struct_reset; + output [0:0]peripheral_reset; + output [0:0]interconnect_aresetn; + output [0:0]peripheral_aresetn; + + wire Bsr_out; + wire MB_out; + wire Pr_out; + wire SEQ_n_3; + wire SEQ_n_4; + wire aux_reset_in; + wire [0:0]bus_struct_reset; + wire dcm_locked; + wire ext_reset_in; + wire [0:0]interconnect_aresetn; + wire lpf_int; + wire mb_debug_sys_rst; + wire mb_reset; + wire [0:0]peripheral_aresetn; + wire [0:0]peripheral_reset; + wire slowest_sync_clk; + + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N + (.C(slowest_sync_clk), + .CE(1'b1), + .D(SEQ_n_3), + .Q(interconnect_aresetn), + .R(1'b0)); + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N + (.C(slowest_sync_clk), + .CE(1'b1), + .D(SEQ_n_4), + .Q(peripheral_aresetn), + .R(1'b0)); + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b1), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + \BSR_OUT_DFF[0].FDRE_BSR + (.C(slowest_sync_clk), + .CE(1'b1), + .D(Bsr_out), + .Q(bus_struct_reset), + .R(1'b0)); + NewExtInst_TOP_proc_sys_reset_0_0_lpf EXT_LPF + (.aux_reset_in(aux_reset_in), + .dcm_locked(dcm_locked), + .ext_reset_in(ext_reset_in), + .lpf_int(lpf_int), + .mb_debug_sys_rst(mb_debug_sys_rst), + .slowest_sync_clk(slowest_sync_clk)); + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b1), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + FDRE_inst + (.C(slowest_sync_clk), + .CE(1'b1), + .D(MB_out), + .Q(mb_reset), + .R(1'b0)); + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b1), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + \PR_OUT_DFF[0].FDRE_PER + (.C(slowest_sync_clk), + .CE(1'b1), + .D(Pr_out), + .Q(peripheral_reset), + .R(1'b0)); + NewExtInst_TOP_proc_sys_reset_0_0_sequence_psr SEQ + (.Bsr_out(Bsr_out), + .MB_out(MB_out), + .Pr_out(Pr_out), + .bsr_reg_0(SEQ_n_3), + .lpf_int(lpf_int), + .pr_reg_0(SEQ_n_4), + .slowest_sync_clk(slowest_sync_clk)); +endmodule + +(* ORIG_REF_NAME = "sequence_psr" *) +module NewExtInst_TOP_proc_sys_reset_0_0_sequence_psr + (MB_out, + Bsr_out, + Pr_out, + bsr_reg_0, + pr_reg_0, + lpf_int, + slowest_sync_clk); + output MB_out; + output Bsr_out; + output Pr_out; + output bsr_reg_0; + output pr_reg_0; + input lpf_int; + input slowest_sync_clk; + + wire Bsr_out; + wire Core_i_1_n_0; + wire MB_out; + wire Pr_out; + wire \bsr_dec_reg_n_0_[0] ; + wire \bsr_dec_reg_n_0_[2] ; + wire bsr_i_1_n_0; + wire bsr_reg_0; + wire \core_dec[0]_i_1_n_0 ; + wire \core_dec[2]_i_1_n_0 ; + wire \core_dec_reg_n_0_[0] ; + wire \core_dec_reg_n_0_[1] ; + wire from_sys_i_1_n_0; + wire lpf_int; + wire p_0_in; + wire [2:0]p_3_out; + wire [2:0]p_5_out; + wire pr_dec0__0; + wire \pr_dec_reg_n_0_[0] ; + wire \pr_dec_reg_n_0_[2] ; + wire pr_i_1_n_0; + wire pr_reg_0; + wire seq_clr; + wire [5:0]seq_cnt; + wire seq_cnt_en; + wire slowest_sync_clk; + + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT1 #( + .INIT(2'h1)) + \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1 + (.I0(Bsr_out), + .O(bsr_reg_0)); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT1 #( + .INIT(2'h1)) + \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1 + (.I0(Pr_out), + .O(pr_reg_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + Core_i_1 + (.I0(MB_out), + .I1(p_0_in), + .O(Core_i_1_n_0)); + FDSE #( + .INIT(1'b1)) + Core_reg + (.C(slowest_sync_clk), + .CE(1'b1), + .D(Core_i_1_n_0), + .Q(MB_out), + .S(lpf_int)); + NewExtInst_TOP_proc_sys_reset_0_0_upcnt_n SEQ_COUNTER + (.Q(seq_cnt), + .seq_clr(seq_clr), + .seq_cnt_en(seq_cnt_en), + .slowest_sync_clk(slowest_sync_clk)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT4 #( + .INIT(16'h0090)) + \bsr_dec[0]_i_1 + (.I0(seq_cnt_en), + .I1(seq_cnt[4]), + .I2(seq_cnt[3]), + .I3(seq_cnt[5]), + .O(p_5_out[0])); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h8)) + \bsr_dec[2]_i_1 + (.I0(\core_dec_reg_n_0_[1] ), + .I1(\bsr_dec_reg_n_0_[0] ), + .O(p_5_out[2])); + FDRE #( + .INIT(1'b0)) + \bsr_dec_reg[0] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(p_5_out[0]), + .Q(\bsr_dec_reg_n_0_[0] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \bsr_dec_reg[2] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(p_5_out[2]), + .Q(\bsr_dec_reg_n_0_[2] ), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h2)) + bsr_i_1 + (.I0(Bsr_out), + .I1(\bsr_dec_reg_n_0_[2] ), + .O(bsr_i_1_n_0)); + FDSE #( + .INIT(1'b1)) + bsr_reg + (.C(slowest_sync_clk), + .CE(1'b1), + .D(bsr_i_1_n_0), + .Q(Bsr_out), + .S(lpf_int)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT4 #( + .INIT(16'h9000)) + \core_dec[0]_i_1 + (.I0(seq_cnt_en), + .I1(seq_cnt[4]), + .I2(seq_cnt[3]), + .I3(seq_cnt[5]), + .O(\core_dec[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h8)) + \core_dec[2]_i_1 + (.I0(\core_dec_reg_n_0_[1] ), + .I1(\core_dec_reg_n_0_[0] ), + .O(\core_dec[2]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \core_dec_reg[0] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(\core_dec[0]_i_1_n_0 ), + .Q(\core_dec_reg_n_0_[0] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \core_dec_reg[1] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(pr_dec0__0), + .Q(\core_dec_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \core_dec_reg[2] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(\core_dec[2]_i_1_n_0 ), + .Q(p_0_in), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h8)) + from_sys_i_1 + (.I0(MB_out), + .I1(seq_cnt_en), + .O(from_sys_i_1_n_0)); + FDSE #( + .INIT(1'b0)) + from_sys_reg + (.C(slowest_sync_clk), + .CE(1'b1), + .D(from_sys_i_1_n_0), + .Q(seq_cnt_en), + .S(lpf_int)); + LUT4 #( + .INIT(16'h0018)) + pr_dec0 + (.I0(seq_cnt_en), + .I1(seq_cnt[0]), + .I2(seq_cnt[2]), + .I3(seq_cnt[1]), + .O(pr_dec0__0)); + LUT4 #( + .INIT(16'h0480)) + \pr_dec[0]_i_1 + (.I0(seq_cnt_en), + .I1(seq_cnt[3]), + .I2(seq_cnt[5]), + .I3(seq_cnt[4]), + .O(p_3_out[0])); + LUT2 #( + .INIT(4'h8)) + \pr_dec[2]_i_1 + (.I0(\core_dec_reg_n_0_[1] ), + .I1(\pr_dec_reg_n_0_[0] ), + .O(p_3_out[2])); + FDRE #( + .INIT(1'b0)) + \pr_dec_reg[0] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(p_3_out[0]), + .Q(\pr_dec_reg_n_0_[0] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \pr_dec_reg[2] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(p_3_out[2]), + .Q(\pr_dec_reg_n_0_[2] ), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT2 #( + .INIT(4'h2)) + pr_i_1 + (.I0(Pr_out), + .I1(\pr_dec_reg_n_0_[2] ), + .O(pr_i_1_n_0)); + FDSE #( + .INIT(1'b1)) + pr_reg + (.C(slowest_sync_clk), + .CE(1'b1), + .D(pr_i_1_n_0), + .Q(Pr_out), + .S(lpf_int)); + FDRE #( + .INIT(1'b0)) + seq_clr_reg + (.C(slowest_sync_clk), + .CE(1'b1), + .D(1'b1), + .Q(seq_clr), + .R(lpf_int)); +endmodule + +(* ORIG_REF_NAME = "upcnt_n" *) +module NewExtInst_TOP_proc_sys_reset_0_0_upcnt_n + (Q, + seq_clr, + seq_cnt_en, + slowest_sync_clk); + output [5:0]Q; + input seq_clr; + input seq_cnt_en; + input slowest_sync_clk; + + wire [5:0]Q; + wire clear; + wire [5:0]q_int0; + wire seq_clr; + wire seq_cnt_en; + wire slowest_sync_clk; + + LUT1 #( + .INIT(2'h1)) + \q_int[0]_i_1 + (.I0(Q[0]), + .O(q_int0[0])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT2 #( + .INIT(4'h6)) + \q_int[1]_i_1 + (.I0(Q[0]), + .I1(Q[1]), + .O(q_int0[1])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT3 #( + .INIT(8'h78)) + \q_int[2]_i_1 + (.I0(Q[0]), + .I1(Q[1]), + .I2(Q[2]), + .O(q_int0[2])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'h7F80)) + \q_int[3]_i_1 + (.I0(Q[1]), + .I1(Q[0]), + .I2(Q[2]), + .I3(Q[3]), + .O(q_int0[3])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \q_int[4]_i_1 + (.I0(Q[2]), + .I1(Q[0]), + .I2(Q[1]), + .I3(Q[3]), + .I4(Q[4]), + .O(q_int0[4])); + LUT1 #( + .INIT(2'h1)) + \q_int[5]_i_1 + (.I0(seq_clr), + .O(clear)); + LUT6 #( + .INIT(64'h7FFFFFFF80000000)) + \q_int[5]_i_2 + (.I0(Q[3]), + .I1(Q[1]), + .I2(Q[0]), + .I3(Q[2]), + .I4(Q[4]), + .I5(Q[5]), + .O(q_int0[5])); + FDRE #( + .INIT(1'b1)) + \q_int_reg[0] + (.C(slowest_sync_clk), + .CE(seq_cnt_en), + .D(q_int0[0]), + .Q(Q[0]), + .R(clear)); + FDRE #( + .INIT(1'b1)) + \q_int_reg[1] + (.C(slowest_sync_clk), + .CE(seq_cnt_en), + .D(q_int0[1]), + .Q(Q[1]), + .R(clear)); + FDRE #( + .INIT(1'b1)) + \q_int_reg[2] + (.C(slowest_sync_clk), + .CE(seq_cnt_en), + .D(q_int0[2]), + .Q(Q[2]), + .R(clear)); + FDRE #( + .INIT(1'b1)) + \q_int_reg[3] + (.C(slowest_sync_clk), + .CE(seq_cnt_en), + .D(q_int0[3]), + .Q(Q[3]), + .R(clear)); + FDRE #( + .INIT(1'b1)) + \q_int_reg[4] + (.C(slowest_sync_clk), + .CE(seq_cnt_en), + .D(q_int0[4]), + .Q(Q[4]), + .R(clear)); + FDRE #( + .INIT(1'b1)) + \q_int_reg[5] + (.C(slowest_sync_clk), + .CE(seq_cnt_en), + .D(q_int0[5]), + .Q(Q[5]), + .R(clear)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_sim_netlist.vhdl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_sim_netlist.vhdl new file mode 100644 index 0000000..4a94790 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_sim_netlist.vhdl @@ -0,0 +1,1135 @@ +-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +-- Date : Fri May 15 15:26:59 2026 +-- Host : mkb running 64-bit unknown +-- Command : write_vhdl -force -mode funcsim +-- /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_sim_netlist.vhdl +-- Design : NewExtInst_TOP_proc_sys_reset_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z035ffg676-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_proc_sys_reset_0_0_cdc_sync is + port ( + lpf_asr_reg : out STD_LOGIC; + scndry_out : out STD_LOGIC; + lpf_asr : in STD_LOGIC; + p_1_in : in STD_LOGIC; + p_2_in : in STD_LOGIC; + asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 ); + aux_reset_in : in STD_LOGIC; + slowest_sync_clk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of NewExtInst_TOP_proc_sys_reset_0_0_cdc_sync : entity is "cdc_sync"; +end NewExtInst_TOP_proc_sys_reset_0_0_cdc_sync; + +architecture STRUCTURE of NewExtInst_TOP_proc_sys_reset_0_0_cdc_sync is + signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : STD_LOGIC; + signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : STD_LOGIC; + signal Q : STD_LOGIC; + signal asr_d1 : STD_LOGIC; + signal \^scndry_out\ : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute XILINX_TRANSFORM_PINMAP : string; + attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE"; + attribute box_type : string; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; + attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "VCC:CE"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; + attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "VCC:CE"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; + attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "VCC:CE"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; +begin + scndry_out <= \^scndry_out\; +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => asr_d1, + Q => Q, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => aux_reset_in, + O => asr_d1 + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => Q, + Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\, + Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\, + Q => \^scndry_out\, + R => '0' + ); +lpf_asr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"EAAAAAA8" + ) + port map ( + I0 => lpf_asr, + I1 => p_1_in, + I2 => p_2_in, + I3 => \^scndry_out\, + I4 => asr_lpf(0), + O => lpf_asr_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_proc_sys_reset_0_0_cdc_sync_0 is + port ( + lpf_exr_reg : out STD_LOGIC; + scndry_out : out STD_LOGIC; + lpf_exr : in STD_LOGIC; + p_1_in4_in : in STD_LOGIC; + p_2_in3_in : in STD_LOGIC; + exr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 ); + mb_debug_sys_rst : in STD_LOGIC; + ext_reset_in : in STD_LOGIC; + slowest_sync_clk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of NewExtInst_TOP_proc_sys_reset_0_0_cdc_sync_0 : entity is "cdc_sync"; +end NewExtInst_TOP_proc_sys_reset_0_0_cdc_sync_0; + +architecture STRUCTURE of NewExtInst_TOP_proc_sys_reset_0_0_cdc_sync_0 is + signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : STD_LOGIC; + signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : STD_LOGIC; + signal Q : STD_LOGIC; + signal exr_d1 : STD_LOGIC; + signal \^scndry_out\ : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute XILINX_TRANSFORM_PINMAP : string; + attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE"; + attribute box_type : string; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; + attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "VCC:CE"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; + attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "VCC:CE"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; + attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "VCC:CE"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; +begin + scndry_out <= \^scndry_out\; +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => exr_d1, + Q => Q, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => mb_debug_sys_rst, + I1 => ext_reset_in, + O => exr_d1 + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => Q, + Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\, + Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\, + Q => \^scndry_out\, + R => '0' + ); +lpf_exr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"EAAAAAA8" + ) + port map ( + I0 => lpf_exr, + I1 => p_1_in4_in, + I2 => p_2_in3_in, + I3 => \^scndry_out\, + I4 => exr_lpf(0), + O => lpf_exr_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_proc_sys_reset_0_0_upcnt_n is + port ( + Q : out STD_LOGIC_VECTOR ( 5 downto 0 ); + seq_clr : in STD_LOGIC; + seq_cnt_en : in STD_LOGIC; + slowest_sync_clk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of NewExtInst_TOP_proc_sys_reset_0_0_upcnt_n : entity is "upcnt_n"; +end NewExtInst_TOP_proc_sys_reset_0_0_upcnt_n; + +architecture STRUCTURE of NewExtInst_TOP_proc_sys_reset_0_0_upcnt_n is + signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal clear : STD_LOGIC; + signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0"; +begin + Q(5 downto 0) <= \^q\(5 downto 0); +\q_int[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^q\(0), + O => q_int0(0) + ); +\q_int[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^q\(0), + I1 => \^q\(1), + O => q_int0(1) + ); +\q_int[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \^q\(0), + I1 => \^q\(1), + I2 => \^q\(2), + O => q_int0(2) + ); +\q_int[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \^q\(1), + I1 => \^q\(0), + I2 => \^q\(2), + I3 => \^q\(3), + O => q_int0(3) + ); +\q_int[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \^q\(2), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => \^q\(3), + I4 => \^q\(4), + O => q_int0(4) + ); +\q_int[5]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => seq_clr, + O => clear + ); +\q_int[5]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFFFFFF80000000" + ) + port map ( + I0 => \^q\(3), + I1 => \^q\(1), + I2 => \^q\(0), + I3 => \^q\(2), + I4 => \^q\(4), + I5 => \^q\(5), + O => q_int0(5) + ); +\q_int_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => slowest_sync_clk, + CE => seq_cnt_en, + D => q_int0(0), + Q => \^q\(0), + R => clear + ); +\q_int_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => slowest_sync_clk, + CE => seq_cnt_en, + D => q_int0(1), + Q => \^q\(1), + R => clear + ); +\q_int_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => slowest_sync_clk, + CE => seq_cnt_en, + D => q_int0(2), + Q => \^q\(2), + R => clear + ); +\q_int_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => slowest_sync_clk, + CE => seq_cnt_en, + D => q_int0(3), + Q => \^q\(3), + R => clear + ); +\q_int_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => slowest_sync_clk, + CE => seq_cnt_en, + D => q_int0(4), + Q => \^q\(4), + R => clear + ); +\q_int_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => slowest_sync_clk, + CE => seq_cnt_en, + D => q_int0(5), + Q => \^q\(5), + R => clear + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_proc_sys_reset_0_0_lpf is + port ( + lpf_int : out STD_LOGIC; + slowest_sync_clk : in STD_LOGIC; + dcm_locked : in STD_LOGIC; + mb_debug_sys_rst : in STD_LOGIC; + ext_reset_in : in STD_LOGIC; + aux_reset_in : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of NewExtInst_TOP_proc_sys_reset_0_0_lpf : entity is "lpf"; +end NewExtInst_TOP_proc_sys_reset_0_0_lpf; + +architecture STRUCTURE of NewExtInst_TOP_proc_sys_reset_0_0_lpf is + signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC; + signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC; + signal Q : STD_LOGIC; + signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 ); + signal exr_lpf : STD_LOGIC_VECTOR ( 0 to 0 ); + signal lpf_asr : STD_LOGIC; + signal lpf_exr : STD_LOGIC; + signal \lpf_int0__0\ : STD_LOGIC; + signal p_1_in : STD_LOGIC; + signal p_1_in4_in : STD_LOGIC; + signal p_2_in : STD_LOGIC; + signal p_2_in3_in : STD_LOGIC; + signal p_3_in1_in : STD_LOGIC; + signal p_3_in6_in : STD_LOGIC; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16"; + attribute XILINX_TRANSFORM_PINMAP : string; + attribute XILINX_TRANSFORM_PINMAP of POR_SRL_I : label is "VCC:CE"; + attribute box_type : string; + attribute box_type of POR_SRL_I : label is "PRIMITIVE"; + attribute srl_name : string; + attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I "; +begin +\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.NewExtInst_TOP_proc_sys_reset_0_0_cdc_sync + port map ( + asr_lpf(0) => asr_lpf(0), + aux_reset_in => aux_reset_in, + lpf_asr => lpf_asr, + lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\, + p_1_in => p_1_in, + p_2_in => p_2_in, + scndry_out => p_3_in1_in, + slowest_sync_clk => slowest_sync_clk + ); +\ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.NewExtInst_TOP_proc_sys_reset_0_0_cdc_sync_0 + port map ( + exr_lpf(0) => exr_lpf(0), + ext_reset_in => ext_reset_in, + lpf_exr => lpf_exr, + lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\, + mb_debug_sys_rst => mb_debug_sys_rst, + p_1_in4_in => p_1_in4_in, + p_2_in3_in => p_2_in3_in, + scndry_out => p_3_in6_in, + slowest_sync_clk => slowest_sync_clk + ); +\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => p_3_in1_in, + Q => p_2_in, + R => '0' + ); +\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => p_2_in, + Q => p_1_in, + R => '0' + ); +\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => p_1_in, + Q => asr_lpf(0), + R => '0' + ); +\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => p_3_in6_in, + Q => p_2_in3_in, + R => '0' + ); +\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => p_2_in3_in, + Q => p_1_in4_in, + R => '0' + ); +\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => p_1_in4_in, + Q => exr_lpf(0), + R => '0' + ); +POR_SRL_I: unisim.vcomponents.SRL16E + generic map( + INIT => X"FFFF" + ) + port map ( + A0 => '1', + A1 => '1', + A2 => '1', + A3 => '1', + CE => '1', + CLK => slowest_sync_clk, + D => '0', + Q => Q + ); +lpf_asr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\, + Q => lpf_asr, + R => '0' + ); +lpf_exr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\, + Q => lpf_exr, + R => '0' + ); +lpf_int0: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFD" + ) + port map ( + I0 => dcm_locked, + I1 => lpf_exr, + I2 => lpf_asr, + I3 => Q, + O => \lpf_int0__0\ + ); +lpf_int_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => \lpf_int0__0\, + Q => lpf_int, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_proc_sys_reset_0_0_sequence_psr is + port ( + MB_out : out STD_LOGIC; + Bsr_out : out STD_LOGIC; + Pr_out : out STD_LOGIC; + bsr_reg_0 : out STD_LOGIC; + pr_reg_0 : out STD_LOGIC; + lpf_int : in STD_LOGIC; + slowest_sync_clk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of NewExtInst_TOP_proc_sys_reset_0_0_sequence_psr : entity is "sequence_psr"; +end NewExtInst_TOP_proc_sys_reset_0_0_sequence_psr; + +architecture STRUCTURE of NewExtInst_TOP_proc_sys_reset_0_0_sequence_psr is + signal \^bsr_out\ : STD_LOGIC; + signal Core_i_1_n_0 : STD_LOGIC; + signal \^mb_out\ : STD_LOGIC; + signal \^pr_out\ : STD_LOGIC; + signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC; + signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC; + signal bsr_i_1_n_0 : STD_LOGIC; + signal \core_dec[0]_i_1_n_0\ : STD_LOGIC; + signal \core_dec[2]_i_1_n_0\ : STD_LOGIC; + signal \core_dec_reg_n_0_[0]\ : STD_LOGIC; + signal \core_dec_reg_n_0_[1]\ : STD_LOGIC; + signal from_sys_i_1_n_0 : STD_LOGIC; + signal p_0_in : STD_LOGIC; + signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \pr_dec0__0\ : STD_LOGIC; + signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC; + signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC; + signal pr_i_1_n_0 : STD_LOGIC; + signal seq_clr : STD_LOGIC; + signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal seq_cnt_en : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \bsr_dec[0]_i_1\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair5"; +begin + Bsr_out <= \^bsr_out\; + MB_out <= \^mb_out\; + Pr_out <= \^pr_out\; +\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^bsr_out\, + O => bsr_reg_0 + ); +\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^pr_out\, + O => pr_reg_0 + ); +Core_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^mb_out\, + I1 => p_0_in, + O => Core_i_1_n_0 + ); +Core_reg: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => Core_i_1_n_0, + Q => \^mb_out\, + S => lpf_int + ); +SEQ_COUNTER: entity work.NewExtInst_TOP_proc_sys_reset_0_0_upcnt_n + port map ( + Q(5 downto 0) => seq_cnt(5 downto 0), + seq_clr => seq_clr, + seq_cnt_en => seq_cnt_en, + slowest_sync_clk => slowest_sync_clk + ); +\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0090" + ) + port map ( + I0 => seq_cnt_en, + I1 => seq_cnt(4), + I2 => seq_cnt(3), + I3 => seq_cnt(5), + O => p_5_out(0) + ); +\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \core_dec_reg_n_0_[1]\, + I1 => \bsr_dec_reg_n_0_[0]\, + O => p_5_out(2) + ); +\bsr_dec_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => p_5_out(0), + Q => \bsr_dec_reg_n_0_[0]\, + R => '0' + ); +\bsr_dec_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => p_5_out(2), + Q => \bsr_dec_reg_n_0_[2]\, + R => '0' + ); +bsr_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^bsr_out\, + I1 => \bsr_dec_reg_n_0_[2]\, + O => bsr_i_1_n_0 + ); +bsr_reg: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => bsr_i_1_n_0, + Q => \^bsr_out\, + S => lpf_int + ); +\core_dec[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9000" + ) + port map ( + I0 => seq_cnt_en, + I1 => seq_cnt(4), + I2 => seq_cnt(3), + I3 => seq_cnt(5), + O => \core_dec[0]_i_1_n_0\ + ); +\core_dec[2]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \core_dec_reg_n_0_[1]\, + I1 => \core_dec_reg_n_0_[0]\, + O => \core_dec[2]_i_1_n_0\ + ); +\core_dec_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => \core_dec[0]_i_1_n_0\, + Q => \core_dec_reg_n_0_[0]\, + R => '0' + ); +\core_dec_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => \pr_dec0__0\, + Q => \core_dec_reg_n_0_[1]\, + R => '0' + ); +\core_dec_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => \core_dec[2]_i_1_n_0\, + Q => p_0_in, + R => '0' + ); +from_sys_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^mb_out\, + I1 => seq_cnt_en, + O => from_sys_i_1_n_0 + ); +from_sys_reg: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => from_sys_i_1_n_0, + Q => seq_cnt_en, + S => lpf_int + ); +pr_dec0: unisim.vcomponents.LUT4 + generic map( + INIT => X"0018" + ) + port map ( + I0 => seq_cnt_en, + I1 => seq_cnt(0), + I2 => seq_cnt(2), + I3 => seq_cnt(1), + O => \pr_dec0__0\ + ); +\pr_dec[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0480" + ) + port map ( + I0 => seq_cnt_en, + I1 => seq_cnt(3), + I2 => seq_cnt(5), + I3 => seq_cnt(4), + O => p_3_out(0) + ); +\pr_dec[2]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \core_dec_reg_n_0_[1]\, + I1 => \pr_dec_reg_n_0_[0]\, + O => p_3_out(2) + ); +\pr_dec_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => p_3_out(0), + Q => \pr_dec_reg_n_0_[0]\, + R => '0' + ); +\pr_dec_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => p_3_out(2), + Q => \pr_dec_reg_n_0_[2]\, + R => '0' + ); +pr_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^pr_out\, + I1 => \pr_dec_reg_n_0_[2]\, + O => pr_i_1_n_0 + ); +pr_reg: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => pr_i_1_n_0, + Q => \^pr_out\, + S => lpf_int + ); +seq_clr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => '1', + Q => seq_clr, + R => lpf_int + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_proc_sys_reset_0_0_proc_sys_reset is + port ( + slowest_sync_clk : in STD_LOGIC; + ext_reset_in : in STD_LOGIC; + aux_reset_in : in STD_LOGIC; + mb_debug_sys_rst : in STD_LOGIC; + dcm_locked : in STD_LOGIC; + mb_reset : out STD_LOGIC; + bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); + peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); + interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); + peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute C_AUX_RESET_HIGH : string; + attribute C_AUX_RESET_HIGH of NewExtInst_TOP_proc_sys_reset_0_0_proc_sys_reset : entity is "1'b0"; + attribute C_AUX_RST_WIDTH : integer; + attribute C_AUX_RST_WIDTH of NewExtInst_TOP_proc_sys_reset_0_0_proc_sys_reset : entity is 4; + attribute C_EXT_RESET_HIGH : string; + attribute C_EXT_RESET_HIGH of NewExtInst_TOP_proc_sys_reset_0_0_proc_sys_reset : entity is "1'b0"; + attribute C_EXT_RST_WIDTH : integer; + attribute C_EXT_RST_WIDTH of NewExtInst_TOP_proc_sys_reset_0_0_proc_sys_reset : entity is 4; + attribute C_FAMILY : string; + attribute C_FAMILY of NewExtInst_TOP_proc_sys_reset_0_0_proc_sys_reset : entity is "zynq"; + attribute C_NUM_BUS_RST : integer; + attribute C_NUM_BUS_RST of NewExtInst_TOP_proc_sys_reset_0_0_proc_sys_reset : entity is 1; + attribute C_NUM_INTERCONNECT_ARESETN : integer; + attribute C_NUM_INTERCONNECT_ARESETN of NewExtInst_TOP_proc_sys_reset_0_0_proc_sys_reset : entity is 1; + attribute C_NUM_PERP_ARESETN : integer; + attribute C_NUM_PERP_ARESETN of NewExtInst_TOP_proc_sys_reset_0_0_proc_sys_reset : entity is 1; + attribute C_NUM_PERP_RST : integer; + attribute C_NUM_PERP_RST of NewExtInst_TOP_proc_sys_reset_0_0_proc_sys_reset : entity is 1; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of NewExtInst_TOP_proc_sys_reset_0_0_proc_sys_reset : entity is "proc_sys_reset"; +end NewExtInst_TOP_proc_sys_reset_0_0_proc_sys_reset; + +architecture STRUCTURE of NewExtInst_TOP_proc_sys_reset_0_0_proc_sys_reset is + signal Bsr_out : STD_LOGIC; + signal MB_out : STD_LOGIC; + signal Pr_out : STD_LOGIC; + signal SEQ_n_3 : STD_LOGIC; + signal SEQ_n_4 : STD_LOGIC; + signal lpf_int : STD_LOGIC; + attribute box_type : string; + attribute box_type of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : label is "PRIMITIVE"; + attribute box_type of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : label is "PRIMITIVE"; + attribute box_type of \BSR_OUT_DFF[0].FDRE_BSR\ : label is "PRIMITIVE"; + attribute box_type of FDRE_inst : label is "PRIMITIVE"; + attribute box_type of \PR_OUT_DFF[0].FDRE_PER\ : label is "PRIMITIVE"; +begin +\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\: unisim.vcomponents.FDRE + generic map( + INIT => '0', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => SEQ_n_3, + Q => interconnect_aresetn(0), + R => '0' + ); +\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\: unisim.vcomponents.FDRE + generic map( + INIT => '0', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => SEQ_n_4, + Q => peripheral_aresetn(0), + R => '0' + ); +\BSR_OUT_DFF[0].FDRE_BSR\: unisim.vcomponents.FDRE + generic map( + INIT => '1', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => Bsr_out, + Q => bus_struct_reset(0), + R => '0' + ); +EXT_LPF: entity work.NewExtInst_TOP_proc_sys_reset_0_0_lpf + port map ( + aux_reset_in => aux_reset_in, + dcm_locked => dcm_locked, + ext_reset_in => ext_reset_in, + lpf_int => lpf_int, + mb_debug_sys_rst => mb_debug_sys_rst, + slowest_sync_clk => slowest_sync_clk + ); +FDRE_inst: unisim.vcomponents.FDRE + generic map( + INIT => '1', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => MB_out, + Q => mb_reset, + R => '0' + ); +\PR_OUT_DFF[0].FDRE_PER\: unisim.vcomponents.FDRE + generic map( + INIT => '1', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => Pr_out, + Q => peripheral_reset(0), + R => '0' + ); +SEQ: entity work.NewExtInst_TOP_proc_sys_reset_0_0_sequence_psr + port map ( + Bsr_out => Bsr_out, + MB_out => MB_out, + Pr_out => Pr_out, + bsr_reg_0 => SEQ_n_3, + lpf_int => lpf_int, + pr_reg_0 => SEQ_n_4, + slowest_sync_clk => slowest_sync_clk + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_proc_sys_reset_0_0 is + port ( + slowest_sync_clk : in STD_LOGIC; + ext_reset_in : in STD_LOGIC; + aux_reset_in : in STD_LOGIC; + mb_debug_sys_rst : in STD_LOGIC; + dcm_locked : in STD_LOGIC; + mb_reset : out STD_LOGIC; + bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); + peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); + interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); + peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of NewExtInst_TOP_proc_sys_reset_0_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of NewExtInst_TOP_proc_sys_reset_0_0 : entity is "NewExtInst_TOP_proc_sys_reset_0_0,proc_sys_reset,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of NewExtInst_TOP_proc_sys_reset_0_0 : entity is "yes"; + attribute x_core_info : string; + attribute x_core_info of NewExtInst_TOP_proc_sys_reset_0_0 : entity is "proc_sys_reset,Vivado 2023.2"; +end NewExtInst_TOP_proc_sys_reset_0_0; + +architecture STRUCTURE of NewExtInst_TOP_proc_sys_reset_0_0 is + attribute C_AUX_RESET_HIGH : string; + attribute C_AUX_RESET_HIGH of U0 : label is "1'b0"; + attribute C_AUX_RST_WIDTH : integer; + attribute C_AUX_RST_WIDTH of U0 : label is 4; + attribute C_EXT_RESET_HIGH : string; + attribute C_EXT_RESET_HIGH of U0 : label is "1'b0"; + attribute C_EXT_RST_WIDTH : integer; + attribute C_EXT_RST_WIDTH of U0 : label is 4; + attribute C_FAMILY : string; + attribute C_FAMILY of U0 : label is "zynq"; + attribute C_NUM_BUS_RST : integer; + attribute C_NUM_BUS_RST of U0 : label is 1; + attribute C_NUM_INTERCONNECT_ARESETN : integer; + attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1; + attribute C_NUM_PERP_ARESETN : integer; + attribute C_NUM_PERP_ARESETN of U0 : label is 1; + attribute C_NUM_PERP_RST : integer; + attribute C_NUM_PERP_RST of U0 : label is 1; + attribute x_interface_info : string; + attribute x_interface_info of aux_reset_in : signal is "xilinx.com:signal:reset:1.0 aux_reset RST"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of aux_reset_in : signal is "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + attribute x_interface_info of ext_reset_in : signal is "xilinx.com:signal:reset:1.0 ext_reset RST"; + attribute x_interface_parameter of ext_reset_in : signal is "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + attribute x_interface_info of mb_debug_sys_rst : signal is "xilinx.com:signal:reset:1.0 dbg_reset RST"; + attribute x_interface_parameter of mb_debug_sys_rst : signal is "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0"; + attribute x_interface_info of mb_reset : signal is "xilinx.com:signal:reset:1.0 mb_rst RST"; + attribute x_interface_parameter of mb_reset : signal is "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0"; + attribute x_interface_info of slowest_sync_clk : signal is "xilinx.com:signal:clock:1.0 clock CLK"; + attribute x_interface_parameter of slowest_sync_clk : signal is "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 25000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN NewExtInst_TOP_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0"; + attribute x_interface_info of bus_struct_reset : signal is "xilinx.com:signal:reset:1.0 bus_struct_reset RST"; + attribute x_interface_parameter of bus_struct_reset : signal is "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0"; + attribute x_interface_info of interconnect_aresetn : signal is "xilinx.com:signal:reset:1.0 interconnect_low_rst RST"; + attribute x_interface_parameter of interconnect_aresetn : signal is "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0"; + attribute x_interface_info of peripheral_aresetn : signal is "xilinx.com:signal:reset:1.0 peripheral_low_rst RST"; + attribute x_interface_parameter of peripheral_aresetn : signal is "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0"; + attribute x_interface_info of peripheral_reset : signal is "xilinx.com:signal:reset:1.0 peripheral_high_rst RST"; + attribute x_interface_parameter of peripheral_reset : signal is "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0"; +begin +U0: entity work.NewExtInst_TOP_proc_sys_reset_0_0_proc_sys_reset + port map ( + aux_reset_in => aux_reset_in, + bus_struct_reset(0) => bus_struct_reset(0), + dcm_locked => dcm_locked, + ext_reset_in => ext_reset_in, + interconnect_aresetn(0) => interconnect_aresetn(0), + mb_debug_sys_rst => mb_debug_sys_rst, + mb_reset => mb_reset, + peripheral_aresetn(0) => peripheral_aresetn(0), + peripheral_reset(0) => peripheral_reset(0), + slowest_sync_clk => slowest_sync_clk + ); +end STRUCTURE; diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/sim/NewExtInst_TOP_proc_sys_reset_0_0.vhd b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/sim/NewExtInst_TOP_proc_sys_reset_0_0.vhd new file mode 100644 index 0000000..32aa332 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/sim/NewExtInst_TOP_proc_sys_reset_0_0.vhd @@ -0,0 +1,147 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0 +-- IP Revision: 14 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY proc_sys_reset_v5_0_14; +USE proc_sys_reset_v5_0_14.proc_sys_reset; + +ENTITY NewExtInst_TOP_proc_sys_reset_0_0 IS + PORT ( + slowest_sync_clk : IN STD_LOGIC; + ext_reset_in : IN STD_LOGIC; + aux_reset_in : IN STD_LOGIC; + mb_debug_sys_rst : IN STD_LOGIC; + dcm_locked : IN STD_LOGIC; + mb_reset : OUT STD_LOGIC; + bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); +END NewExtInst_TOP_proc_sys_reset_0_0; + +ARCHITECTURE NewExtInst_TOP_proc_sys_reset_0_0_arch OF NewExtInst_TOP_proc_sys_reset_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF NewExtInst_TOP_proc_sys_reset_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT proc_sys_reset IS + GENERIC ( + C_FAMILY : STRING; + C_EXT_RST_WIDTH : INTEGER; + C_AUX_RST_WIDTH : INTEGER; + C_EXT_RESET_HIGH : STD_LOGIC; + C_AUX_RESET_HIGH : STD_LOGIC; + C_NUM_BUS_RST : INTEGER; + C_NUM_PERP_RST : INTEGER; + C_NUM_INTERCONNECT_ARESETN : INTEGER; + C_NUM_PERP_ARESETN : INTEGER + ); + PORT ( + slowest_sync_clk : IN STD_LOGIC; + ext_reset_in : IN STD_LOGIC; + aux_reset_in : IN STD_LOGIC; + mb_debug_sys_rst : IN STD_LOGIC; + dcm_locked : IN STD_LOGIC; + mb_reset : OUT STD_LOGIC; + bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); + END COMPONENT proc_sys_reset; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 25000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN NewExtInst_TOP_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK"; +BEGIN + U0 : proc_sys_reset + GENERIC MAP ( + C_FAMILY => "zynq", + C_EXT_RST_WIDTH => 4, + C_AUX_RST_WIDTH => 4, + C_EXT_RESET_HIGH => '0', + C_AUX_RESET_HIGH => '0', + C_NUM_BUS_RST => 1, + C_NUM_PERP_RST => 1, + C_NUM_INTERCONNECT_ARESETN => 1, + C_NUM_PERP_ARESETN => 1 + ) + PORT MAP ( + slowest_sync_clk => slowest_sync_clk, + ext_reset_in => ext_reset_in, + aux_reset_in => aux_reset_in, + mb_debug_sys_rst => mb_debug_sys_rst, + dcm_locked => dcm_locked, + mb_reset => mb_reset, + bus_struct_reset => bus_struct_reset, + peripheral_reset => peripheral_reset, + interconnect_aresetn => interconnect_aresetn, + peripheral_aresetn => peripheral_aresetn + ); +END NewExtInst_TOP_proc_sys_reset_0_0_arch; diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0_sim_netlist.v b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0_sim_netlist.v new file mode 100644 index 0000000..112b086 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0_sim_netlist.v @@ -0,0 +1,6425 @@ +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +// Date : Fri May 15 15:27:00 2026 +// Host : mkb running 64-bit unknown +// Command : write_verilog -force -mode funcsim +// /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0_sim_netlist.v +// Design : NewExtInst_TOP_processing_system7_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z035ffg676-2 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "NewExtInst_TOP_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2023.2" *) +(* NotValidForBitStream *) +module NewExtInst_TOP_processing_system7_0_0 + (M_AXI_GP0_ARVALID, + M_AXI_GP0_AWVALID, + M_AXI_GP0_BREADY, + M_AXI_GP0_RREADY, + M_AXI_GP0_WLAST, + M_AXI_GP0_WVALID, + M_AXI_GP0_ARID, + M_AXI_GP0_AWID, + M_AXI_GP0_WID, + M_AXI_GP0_ARBURST, + M_AXI_GP0_ARLOCK, + M_AXI_GP0_ARSIZE, + M_AXI_GP0_AWBURST, + M_AXI_GP0_AWLOCK, + M_AXI_GP0_AWSIZE, + M_AXI_GP0_ARPROT, + M_AXI_GP0_AWPROT, + M_AXI_GP0_ARADDR, + M_AXI_GP0_AWADDR, + M_AXI_GP0_WDATA, + M_AXI_GP0_ARCACHE, + M_AXI_GP0_ARLEN, + M_AXI_GP0_ARQOS, + M_AXI_GP0_AWCACHE, + M_AXI_GP0_AWLEN, + M_AXI_GP0_AWQOS, + M_AXI_GP0_WSTRB, + M_AXI_GP0_ACLK, + M_AXI_GP0_ARREADY, + M_AXI_GP0_AWREADY, + M_AXI_GP0_BVALID, + M_AXI_GP0_RLAST, + M_AXI_GP0_RVALID, + M_AXI_GP0_WREADY, + M_AXI_GP0_BID, + M_AXI_GP0_RID, + M_AXI_GP0_BRESP, + M_AXI_GP0_RRESP, + M_AXI_GP0_RDATA, + FCLK_CLK0, + FCLK_CLK1, + FCLK_CLK2, + FCLK_CLK3, + FCLK_RESET0_N, + MIO, + DDR_CAS_n, + DDR_CKE, + DDR_Clk_n, + DDR_Clk, + DDR_CS_n, + DDR_DRSTB, + DDR_ODT, + DDR_RAS_n, + DDR_WEB, + DDR_BankAddr, + DDR_Addr, + DDR_VRN, + DDR_VRP, + DDR_DM, + DDR_DQ, + DDR_DQS_n, + DDR_DQS, + PS_SRSTB, + PS_CLK, + PS_PORB); + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) output M_AXI_GP0_ARVALID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) output M_AXI_GP0_AWVALID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) output M_AXI_GP0_BREADY; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) output M_AXI_GP0_RREADY; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) output M_AXI_GP0_WLAST; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) output M_AXI_GP0_WVALID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) output [11:0]M_AXI_GP0_ARID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) output [11:0]M_AXI_GP0_AWID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) output [11:0]M_AXI_GP0_WID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) output [1:0]M_AXI_GP0_ARBURST; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) output [1:0]M_AXI_GP0_ARLOCK; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) output [2:0]M_AXI_GP0_ARSIZE; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) output [1:0]M_AXI_GP0_AWBURST; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) output [1:0]M_AXI_GP0_AWLOCK; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) output [2:0]M_AXI_GP0_AWSIZE; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) output [2:0]M_AXI_GP0_ARPROT; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) output [2:0]M_AXI_GP0_AWPROT; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) output [31:0]M_AXI_GP0_ARADDR; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) output [31:0]M_AXI_GP0_AWADDR; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) output [31:0]M_AXI_GP0_WDATA; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) output [3:0]M_AXI_GP0_ARCACHE; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) output [3:0]M_AXI_GP0_ARLEN; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) output [3:0]M_AXI_GP0_ARQOS; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) output [3:0]M_AXI_GP0_AWCACHE; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) output [3:0]M_AXI_GP0_AWLEN; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) output [3:0]M_AXI_GP0_AWQOS; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) output [3:0]M_AXI_GP0_WSTRB; + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0" *) input M_AXI_GP0_ACLK; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) input M_AXI_GP0_ARREADY; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) input M_AXI_GP0_AWREADY; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) input M_AXI_GP0_BVALID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) input M_AXI_GP0_RLAST; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) input M_AXI_GP0_RVALID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) input M_AXI_GP0_WREADY; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) input [11:0]M_AXI_GP0_BID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input [11:0]M_AXI_GP0_RID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input [1:0]M_AXI_GP0_BRESP; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input [1:0]M_AXI_GP0_RRESP; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [31:0]M_AXI_GP0_RDATA; + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 25000000, PHASE 0.000, CLK_DOMAIN NewExtInst_TOP_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) output FCLK_CLK0; + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK1 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK1, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN NewExtInst_TOP_processing_system7_0_0_FCLK_CLK1, INSERT_VIP 0" *) output FCLK_CLK1; + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK2 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK2, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN NewExtInst_TOP_processing_system7_0_0_FCLK_CLK2, INSERT_VIP 0" *) output FCLK_CLK2; + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK3 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK3, FREQ_HZ 200000000, PHASE 0.000, CLK_DOMAIN NewExtInst_TOP_processing_system7_0_0_FCLK_CLK3, INSERT_VIP 0" *) output FCLK_CLK3; + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) output FCLK_RESET0_N; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11" *) inout [3:0]DDR_DQS; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout PS_PORB; + + wire \ ; + wire \ ; + wire [14:0]DDR_Addr; + wire [2:0]DDR_BankAddr; + wire DDR_CAS_n; + wire DDR_CKE; + wire DDR_CS_n; + wire DDR_Clk; + wire DDR_Clk_n; + wire [3:0]DDR_DM; + wire [31:0]DDR_DQ; + wire [3:0]DDR_DQS; + wire [3:0]DDR_DQS_n; + wire DDR_DRSTB; + wire DDR_ODT; + wire DDR_RAS_n; + wire DDR_VRN; + wire DDR_VRP; + wire DDR_WEB; + wire FCLK_CLK0; + wire FCLK_CLK1; + wire FCLK_CLK2; + wire FCLK_CLK3; + wire FCLK_RESET0_N; + wire [53:0]MIO; + wire M_AXI_GP0_ACLK; + wire [31:0]M_AXI_GP0_ARADDR; + wire [1:0]M_AXI_GP0_ARBURST; + wire [3:0]\^M_AXI_GP0_ARCACHE ; + wire [11:0]M_AXI_GP0_ARID; + wire [3:0]M_AXI_GP0_ARLEN; + wire [1:0]M_AXI_GP0_ARLOCK; + wire [2:0]M_AXI_GP0_ARPROT; + wire [3:0]M_AXI_GP0_ARQOS; + wire M_AXI_GP0_ARREADY; + wire [1:0]\^M_AXI_GP0_ARSIZE ; + wire M_AXI_GP0_ARVALID; + wire [31:0]M_AXI_GP0_AWADDR; + wire [1:0]M_AXI_GP0_AWBURST; + wire [3:0]\^M_AXI_GP0_AWCACHE ; + wire [11:0]M_AXI_GP0_AWID; + wire [3:0]M_AXI_GP0_AWLEN; + wire [1:0]M_AXI_GP0_AWLOCK; + wire [2:0]M_AXI_GP0_AWPROT; + wire [3:0]M_AXI_GP0_AWQOS; + wire M_AXI_GP0_AWREADY; + wire [1:0]\^M_AXI_GP0_AWSIZE ; + wire M_AXI_GP0_AWVALID; + wire [11:0]M_AXI_GP0_BID; + wire M_AXI_GP0_BREADY; + wire [1:0]M_AXI_GP0_BRESP; + wire M_AXI_GP0_BVALID; + wire [31:0]M_AXI_GP0_RDATA; + wire [11:0]M_AXI_GP0_RID; + wire M_AXI_GP0_RLAST; + wire M_AXI_GP0_RREADY; + wire [1:0]M_AXI_GP0_RRESP; + wire M_AXI_GP0_RVALID; + wire [31:0]M_AXI_GP0_WDATA; + wire [11:0]M_AXI_GP0_WID; + wire M_AXI_GP0_WLAST; + wire M_AXI_GP0_WREADY; + wire [3:0]M_AXI_GP0_WSTRB; + wire M_AXI_GP0_WVALID; + wire PS_CLK; + wire PS_PORB; + wire PS_SRSTB; + wire NLW_inst_CAN0_PHY_TX_UNCONNECTED; + wire NLW_inst_CAN1_PHY_TX_UNCONNECTED; + wire NLW_inst_DMA0_DAVALID_UNCONNECTED; + wire NLW_inst_DMA0_DRREADY_UNCONNECTED; + wire NLW_inst_DMA0_RSTN_UNCONNECTED; + wire NLW_inst_DMA1_DAVALID_UNCONNECTED; + wire NLW_inst_DMA1_DRREADY_UNCONNECTED; + wire NLW_inst_DMA1_RSTN_UNCONNECTED; + wire NLW_inst_DMA2_DAVALID_UNCONNECTED; + wire NLW_inst_DMA2_DRREADY_UNCONNECTED; + wire NLW_inst_DMA2_RSTN_UNCONNECTED; + wire NLW_inst_DMA3_DAVALID_UNCONNECTED; + wire NLW_inst_DMA3_DRREADY_UNCONNECTED; + wire NLW_inst_DMA3_RSTN_UNCONNECTED; + wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED; + wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED; + wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED; + wire NLW_inst_ENET0_MDIO_O_UNCONNECTED; + wire NLW_inst_ENET0_MDIO_T_UNCONNECTED; + wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED; + wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED; + wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED; + wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED; + wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED; + wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED; + wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED; + wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED; + wire NLW_inst_ENET0_SOF_RX_UNCONNECTED; + wire NLW_inst_ENET0_SOF_TX_UNCONNECTED; + wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED; + wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED; + wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED; + wire NLW_inst_ENET1_MDIO_O_UNCONNECTED; + wire NLW_inst_ENET1_MDIO_T_UNCONNECTED; + wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED; + wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED; + wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED; + wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED; + wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED; + wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED; + wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED; + wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED; + wire NLW_inst_ENET1_SOF_RX_UNCONNECTED; + wire NLW_inst_ENET1_SOF_TX_UNCONNECTED; + wire NLW_inst_EVENT_EVENTO_UNCONNECTED; + wire NLW_inst_FCLK_RESET1_N_UNCONNECTED; + wire NLW_inst_FCLK_RESET2_N_UNCONNECTED; + wire NLW_inst_FCLK_RESET3_N_UNCONNECTED; + wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED; + wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED; + wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED; + wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED; + wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED; + wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED; + wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED; + wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED; + wire NLW_inst_I2C0_SCL_O_UNCONNECTED; + wire NLW_inst_I2C0_SCL_T_UNCONNECTED; + wire NLW_inst_I2C0_SDA_O_UNCONNECTED; + wire NLW_inst_I2C0_SDA_T_UNCONNECTED; + wire NLW_inst_I2C1_SCL_O_UNCONNECTED; + wire NLW_inst_I2C1_SCL_T_UNCONNECTED; + wire NLW_inst_I2C1_SDA_O_UNCONNECTED; + wire NLW_inst_I2C1_SDA_T_UNCONNECTED; + wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED; + wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED; + wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED; + wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED; + wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED; + wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED; + wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED; + wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED; + wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED; + wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED; + wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED; + wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED; + wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED; + wire NLW_inst_PJTAG_TDO_UNCONNECTED; + wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED; + wire NLW_inst_SDIO0_CLK_UNCONNECTED; + wire NLW_inst_SDIO0_CMD_O_UNCONNECTED; + wire NLW_inst_SDIO0_CMD_T_UNCONNECTED; + wire NLW_inst_SDIO0_LED_UNCONNECTED; + wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED; + wire NLW_inst_SDIO1_CLK_UNCONNECTED; + wire NLW_inst_SDIO1_CMD_O_UNCONNECTED; + wire NLW_inst_SDIO1_CMD_T_UNCONNECTED; + wire NLW_inst_SDIO1_LED_UNCONNECTED; + wire NLW_inst_SPI0_MISO_O_UNCONNECTED; + wire NLW_inst_SPI0_MISO_T_UNCONNECTED; + wire NLW_inst_SPI0_MOSI_O_UNCONNECTED; + wire NLW_inst_SPI0_MOSI_T_UNCONNECTED; + wire NLW_inst_SPI0_SCLK_O_UNCONNECTED; + wire NLW_inst_SPI0_SCLK_T_UNCONNECTED; + wire NLW_inst_SPI0_SS1_O_UNCONNECTED; + wire NLW_inst_SPI0_SS2_O_UNCONNECTED; + wire NLW_inst_SPI0_SS_O_UNCONNECTED; + wire NLW_inst_SPI0_SS_T_UNCONNECTED; + wire NLW_inst_SPI1_MISO_O_UNCONNECTED; + wire NLW_inst_SPI1_MISO_T_UNCONNECTED; + wire NLW_inst_SPI1_MOSI_O_UNCONNECTED; + wire NLW_inst_SPI1_MOSI_T_UNCONNECTED; + wire NLW_inst_SPI1_SCLK_O_UNCONNECTED; + wire NLW_inst_SPI1_SCLK_T_UNCONNECTED; + wire NLW_inst_SPI1_SS1_O_UNCONNECTED; + wire NLW_inst_SPI1_SS2_O_UNCONNECTED; + wire NLW_inst_SPI1_SS_O_UNCONNECTED; + wire NLW_inst_SPI1_SS_T_UNCONNECTED; + wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED; + wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED; + wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED; + wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED; + wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED; + wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED; + wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED; + wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED; + wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED; + wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED; + wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED; + wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED; + wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED; + wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED; + wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED; + wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED; + wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED; + wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED; + wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED; + wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED; + wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED; + wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED; + wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED; + wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED; + wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED; + wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED; + wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED; + wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED; + wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED; + wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED; + wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED; + wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED; + wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED; + wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED; + wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED; + wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED; + wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED; + wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED; + wire NLW_inst_TRACE_CTL_UNCONNECTED; + wire NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED; + wire NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED; + wire NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED; + wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED; + wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED; + wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED; + wire NLW_inst_UART0_DTRN_UNCONNECTED; + wire NLW_inst_UART0_RTSN_UNCONNECTED; + wire NLW_inst_UART0_TX_UNCONNECTED; + wire NLW_inst_UART1_DTRN_UNCONNECTED; + wire NLW_inst_UART1_RTSN_UNCONNECTED; + wire NLW_inst_UART1_TX_UNCONNECTED; + wire NLW_inst_USB0_VBUS_PWRSELECT_UNCONNECTED; + wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED; + wire NLW_inst_WDT_RST_OUT_UNCONNECTED; + wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED; + wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED; + wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED; + wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED; + wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED; + wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED; + wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED; + wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED; + wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED; + wire [63:0]NLW_inst_GPIO_O_UNCONNECTED; + wire [63:0]NLW_inst_GPIO_T_UNCONNECTED; + wire [1:1]NLW_inst_M_AXI_GP0_ARCACHE_UNCONNECTED; + wire [2:2]NLW_inst_M_AXI_GP0_ARSIZE_UNCONNECTED; + wire [1:1]NLW_inst_M_AXI_GP0_AWCACHE_UNCONNECTED; + wire [2:2]NLW_inst_M_AXI_GP0_AWSIZE_UNCONNECTED; + wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED; + wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED; + wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED; + wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED; + wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED; + wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED; + wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED; + wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED; + wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED; + wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED; + wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED; + wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED; + wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED; + wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED; + wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED; + wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED; + wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED; + wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED; + wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED; + wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED; + wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED; + wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED; + wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED; + wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED; + wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED; + wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED; + wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED; + wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED; + wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED; + wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED; + wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED; + wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED; + wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED; + wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED; + wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED; + wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED; + wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED; + wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED; + wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED; + wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED; + wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED; + wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED; + wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED; + wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED; + wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED; + wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED; + wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED; + wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED; + wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED; + wire [1:0]NLW_inst_USB0_PORT_INDCTL_UNCONNECTED; + wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED; + + assign M_AXI_GP0_ARCACHE[3:2] = \^M_AXI_GP0_ARCACHE [3:2]; + assign M_AXI_GP0_ARCACHE[1] = \ ; + assign M_AXI_GP0_ARCACHE[0] = \^M_AXI_GP0_ARCACHE [0]; + assign M_AXI_GP0_ARSIZE[2] = \ ; + assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0]; + assign M_AXI_GP0_AWCACHE[3:2] = \^M_AXI_GP0_AWCACHE [3:2]; + assign M_AXI_GP0_AWCACHE[1] = \ ; + assign M_AXI_GP0_AWCACHE[0] = \^M_AXI_GP0_AWCACHE [0]; + assign M_AXI_GP0_AWSIZE[2] = \ ; + assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0]; + GND GND + (.G(\ )); + VCC VCC + (.P(\ )); + (* C_DM_WIDTH = "4" *) + (* C_DQS_WIDTH = "4" *) + (* C_DQ_WIDTH = "32" *) + (* C_EMIO_GPIO_WIDTH = "64" *) + (* C_EN_EMIO_ENET0 = "0" *) + (* C_EN_EMIO_ENET1 = "0" *) + (* C_EN_EMIO_PJTAG = "0" *) + (* C_EN_EMIO_TRACE = "0" *) + (* C_FCLK_CLK0_BUF = "TRUE" *) + (* C_FCLK_CLK1_BUF = "TRUE" *) + (* C_FCLK_CLK2_BUF = "TRUE" *) + (* C_FCLK_CLK3_BUF = "TRUE" *) + (* C_GP0_EN_MODIFIABLE_TXN = "1" *) + (* C_GP1_EN_MODIFIABLE_TXN = "1" *) + (* C_INCLUDE_ACP_TRANS_CHECK = "0" *) + (* C_INCLUDE_TRACE_BUFFER = "0" *) + (* C_IRQ_F2P_MODE = "DIRECT" *) + (* C_MIO_PRIMITIVE = "54" *) + (* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) + (* C_M_AXI_GP0_ID_WIDTH = "12" *) + (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *) + (* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) + (* C_M_AXI_GP1_ID_WIDTH = "12" *) + (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *) + (* C_NUM_F2P_INTR_INPUTS = "1" *) + (* C_PACKAGE_NAME = "ffg676" *) + (* C_PS7_SI_REV = "PRODUCTION" *) + (* C_S_AXI_ACP_ARUSER_VAL = "31" *) + (* C_S_AXI_ACP_AWUSER_VAL = "31" *) + (* C_S_AXI_ACP_ID_WIDTH = "3" *) + (* C_S_AXI_GP0_ID_WIDTH = "6" *) + (* C_S_AXI_GP1_ID_WIDTH = "6" *) + (* C_S_AXI_HP0_DATA_WIDTH = "64" *) + (* C_S_AXI_HP0_ID_WIDTH = "6" *) + (* C_S_AXI_HP1_DATA_WIDTH = "64" *) + (* C_S_AXI_HP1_ID_WIDTH = "6" *) + (* C_S_AXI_HP2_DATA_WIDTH = "64" *) + (* C_S_AXI_HP2_ID_WIDTH = "6" *) + (* C_S_AXI_HP3_DATA_WIDTH = "64" *) + (* C_S_AXI_HP3_ID_WIDTH = "6" *) + (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) + (* C_TRACE_BUFFER_FIFO_SIZE = "128" *) + (* C_TRACE_INTERNAL_WIDTH = "2" *) + (* C_TRACE_PIPELINE_WIDTH = "8" *) + (* C_USE_AXI_NONSECURE = "0" *) + (* C_USE_DEFAULT_ACP_USER_VAL = "0" *) + (* C_USE_M_AXI_GP0 = "1" *) + (* C_USE_M_AXI_GP1 = "0" *) + (* C_USE_S_AXI_ACP = "0" *) + (* C_USE_S_AXI_GP0 = "0" *) + (* C_USE_S_AXI_GP1 = "0" *) + (* C_USE_S_AXI_HP0 = "0" *) + (* C_USE_S_AXI_HP1 = "0" *) + (* C_USE_S_AXI_HP2 = "0" *) + (* C_USE_S_AXI_HP3 = "0" *) + (* HW_HANDOFF = "NewExtInst_TOP_processing_system7_0_0.hwdef" *) + (* POWER = "/>" *) + (* USE_TRACE_DATA_EDGE_DETECTOR = "0" *) + NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 inst + (.CAN0_PHY_RX(1'b0), + .CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED), + .CAN1_PHY_RX(1'b0), + .CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED), + .Core0_nFIQ(1'b0), + .Core0_nIRQ(1'b0), + .Core1_nFIQ(1'b0), + .Core1_nIRQ(1'b0), + .DDR_ARB({1'b0,1'b0,1'b0,1'b0}), + .DDR_Addr(DDR_Addr), + .DDR_BankAddr(DDR_BankAddr), + .DDR_CAS_n(DDR_CAS_n), + .DDR_CKE(DDR_CKE), + .DDR_CS_n(DDR_CS_n), + .DDR_Clk(DDR_Clk), + .DDR_Clk_n(DDR_Clk_n), + .DDR_DM(DDR_DM), + .DDR_DQ(DDR_DQ), + .DDR_DQS(DDR_DQS), + .DDR_DQS_n(DDR_DQS_n), + .DDR_DRSTB(DDR_DRSTB), + .DDR_ODT(DDR_ODT), + .DDR_RAS_n(DDR_RAS_n), + .DDR_VRN(DDR_VRN), + .DDR_VRP(DDR_VRP), + .DDR_WEB(DDR_WEB), + .DMA0_ACLK(1'b0), + .DMA0_DAREADY(1'b0), + .DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]), + .DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED), + .DMA0_DRLAST(1'b0), + .DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED), + .DMA0_DRTYPE({1'b0,1'b0}), + .DMA0_DRVALID(1'b0), + .DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED), + .DMA1_ACLK(1'b0), + .DMA1_DAREADY(1'b0), + .DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]), + .DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED), + .DMA1_DRLAST(1'b0), + .DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED), + .DMA1_DRTYPE({1'b0,1'b0}), + .DMA1_DRVALID(1'b0), + .DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED), + .DMA2_ACLK(1'b0), + .DMA2_DAREADY(1'b0), + .DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]), + .DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED), + .DMA2_DRLAST(1'b0), + .DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED), + .DMA2_DRTYPE({1'b0,1'b0}), + .DMA2_DRVALID(1'b0), + .DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED), + .DMA3_ACLK(1'b0), + .DMA3_DAREADY(1'b0), + .DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]), + .DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED), + .DMA3_DRLAST(1'b0), + .DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED), + .DMA3_DRTYPE({1'b0,1'b0}), + .DMA3_DRVALID(1'b0), + .DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED), + .ENET0_EXT_INTIN(1'b0), + .ENET0_GMII_COL(1'b0), + .ENET0_GMII_CRS(1'b0), + .ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .ENET0_GMII_RX_CLK(1'b0), + .ENET0_GMII_RX_DV(1'b0), + .ENET0_GMII_RX_ER(1'b0), + .ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]), + .ENET0_GMII_TX_CLK(1'b0), + .ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED), + .ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED), + .ENET0_MDIO_I(1'b0), + .ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED), + .ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED), + .ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED), + .ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED), + .ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED), + .ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED), + .ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED), + .ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED), + .ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED), + .ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED), + .ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED), + .ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED), + .ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED), + .ENET1_EXT_INTIN(1'b0), + .ENET1_GMII_COL(1'b0), + .ENET1_GMII_CRS(1'b0), + .ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .ENET1_GMII_RX_CLK(1'b0), + .ENET1_GMII_RX_DV(1'b0), + .ENET1_GMII_RX_ER(1'b0), + .ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]), + .ENET1_GMII_TX_CLK(1'b0), + .ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED), + .ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED), + .ENET1_MDIO_I(1'b0), + .ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED), + .ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED), + .ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED), + .ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED), + .ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED), + .ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED), + .ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED), + .ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED), + .ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED), + .ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED), + .ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED), + .ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED), + .ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED), + .EVENT_EVENTI(1'b0), + .EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED), + .EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]), + .EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]), + .FCLK_CLK0(FCLK_CLK0), + .FCLK_CLK1(FCLK_CLK1), + .FCLK_CLK2(FCLK_CLK2), + .FCLK_CLK3(FCLK_CLK3), + .FCLK_CLKTRIG0_N(1'b0), + .FCLK_CLKTRIG1_N(1'b0), + .FCLK_CLKTRIG2_N(1'b0), + .FCLK_CLKTRIG3_N(1'b0), + .FCLK_RESET0_N(FCLK_RESET0_N), + .FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED), + .FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED), + .FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED), + .FPGA_IDLE_N(1'b0), + .FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}), + .FTMD_TRACEIN_CLK(1'b0), + .FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .FTMD_TRACEIN_VALID(1'b0), + .FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED), + .FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED), + .FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED), + .FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED), + .FTMT_F2P_TRIG_0(1'b0), + .FTMT_F2P_TRIG_1(1'b0), + .FTMT_F2P_TRIG_2(1'b0), + .FTMT_F2P_TRIG_3(1'b0), + .FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]), + .FTMT_P2F_TRIGACK_0(1'b0), + .FTMT_P2F_TRIGACK_1(1'b0), + .FTMT_P2F_TRIGACK_2(1'b0), + .FTMT_P2F_TRIGACK_3(1'b0), + .FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED), + .FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED), + .FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED), + .FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED), + .GPIO_I({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .GPIO_O(NLW_inst_GPIO_O_UNCONNECTED[63:0]), + .GPIO_T(NLW_inst_GPIO_T_UNCONNECTED[63:0]), + .I2C0_SCL_I(1'b0), + .I2C0_SCL_O(NLW_inst_I2C0_SCL_O_UNCONNECTED), + .I2C0_SCL_T(NLW_inst_I2C0_SCL_T_UNCONNECTED), + .I2C0_SDA_I(1'b0), + .I2C0_SDA_O(NLW_inst_I2C0_SDA_O_UNCONNECTED), + .I2C0_SDA_T(NLW_inst_I2C0_SDA_T_UNCONNECTED), + .I2C1_SCL_I(1'b0), + .I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED), + .I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED), + .I2C1_SDA_I(1'b0), + .I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED), + .I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED), + .IRQ_F2P(1'b0), + .IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED), + .IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED), + .IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED), + .IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED), + .IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED), + .IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED), + .IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED), + .IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED), + .IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED), + .IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED), + .IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED), + .IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED), + .IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED), + .IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED), + .IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED), + .IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED), + .IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED), + .IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED), + .IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED), + .IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED), + .IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED), + .IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED), + .IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED), + .IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED), + .IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED), + .IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED), + .IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED), + .IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED), + .IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED), + .MIO(MIO), + .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK), + .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR), + .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST), + .M_AXI_GP0_ARCACHE(\^M_AXI_GP0_ARCACHE ), + .M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED), + .M_AXI_GP0_ARID(M_AXI_GP0_ARID), + .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN), + .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK), + .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT), + .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS), + .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY), + .M_AXI_GP0_ARSIZE({NLW_inst_M_AXI_GP0_ARSIZE_UNCONNECTED[2],\^M_AXI_GP0_ARSIZE }), + .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID), + .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR), + .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST), + .M_AXI_GP0_AWCACHE(\^M_AXI_GP0_AWCACHE ), + .M_AXI_GP0_AWID(M_AXI_GP0_AWID), + .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN), + .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK), + .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT), + .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS), + .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY), + .M_AXI_GP0_AWSIZE({NLW_inst_M_AXI_GP0_AWSIZE_UNCONNECTED[2],\^M_AXI_GP0_AWSIZE }), + .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID), + .M_AXI_GP0_BID(M_AXI_GP0_BID), + .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY), + .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP), + .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID), + .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA), + .M_AXI_GP0_RID(M_AXI_GP0_RID), + .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST), + .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY), + .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP), + .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID), + .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA), + .M_AXI_GP0_WID(M_AXI_GP0_WID), + .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST), + .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY), + .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB), + .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID), + .M_AXI_GP1_ACLK(1'b0), + .M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]), + .M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]), + .M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]), + .M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED), + .M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]), + .M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]), + .M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]), + .M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]), + .M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]), + .M_AXI_GP1_ARREADY(1'b0), + .M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]), + .M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED), + .M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]), + .M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]), + .M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]), + .M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]), + .M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]), + .M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]), + .M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]), + .M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]), + .M_AXI_GP1_AWREADY(1'b0), + .M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]), + .M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED), + .M_AXI_GP1_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED), + .M_AXI_GP1_BRESP({1'b0,1'b0}), + .M_AXI_GP1_BVALID(1'b0), + .M_AXI_GP1_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .M_AXI_GP1_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .M_AXI_GP1_RLAST(1'b0), + .M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED), + .M_AXI_GP1_RRESP({1'b0,1'b0}), + .M_AXI_GP1_RVALID(1'b0), + .M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]), + .M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]), + .M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED), + .M_AXI_GP1_WREADY(1'b0), + .M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]), + .M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED), + .PJTAG_TCK(1'b0), + .PJTAG_TDI(1'b0), + .PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED), + .PJTAG_TMS(1'b0), + .PS_CLK(PS_CLK), + .PS_PORB(PS_PORB), + .PS_SRSTB(PS_SRSTB), + .SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED), + .SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]), + .SDIO0_CDN(1'b0), + .SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED), + .SDIO0_CLK_FB(1'b0), + .SDIO0_CMD_I(1'b0), + .SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED), + .SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED), + .SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}), + .SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]), + .SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]), + .SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED), + .SDIO0_WP(1'b0), + .SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED), + .SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]), + .SDIO1_CDN(1'b0), + .SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED), + .SDIO1_CLK_FB(1'b0), + .SDIO1_CMD_I(1'b0), + .SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED), + .SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED), + .SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}), + .SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]), + .SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]), + .SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED), + .SDIO1_WP(1'b0), + .SPI0_MISO_I(1'b0), + .SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED), + .SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED), + .SPI0_MOSI_I(1'b0), + .SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED), + .SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED), + .SPI0_SCLK_I(1'b0), + .SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED), + .SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED), + .SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED), + .SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED), + .SPI0_SS_I(1'b0), + .SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED), + .SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED), + .SPI1_MISO_I(1'b0), + .SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED), + .SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED), + .SPI1_MOSI_I(1'b0), + .SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED), + .SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED), + .SPI1_SCLK_I(1'b0), + .SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED), + .SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED), + .SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED), + .SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED), + .SPI1_SS_I(1'b0), + .SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED), + .SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED), + .SRAM_INTIN(1'b0), + .S_AXI_ACP_ACLK(1'b0), + .S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARBURST({1'b0,1'b0}), + .S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED), + .S_AXI_ACP_ARID({1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARLOCK({1'b0,1'b0}), + .S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED), + .S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARVALID(1'b0), + .S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWBURST({1'b0,1'b0}), + .S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWID({1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWLOCK({1'b0,1'b0}), + .S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED), + .S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWVALID(1'b0), + .S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]), + .S_AXI_ACP_BREADY(1'b0), + .S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]), + .S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED), + .S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]), + .S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]), + .S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED), + .S_AXI_ACP_RREADY(1'b0), + .S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]), + .S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED), + .S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_WID({1'b0,1'b0,1'b0}), + .S_AXI_ACP_WLAST(1'b0), + .S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED), + .S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_WVALID(1'b0), + .S_AXI_GP0_ACLK(1'b0), + .S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_ARBURST({1'b0,1'b0}), + .S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED), + .S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_ARLOCK({1'b0,1'b0}), + .S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}), + .S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED), + .S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}), + .S_AXI_GP0_ARVALID(1'b0), + .S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_AWBURST({1'b0,1'b0}), + .S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_AWLOCK({1'b0,1'b0}), + .S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}), + .S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED), + .S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}), + .S_AXI_GP0_AWVALID(1'b0), + .S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]), + .S_AXI_GP0_BREADY(1'b0), + .S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]), + .S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED), + .S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]), + .S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]), + .S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED), + .S_AXI_GP0_RREADY(1'b0), + .S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]), + .S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED), + .S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_WLAST(1'b0), + .S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED), + .S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_WVALID(1'b0), + .S_AXI_GP1_ACLK(1'b0), + .S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_ARBURST({1'b0,1'b0}), + .S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED), + .S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_ARLOCK({1'b0,1'b0}), + .S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}), + .S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED), + .S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}), + .S_AXI_GP1_ARVALID(1'b0), + .S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_AWBURST({1'b0,1'b0}), + .S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_AWLOCK({1'b0,1'b0}), + .S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}), + .S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED), + .S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}), + .S_AXI_GP1_AWVALID(1'b0), + .S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]), + .S_AXI_GP1_BREADY(1'b0), + .S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]), + .S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED), + .S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]), + .S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]), + .S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED), + .S_AXI_GP1_RREADY(1'b0), + .S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]), + .S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED), + .S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_WLAST(1'b0), + .S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED), + .S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_WVALID(1'b0), + .S_AXI_HP0_ACLK(1'b0), + .S_AXI_HP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_ARBURST({1'b0,1'b0}), + .S_AXI_HP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED), + .S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_ARLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_ARLOCK({1'b0,1'b0}), + .S_AXI_HP0_ARPROT({1'b0,1'b0,1'b0}), + .S_AXI_HP0_ARQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED), + .S_AXI_HP0_ARSIZE({1'b0,1'b0,1'b0}), + .S_AXI_HP0_ARVALID(1'b0), + .S_AXI_HP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_AWBURST({1'b0,1'b0}), + .S_AXI_HP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_AWLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_AWLOCK({1'b0,1'b0}), + .S_AXI_HP0_AWPROT({1'b0,1'b0,1'b0}), + .S_AXI_HP0_AWQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED), + .S_AXI_HP0_AWSIZE({1'b0,1'b0,1'b0}), + .S_AXI_HP0_AWVALID(1'b0), + .S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]), + .S_AXI_HP0_BREADY(1'b0), + .S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]), + .S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED), + .S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]), + .S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]), + .S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]), + .S_AXI_HP0_RDISSUECAP1_EN(1'b0), + .S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]), + .S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED), + .S_AXI_HP0_RREADY(1'b0), + .S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]), + .S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED), + .S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]), + .S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]), + .S_AXI_HP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_WLAST(1'b0), + .S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED), + .S_AXI_HP0_WRISSUECAP1_EN(1'b0), + .S_AXI_HP0_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_WVALID(1'b0), + .S_AXI_HP1_ACLK(1'b0), + .S_AXI_HP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_ARBURST({1'b0,1'b0}), + .S_AXI_HP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED), + .S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_ARLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_ARLOCK({1'b0,1'b0}), + .S_AXI_HP1_ARPROT({1'b0,1'b0,1'b0}), + .S_AXI_HP1_ARQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED), + .S_AXI_HP1_ARSIZE({1'b0,1'b0,1'b0}), + .S_AXI_HP1_ARVALID(1'b0), + .S_AXI_HP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_AWBURST({1'b0,1'b0}), + .S_AXI_HP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_AWLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_AWLOCK({1'b0,1'b0}), + .S_AXI_HP1_AWPROT({1'b0,1'b0,1'b0}), + .S_AXI_HP1_AWQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED), + .S_AXI_HP1_AWSIZE({1'b0,1'b0,1'b0}), + .S_AXI_HP1_AWVALID(1'b0), + .S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]), + .S_AXI_HP1_BREADY(1'b0), + .S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]), + .S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED), + .S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]), + .S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]), + .S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]), + .S_AXI_HP1_RDISSUECAP1_EN(1'b0), + .S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]), + .S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED), + .S_AXI_HP1_RREADY(1'b0), + .S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]), + .S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED), + .S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]), + .S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]), + .S_AXI_HP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_WLAST(1'b0), + .S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED), + .S_AXI_HP1_WRISSUECAP1_EN(1'b0), + .S_AXI_HP1_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_WVALID(1'b0), + .S_AXI_HP2_ACLK(1'b0), + .S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_ARBURST({1'b0,1'b0}), + .S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED), + .S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_ARLOCK({1'b0,1'b0}), + .S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}), + .S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED), + .S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}), + .S_AXI_HP2_ARVALID(1'b0), + .S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_AWBURST({1'b0,1'b0}), + .S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_AWLOCK({1'b0,1'b0}), + .S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}), + .S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED), + .S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}), + .S_AXI_HP2_AWVALID(1'b0), + .S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]), + .S_AXI_HP2_BREADY(1'b0), + .S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]), + .S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED), + .S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]), + .S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]), + .S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]), + .S_AXI_HP2_RDISSUECAP1_EN(1'b0), + .S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]), + .S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED), + .S_AXI_HP2_RREADY(1'b0), + .S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]), + .S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED), + .S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]), + .S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]), + .S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_WLAST(1'b0), + .S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED), + .S_AXI_HP2_WRISSUECAP1_EN(1'b0), + .S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_WVALID(1'b0), + .S_AXI_HP3_ACLK(1'b0), + .S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_ARBURST({1'b0,1'b0}), + .S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED), + .S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_ARLOCK({1'b0,1'b0}), + .S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}), + .S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED), + .S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}), + .S_AXI_HP3_ARVALID(1'b0), + .S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_AWBURST({1'b0,1'b0}), + .S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_AWLOCK({1'b0,1'b0}), + .S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}), + .S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED), + .S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}), + .S_AXI_HP3_AWVALID(1'b0), + .S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]), + .S_AXI_HP3_BREADY(1'b0), + .S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]), + .S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED), + .S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]), + .S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]), + .S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]), + .S_AXI_HP3_RDISSUECAP1_EN(1'b0), + .S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]), + .S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED), + .S_AXI_HP3_RREADY(1'b0), + .S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]), + .S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED), + .S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]), + .S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]), + .S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_WLAST(1'b0), + .S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED), + .S_AXI_HP3_WRISSUECAP1_EN(1'b0), + .S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_WVALID(1'b0), + .TRACE_CLK(1'b0), + .TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED), + .TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED), + .TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]), + .TTC0_CLK0_IN(1'b0), + .TTC0_CLK1_IN(1'b0), + .TTC0_CLK2_IN(1'b0), + .TTC0_WAVE0_OUT(NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED), + .TTC0_WAVE1_OUT(NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED), + .TTC0_WAVE2_OUT(NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED), + .TTC1_CLK0_IN(1'b0), + .TTC1_CLK1_IN(1'b0), + .TTC1_CLK2_IN(1'b0), + .TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED), + .TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED), + .TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED), + .UART0_CTSN(1'b0), + .UART0_DCDN(1'b0), + .UART0_DSRN(1'b0), + .UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED), + .UART0_RIN(1'b0), + .UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED), + .UART0_RX(1'b1), + .UART0_TX(NLW_inst_UART0_TX_UNCONNECTED), + .UART1_CTSN(1'b0), + .UART1_DCDN(1'b0), + .UART1_DSRN(1'b0), + .UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED), + .UART1_RIN(1'b0), + .UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED), + .UART1_RX(1'b1), + .UART1_TX(NLW_inst_UART1_TX_UNCONNECTED), + .USB0_PORT_INDCTL(NLW_inst_USB0_PORT_INDCTL_UNCONNECTED[1:0]), + .USB0_VBUS_PWRFAULT(1'b0), + .USB0_VBUS_PWRSELECT(NLW_inst_USB0_VBUS_PWRSELECT_UNCONNECTED), + .USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]), + .USB1_VBUS_PWRFAULT(1'b0), + .USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED), + .WDT_CLK_IN(1'b0), + .WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED)); +endmodule + +(* C_DM_WIDTH = "4" *) (* C_DQS_WIDTH = "4" *) (* C_DQ_WIDTH = "32" *) +(* C_EMIO_GPIO_WIDTH = "64" *) (* C_EN_EMIO_ENET0 = "0" *) (* C_EN_EMIO_ENET1 = "0" *) +(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "TRUE" *) +(* C_FCLK_CLK1_BUF = "TRUE" *) (* C_FCLK_CLK2_BUF = "TRUE" *) (* C_FCLK_CLK3_BUF = "TRUE" *) +(* C_GP0_EN_MODIFIABLE_TXN = "1" *) (* C_GP1_EN_MODIFIABLE_TXN = "1" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *) +(* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "54" *) +(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP0_ID_WIDTH = "12" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *) +(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP1_ID_WIDTH = "12" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *) +(* C_NUM_F2P_INTR_INPUTS = "1" *) (* C_PACKAGE_NAME = "ffg676" *) (* C_PS7_SI_REV = "PRODUCTION" *) +(* C_S_AXI_ACP_ARUSER_VAL = "31" *) (* C_S_AXI_ACP_AWUSER_VAL = "31" *) (* C_S_AXI_ACP_ID_WIDTH = "3" *) +(* C_S_AXI_GP0_ID_WIDTH = "6" *) (* C_S_AXI_GP1_ID_WIDTH = "6" *) (* C_S_AXI_HP0_DATA_WIDTH = "64" *) +(* C_S_AXI_HP0_ID_WIDTH = "6" *) (* C_S_AXI_HP1_DATA_WIDTH = "64" *) (* C_S_AXI_HP1_ID_WIDTH = "6" *) +(* C_S_AXI_HP2_DATA_WIDTH = "64" *) (* C_S_AXI_HP2_ID_WIDTH = "6" *) (* C_S_AXI_HP3_DATA_WIDTH = "64" *) +(* C_S_AXI_HP3_ID_WIDTH = "6" *) (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) (* C_TRACE_BUFFER_FIFO_SIZE = "128" *) +(* C_TRACE_INTERNAL_WIDTH = "2" *) (* C_TRACE_PIPELINE_WIDTH = "8" *) (* C_USE_AXI_NONSECURE = "0" *) +(* C_USE_DEFAULT_ACP_USER_VAL = "0" *) (* C_USE_M_AXI_GP0 = "1" *) (* C_USE_M_AXI_GP1 = "0" *) +(* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *) +(* C_USE_S_AXI_HP0 = "0" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *) +(* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "NewExtInst_TOP_processing_system7_0_0.hwdef" *) (* ORIG_REF_NAME = "processing_system7_v5_5_processing_system7" *) +(* POWER = "/>" *) (* USE_TRACE_DATA_EDGE_DETECTOR = "0" *) +module NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 + (CAN0_PHY_TX, + CAN0_PHY_RX, + CAN1_PHY_TX, + CAN1_PHY_RX, + ENET0_GMII_TX_EN, + ENET0_GMII_TX_ER, + ENET0_MDIO_MDC, + ENET0_MDIO_O, + ENET0_MDIO_T, + ENET0_PTP_DELAY_REQ_RX, + ENET0_PTP_DELAY_REQ_TX, + ENET0_PTP_PDELAY_REQ_RX, + ENET0_PTP_PDELAY_REQ_TX, + ENET0_PTP_PDELAY_RESP_RX, + ENET0_PTP_PDELAY_RESP_TX, + ENET0_PTP_SYNC_FRAME_RX, + ENET0_PTP_SYNC_FRAME_TX, + ENET0_SOF_RX, + ENET0_SOF_TX, + ENET0_GMII_TXD, + ENET0_GMII_COL, + ENET0_GMII_CRS, + ENET0_GMII_RX_CLK, + ENET0_GMII_RX_DV, + ENET0_GMII_RX_ER, + ENET0_GMII_TX_CLK, + ENET0_MDIO_I, + ENET0_EXT_INTIN, + ENET0_GMII_RXD, + ENET1_GMII_TX_EN, + ENET1_GMII_TX_ER, + ENET1_MDIO_MDC, + ENET1_MDIO_O, + ENET1_MDIO_T, + ENET1_PTP_DELAY_REQ_RX, + ENET1_PTP_DELAY_REQ_TX, + ENET1_PTP_PDELAY_REQ_RX, + ENET1_PTP_PDELAY_REQ_TX, + ENET1_PTP_PDELAY_RESP_RX, + ENET1_PTP_PDELAY_RESP_TX, + ENET1_PTP_SYNC_FRAME_RX, + ENET1_PTP_SYNC_FRAME_TX, + ENET1_SOF_RX, + ENET1_SOF_TX, + ENET1_GMII_TXD, + ENET1_GMII_COL, + ENET1_GMII_CRS, + ENET1_GMII_RX_CLK, + ENET1_GMII_RX_DV, + ENET1_GMII_RX_ER, + ENET1_GMII_TX_CLK, + ENET1_MDIO_I, + ENET1_EXT_INTIN, + ENET1_GMII_RXD, + GPIO_I, + GPIO_O, + GPIO_T, + I2C0_SDA_I, + I2C0_SDA_O, + I2C0_SDA_T, + I2C0_SCL_I, + I2C0_SCL_O, + I2C0_SCL_T, + I2C1_SDA_I, + I2C1_SDA_O, + I2C1_SDA_T, + I2C1_SCL_I, + I2C1_SCL_O, + I2C1_SCL_T, + PJTAG_TCK, + PJTAG_TMS, + PJTAG_TDI, + PJTAG_TDO, + SDIO0_CLK, + SDIO0_CLK_FB, + SDIO0_CMD_O, + SDIO0_CMD_I, + SDIO0_CMD_T, + SDIO0_DATA_I, + SDIO0_DATA_O, + SDIO0_DATA_T, + SDIO0_LED, + SDIO0_CDN, + SDIO0_WP, + SDIO0_BUSPOW, + SDIO0_BUSVOLT, + SDIO1_CLK, + SDIO1_CLK_FB, + SDIO1_CMD_O, + SDIO1_CMD_I, + SDIO1_CMD_T, + SDIO1_DATA_I, + SDIO1_DATA_O, + SDIO1_DATA_T, + SDIO1_LED, + SDIO1_CDN, + SDIO1_WP, + SDIO1_BUSPOW, + SDIO1_BUSVOLT, + SPI0_SCLK_I, + SPI0_SCLK_O, + SPI0_SCLK_T, + SPI0_MOSI_I, + SPI0_MOSI_O, + SPI0_MOSI_T, + SPI0_MISO_I, + SPI0_MISO_O, + SPI0_MISO_T, + SPI0_SS_I, + SPI0_SS_O, + SPI0_SS1_O, + SPI0_SS2_O, + SPI0_SS_T, + SPI1_SCLK_I, + SPI1_SCLK_O, + SPI1_SCLK_T, + SPI1_MOSI_I, + SPI1_MOSI_O, + SPI1_MOSI_T, + SPI1_MISO_I, + SPI1_MISO_O, + SPI1_MISO_T, + SPI1_SS_I, + SPI1_SS_O, + SPI1_SS1_O, + SPI1_SS2_O, + SPI1_SS_T, + UART0_DTRN, + UART0_RTSN, + UART0_TX, + UART0_CTSN, + UART0_DCDN, + UART0_DSRN, + UART0_RIN, + UART0_RX, + UART1_DTRN, + UART1_RTSN, + UART1_TX, + UART1_CTSN, + UART1_DCDN, + UART1_DSRN, + UART1_RIN, + UART1_RX, + TTC0_WAVE0_OUT, + TTC0_WAVE1_OUT, + TTC0_WAVE2_OUT, + TTC0_CLK0_IN, + TTC0_CLK1_IN, + TTC0_CLK2_IN, + TTC1_WAVE0_OUT, + TTC1_WAVE1_OUT, + TTC1_WAVE2_OUT, + TTC1_CLK0_IN, + TTC1_CLK1_IN, + TTC1_CLK2_IN, + WDT_CLK_IN, + WDT_RST_OUT, + TRACE_CLK, + TRACE_CTL, + TRACE_DATA, + TRACE_CLK_OUT, + USB0_PORT_INDCTL, + USB0_VBUS_PWRSELECT, + USB0_VBUS_PWRFAULT, + USB1_PORT_INDCTL, + USB1_VBUS_PWRSELECT, + USB1_VBUS_PWRFAULT, + SRAM_INTIN, + M_AXI_GP0_ARESETN, + M_AXI_GP0_ARVALID, + M_AXI_GP0_AWVALID, + M_AXI_GP0_BREADY, + M_AXI_GP0_RREADY, + M_AXI_GP0_WLAST, + M_AXI_GP0_WVALID, + M_AXI_GP0_ARID, + M_AXI_GP0_AWID, + M_AXI_GP0_WID, + M_AXI_GP0_ARBURST, + M_AXI_GP0_ARLOCK, + M_AXI_GP0_ARSIZE, + M_AXI_GP0_AWBURST, + M_AXI_GP0_AWLOCK, + M_AXI_GP0_AWSIZE, + M_AXI_GP0_ARPROT, + M_AXI_GP0_AWPROT, + M_AXI_GP0_ARADDR, + M_AXI_GP0_AWADDR, + M_AXI_GP0_WDATA, + M_AXI_GP0_ARCACHE, + M_AXI_GP0_ARLEN, + M_AXI_GP0_ARQOS, + M_AXI_GP0_AWCACHE, + M_AXI_GP0_AWLEN, + M_AXI_GP0_AWQOS, + M_AXI_GP0_WSTRB, + M_AXI_GP0_ACLK, + M_AXI_GP0_ARREADY, + M_AXI_GP0_AWREADY, + M_AXI_GP0_BVALID, + M_AXI_GP0_RLAST, + M_AXI_GP0_RVALID, + M_AXI_GP0_WREADY, + M_AXI_GP0_BID, + M_AXI_GP0_RID, + M_AXI_GP0_BRESP, + M_AXI_GP0_RRESP, + M_AXI_GP0_RDATA, + M_AXI_GP1_ARESETN, + M_AXI_GP1_ARVALID, + M_AXI_GP1_AWVALID, + M_AXI_GP1_BREADY, + M_AXI_GP1_RREADY, + M_AXI_GP1_WLAST, + M_AXI_GP1_WVALID, + M_AXI_GP1_ARID, + M_AXI_GP1_AWID, + M_AXI_GP1_WID, + M_AXI_GP1_ARBURST, + M_AXI_GP1_ARLOCK, + M_AXI_GP1_ARSIZE, + M_AXI_GP1_AWBURST, + M_AXI_GP1_AWLOCK, + M_AXI_GP1_AWSIZE, + M_AXI_GP1_ARPROT, + M_AXI_GP1_AWPROT, + M_AXI_GP1_ARADDR, + M_AXI_GP1_AWADDR, + M_AXI_GP1_WDATA, + M_AXI_GP1_ARCACHE, + M_AXI_GP1_ARLEN, + M_AXI_GP1_ARQOS, + M_AXI_GP1_AWCACHE, + M_AXI_GP1_AWLEN, + M_AXI_GP1_AWQOS, + M_AXI_GP1_WSTRB, + M_AXI_GP1_ACLK, + M_AXI_GP1_ARREADY, + M_AXI_GP1_AWREADY, + M_AXI_GP1_BVALID, + M_AXI_GP1_RLAST, + M_AXI_GP1_RVALID, + M_AXI_GP1_WREADY, + M_AXI_GP1_BID, + M_AXI_GP1_RID, + M_AXI_GP1_BRESP, + M_AXI_GP1_RRESP, + M_AXI_GP1_RDATA, + S_AXI_GP0_ARESETN, + S_AXI_GP0_ARREADY, + S_AXI_GP0_AWREADY, + S_AXI_GP0_BVALID, + S_AXI_GP0_RLAST, + S_AXI_GP0_RVALID, + S_AXI_GP0_WREADY, + S_AXI_GP0_BRESP, + S_AXI_GP0_RRESP, + S_AXI_GP0_RDATA, + S_AXI_GP0_BID, + S_AXI_GP0_RID, + S_AXI_GP0_ACLK, + S_AXI_GP0_ARVALID, + S_AXI_GP0_AWVALID, + S_AXI_GP0_BREADY, + S_AXI_GP0_RREADY, + S_AXI_GP0_WLAST, + S_AXI_GP0_WVALID, + S_AXI_GP0_ARBURST, + S_AXI_GP0_ARLOCK, + S_AXI_GP0_ARSIZE, + S_AXI_GP0_AWBURST, + S_AXI_GP0_AWLOCK, + S_AXI_GP0_AWSIZE, + S_AXI_GP0_ARPROT, + S_AXI_GP0_AWPROT, + S_AXI_GP0_ARADDR, + S_AXI_GP0_AWADDR, + S_AXI_GP0_WDATA, + S_AXI_GP0_ARCACHE, + S_AXI_GP0_ARLEN, + S_AXI_GP0_ARQOS, + S_AXI_GP0_AWCACHE, + S_AXI_GP0_AWLEN, + S_AXI_GP0_AWQOS, + S_AXI_GP0_WSTRB, + S_AXI_GP0_ARID, + S_AXI_GP0_AWID, + S_AXI_GP0_WID, + S_AXI_GP1_ARESETN, + S_AXI_GP1_ARREADY, + S_AXI_GP1_AWREADY, + S_AXI_GP1_BVALID, + S_AXI_GP1_RLAST, + S_AXI_GP1_RVALID, + S_AXI_GP1_WREADY, + S_AXI_GP1_BRESP, + S_AXI_GP1_RRESP, + S_AXI_GP1_RDATA, + S_AXI_GP1_BID, + S_AXI_GP1_RID, + S_AXI_GP1_ACLK, + S_AXI_GP1_ARVALID, + S_AXI_GP1_AWVALID, + S_AXI_GP1_BREADY, + S_AXI_GP1_RREADY, + S_AXI_GP1_WLAST, + S_AXI_GP1_WVALID, + S_AXI_GP1_ARBURST, + S_AXI_GP1_ARLOCK, + S_AXI_GP1_ARSIZE, + S_AXI_GP1_AWBURST, + S_AXI_GP1_AWLOCK, + S_AXI_GP1_AWSIZE, + S_AXI_GP1_ARPROT, + S_AXI_GP1_AWPROT, + S_AXI_GP1_ARADDR, + S_AXI_GP1_AWADDR, + S_AXI_GP1_WDATA, + S_AXI_GP1_ARCACHE, + S_AXI_GP1_ARLEN, + S_AXI_GP1_ARQOS, + S_AXI_GP1_AWCACHE, + S_AXI_GP1_AWLEN, + S_AXI_GP1_AWQOS, + S_AXI_GP1_WSTRB, + S_AXI_GP1_ARID, + S_AXI_GP1_AWID, + S_AXI_GP1_WID, + S_AXI_ACP_ARESETN, + S_AXI_ACP_ARREADY, + S_AXI_ACP_AWREADY, + S_AXI_ACP_BVALID, + S_AXI_ACP_RLAST, + S_AXI_ACP_RVALID, + S_AXI_ACP_WREADY, + S_AXI_ACP_BRESP, + S_AXI_ACP_RRESP, + S_AXI_ACP_BID, + S_AXI_ACP_RID, + S_AXI_ACP_RDATA, + S_AXI_ACP_ACLK, + S_AXI_ACP_ARVALID, + S_AXI_ACP_AWVALID, + S_AXI_ACP_BREADY, + S_AXI_ACP_RREADY, + S_AXI_ACP_WLAST, + S_AXI_ACP_WVALID, + S_AXI_ACP_ARID, + S_AXI_ACP_ARPROT, + S_AXI_ACP_AWID, + S_AXI_ACP_AWPROT, + S_AXI_ACP_WID, + S_AXI_ACP_ARADDR, + S_AXI_ACP_AWADDR, + S_AXI_ACP_ARCACHE, + S_AXI_ACP_ARLEN, + S_AXI_ACP_ARQOS, + S_AXI_ACP_AWCACHE, + S_AXI_ACP_AWLEN, + S_AXI_ACP_AWQOS, + S_AXI_ACP_ARBURST, + S_AXI_ACP_ARLOCK, + S_AXI_ACP_ARSIZE, + S_AXI_ACP_AWBURST, + S_AXI_ACP_AWLOCK, + S_AXI_ACP_AWSIZE, + S_AXI_ACP_ARUSER, + S_AXI_ACP_AWUSER, + S_AXI_ACP_WDATA, + S_AXI_ACP_WSTRB, + S_AXI_HP0_ARESETN, + S_AXI_HP0_ARREADY, + S_AXI_HP0_AWREADY, + S_AXI_HP0_BVALID, + S_AXI_HP0_RLAST, + S_AXI_HP0_RVALID, + S_AXI_HP0_WREADY, + S_AXI_HP0_BRESP, + S_AXI_HP0_RRESP, + S_AXI_HP0_BID, + S_AXI_HP0_RID, + S_AXI_HP0_RDATA, + S_AXI_HP0_RCOUNT, + S_AXI_HP0_WCOUNT, + S_AXI_HP0_RACOUNT, + S_AXI_HP0_WACOUNT, + S_AXI_HP0_ACLK, + S_AXI_HP0_ARVALID, + S_AXI_HP0_AWVALID, + S_AXI_HP0_BREADY, + S_AXI_HP0_RDISSUECAP1_EN, + S_AXI_HP0_RREADY, + S_AXI_HP0_WLAST, + S_AXI_HP0_WRISSUECAP1_EN, + S_AXI_HP0_WVALID, + S_AXI_HP0_ARBURST, + S_AXI_HP0_ARLOCK, + S_AXI_HP0_ARSIZE, + S_AXI_HP0_AWBURST, + S_AXI_HP0_AWLOCK, + S_AXI_HP0_AWSIZE, + S_AXI_HP0_ARPROT, + S_AXI_HP0_AWPROT, + S_AXI_HP0_ARADDR, + S_AXI_HP0_AWADDR, + S_AXI_HP0_ARCACHE, + S_AXI_HP0_ARLEN, + S_AXI_HP0_ARQOS, + S_AXI_HP0_AWCACHE, + S_AXI_HP0_AWLEN, + S_AXI_HP0_AWQOS, + S_AXI_HP0_ARID, + S_AXI_HP0_AWID, + S_AXI_HP0_WID, + S_AXI_HP0_WDATA, + S_AXI_HP0_WSTRB, + S_AXI_HP1_ARESETN, + S_AXI_HP1_ARREADY, + S_AXI_HP1_AWREADY, + S_AXI_HP1_BVALID, + S_AXI_HP1_RLAST, + S_AXI_HP1_RVALID, + S_AXI_HP1_WREADY, + S_AXI_HP1_BRESP, + S_AXI_HP1_RRESP, + S_AXI_HP1_BID, + S_AXI_HP1_RID, + S_AXI_HP1_RDATA, + S_AXI_HP1_RCOUNT, + S_AXI_HP1_WCOUNT, + S_AXI_HP1_RACOUNT, + S_AXI_HP1_WACOUNT, + S_AXI_HP1_ACLK, + S_AXI_HP1_ARVALID, + S_AXI_HP1_AWVALID, + S_AXI_HP1_BREADY, + S_AXI_HP1_RDISSUECAP1_EN, + S_AXI_HP1_RREADY, + S_AXI_HP1_WLAST, + S_AXI_HP1_WRISSUECAP1_EN, + S_AXI_HP1_WVALID, + S_AXI_HP1_ARBURST, + S_AXI_HP1_ARLOCK, + S_AXI_HP1_ARSIZE, + S_AXI_HP1_AWBURST, + S_AXI_HP1_AWLOCK, + S_AXI_HP1_AWSIZE, + S_AXI_HP1_ARPROT, + S_AXI_HP1_AWPROT, + S_AXI_HP1_ARADDR, + S_AXI_HP1_AWADDR, + S_AXI_HP1_ARCACHE, + S_AXI_HP1_ARLEN, + S_AXI_HP1_ARQOS, + S_AXI_HP1_AWCACHE, + S_AXI_HP1_AWLEN, + S_AXI_HP1_AWQOS, + S_AXI_HP1_ARID, + S_AXI_HP1_AWID, + S_AXI_HP1_WID, + S_AXI_HP1_WDATA, + S_AXI_HP1_WSTRB, + S_AXI_HP2_ARESETN, + S_AXI_HP2_ARREADY, + S_AXI_HP2_AWREADY, + S_AXI_HP2_BVALID, + S_AXI_HP2_RLAST, + S_AXI_HP2_RVALID, + S_AXI_HP2_WREADY, + S_AXI_HP2_BRESP, + S_AXI_HP2_RRESP, + S_AXI_HP2_BID, + S_AXI_HP2_RID, + S_AXI_HP2_RDATA, + S_AXI_HP2_RCOUNT, + S_AXI_HP2_WCOUNT, + S_AXI_HP2_RACOUNT, + S_AXI_HP2_WACOUNT, + S_AXI_HP2_ACLK, + S_AXI_HP2_ARVALID, + S_AXI_HP2_AWVALID, + S_AXI_HP2_BREADY, + S_AXI_HP2_RDISSUECAP1_EN, + S_AXI_HP2_RREADY, + S_AXI_HP2_WLAST, + S_AXI_HP2_WRISSUECAP1_EN, + S_AXI_HP2_WVALID, + S_AXI_HP2_ARBURST, + S_AXI_HP2_ARLOCK, + S_AXI_HP2_ARSIZE, + S_AXI_HP2_AWBURST, + S_AXI_HP2_AWLOCK, + S_AXI_HP2_AWSIZE, + S_AXI_HP2_ARPROT, + S_AXI_HP2_AWPROT, + S_AXI_HP2_ARADDR, + S_AXI_HP2_AWADDR, + S_AXI_HP2_ARCACHE, + S_AXI_HP2_ARLEN, + S_AXI_HP2_ARQOS, + S_AXI_HP2_AWCACHE, + S_AXI_HP2_AWLEN, + S_AXI_HP2_AWQOS, + S_AXI_HP2_ARID, + S_AXI_HP2_AWID, + S_AXI_HP2_WID, + S_AXI_HP2_WDATA, + S_AXI_HP2_WSTRB, + S_AXI_HP3_ARESETN, + S_AXI_HP3_ARREADY, + S_AXI_HP3_AWREADY, + S_AXI_HP3_BVALID, + S_AXI_HP3_RLAST, + S_AXI_HP3_RVALID, + S_AXI_HP3_WREADY, + S_AXI_HP3_BRESP, + S_AXI_HP3_RRESP, + S_AXI_HP3_BID, + S_AXI_HP3_RID, + S_AXI_HP3_RDATA, + S_AXI_HP3_RCOUNT, + S_AXI_HP3_WCOUNT, + S_AXI_HP3_RACOUNT, + S_AXI_HP3_WACOUNT, + S_AXI_HP3_ACLK, + S_AXI_HP3_ARVALID, + S_AXI_HP3_AWVALID, + S_AXI_HP3_BREADY, + S_AXI_HP3_RDISSUECAP1_EN, + S_AXI_HP3_RREADY, + S_AXI_HP3_WLAST, + S_AXI_HP3_WRISSUECAP1_EN, + S_AXI_HP3_WVALID, + S_AXI_HP3_ARBURST, + S_AXI_HP3_ARLOCK, + S_AXI_HP3_ARSIZE, + S_AXI_HP3_AWBURST, + S_AXI_HP3_AWLOCK, + S_AXI_HP3_AWSIZE, + S_AXI_HP3_ARPROT, + S_AXI_HP3_AWPROT, + S_AXI_HP3_ARADDR, + S_AXI_HP3_AWADDR, + S_AXI_HP3_ARCACHE, + S_AXI_HP3_ARLEN, + S_AXI_HP3_ARQOS, + S_AXI_HP3_AWCACHE, + S_AXI_HP3_AWLEN, + S_AXI_HP3_AWQOS, + S_AXI_HP3_ARID, + S_AXI_HP3_AWID, + S_AXI_HP3_WID, + S_AXI_HP3_WDATA, + S_AXI_HP3_WSTRB, + IRQ_P2F_DMAC_ABORT, + IRQ_P2F_DMAC0, + IRQ_P2F_DMAC1, + IRQ_P2F_DMAC2, + IRQ_P2F_DMAC3, + IRQ_P2F_DMAC4, + IRQ_P2F_DMAC5, + IRQ_P2F_DMAC6, + IRQ_P2F_DMAC7, + IRQ_P2F_SMC, + IRQ_P2F_QSPI, + IRQ_P2F_CTI, + IRQ_P2F_GPIO, + IRQ_P2F_USB0, + IRQ_P2F_ENET0, + IRQ_P2F_ENET_WAKE0, + IRQ_P2F_SDIO0, + IRQ_P2F_I2C0, + IRQ_P2F_SPI0, + IRQ_P2F_UART0, + IRQ_P2F_CAN0, + IRQ_P2F_USB1, + IRQ_P2F_ENET1, + IRQ_P2F_ENET_WAKE1, + IRQ_P2F_SDIO1, + IRQ_P2F_I2C1, + IRQ_P2F_SPI1, + IRQ_P2F_UART1, + IRQ_P2F_CAN1, + IRQ_F2P, + Core0_nFIQ, + Core0_nIRQ, + Core1_nFIQ, + Core1_nIRQ, + DMA0_DATYPE, + DMA0_DAVALID, + DMA0_DRREADY, + DMA0_RSTN, + DMA1_DATYPE, + DMA1_DAVALID, + DMA1_DRREADY, + DMA1_RSTN, + DMA2_DATYPE, + DMA2_DAVALID, + DMA2_DRREADY, + DMA2_RSTN, + DMA3_DATYPE, + DMA3_DAVALID, + DMA3_DRREADY, + DMA3_RSTN, + DMA0_ACLK, + DMA0_DAREADY, + DMA0_DRLAST, + DMA0_DRVALID, + DMA1_ACLK, + DMA1_DAREADY, + DMA1_DRLAST, + DMA1_DRVALID, + DMA2_ACLK, + DMA2_DAREADY, + DMA2_DRLAST, + DMA2_DRVALID, + DMA3_ACLK, + DMA3_DAREADY, + DMA3_DRLAST, + DMA3_DRVALID, + DMA0_DRTYPE, + DMA1_DRTYPE, + DMA2_DRTYPE, + DMA3_DRTYPE, + FCLK_CLK3, + FCLK_CLK2, + FCLK_CLK1, + FCLK_CLK0, + FCLK_CLKTRIG3_N, + FCLK_CLKTRIG2_N, + FCLK_CLKTRIG1_N, + FCLK_CLKTRIG0_N, + FCLK_RESET3_N, + FCLK_RESET2_N, + FCLK_RESET1_N, + FCLK_RESET0_N, + FTMD_TRACEIN_DATA, + FTMD_TRACEIN_VALID, + FTMD_TRACEIN_CLK, + FTMD_TRACEIN_ATID, + FTMT_F2P_TRIG_0, + FTMT_F2P_TRIGACK_0, + FTMT_F2P_TRIG_1, + FTMT_F2P_TRIGACK_1, + FTMT_F2P_TRIG_2, + FTMT_F2P_TRIGACK_2, + FTMT_F2P_TRIG_3, + FTMT_F2P_TRIGACK_3, + FTMT_F2P_DEBUG, + FTMT_P2F_TRIGACK_0, + FTMT_P2F_TRIG_0, + FTMT_P2F_TRIGACK_1, + FTMT_P2F_TRIG_1, + FTMT_P2F_TRIGACK_2, + FTMT_P2F_TRIG_2, + FTMT_P2F_TRIGACK_3, + FTMT_P2F_TRIG_3, + FTMT_P2F_DEBUG, + FPGA_IDLE_N, + EVENT_EVENTO, + EVENT_STANDBYWFE, + EVENT_STANDBYWFI, + EVENT_EVENTI, + DDR_ARB, + MIO, + DDR_CAS_n, + DDR_CKE, + DDR_Clk_n, + DDR_Clk, + DDR_CS_n, + DDR_DRSTB, + DDR_ODT, + DDR_RAS_n, + DDR_WEB, + DDR_BankAddr, + DDR_Addr, + DDR_VRN, + DDR_VRP, + DDR_DM, + DDR_DQ, + DDR_DQS_n, + DDR_DQS, + PS_SRSTB, + PS_CLK, + PS_PORB); + output CAN0_PHY_TX; + input CAN0_PHY_RX; + output CAN1_PHY_TX; + input CAN1_PHY_RX; + output ENET0_GMII_TX_EN; + output ENET0_GMII_TX_ER; + output ENET0_MDIO_MDC; + output ENET0_MDIO_O; + output ENET0_MDIO_T; + output ENET0_PTP_DELAY_REQ_RX; + output ENET0_PTP_DELAY_REQ_TX; + output ENET0_PTP_PDELAY_REQ_RX; + output ENET0_PTP_PDELAY_REQ_TX; + output ENET0_PTP_PDELAY_RESP_RX; + output ENET0_PTP_PDELAY_RESP_TX; + output ENET0_PTP_SYNC_FRAME_RX; + output ENET0_PTP_SYNC_FRAME_TX; + output ENET0_SOF_RX; + output ENET0_SOF_TX; + output [7:0]ENET0_GMII_TXD; + input ENET0_GMII_COL; + input ENET0_GMII_CRS; + input ENET0_GMII_RX_CLK; + input ENET0_GMII_RX_DV; + input ENET0_GMII_RX_ER; + input ENET0_GMII_TX_CLK; + input ENET0_MDIO_I; + input ENET0_EXT_INTIN; + input [7:0]ENET0_GMII_RXD; + output ENET1_GMII_TX_EN; + output ENET1_GMII_TX_ER; + output ENET1_MDIO_MDC; + output ENET1_MDIO_O; + output ENET1_MDIO_T; + output ENET1_PTP_DELAY_REQ_RX; + output ENET1_PTP_DELAY_REQ_TX; + output ENET1_PTP_PDELAY_REQ_RX; + output ENET1_PTP_PDELAY_REQ_TX; + output ENET1_PTP_PDELAY_RESP_RX; + output ENET1_PTP_PDELAY_RESP_TX; + output ENET1_PTP_SYNC_FRAME_RX; + output ENET1_PTP_SYNC_FRAME_TX; + output ENET1_SOF_RX; + output ENET1_SOF_TX; + output [7:0]ENET1_GMII_TXD; + input ENET1_GMII_COL; + input ENET1_GMII_CRS; + input ENET1_GMII_RX_CLK; + input ENET1_GMII_RX_DV; + input ENET1_GMII_RX_ER; + input ENET1_GMII_TX_CLK; + input ENET1_MDIO_I; + input ENET1_EXT_INTIN; + input [7:0]ENET1_GMII_RXD; + input [63:0]GPIO_I; + output [63:0]GPIO_O; + output [63:0]GPIO_T; + input I2C0_SDA_I; + output I2C0_SDA_O; + output I2C0_SDA_T; + input I2C0_SCL_I; + output I2C0_SCL_O; + output I2C0_SCL_T; + input I2C1_SDA_I; + output I2C1_SDA_O; + output I2C1_SDA_T; + input I2C1_SCL_I; + output I2C1_SCL_O; + output I2C1_SCL_T; + input PJTAG_TCK; + input PJTAG_TMS; + input PJTAG_TDI; + output PJTAG_TDO; + output SDIO0_CLK; + input SDIO0_CLK_FB; + output SDIO0_CMD_O; + input SDIO0_CMD_I; + output SDIO0_CMD_T; + input [3:0]SDIO0_DATA_I; + output [3:0]SDIO0_DATA_O; + output [3:0]SDIO0_DATA_T; + output SDIO0_LED; + input SDIO0_CDN; + input SDIO0_WP; + output SDIO0_BUSPOW; + output [2:0]SDIO0_BUSVOLT; + output SDIO1_CLK; + input SDIO1_CLK_FB; + output SDIO1_CMD_O; + input SDIO1_CMD_I; + output SDIO1_CMD_T; + input [3:0]SDIO1_DATA_I; + output [3:0]SDIO1_DATA_O; + output [3:0]SDIO1_DATA_T; + output SDIO1_LED; + input SDIO1_CDN; + input SDIO1_WP; + output SDIO1_BUSPOW; + output [2:0]SDIO1_BUSVOLT; + input SPI0_SCLK_I; + output SPI0_SCLK_O; + output SPI0_SCLK_T; + input SPI0_MOSI_I; + output SPI0_MOSI_O; + output SPI0_MOSI_T; + input SPI0_MISO_I; + output SPI0_MISO_O; + output SPI0_MISO_T; + input SPI0_SS_I; + output SPI0_SS_O; + output SPI0_SS1_O; + output SPI0_SS2_O; + output SPI0_SS_T; + input SPI1_SCLK_I; + output SPI1_SCLK_O; + output SPI1_SCLK_T; + input SPI1_MOSI_I; + output SPI1_MOSI_O; + output SPI1_MOSI_T; + input SPI1_MISO_I; + output SPI1_MISO_O; + output SPI1_MISO_T; + input SPI1_SS_I; + output SPI1_SS_O; + output SPI1_SS1_O; + output SPI1_SS2_O; + output SPI1_SS_T; + output UART0_DTRN; + output UART0_RTSN; + output UART0_TX; + input UART0_CTSN; + input UART0_DCDN; + input UART0_DSRN; + input UART0_RIN; + input UART0_RX; + output UART1_DTRN; + output UART1_RTSN; + output UART1_TX; + input UART1_CTSN; + input UART1_DCDN; + input UART1_DSRN; + input UART1_RIN; + input UART1_RX; + output TTC0_WAVE0_OUT; + output TTC0_WAVE1_OUT; + output TTC0_WAVE2_OUT; + input TTC0_CLK0_IN; + input TTC0_CLK1_IN; + input TTC0_CLK2_IN; + output TTC1_WAVE0_OUT; + output TTC1_WAVE1_OUT; + output TTC1_WAVE2_OUT; + input TTC1_CLK0_IN; + input TTC1_CLK1_IN; + input TTC1_CLK2_IN; + input WDT_CLK_IN; + output WDT_RST_OUT; + input TRACE_CLK; + output TRACE_CTL; + output [1:0]TRACE_DATA; + output TRACE_CLK_OUT; + output [1:0]USB0_PORT_INDCTL; + output USB0_VBUS_PWRSELECT; + input USB0_VBUS_PWRFAULT; + output [1:0]USB1_PORT_INDCTL; + output USB1_VBUS_PWRSELECT; + input USB1_VBUS_PWRFAULT; + input SRAM_INTIN; + output M_AXI_GP0_ARESETN; + output M_AXI_GP0_ARVALID; + output M_AXI_GP0_AWVALID; + output M_AXI_GP0_BREADY; + output M_AXI_GP0_RREADY; + output M_AXI_GP0_WLAST; + output M_AXI_GP0_WVALID; + output [11:0]M_AXI_GP0_ARID; + output [11:0]M_AXI_GP0_AWID; + output [11:0]M_AXI_GP0_WID; + output [1:0]M_AXI_GP0_ARBURST; + output [1:0]M_AXI_GP0_ARLOCK; + output [2:0]M_AXI_GP0_ARSIZE; + output [1:0]M_AXI_GP0_AWBURST; + output [1:0]M_AXI_GP0_AWLOCK; + output [2:0]M_AXI_GP0_AWSIZE; + output [2:0]M_AXI_GP0_ARPROT; + output [2:0]M_AXI_GP0_AWPROT; + output [31:0]M_AXI_GP0_ARADDR; + output [31:0]M_AXI_GP0_AWADDR; + output [31:0]M_AXI_GP0_WDATA; + output [3:0]M_AXI_GP0_ARCACHE; + output [3:0]M_AXI_GP0_ARLEN; + output [3:0]M_AXI_GP0_ARQOS; + output [3:0]M_AXI_GP0_AWCACHE; + output [3:0]M_AXI_GP0_AWLEN; + output [3:0]M_AXI_GP0_AWQOS; + output [3:0]M_AXI_GP0_WSTRB; + input M_AXI_GP0_ACLK; + input M_AXI_GP0_ARREADY; + input M_AXI_GP0_AWREADY; + input M_AXI_GP0_BVALID; + input M_AXI_GP0_RLAST; + input M_AXI_GP0_RVALID; + input M_AXI_GP0_WREADY; + input [11:0]M_AXI_GP0_BID; + input [11:0]M_AXI_GP0_RID; + input [1:0]M_AXI_GP0_BRESP; + input [1:0]M_AXI_GP0_RRESP; + input [31:0]M_AXI_GP0_RDATA; + output M_AXI_GP1_ARESETN; + output M_AXI_GP1_ARVALID; + output M_AXI_GP1_AWVALID; + output M_AXI_GP1_BREADY; + output M_AXI_GP1_RREADY; + output M_AXI_GP1_WLAST; + output M_AXI_GP1_WVALID; + output [11:0]M_AXI_GP1_ARID; + output [11:0]M_AXI_GP1_AWID; + output [11:0]M_AXI_GP1_WID; + output [1:0]M_AXI_GP1_ARBURST; + output [1:0]M_AXI_GP1_ARLOCK; + output [2:0]M_AXI_GP1_ARSIZE; + output [1:0]M_AXI_GP1_AWBURST; + output [1:0]M_AXI_GP1_AWLOCK; + output [2:0]M_AXI_GP1_AWSIZE; + output [2:0]M_AXI_GP1_ARPROT; + output [2:0]M_AXI_GP1_AWPROT; + output [31:0]M_AXI_GP1_ARADDR; + output [31:0]M_AXI_GP1_AWADDR; + output [31:0]M_AXI_GP1_WDATA; + output [3:0]M_AXI_GP1_ARCACHE; + output [3:0]M_AXI_GP1_ARLEN; + output [3:0]M_AXI_GP1_ARQOS; + output [3:0]M_AXI_GP1_AWCACHE; + output [3:0]M_AXI_GP1_AWLEN; + output [3:0]M_AXI_GP1_AWQOS; + output [3:0]M_AXI_GP1_WSTRB; + input M_AXI_GP1_ACLK; + input M_AXI_GP1_ARREADY; + input M_AXI_GP1_AWREADY; + input M_AXI_GP1_BVALID; + input M_AXI_GP1_RLAST; + input M_AXI_GP1_RVALID; + input M_AXI_GP1_WREADY; + input [11:0]M_AXI_GP1_BID; + input [11:0]M_AXI_GP1_RID; + input [1:0]M_AXI_GP1_BRESP; + input [1:0]M_AXI_GP1_RRESP; + input [31:0]M_AXI_GP1_RDATA; + output S_AXI_GP0_ARESETN; + output S_AXI_GP0_ARREADY; + output S_AXI_GP0_AWREADY; + output S_AXI_GP0_BVALID; + output S_AXI_GP0_RLAST; + output S_AXI_GP0_RVALID; + output S_AXI_GP0_WREADY; + output [1:0]S_AXI_GP0_BRESP; + output [1:0]S_AXI_GP0_RRESP; + output [31:0]S_AXI_GP0_RDATA; + output [5:0]S_AXI_GP0_BID; + output [5:0]S_AXI_GP0_RID; + input S_AXI_GP0_ACLK; + input S_AXI_GP0_ARVALID; + input S_AXI_GP0_AWVALID; + input S_AXI_GP0_BREADY; + input S_AXI_GP0_RREADY; + input S_AXI_GP0_WLAST; + input S_AXI_GP0_WVALID; + input [1:0]S_AXI_GP0_ARBURST; + input [1:0]S_AXI_GP0_ARLOCK; + input [2:0]S_AXI_GP0_ARSIZE; + input [1:0]S_AXI_GP0_AWBURST; + input [1:0]S_AXI_GP0_AWLOCK; + input [2:0]S_AXI_GP0_AWSIZE; + input [2:0]S_AXI_GP0_ARPROT; + input [2:0]S_AXI_GP0_AWPROT; + input [31:0]S_AXI_GP0_ARADDR; + input [31:0]S_AXI_GP0_AWADDR; + input [31:0]S_AXI_GP0_WDATA; + input [3:0]S_AXI_GP0_ARCACHE; + input [3:0]S_AXI_GP0_ARLEN; + input [3:0]S_AXI_GP0_ARQOS; + input [3:0]S_AXI_GP0_AWCACHE; + input [3:0]S_AXI_GP0_AWLEN; + input [3:0]S_AXI_GP0_AWQOS; + input [3:0]S_AXI_GP0_WSTRB; + input [5:0]S_AXI_GP0_ARID; + input [5:0]S_AXI_GP0_AWID; + input [5:0]S_AXI_GP0_WID; + output S_AXI_GP1_ARESETN; + output S_AXI_GP1_ARREADY; + output S_AXI_GP1_AWREADY; + output S_AXI_GP1_BVALID; + output S_AXI_GP1_RLAST; + output S_AXI_GP1_RVALID; + output S_AXI_GP1_WREADY; + output [1:0]S_AXI_GP1_BRESP; + output [1:0]S_AXI_GP1_RRESP; + output [31:0]S_AXI_GP1_RDATA; + output [5:0]S_AXI_GP1_BID; + output [5:0]S_AXI_GP1_RID; + input S_AXI_GP1_ACLK; + input S_AXI_GP1_ARVALID; + input S_AXI_GP1_AWVALID; + input S_AXI_GP1_BREADY; + input S_AXI_GP1_RREADY; + input S_AXI_GP1_WLAST; + input S_AXI_GP1_WVALID; + input [1:0]S_AXI_GP1_ARBURST; + input [1:0]S_AXI_GP1_ARLOCK; + input [2:0]S_AXI_GP1_ARSIZE; + input [1:0]S_AXI_GP1_AWBURST; + input [1:0]S_AXI_GP1_AWLOCK; + input [2:0]S_AXI_GP1_AWSIZE; + input [2:0]S_AXI_GP1_ARPROT; + input [2:0]S_AXI_GP1_AWPROT; + input [31:0]S_AXI_GP1_ARADDR; + input [31:0]S_AXI_GP1_AWADDR; + input [31:0]S_AXI_GP1_WDATA; + input [3:0]S_AXI_GP1_ARCACHE; + input [3:0]S_AXI_GP1_ARLEN; + input [3:0]S_AXI_GP1_ARQOS; + input [3:0]S_AXI_GP1_AWCACHE; + input [3:0]S_AXI_GP1_AWLEN; + input [3:0]S_AXI_GP1_AWQOS; + input [3:0]S_AXI_GP1_WSTRB; + input [5:0]S_AXI_GP1_ARID; + input [5:0]S_AXI_GP1_AWID; + input [5:0]S_AXI_GP1_WID; + output S_AXI_ACP_ARESETN; + output S_AXI_ACP_ARREADY; + output S_AXI_ACP_AWREADY; + output S_AXI_ACP_BVALID; + output S_AXI_ACP_RLAST; + output S_AXI_ACP_RVALID; + output S_AXI_ACP_WREADY; + output [1:0]S_AXI_ACP_BRESP; + output [1:0]S_AXI_ACP_RRESP; + output [2:0]S_AXI_ACP_BID; + output [2:0]S_AXI_ACP_RID; + output [63:0]S_AXI_ACP_RDATA; + input S_AXI_ACP_ACLK; + input S_AXI_ACP_ARVALID; + input S_AXI_ACP_AWVALID; + input S_AXI_ACP_BREADY; + input S_AXI_ACP_RREADY; + input S_AXI_ACP_WLAST; + input S_AXI_ACP_WVALID; + input [2:0]S_AXI_ACP_ARID; + input [2:0]S_AXI_ACP_ARPROT; + input [2:0]S_AXI_ACP_AWID; + input [2:0]S_AXI_ACP_AWPROT; + input [2:0]S_AXI_ACP_WID; + input [31:0]S_AXI_ACP_ARADDR; + input [31:0]S_AXI_ACP_AWADDR; + input [3:0]S_AXI_ACP_ARCACHE; + input [3:0]S_AXI_ACP_ARLEN; + input [3:0]S_AXI_ACP_ARQOS; + input [3:0]S_AXI_ACP_AWCACHE; + input [3:0]S_AXI_ACP_AWLEN; + input [3:0]S_AXI_ACP_AWQOS; + input [1:0]S_AXI_ACP_ARBURST; + input [1:0]S_AXI_ACP_ARLOCK; + input [2:0]S_AXI_ACP_ARSIZE; + input [1:0]S_AXI_ACP_AWBURST; + input [1:0]S_AXI_ACP_AWLOCK; + input [2:0]S_AXI_ACP_AWSIZE; + input [4:0]S_AXI_ACP_ARUSER; + input [4:0]S_AXI_ACP_AWUSER; + input [63:0]S_AXI_ACP_WDATA; + input [7:0]S_AXI_ACP_WSTRB; + output S_AXI_HP0_ARESETN; + output S_AXI_HP0_ARREADY; + output S_AXI_HP0_AWREADY; + output S_AXI_HP0_BVALID; + output S_AXI_HP0_RLAST; + output S_AXI_HP0_RVALID; + output S_AXI_HP0_WREADY; + output [1:0]S_AXI_HP0_BRESP; + output [1:0]S_AXI_HP0_RRESP; + output [5:0]S_AXI_HP0_BID; + output [5:0]S_AXI_HP0_RID; + output [63:0]S_AXI_HP0_RDATA; + output [7:0]S_AXI_HP0_RCOUNT; + output [7:0]S_AXI_HP0_WCOUNT; + output [2:0]S_AXI_HP0_RACOUNT; + output [5:0]S_AXI_HP0_WACOUNT; + input S_AXI_HP0_ACLK; + input S_AXI_HP0_ARVALID; + input S_AXI_HP0_AWVALID; + input S_AXI_HP0_BREADY; + input S_AXI_HP0_RDISSUECAP1_EN; + input S_AXI_HP0_RREADY; + input S_AXI_HP0_WLAST; + input S_AXI_HP0_WRISSUECAP1_EN; + input S_AXI_HP0_WVALID; + input [1:0]S_AXI_HP0_ARBURST; + input [1:0]S_AXI_HP0_ARLOCK; + input [2:0]S_AXI_HP0_ARSIZE; + input [1:0]S_AXI_HP0_AWBURST; + input [1:0]S_AXI_HP0_AWLOCK; + input [2:0]S_AXI_HP0_AWSIZE; + input [2:0]S_AXI_HP0_ARPROT; + input [2:0]S_AXI_HP0_AWPROT; + input [31:0]S_AXI_HP0_ARADDR; + input [31:0]S_AXI_HP0_AWADDR; + input [3:0]S_AXI_HP0_ARCACHE; + input [3:0]S_AXI_HP0_ARLEN; + input [3:0]S_AXI_HP0_ARQOS; + input [3:0]S_AXI_HP0_AWCACHE; + input [3:0]S_AXI_HP0_AWLEN; + input [3:0]S_AXI_HP0_AWQOS; + input [5:0]S_AXI_HP0_ARID; + input [5:0]S_AXI_HP0_AWID; + input [5:0]S_AXI_HP0_WID; + input [63:0]S_AXI_HP0_WDATA; + input [7:0]S_AXI_HP0_WSTRB; + output S_AXI_HP1_ARESETN; + output S_AXI_HP1_ARREADY; + output S_AXI_HP1_AWREADY; + output S_AXI_HP1_BVALID; + output S_AXI_HP1_RLAST; + output S_AXI_HP1_RVALID; + output S_AXI_HP1_WREADY; + output [1:0]S_AXI_HP1_BRESP; + output [1:0]S_AXI_HP1_RRESP; + output [5:0]S_AXI_HP1_BID; + output [5:0]S_AXI_HP1_RID; + output [63:0]S_AXI_HP1_RDATA; + output [7:0]S_AXI_HP1_RCOUNT; + output [7:0]S_AXI_HP1_WCOUNT; + output [2:0]S_AXI_HP1_RACOUNT; + output [5:0]S_AXI_HP1_WACOUNT; + input S_AXI_HP1_ACLK; + input S_AXI_HP1_ARVALID; + input S_AXI_HP1_AWVALID; + input S_AXI_HP1_BREADY; + input S_AXI_HP1_RDISSUECAP1_EN; + input S_AXI_HP1_RREADY; + input S_AXI_HP1_WLAST; + input S_AXI_HP1_WRISSUECAP1_EN; + input S_AXI_HP1_WVALID; + input [1:0]S_AXI_HP1_ARBURST; + input [1:0]S_AXI_HP1_ARLOCK; + input [2:0]S_AXI_HP1_ARSIZE; + input [1:0]S_AXI_HP1_AWBURST; + input [1:0]S_AXI_HP1_AWLOCK; + input [2:0]S_AXI_HP1_AWSIZE; + input [2:0]S_AXI_HP1_ARPROT; + input [2:0]S_AXI_HP1_AWPROT; + input [31:0]S_AXI_HP1_ARADDR; + input [31:0]S_AXI_HP1_AWADDR; + input [3:0]S_AXI_HP1_ARCACHE; + input [3:0]S_AXI_HP1_ARLEN; + input [3:0]S_AXI_HP1_ARQOS; + input [3:0]S_AXI_HP1_AWCACHE; + input [3:0]S_AXI_HP1_AWLEN; + input [3:0]S_AXI_HP1_AWQOS; + input [5:0]S_AXI_HP1_ARID; + input [5:0]S_AXI_HP1_AWID; + input [5:0]S_AXI_HP1_WID; + input [63:0]S_AXI_HP1_WDATA; + input [7:0]S_AXI_HP1_WSTRB; + output S_AXI_HP2_ARESETN; + output S_AXI_HP2_ARREADY; + output S_AXI_HP2_AWREADY; + output S_AXI_HP2_BVALID; + output S_AXI_HP2_RLAST; + output S_AXI_HP2_RVALID; + output S_AXI_HP2_WREADY; + output [1:0]S_AXI_HP2_BRESP; + output [1:0]S_AXI_HP2_RRESP; + output [5:0]S_AXI_HP2_BID; + output [5:0]S_AXI_HP2_RID; + output [63:0]S_AXI_HP2_RDATA; + output [7:0]S_AXI_HP2_RCOUNT; + output [7:0]S_AXI_HP2_WCOUNT; + output [2:0]S_AXI_HP2_RACOUNT; + output [5:0]S_AXI_HP2_WACOUNT; + input S_AXI_HP2_ACLK; + input S_AXI_HP2_ARVALID; + input S_AXI_HP2_AWVALID; + input S_AXI_HP2_BREADY; + input S_AXI_HP2_RDISSUECAP1_EN; + input S_AXI_HP2_RREADY; + input S_AXI_HP2_WLAST; + input S_AXI_HP2_WRISSUECAP1_EN; + input S_AXI_HP2_WVALID; + input [1:0]S_AXI_HP2_ARBURST; + input [1:0]S_AXI_HP2_ARLOCK; + input [2:0]S_AXI_HP2_ARSIZE; + input [1:0]S_AXI_HP2_AWBURST; + input [1:0]S_AXI_HP2_AWLOCK; + input [2:0]S_AXI_HP2_AWSIZE; + input [2:0]S_AXI_HP2_ARPROT; + input [2:0]S_AXI_HP2_AWPROT; + input [31:0]S_AXI_HP2_ARADDR; + input [31:0]S_AXI_HP2_AWADDR; + input [3:0]S_AXI_HP2_ARCACHE; + input [3:0]S_AXI_HP2_ARLEN; + input [3:0]S_AXI_HP2_ARQOS; + input [3:0]S_AXI_HP2_AWCACHE; + input [3:0]S_AXI_HP2_AWLEN; + input [3:0]S_AXI_HP2_AWQOS; + input [5:0]S_AXI_HP2_ARID; + input [5:0]S_AXI_HP2_AWID; + input [5:0]S_AXI_HP2_WID; + input [63:0]S_AXI_HP2_WDATA; + input [7:0]S_AXI_HP2_WSTRB; + output S_AXI_HP3_ARESETN; + output S_AXI_HP3_ARREADY; + output S_AXI_HP3_AWREADY; + output S_AXI_HP3_BVALID; + output S_AXI_HP3_RLAST; + output S_AXI_HP3_RVALID; + output S_AXI_HP3_WREADY; + output [1:0]S_AXI_HP3_BRESP; + output [1:0]S_AXI_HP3_RRESP; + output [5:0]S_AXI_HP3_BID; + output [5:0]S_AXI_HP3_RID; + output [63:0]S_AXI_HP3_RDATA; + output [7:0]S_AXI_HP3_RCOUNT; + output [7:0]S_AXI_HP3_WCOUNT; + output [2:0]S_AXI_HP3_RACOUNT; + output [5:0]S_AXI_HP3_WACOUNT; + input S_AXI_HP3_ACLK; + input S_AXI_HP3_ARVALID; + input S_AXI_HP3_AWVALID; + input S_AXI_HP3_BREADY; + input S_AXI_HP3_RDISSUECAP1_EN; + input S_AXI_HP3_RREADY; + input S_AXI_HP3_WLAST; + input S_AXI_HP3_WRISSUECAP1_EN; + input S_AXI_HP3_WVALID; + input [1:0]S_AXI_HP3_ARBURST; + input [1:0]S_AXI_HP3_ARLOCK; + input [2:0]S_AXI_HP3_ARSIZE; + input [1:0]S_AXI_HP3_AWBURST; + input [1:0]S_AXI_HP3_AWLOCK; + input [2:0]S_AXI_HP3_AWSIZE; + input [2:0]S_AXI_HP3_ARPROT; + input [2:0]S_AXI_HP3_AWPROT; + input [31:0]S_AXI_HP3_ARADDR; + input [31:0]S_AXI_HP3_AWADDR; + input [3:0]S_AXI_HP3_ARCACHE; + input [3:0]S_AXI_HP3_ARLEN; + input [3:0]S_AXI_HP3_ARQOS; + input [3:0]S_AXI_HP3_AWCACHE; + input [3:0]S_AXI_HP3_AWLEN; + input [3:0]S_AXI_HP3_AWQOS; + input [5:0]S_AXI_HP3_ARID; + input [5:0]S_AXI_HP3_AWID; + input [5:0]S_AXI_HP3_WID; + input [63:0]S_AXI_HP3_WDATA; + input [7:0]S_AXI_HP3_WSTRB; + output IRQ_P2F_DMAC_ABORT; + output IRQ_P2F_DMAC0; + output IRQ_P2F_DMAC1; + output IRQ_P2F_DMAC2; + output IRQ_P2F_DMAC3; + output IRQ_P2F_DMAC4; + output IRQ_P2F_DMAC5; + output IRQ_P2F_DMAC6; + output IRQ_P2F_DMAC7; + output IRQ_P2F_SMC; + output IRQ_P2F_QSPI; + output IRQ_P2F_CTI; + output IRQ_P2F_GPIO; + output IRQ_P2F_USB0; + output IRQ_P2F_ENET0; + output IRQ_P2F_ENET_WAKE0; + output IRQ_P2F_SDIO0; + output IRQ_P2F_I2C0; + output IRQ_P2F_SPI0; + output IRQ_P2F_UART0; + output IRQ_P2F_CAN0; + output IRQ_P2F_USB1; + output IRQ_P2F_ENET1; + output IRQ_P2F_ENET_WAKE1; + output IRQ_P2F_SDIO1; + output IRQ_P2F_I2C1; + output IRQ_P2F_SPI1; + output IRQ_P2F_UART1; + output IRQ_P2F_CAN1; + input [0:0]IRQ_F2P; + input Core0_nFIQ; + input Core0_nIRQ; + input Core1_nFIQ; + input Core1_nIRQ; + output [1:0]DMA0_DATYPE; + output DMA0_DAVALID; + output DMA0_DRREADY; + output DMA0_RSTN; + output [1:0]DMA1_DATYPE; + output DMA1_DAVALID; + output DMA1_DRREADY; + output DMA1_RSTN; + output [1:0]DMA2_DATYPE; + output DMA2_DAVALID; + output DMA2_DRREADY; + output DMA2_RSTN; + output [1:0]DMA3_DATYPE; + output DMA3_DAVALID; + output DMA3_DRREADY; + output DMA3_RSTN; + input DMA0_ACLK; + input DMA0_DAREADY; + input DMA0_DRLAST; + input DMA0_DRVALID; + input DMA1_ACLK; + input DMA1_DAREADY; + input DMA1_DRLAST; + input DMA1_DRVALID; + input DMA2_ACLK; + input DMA2_DAREADY; + input DMA2_DRLAST; + input DMA2_DRVALID; + input DMA3_ACLK; + input DMA3_DAREADY; + input DMA3_DRLAST; + input DMA3_DRVALID; + input [1:0]DMA0_DRTYPE; + input [1:0]DMA1_DRTYPE; + input [1:0]DMA2_DRTYPE; + input [1:0]DMA3_DRTYPE; + output FCLK_CLK3; + output FCLK_CLK2; + output FCLK_CLK1; + output FCLK_CLK0; + input FCLK_CLKTRIG3_N; + input FCLK_CLKTRIG2_N; + input FCLK_CLKTRIG1_N; + input FCLK_CLKTRIG0_N; + output FCLK_RESET3_N; + output FCLK_RESET2_N; + output FCLK_RESET1_N; + output FCLK_RESET0_N; + input [31:0]FTMD_TRACEIN_DATA; + input FTMD_TRACEIN_VALID; + input FTMD_TRACEIN_CLK; + input [3:0]FTMD_TRACEIN_ATID; + input FTMT_F2P_TRIG_0; + output FTMT_F2P_TRIGACK_0; + input FTMT_F2P_TRIG_1; + output FTMT_F2P_TRIGACK_1; + input FTMT_F2P_TRIG_2; + output FTMT_F2P_TRIGACK_2; + input FTMT_F2P_TRIG_3; + output FTMT_F2P_TRIGACK_3; + input [31:0]FTMT_F2P_DEBUG; + input FTMT_P2F_TRIGACK_0; + output FTMT_P2F_TRIG_0; + input FTMT_P2F_TRIGACK_1; + output FTMT_P2F_TRIG_1; + input FTMT_P2F_TRIGACK_2; + output FTMT_P2F_TRIG_2; + input FTMT_P2F_TRIGACK_3; + output FTMT_P2F_TRIG_3; + output [31:0]FTMT_P2F_DEBUG; + input FPGA_IDLE_N; + output EVENT_EVENTO; + output [1:0]EVENT_STANDBYWFE; + output [1:0]EVENT_STANDBYWFI; + input EVENT_EVENTI; + input [3:0]DDR_ARB; + inout [53:0]MIO; + inout DDR_CAS_n; + inout DDR_CKE; + inout DDR_Clk_n; + inout DDR_Clk; + inout DDR_CS_n; + inout DDR_DRSTB; + inout DDR_ODT; + inout DDR_RAS_n; + inout DDR_WEB; + inout [2:0]DDR_BankAddr; + inout [14:0]DDR_Addr; + inout DDR_VRN; + inout DDR_VRP; + inout [3:0]DDR_DM; + inout [31:0]DDR_DQ; + inout [3:0]DDR_DQS_n; + inout [3:0]DDR_DQS; + inout PS_SRSTB; + inout PS_CLK; + inout PS_PORB; + + wire \ ; + wire [14:0]DDR_Addr; + wire [2:0]DDR_BankAddr; + wire DDR_CAS_n; + wire DDR_CKE; + wire DDR_CS_n; + wire DDR_Clk; + wire DDR_Clk_n; + wire [3:0]DDR_DM; + wire [31:0]DDR_DQ; + wire [3:0]DDR_DQS; + wire [3:0]DDR_DQS_n; + wire DDR_DRSTB; + wire DDR_ODT; + wire DDR_RAS_n; + wire DDR_VRN; + wire DDR_VRP; + wire DDR_WEB; + wire ENET0_MDIO_T_n; + wire ENET1_MDIO_T_n; + wire FCLK_CLK0; + wire FCLK_CLK1; + wire FCLK_CLK2; + wire FCLK_CLK3; + wire [3:0]FCLK_CLK_unbuffered; + wire FCLK_RESET0_N; + wire I2C0_SCL_T_n; + wire I2C0_SDA_T_n; + wire I2C1_SCL_T_n; + wire I2C1_SDA_T_n; + wire [53:0]MIO; + wire M_AXI_GP0_ACLK; + wire [31:0]M_AXI_GP0_ARADDR; + wire [1:0]M_AXI_GP0_ARBURST; + wire [3:0]\^M_AXI_GP0_ARCACHE ; + wire [11:0]M_AXI_GP0_ARID; + wire [3:0]M_AXI_GP0_ARLEN; + wire [1:0]M_AXI_GP0_ARLOCK; + wire [2:0]M_AXI_GP0_ARPROT; + wire [3:0]M_AXI_GP0_ARQOS; + wire M_AXI_GP0_ARREADY; + wire [1:0]\^M_AXI_GP0_ARSIZE ; + wire M_AXI_GP0_ARVALID; + wire [31:0]M_AXI_GP0_AWADDR; + wire [1:0]M_AXI_GP0_AWBURST; + wire [3:0]\^M_AXI_GP0_AWCACHE ; + wire [11:0]M_AXI_GP0_AWID; + wire [3:0]M_AXI_GP0_AWLEN; + wire [1:0]M_AXI_GP0_AWLOCK; + wire [2:0]M_AXI_GP0_AWPROT; + wire [3:0]M_AXI_GP0_AWQOS; + wire M_AXI_GP0_AWREADY; + wire [1:0]\^M_AXI_GP0_AWSIZE ; + wire M_AXI_GP0_AWVALID; + wire [11:0]M_AXI_GP0_BID; + wire M_AXI_GP0_BREADY; + wire [1:0]M_AXI_GP0_BRESP; + wire M_AXI_GP0_BVALID; + wire [31:0]M_AXI_GP0_RDATA; + wire [11:0]M_AXI_GP0_RID; + wire M_AXI_GP0_RLAST; + wire M_AXI_GP0_RREADY; + wire [1:0]M_AXI_GP0_RRESP; + wire M_AXI_GP0_RVALID; + wire [31:0]M_AXI_GP0_WDATA; + wire [11:0]M_AXI_GP0_WID; + wire M_AXI_GP0_WLAST; + wire M_AXI_GP0_WREADY; + wire [3:0]M_AXI_GP0_WSTRB; + wire M_AXI_GP0_WVALID; + wire PS7_i_n_0; + wire PS7_i_n_1; + wire PS7_i_n_10; + wire PS7_i_n_100; + wire PS7_i_n_1001; + wire PS7_i_n_1002; + wire PS7_i_n_1003; + wire PS7_i_n_1004; + wire PS7_i_n_1005; + wire PS7_i_n_1006; + wire PS7_i_n_1007; + wire PS7_i_n_1008; + wire PS7_i_n_1009; + wire PS7_i_n_101; + wire PS7_i_n_1010; + wire PS7_i_n_1011; + wire PS7_i_n_1012; + wire PS7_i_n_1013; + wire PS7_i_n_1014; + wire PS7_i_n_1015; + wire PS7_i_n_1016; + wire PS7_i_n_1017; + wire PS7_i_n_1018; + wire PS7_i_n_1019; + wire PS7_i_n_102; + wire PS7_i_n_1020; + wire PS7_i_n_1021; + wire PS7_i_n_1022; + wire PS7_i_n_1023; + wire PS7_i_n_1024; + wire PS7_i_n_1025; + wire PS7_i_n_1026; + wire PS7_i_n_1027; + wire PS7_i_n_1028; + wire PS7_i_n_1029; + wire PS7_i_n_103; + wire PS7_i_n_1030; + wire PS7_i_n_1031; + wire PS7_i_n_1032; + wire PS7_i_n_1033; + wire PS7_i_n_1034; + wire PS7_i_n_1035; + wire PS7_i_n_1036; + wire PS7_i_n_1037; + wire PS7_i_n_1038; + wire PS7_i_n_1039; + wire PS7_i_n_104; + wire PS7_i_n_1040; + wire PS7_i_n_1041; + wire PS7_i_n_1042; + wire PS7_i_n_1043; + wire PS7_i_n_1044; + wire PS7_i_n_1045; + wire PS7_i_n_1046; + wire PS7_i_n_1047; + wire PS7_i_n_1048; + wire PS7_i_n_1049; + wire PS7_i_n_105; + wire PS7_i_n_1050; + wire PS7_i_n_1051; + wire PS7_i_n_1052; + wire PS7_i_n_1053; + wire PS7_i_n_1054; + wire PS7_i_n_1055; + wire PS7_i_n_1056; + wire PS7_i_n_1057; + wire PS7_i_n_1058; + wire PS7_i_n_1059; + wire PS7_i_n_106; + wire PS7_i_n_1060; + wire PS7_i_n_1061; + wire PS7_i_n_1062; + wire PS7_i_n_1063; + wire PS7_i_n_1064; + wire PS7_i_n_1065; + wire PS7_i_n_1066; + wire PS7_i_n_1067; + wire PS7_i_n_1068; + wire PS7_i_n_1069; + wire PS7_i_n_107; + wire PS7_i_n_1070; + wire PS7_i_n_1071; + wire PS7_i_n_1072; + wire PS7_i_n_1073; + wire PS7_i_n_1074; + wire PS7_i_n_1075; + wire PS7_i_n_1076; + wire PS7_i_n_1077; + wire PS7_i_n_1078; + wire PS7_i_n_1079; + wire PS7_i_n_108; + wire PS7_i_n_1080; + wire PS7_i_n_1081; + wire PS7_i_n_1082; + wire PS7_i_n_1083; + wire PS7_i_n_1084; + wire PS7_i_n_1085; + wire PS7_i_n_1086; + wire PS7_i_n_1087; + wire PS7_i_n_1088; + wire PS7_i_n_1089; + wire PS7_i_n_109; + wire PS7_i_n_1090; + wire PS7_i_n_1091; + wire PS7_i_n_1092; + wire PS7_i_n_1093; + wire PS7_i_n_1094; + wire PS7_i_n_1095; + wire PS7_i_n_1096; + wire PS7_i_n_1097; + wire PS7_i_n_1098; + wire PS7_i_n_1099; + wire PS7_i_n_11; + wire PS7_i_n_110; + wire PS7_i_n_1100; + wire PS7_i_n_1101; + wire PS7_i_n_1102; + wire PS7_i_n_1103; + wire PS7_i_n_1104; + wire PS7_i_n_1105; + wire PS7_i_n_1106; + wire PS7_i_n_1107; + wire PS7_i_n_1108; + wire PS7_i_n_1109; + wire PS7_i_n_111; + wire PS7_i_n_1110; + wire PS7_i_n_1111; + wire PS7_i_n_1112; + wire PS7_i_n_1113; + wire PS7_i_n_1114; + wire PS7_i_n_1115; + wire PS7_i_n_1116; + wire PS7_i_n_1117; + wire PS7_i_n_1118; + wire PS7_i_n_1119; + wire PS7_i_n_112; + wire PS7_i_n_1120; + wire PS7_i_n_1121; + wire PS7_i_n_1122; + wire PS7_i_n_1123; + wire PS7_i_n_1124; + wire PS7_i_n_1125; + wire PS7_i_n_1126; + wire PS7_i_n_1127; + wire PS7_i_n_1128; + wire PS7_i_n_1129; + wire PS7_i_n_113; + wire PS7_i_n_1130; + wire PS7_i_n_1131; + wire PS7_i_n_1132; + wire PS7_i_n_1133; + wire PS7_i_n_1134; + wire PS7_i_n_1135; + wire PS7_i_n_1136; + wire PS7_i_n_1137; + wire PS7_i_n_1138; + wire PS7_i_n_1139; + wire PS7_i_n_114; + wire PS7_i_n_1140; + wire PS7_i_n_1141; + wire PS7_i_n_1142; + wire PS7_i_n_1143; + wire PS7_i_n_1144; + wire PS7_i_n_1145; + wire PS7_i_n_1146; + wire PS7_i_n_1147; + wire PS7_i_n_1148; + wire PS7_i_n_1149; + wire PS7_i_n_115; + wire PS7_i_n_1150; + wire PS7_i_n_1151; + wire PS7_i_n_1152; + wire PS7_i_n_1153; + wire PS7_i_n_1154; + wire PS7_i_n_1155; + wire PS7_i_n_1156; + wire PS7_i_n_1157; + wire PS7_i_n_1158; + wire PS7_i_n_1159; + wire PS7_i_n_116; + wire PS7_i_n_1160; + wire PS7_i_n_1161; + wire PS7_i_n_1162; + wire PS7_i_n_1163; + wire PS7_i_n_1164; + wire PS7_i_n_1165; + wire PS7_i_n_1166; + wire PS7_i_n_1167; + wire PS7_i_n_1168; + wire PS7_i_n_1169; + wire PS7_i_n_117; + wire PS7_i_n_1170; + wire PS7_i_n_1171; + wire PS7_i_n_1172; + wire PS7_i_n_1173; + wire PS7_i_n_1174; + wire PS7_i_n_1175; + wire PS7_i_n_1176; + wire PS7_i_n_1177; + wire PS7_i_n_1178; + wire PS7_i_n_1179; + wire PS7_i_n_118; + wire PS7_i_n_1180; + wire PS7_i_n_1181; + wire PS7_i_n_1182; + wire PS7_i_n_1183; + wire PS7_i_n_1184; + wire PS7_i_n_1185; + wire PS7_i_n_1186; + wire PS7_i_n_1187; + wire PS7_i_n_1188; + wire PS7_i_n_1189; + wire PS7_i_n_119; + wire PS7_i_n_1190; + wire PS7_i_n_1191; + wire PS7_i_n_1192; + wire PS7_i_n_1193; + wire PS7_i_n_1194; + wire PS7_i_n_1195; + wire PS7_i_n_1196; + wire PS7_i_n_1197; + wire PS7_i_n_1198; + wire PS7_i_n_1199; + wire PS7_i_n_12; + wire PS7_i_n_120; + wire PS7_i_n_1200; + wire PS7_i_n_1201; + wire PS7_i_n_1202; + wire PS7_i_n_1203; + wire PS7_i_n_1204; + wire PS7_i_n_1205; + wire PS7_i_n_1206; + wire PS7_i_n_1207; + wire PS7_i_n_1208; + wire PS7_i_n_1209; + wire PS7_i_n_121; + wire PS7_i_n_1210; + wire PS7_i_n_1211; + wire PS7_i_n_1212; + wire PS7_i_n_1213; + wire PS7_i_n_1214; + wire PS7_i_n_1215; + wire PS7_i_n_1216; + wire PS7_i_n_1217; + wire PS7_i_n_1218; + wire PS7_i_n_1219; + wire PS7_i_n_122; + wire PS7_i_n_1220; + wire PS7_i_n_1221; + wire PS7_i_n_1222; + wire PS7_i_n_1223; + wire PS7_i_n_1224; + wire PS7_i_n_1225; + wire PS7_i_n_1226; + wire PS7_i_n_1227; + wire PS7_i_n_1228; + wire PS7_i_n_1229; + wire PS7_i_n_123; + wire PS7_i_n_1230; + wire PS7_i_n_1231; + wire PS7_i_n_1232; + wire PS7_i_n_1233; + wire PS7_i_n_1234; + wire PS7_i_n_1235; + wire PS7_i_n_1236; + wire PS7_i_n_1237; + wire PS7_i_n_1238; + wire PS7_i_n_1239; + wire PS7_i_n_124; + wire PS7_i_n_1240; + wire PS7_i_n_1241; + wire PS7_i_n_1242; + wire PS7_i_n_1243; + wire PS7_i_n_1244; + wire PS7_i_n_1245; + wire PS7_i_n_1246; + wire PS7_i_n_1247; + wire PS7_i_n_1248; + wire PS7_i_n_1249; + wire PS7_i_n_125; + wire PS7_i_n_1250; + wire PS7_i_n_1251; + wire PS7_i_n_1252; + wire PS7_i_n_1253; + wire PS7_i_n_1254; + wire PS7_i_n_1255; + wire PS7_i_n_1256; + wire PS7_i_n_1257; + wire PS7_i_n_1258; + wire PS7_i_n_1259; + wire PS7_i_n_126; + wire PS7_i_n_1260; + wire PS7_i_n_1261; + wire PS7_i_n_1262; + wire PS7_i_n_1263; + wire PS7_i_n_1264; + wire PS7_i_n_1265; + wire PS7_i_n_1266; + wire PS7_i_n_1267; + wire PS7_i_n_1268; + wire PS7_i_n_1269; + wire PS7_i_n_127; + wire PS7_i_n_1270; + wire PS7_i_n_1271; + wire PS7_i_n_1272; + wire PS7_i_n_1273; + wire PS7_i_n_1274; + wire PS7_i_n_1275; + wire PS7_i_n_1276; + wire PS7_i_n_1277; + wire PS7_i_n_1278; + wire PS7_i_n_1279; + wire PS7_i_n_128; + wire PS7_i_n_1280; + wire PS7_i_n_1281; + wire PS7_i_n_1282; + wire PS7_i_n_1283; + wire PS7_i_n_1284; + wire PS7_i_n_1285; + wire PS7_i_n_1286; + wire PS7_i_n_1287; + wire PS7_i_n_1288; + wire PS7_i_n_1289; + wire PS7_i_n_129; + wire PS7_i_n_1290; + wire PS7_i_n_1291; + wire PS7_i_n_1292; + wire PS7_i_n_1293; + wire PS7_i_n_1294; + wire PS7_i_n_1295; + wire PS7_i_n_1296; + wire PS7_i_n_1297; + wire PS7_i_n_1298; + wire PS7_i_n_1299; + wire PS7_i_n_13; + wire PS7_i_n_130; + wire PS7_i_n_1300; + wire PS7_i_n_1301; + wire PS7_i_n_1302; + wire PS7_i_n_1303; + wire PS7_i_n_1304; + wire PS7_i_n_1305; + wire PS7_i_n_1306; + wire PS7_i_n_1307; + wire PS7_i_n_1308; + wire PS7_i_n_1309; + wire PS7_i_n_131; + wire PS7_i_n_1310; + wire PS7_i_n_1311; + wire PS7_i_n_1312; + wire PS7_i_n_1313; + wire PS7_i_n_1314; + wire PS7_i_n_1315; + wire PS7_i_n_1316; + wire PS7_i_n_1317; + wire PS7_i_n_1318; + wire PS7_i_n_1319; + wire PS7_i_n_132; + wire PS7_i_n_1320; + wire PS7_i_n_133; + wire PS7_i_n_1337; + wire PS7_i_n_1338; + wire PS7_i_n_1339; + wire PS7_i_n_134; + wire PS7_i_n_1340; + wire PS7_i_n_1341; + wire PS7_i_n_1342; + wire PS7_i_n_1343; + wire PS7_i_n_1344; + wire PS7_i_n_1345; + wire PS7_i_n_1346; + wire PS7_i_n_1347; + wire PS7_i_n_1348; + wire PS7_i_n_1349; + wire PS7_i_n_135; + wire PS7_i_n_1350; + wire PS7_i_n_1351; + wire PS7_i_n_1352; + wire PS7_i_n_1353; + wire PS7_i_n_1354; + wire PS7_i_n_1355; + wire PS7_i_n_1356; + wire PS7_i_n_1357; + wire PS7_i_n_1358; + wire PS7_i_n_1359; + wire PS7_i_n_136; + wire PS7_i_n_1360; + wire PS7_i_n_1361; + wire PS7_i_n_1362; + wire PS7_i_n_1363; + wire PS7_i_n_1364; + wire PS7_i_n_1365; + wire PS7_i_n_1366; + wire PS7_i_n_1367; + wire PS7_i_n_1368; + wire PS7_i_n_1369; + wire PS7_i_n_137; + wire PS7_i_n_1370; + wire PS7_i_n_1371; + wire PS7_i_n_1372; + wire PS7_i_n_1373; + wire PS7_i_n_1374; + wire PS7_i_n_1375; + wire PS7_i_n_1376; + wire PS7_i_n_1377; + wire PS7_i_n_1378; + wire PS7_i_n_1379; + wire PS7_i_n_138; + wire PS7_i_n_1380; + wire PS7_i_n_1381; + wire PS7_i_n_1382; + wire PS7_i_n_1383; + wire PS7_i_n_1384; + wire PS7_i_n_1385; + wire PS7_i_n_1386; + wire PS7_i_n_1387; + wire PS7_i_n_1388; + wire PS7_i_n_1389; + wire PS7_i_n_139; + wire PS7_i_n_1390; + wire PS7_i_n_1391; + wire PS7_i_n_1392; + wire PS7_i_n_1393; + wire PS7_i_n_1394; + wire PS7_i_n_1395; + wire PS7_i_n_1396; + wire PS7_i_n_1397; + wire PS7_i_n_1398; + wire PS7_i_n_1399; + wire PS7_i_n_140; + wire PS7_i_n_1400; + wire PS7_i_n_141; + wire PS7_i_n_142; + wire PS7_i_n_143; + wire PS7_i_n_144; + wire PS7_i_n_145; + wire PS7_i_n_146; + wire PS7_i_n_147; + wire PS7_i_n_148; + wire PS7_i_n_149; + wire PS7_i_n_150; + wire PS7_i_n_151; + wire PS7_i_n_16; + wire PS7_i_n_17; + wire PS7_i_n_188; + wire PS7_i_n_189; + wire PS7_i_n_19; + wire PS7_i_n_190; + wire PS7_i_n_191; + wire PS7_i_n_192; + wire PS7_i_n_193; + wire PS7_i_n_194; + wire PS7_i_n_195; + wire PS7_i_n_196; + wire PS7_i_n_197; + wire PS7_i_n_198; + wire PS7_i_n_199; + wire PS7_i_n_2; + wire PS7_i_n_20; + wire PS7_i_n_200; + wire PS7_i_n_201; + wire PS7_i_n_202; + wire PS7_i_n_203; + wire PS7_i_n_204; + wire PS7_i_n_205; + wire PS7_i_n_206; + wire PS7_i_n_207; + wire PS7_i_n_208; + wire PS7_i_n_209; + wire PS7_i_n_21; + wire PS7_i_n_210; + wire PS7_i_n_211; + wire PS7_i_n_212; + wire PS7_i_n_213; + wire PS7_i_n_214; + wire PS7_i_n_215; + wire PS7_i_n_216; + wire PS7_i_n_217; + wire PS7_i_n_218; + wire PS7_i_n_219; + wire PS7_i_n_22; + wire PS7_i_n_220; + wire PS7_i_n_221; + wire PS7_i_n_222; + wire PS7_i_n_223; + wire PS7_i_n_224; + wire PS7_i_n_225; + wire PS7_i_n_226; + wire PS7_i_n_227; + wire PS7_i_n_228; + wire PS7_i_n_229; + wire PS7_i_n_23; + wire PS7_i_n_230; + wire PS7_i_n_231; + wire PS7_i_n_232; + wire PS7_i_n_233; + wire PS7_i_n_234; + wire PS7_i_n_235; + wire PS7_i_n_236; + wire PS7_i_n_237; + wire PS7_i_n_238; + wire PS7_i_n_239; + wire PS7_i_n_24; + wire PS7_i_n_25; + wire PS7_i_n_252; + wire PS7_i_n_253; + wire PS7_i_n_254; + wire PS7_i_n_255; + wire PS7_i_n_256; + wire PS7_i_n_257; + wire PS7_i_n_258; + wire PS7_i_n_259; + wire PS7_i_n_26; + wire PS7_i_n_260; + wire PS7_i_n_261; + wire PS7_i_n_262; + wire PS7_i_n_263; + wire PS7_i_n_264; + wire PS7_i_n_265; + wire PS7_i_n_266; + wire PS7_i_n_267; + wire PS7_i_n_268; + wire PS7_i_n_269; + wire PS7_i_n_27; + wire PS7_i_n_270; + wire PS7_i_n_271; + wire PS7_i_n_272; + wire PS7_i_n_273; + wire PS7_i_n_274; + wire PS7_i_n_275; + wire PS7_i_n_276; + wire PS7_i_n_277; + wire PS7_i_n_278; + wire PS7_i_n_279; + wire PS7_i_n_28; + wire PS7_i_n_280; + wire PS7_i_n_281; + wire PS7_i_n_282; + wire PS7_i_n_283; + wire PS7_i_n_284; + wire PS7_i_n_285; + wire PS7_i_n_286; + wire PS7_i_n_287; + wire PS7_i_n_288; + wire PS7_i_n_289; + wire PS7_i_n_290; + wire PS7_i_n_291; + wire PS7_i_n_292; + wire PS7_i_n_293; + wire PS7_i_n_294; + wire PS7_i_n_295; + wire PS7_i_n_296; + wire PS7_i_n_297; + wire PS7_i_n_298; + wire PS7_i_n_299; + wire PS7_i_n_3; + wire PS7_i_n_300; + wire PS7_i_n_301; + wire PS7_i_n_302; + wire PS7_i_n_303; + wire PS7_i_n_304; + wire PS7_i_n_305; + wire PS7_i_n_306; + wire PS7_i_n_307; + wire PS7_i_n_308; + wire PS7_i_n_309; + wire PS7_i_n_31; + wire PS7_i_n_310; + wire PS7_i_n_311; + wire PS7_i_n_312; + wire PS7_i_n_313; + wire PS7_i_n_314; + wire PS7_i_n_315; + wire PS7_i_n_316; + wire PS7_i_n_317; + wire PS7_i_n_318; + wire PS7_i_n_319; + wire PS7_i_n_32; + wire PS7_i_n_320; + wire PS7_i_n_321; + wire PS7_i_n_322; + wire PS7_i_n_323; + wire PS7_i_n_324; + wire PS7_i_n_325; + wire PS7_i_n_326; + wire PS7_i_n_327; + wire PS7_i_n_328; + wire PS7_i_n_329; + wire PS7_i_n_330; + wire PS7_i_n_331; + wire PS7_i_n_332; + wire PS7_i_n_333; + wire PS7_i_n_334; + wire PS7_i_n_335; + wire PS7_i_n_336; + wire PS7_i_n_337; + wire PS7_i_n_338; + wire PS7_i_n_34; + wire PS7_i_n_345; + wire PS7_i_n_346; + wire PS7_i_n_347; + wire PS7_i_n_348; + wire PS7_i_n_349; + wire PS7_i_n_35; + wire PS7_i_n_350; + wire PS7_i_n_351; + wire PS7_i_n_352; + wire PS7_i_n_353; + wire PS7_i_n_354; + wire PS7_i_n_355; + wire PS7_i_n_356; + wire PS7_i_n_357; + wire PS7_i_n_358; + wire PS7_i_n_359; + wire PS7_i_n_36; + wire PS7_i_n_360; + wire PS7_i_n_361; + wire PS7_i_n_362; + wire PS7_i_n_363; + wire PS7_i_n_364; + wire PS7_i_n_365; + wire PS7_i_n_366; + wire PS7_i_n_367; + wire PS7_i_n_368; + wire PS7_i_n_37; + wire PS7_i_n_38; + wire PS7_i_n_39; + wire PS7_i_n_4; + wire PS7_i_n_40; + wire PS7_i_n_401; + wire PS7_i_n_402; + wire PS7_i_n_403; + wire PS7_i_n_404; + wire PS7_i_n_405; + wire PS7_i_n_406; + wire PS7_i_n_407; + wire PS7_i_n_408; + wire PS7_i_n_409; + wire PS7_i_n_41; + wire PS7_i_n_410; + wire PS7_i_n_411; + wire PS7_i_n_412; + wire PS7_i_n_413; + wire PS7_i_n_414; + wire PS7_i_n_415; + wire PS7_i_n_416; + wire PS7_i_n_417; + wire PS7_i_n_418; + wire PS7_i_n_419; + wire PS7_i_n_42; + wire PS7_i_n_420; + wire PS7_i_n_421; + wire PS7_i_n_422; + wire PS7_i_n_423; + wire PS7_i_n_424; + wire PS7_i_n_425; + wire PS7_i_n_426; + wire PS7_i_n_427; + wire PS7_i_n_428; + wire PS7_i_n_429; + wire PS7_i_n_43; + wire PS7_i_n_430; + wire PS7_i_n_431; + wire PS7_i_n_432; + wire PS7_i_n_44; + wire PS7_i_n_46; + wire PS7_i_n_48; + wire PS7_i_n_5; + wire PS7_i_n_50; + wire PS7_i_n_529; + wire PS7_i_n_530; + wire PS7_i_n_531; + wire PS7_i_n_532; + wire PS7_i_n_533; + wire PS7_i_n_534; + wire PS7_i_n_535; + wire PS7_i_n_536; + wire PS7_i_n_537; + wire PS7_i_n_538; + wire PS7_i_n_539; + wire PS7_i_n_54; + wire PS7_i_n_540; + wire PS7_i_n_541; + wire PS7_i_n_542; + wire PS7_i_n_543; + wire PS7_i_n_544; + wire PS7_i_n_545; + wire PS7_i_n_546; + wire PS7_i_n_547; + wire PS7_i_n_548; + wire PS7_i_n_549; + wire PS7_i_n_55; + wire PS7_i_n_550; + wire PS7_i_n_551; + wire PS7_i_n_552; + wire PS7_i_n_553; + wire PS7_i_n_554; + wire PS7_i_n_555; + wire PS7_i_n_556; + wire PS7_i_n_557; + wire PS7_i_n_558; + wire PS7_i_n_559; + wire PS7_i_n_56; + wire PS7_i_n_560; + wire PS7_i_n_561; + wire PS7_i_n_562; + wire PS7_i_n_563; + wire PS7_i_n_564; + wire PS7_i_n_565; + wire PS7_i_n_566; + wire PS7_i_n_567; + wire PS7_i_n_568; + wire PS7_i_n_569; + wire PS7_i_n_570; + wire PS7_i_n_571; + wire PS7_i_n_572; + wire PS7_i_n_573; + wire PS7_i_n_574; + wire PS7_i_n_575; + wire PS7_i_n_576; + wire PS7_i_n_577; + wire PS7_i_n_578; + wire PS7_i_n_579; + wire PS7_i_n_58; + wire PS7_i_n_580; + wire PS7_i_n_581; + wire PS7_i_n_582; + wire PS7_i_n_583; + wire PS7_i_n_584; + wire PS7_i_n_585; + wire PS7_i_n_586; + wire PS7_i_n_587; + wire PS7_i_n_588; + wire PS7_i_n_589; + wire PS7_i_n_59; + wire PS7_i_n_590; + wire PS7_i_n_591; + wire PS7_i_n_592; + wire PS7_i_n_593; + wire PS7_i_n_594; + wire PS7_i_n_595; + wire PS7_i_n_596; + wire PS7_i_n_597; + wire PS7_i_n_598; + wire PS7_i_n_599; + wire PS7_i_n_6; + wire PS7_i_n_60; + wire PS7_i_n_600; + wire PS7_i_n_601; + wire PS7_i_n_602; + wire PS7_i_n_603; + wire PS7_i_n_604; + wire PS7_i_n_605; + wire PS7_i_n_606; + wire PS7_i_n_607; + wire PS7_i_n_608; + wire PS7_i_n_609; + wire PS7_i_n_61; + wire PS7_i_n_610; + wire PS7_i_n_611; + wire PS7_i_n_612; + wire PS7_i_n_613; + wire PS7_i_n_614; + wire PS7_i_n_615; + wire PS7_i_n_616; + wire PS7_i_n_617; + wire PS7_i_n_618; + wire PS7_i_n_619; + wire PS7_i_n_620; + wire PS7_i_n_621; + wire PS7_i_n_622; + wire PS7_i_n_623; + wire PS7_i_n_624; + wire PS7_i_n_625; + wire PS7_i_n_626; + wire PS7_i_n_627; + wire PS7_i_n_628; + wire PS7_i_n_629; + wire PS7_i_n_63; + wire PS7_i_n_630; + wire PS7_i_n_631; + wire PS7_i_n_632; + wire PS7_i_n_633; + wire PS7_i_n_634; + wire PS7_i_n_635; + wire PS7_i_n_636; + wire PS7_i_n_637; + wire PS7_i_n_638; + wire PS7_i_n_639; + wire PS7_i_n_64; + wire PS7_i_n_640; + wire PS7_i_n_641; + wire PS7_i_n_642; + wire PS7_i_n_643; + wire PS7_i_n_644; + wire PS7_i_n_645; + wire PS7_i_n_646; + wire PS7_i_n_647; + wire PS7_i_n_648; + wire PS7_i_n_649; + wire PS7_i_n_650; + wire PS7_i_n_651; + wire PS7_i_n_652; + wire PS7_i_n_653; + wire PS7_i_n_654; + wire PS7_i_n_655; + wire PS7_i_n_656; + wire PS7_i_n_657; + wire PS7_i_n_658; + wire PS7_i_n_659; + wire PS7_i_n_66; + wire PS7_i_n_660; + wire PS7_i_n_661; + wire PS7_i_n_662; + wire PS7_i_n_663; + wire PS7_i_n_664; + wire PS7_i_n_665; + wire PS7_i_n_666; + wire PS7_i_n_667; + wire PS7_i_n_668; + wire PS7_i_n_669; + wire PS7_i_n_670; + wire PS7_i_n_671; + wire PS7_i_n_672; + wire PS7_i_n_673; + wire PS7_i_n_674; + wire PS7_i_n_675; + wire PS7_i_n_676; + wire PS7_i_n_677; + wire PS7_i_n_678; + wire PS7_i_n_679; + wire PS7_i_n_68; + wire PS7_i_n_680; + wire PS7_i_n_681; + wire PS7_i_n_682; + wire PS7_i_n_683; + wire PS7_i_n_684; + wire PS7_i_n_685; + wire PS7_i_n_686; + wire PS7_i_n_687; + wire PS7_i_n_688; + wire PS7_i_n_689; + wire PS7_i_n_690; + wire PS7_i_n_691; + wire PS7_i_n_692; + wire PS7_i_n_697; + wire PS7_i_n_698; + wire PS7_i_n_699; + wire PS7_i_n_7; + wire PS7_i_n_700; + wire PS7_i_n_709; + wire PS7_i_n_71; + wire PS7_i_n_710; + wire PS7_i_n_711; + wire PS7_i_n_713; + wire PS7_i_n_714; + wire PS7_i_n_715; + wire PS7_i_n_716; + wire PS7_i_n_717; + wire PS7_i_n_718; + wire PS7_i_n_719; + wire PS7_i_n_720; + wire PS7_i_n_73; + wire PS7_i_n_749; + wire PS7_i_n_75; + wire PS7_i_n_750; + wire PS7_i_n_752; + wire PS7_i_n_753; + wire PS7_i_n_754; + wire PS7_i_n_755; + wire PS7_i_n_756; + wire PS7_i_n_757; + wire PS7_i_n_758; + wire PS7_i_n_759; + wire PS7_i_n_760; + wire PS7_i_n_761; + wire PS7_i_n_762; + wire PS7_i_n_764; + wire PS7_i_n_765; + wire PS7_i_n_766; + wire PS7_i_n_767; + wire PS7_i_n_768; + wire PS7_i_n_769; + wire PS7_i_n_770; + wire PS7_i_n_771; + wire PS7_i_n_772; + wire PS7_i_n_773; + wire PS7_i_n_774; + wire PS7_i_n_775; + wire PS7_i_n_776; + wire PS7_i_n_777; + wire PS7_i_n_778; + wire PS7_i_n_779; + wire PS7_i_n_780; + wire PS7_i_n_781; + wire PS7_i_n_782; + wire PS7_i_n_783; + wire PS7_i_n_784; + wire PS7_i_n_785; + wire PS7_i_n_786; + wire PS7_i_n_787; + wire PS7_i_n_788; + wire PS7_i_n_789; + wire PS7_i_n_79; + wire PS7_i_n_790; + wire PS7_i_n_791; + wire PS7_i_n_792; + wire PS7_i_n_793; + wire PS7_i_n_794; + wire PS7_i_n_795; + wire PS7_i_n_796; + wire PS7_i_n_797; + wire PS7_i_n_798; + wire PS7_i_n_799; + wire PS7_i_n_8; + wire PS7_i_n_80; + wire PS7_i_n_800; + wire PS7_i_n_801; + wire PS7_i_n_802; + wire PS7_i_n_803; + wire PS7_i_n_804; + wire PS7_i_n_805; + wire PS7_i_n_806; + wire PS7_i_n_807; + wire PS7_i_n_808; + wire PS7_i_n_809; + wire PS7_i_n_81; + wire PS7_i_n_810; + wire PS7_i_n_811; + wire PS7_i_n_812; + wire PS7_i_n_813; + wire PS7_i_n_814; + wire PS7_i_n_815; + wire PS7_i_n_816; + wire PS7_i_n_817; + wire PS7_i_n_818; + wire PS7_i_n_819; + wire PS7_i_n_82; + wire PS7_i_n_820; + wire PS7_i_n_821; + wire PS7_i_n_822; + wire PS7_i_n_823; + wire PS7_i_n_824; + wire PS7_i_n_825; + wire PS7_i_n_826; + wire PS7_i_n_827; + wire PS7_i_n_828; + wire PS7_i_n_829; + wire PS7_i_n_83; + wire PS7_i_n_830; + wire PS7_i_n_831; + wire PS7_i_n_832; + wire PS7_i_n_833; + wire PS7_i_n_834; + wire PS7_i_n_835; + wire PS7_i_n_836; + wire PS7_i_n_837; + wire PS7_i_n_838; + wire PS7_i_n_839; + wire PS7_i_n_84; + wire PS7_i_n_840; + wire PS7_i_n_841; + wire PS7_i_n_842; + wire PS7_i_n_843; + wire PS7_i_n_844; + wire PS7_i_n_845; + wire PS7_i_n_846; + wire PS7_i_n_847; + wire PS7_i_n_848; + wire PS7_i_n_849; + wire PS7_i_n_85; + wire PS7_i_n_850; + wire PS7_i_n_851; + wire PS7_i_n_852; + wire PS7_i_n_853; + wire PS7_i_n_854; + wire PS7_i_n_855; + wire PS7_i_n_856; + wire PS7_i_n_857; + wire PS7_i_n_858; + wire PS7_i_n_859; + wire PS7_i_n_86; + wire PS7_i_n_860; + wire PS7_i_n_861; + wire PS7_i_n_862; + wire PS7_i_n_863; + wire PS7_i_n_864; + wire PS7_i_n_865; + wire PS7_i_n_866; + wire PS7_i_n_867; + wire PS7_i_n_868; + wire PS7_i_n_869; + wire PS7_i_n_87; + wire PS7_i_n_870; + wire PS7_i_n_871; + wire PS7_i_n_872; + wire PS7_i_n_873; + wire PS7_i_n_874; + wire PS7_i_n_875; + wire PS7_i_n_876; + wire PS7_i_n_877; + wire PS7_i_n_878; + wire PS7_i_n_879; + wire PS7_i_n_88; + wire PS7_i_n_880; + wire PS7_i_n_881; + wire PS7_i_n_882; + wire PS7_i_n_883; + wire PS7_i_n_884; + wire PS7_i_n_885; + wire PS7_i_n_886; + wire PS7_i_n_887; + wire PS7_i_n_888; + wire PS7_i_n_889; + wire PS7_i_n_89; + wire PS7_i_n_890; + wire PS7_i_n_891; + wire PS7_i_n_892; + wire PS7_i_n_893; + wire PS7_i_n_894; + wire PS7_i_n_895; + wire PS7_i_n_896; + wire PS7_i_n_897; + wire PS7_i_n_898; + wire PS7_i_n_899; + wire PS7_i_n_9; + wire PS7_i_n_900; + wire PS7_i_n_901; + wire PS7_i_n_902; + wire PS7_i_n_903; + wire PS7_i_n_904; + wire PS7_i_n_905; + wire PS7_i_n_906; + wire PS7_i_n_907; + wire PS7_i_n_908; + wire PS7_i_n_909; + wire PS7_i_n_910; + wire PS7_i_n_911; + wire PS7_i_n_912; + wire PS7_i_n_913; + wire PS7_i_n_914; + wire PS7_i_n_915; + wire PS7_i_n_916; + wire PS7_i_n_917; + wire PS7_i_n_918; + wire PS7_i_n_919; + wire PS7_i_n_920; + wire PS7_i_n_921; + wire PS7_i_n_922; + wire PS7_i_n_923; + wire PS7_i_n_924; + wire PS7_i_n_925; + wire PS7_i_n_926; + wire PS7_i_n_927; + wire PS7_i_n_928; + wire PS7_i_n_929; + wire PS7_i_n_930; + wire PS7_i_n_931; + wire PS7_i_n_932; + wire PS7_i_n_933; + wire PS7_i_n_934; + wire PS7_i_n_935; + wire PS7_i_n_936; + wire PS7_i_n_96; + wire PS7_i_n_97; + wire PS7_i_n_98; + wire PS7_i_n_99; + wire PS_CLK; + wire PS_PORB; + wire PS_SRSTB; + wire SDIO0_CMD_T_n; + wire [3:0]SDIO0_DATA_T_n; + wire SDIO1_CMD_T_n; + wire [3:0]SDIO1_DATA_T_n; + wire SPI0_MISO_T_n; + wire SPI0_MOSI_T_n; + wire SPI0_SCLK_T_n; + wire SPI0_SS_T_n; + wire SPI1_MISO_T_n; + wire SPI1_MOSI_T_n; + wire SPI1_SCLK_T_n; + wire SPI1_SS_T_n; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[0] ; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[1] ; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[2] ; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[3] ; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[4] ; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[5] ; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[6] ; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[7] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[0] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[1] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[2] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[3] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[4] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[5] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[6] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[7] ; + wire [14:0]buffered_DDR_Addr; + wire [2:0]buffered_DDR_BankAddr; + wire buffered_DDR_CAS_n; + wire buffered_DDR_CKE; + wire buffered_DDR_CS_n; + wire buffered_DDR_Clk; + wire buffered_DDR_Clk_n; + wire [3:0]buffered_DDR_DM; + wire [31:0]buffered_DDR_DQ; + wire [3:0]buffered_DDR_DQS; + wire [3:0]buffered_DDR_DQS_n; + wire buffered_DDR_DRSTB; + wire buffered_DDR_ODT; + wire buffered_DDR_RAS_n; + wire buffered_DDR_VRN; + wire buffered_DDR_VRP; + wire buffered_DDR_WEB; + wire [53:0]buffered_MIO; + wire buffered_PS_CLK; + wire buffered_PS_PORB; + wire buffered_PS_SRSTB; + wire [63:0]gpio_out_t_n; + wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED; + wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED; + wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED; + wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED; + wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED; + wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED; + wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED; + wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED; + wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED; + wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED; + wire [1:1]NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED; + wire [1:1]NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED; + wire [1:1]NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED; + wire [1:1]NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED; + + assign CAN0_PHY_TX = \ ; + assign CAN1_PHY_TX = \ ; + assign DMA0_DATYPE[1] = \ ; + assign DMA0_DATYPE[0] = \ ; + assign DMA0_DAVALID = \ ; + assign DMA0_DRREADY = \ ; + assign DMA0_RSTN = \ ; + assign DMA1_DATYPE[1] = \ ; + assign DMA1_DATYPE[0] = \ ; + assign DMA1_DAVALID = \ ; + assign DMA1_DRREADY = \ ; + assign DMA1_RSTN = \ ; + assign DMA2_DATYPE[1] = \ ; + assign DMA2_DATYPE[0] = \ ; + assign DMA2_DAVALID = \ ; + assign DMA2_DRREADY = \ ; + assign DMA2_RSTN = \ ; + assign DMA3_DATYPE[1] = \ ; + assign DMA3_DATYPE[0] = \ ; + assign DMA3_DAVALID = \ ; + assign DMA3_DRREADY = \ ; + assign DMA3_RSTN = \ ; + assign ENET0_GMII_TXD[7] = \ ; + assign ENET0_GMII_TXD[6] = \ ; + assign ENET0_GMII_TXD[5] = \ ; + assign ENET0_GMII_TXD[4] = \ ; + assign ENET0_GMII_TXD[3] = \ ; + assign ENET0_GMII_TXD[2] = \ ; + assign ENET0_GMII_TXD[1] = \ ; + assign ENET0_GMII_TXD[0] = \ ; + assign ENET0_GMII_TX_EN = \ ; + assign ENET0_GMII_TX_ER = \ ; + assign ENET0_MDIO_MDC = \ ; + assign ENET0_MDIO_O = \ ; + assign ENET0_MDIO_T = \ ; + assign ENET0_PTP_DELAY_REQ_RX = \ ; + assign ENET0_PTP_DELAY_REQ_TX = \ ; + assign ENET0_PTP_PDELAY_REQ_RX = \ ; + assign ENET0_PTP_PDELAY_REQ_TX = \ ; + assign ENET0_PTP_PDELAY_RESP_RX = \ ; + assign ENET0_PTP_PDELAY_RESP_TX = \ ; + assign ENET0_PTP_SYNC_FRAME_RX = \ ; + assign ENET0_PTP_SYNC_FRAME_TX = \ ; + assign ENET0_SOF_RX = \ ; + assign ENET0_SOF_TX = \ ; + assign ENET1_GMII_TXD[7] = \ ; + assign ENET1_GMII_TXD[6] = \ ; + assign ENET1_GMII_TXD[5] = \ ; + assign ENET1_GMII_TXD[4] = \ ; + assign ENET1_GMII_TXD[3] = \ ; + assign ENET1_GMII_TXD[2] = \ ; + assign ENET1_GMII_TXD[1] = \ ; + assign ENET1_GMII_TXD[0] = \ ; + assign ENET1_GMII_TX_EN = \ ; + assign ENET1_GMII_TX_ER = \ ; + assign ENET1_MDIO_MDC = \ ; + assign ENET1_MDIO_O = \ ; + assign ENET1_MDIO_T = \ ; + assign ENET1_PTP_DELAY_REQ_RX = \ ; + assign ENET1_PTP_DELAY_REQ_TX = \ ; + assign ENET1_PTP_PDELAY_REQ_RX = \ ; + assign ENET1_PTP_PDELAY_REQ_TX = \ ; + assign ENET1_PTP_PDELAY_RESP_RX = \ ; + assign ENET1_PTP_PDELAY_RESP_TX = \ ; + assign ENET1_PTP_SYNC_FRAME_RX = \ ; + assign ENET1_PTP_SYNC_FRAME_TX = \ ; + assign ENET1_SOF_RX = \ ; + assign ENET1_SOF_TX = \ ; + assign EVENT_EVENTO = \ ; + assign EVENT_STANDBYWFE[1] = \ ; + assign EVENT_STANDBYWFE[0] = \ ; + assign EVENT_STANDBYWFI[1] = \ ; + assign EVENT_STANDBYWFI[0] = \ ; + assign FCLK_RESET1_N = \ ; + assign FCLK_RESET2_N = \ ; + assign FCLK_RESET3_N = \ ; + assign FTMT_F2P_TRIGACK_0 = \ ; + assign FTMT_F2P_TRIGACK_1 = \ ; + assign FTMT_F2P_TRIGACK_2 = \ ; + assign FTMT_F2P_TRIGACK_3 = \ ; + assign FTMT_P2F_DEBUG[31] = \ ; + assign FTMT_P2F_DEBUG[30] = \ ; + assign FTMT_P2F_DEBUG[29] = \ ; + assign FTMT_P2F_DEBUG[28] = \ ; + assign FTMT_P2F_DEBUG[27] = \ ; + assign FTMT_P2F_DEBUG[26] = \ ; + assign FTMT_P2F_DEBUG[25] = \ ; + assign FTMT_P2F_DEBUG[24] = \ ; + assign FTMT_P2F_DEBUG[23] = \ ; + assign FTMT_P2F_DEBUG[22] = \ ; + assign FTMT_P2F_DEBUG[21] = \ ; + assign FTMT_P2F_DEBUG[20] = \ ; + assign FTMT_P2F_DEBUG[19] = \ ; + assign FTMT_P2F_DEBUG[18] = \ ; + assign FTMT_P2F_DEBUG[17] = \ ; + assign FTMT_P2F_DEBUG[16] = \ ; + assign FTMT_P2F_DEBUG[15] = \ ; + assign FTMT_P2F_DEBUG[14] = \ ; + assign FTMT_P2F_DEBUG[13] = \ ; + assign FTMT_P2F_DEBUG[12] = \ ; + assign FTMT_P2F_DEBUG[11] = \ ; + assign FTMT_P2F_DEBUG[10] = \ ; + assign FTMT_P2F_DEBUG[9] = \ ; + assign FTMT_P2F_DEBUG[8] = \ ; + assign FTMT_P2F_DEBUG[7] = \ ; + assign FTMT_P2F_DEBUG[6] = \ ; + assign FTMT_P2F_DEBUG[5] = \ ; + assign FTMT_P2F_DEBUG[4] = \ ; + assign FTMT_P2F_DEBUG[3] = \ ; + assign FTMT_P2F_DEBUG[2] = \ ; + assign FTMT_P2F_DEBUG[1] = \ ; + assign FTMT_P2F_DEBUG[0] = \ ; + assign FTMT_P2F_TRIG_0 = \ ; + assign FTMT_P2F_TRIG_1 = \ ; + assign FTMT_P2F_TRIG_2 = \ ; + assign FTMT_P2F_TRIG_3 = \ ; + assign GPIO_O[63] = \ ; + assign GPIO_O[62] = \ ; + assign GPIO_O[61] = \ ; + assign GPIO_O[60] = \ ; + assign GPIO_O[59] = \ ; + assign GPIO_O[58] = \ ; + assign GPIO_O[57] = \ ; + assign GPIO_O[56] = \ ; + assign GPIO_O[55] = \ ; + assign GPIO_O[54] = \ ; + assign GPIO_O[53] = \ ; + assign GPIO_O[52] = \ ; + assign GPIO_O[51] = \ ; + assign GPIO_O[50] = \ ; + assign GPIO_O[49] = \ ; + assign GPIO_O[48] = \ ; + assign GPIO_O[47] = \ ; + assign GPIO_O[46] = \ ; + assign GPIO_O[45] = \ ; + assign GPIO_O[44] = \ ; + assign GPIO_O[43] = \ ; + assign GPIO_O[42] = \ ; + assign GPIO_O[41] = \ ; + assign GPIO_O[40] = \ ; + assign GPIO_O[39] = \ ; + assign GPIO_O[38] = \ ; + assign GPIO_O[37] = \ ; + assign GPIO_O[36] = \ ; + assign GPIO_O[35] = \ ; + assign GPIO_O[34] = \ ; + assign GPIO_O[33] = \ ; + assign GPIO_O[32] = \ ; + assign GPIO_O[31] = \ ; + assign GPIO_O[30] = \ ; + assign GPIO_O[29] = \ ; + assign GPIO_O[28] = \ ; + assign GPIO_O[27] = \ ; + assign GPIO_O[26] = \ ; + assign GPIO_O[25] = \ ; + assign GPIO_O[24] = \ ; + assign GPIO_O[23] = \ ; + assign GPIO_O[22] = \ ; + assign GPIO_O[21] = \ ; + assign GPIO_O[20] = \ ; + assign GPIO_O[19] = \ ; + assign GPIO_O[18] = \ ; + assign GPIO_O[17] = \ ; + assign GPIO_O[16] = \ ; + assign GPIO_O[15] = \ ; + assign GPIO_O[14] = \ ; + assign GPIO_O[13] = \ ; + assign GPIO_O[12] = \ ; + assign GPIO_O[11] = \ ; + assign GPIO_O[10] = \ ; + assign GPIO_O[9] = \ ; + assign GPIO_O[8] = \ ; + assign GPIO_O[7] = \ ; + assign GPIO_O[6] = \ ; + assign GPIO_O[5] = \ ; + assign GPIO_O[4] = \ ; + assign GPIO_O[3] = \ ; + assign GPIO_O[2] = \ ; + assign GPIO_O[1] = \ ; + assign GPIO_O[0] = \ ; + assign GPIO_T[63] = \ ; + assign GPIO_T[62] = \ ; + assign GPIO_T[61] = \ ; + assign GPIO_T[60] = \ ; + assign GPIO_T[59] = \ ; + assign GPIO_T[58] = \ ; + assign GPIO_T[57] = \ ; + assign GPIO_T[56] = \ ; + assign GPIO_T[55] = \ ; + assign GPIO_T[54] = \ ; + assign GPIO_T[53] = \ ; + assign GPIO_T[52] = \ ; + assign GPIO_T[51] = \ ; + assign GPIO_T[50] = \ ; + assign GPIO_T[49] = \ ; + assign GPIO_T[48] = \ ; + assign GPIO_T[47] = \ ; + assign GPIO_T[46] = \ ; + assign GPIO_T[45] = \ ; + assign GPIO_T[44] = \ ; + assign GPIO_T[43] = \ ; + assign GPIO_T[42] = \ ; + assign GPIO_T[41] = \ ; + assign GPIO_T[40] = \ ; + assign GPIO_T[39] = \ ; + assign GPIO_T[38] = \ ; + assign GPIO_T[37] = \ ; + assign GPIO_T[36] = \ ; + assign GPIO_T[35] = \ ; + assign GPIO_T[34] = \ ; + assign GPIO_T[33] = \ ; + assign GPIO_T[32] = \ ; + assign GPIO_T[31] = \ ; + assign GPIO_T[30] = \ ; + assign GPIO_T[29] = \ ; + assign GPIO_T[28] = \ ; + assign GPIO_T[27] = \ ; + assign GPIO_T[26] = \ ; + assign GPIO_T[25] = \ ; + assign GPIO_T[24] = \ ; + assign GPIO_T[23] = \ ; + assign GPIO_T[22] = \ ; + assign GPIO_T[21] = \ ; + assign GPIO_T[20] = \ ; + assign GPIO_T[19] = \ ; + assign GPIO_T[18] = \ ; + assign GPIO_T[17] = \ ; + assign GPIO_T[16] = \ ; + assign GPIO_T[15] = \ ; + assign GPIO_T[14] = \ ; + assign GPIO_T[13] = \ ; + assign GPIO_T[12] = \ ; + assign GPIO_T[11] = \ ; + assign GPIO_T[10] = \ ; + assign GPIO_T[9] = \ ; + assign GPIO_T[8] = \ ; + assign GPIO_T[7] = \ ; + assign GPIO_T[6] = \ ; + assign GPIO_T[5] = \ ; + assign GPIO_T[4] = \ ; + assign GPIO_T[3] = \ ; + assign GPIO_T[2] = \ ; + assign GPIO_T[1] = \ ; + assign GPIO_T[0] = \ ; + assign I2C0_SCL_O = \ ; + assign I2C0_SCL_T = \ ; + assign I2C0_SDA_O = \ ; + assign I2C0_SDA_T = \ ; + assign I2C1_SCL_O = \ ; + assign I2C1_SCL_T = \ ; + assign I2C1_SDA_O = \ ; + assign I2C1_SDA_T = \ ; + assign IRQ_P2F_CAN0 = \ ; + assign IRQ_P2F_CAN1 = \ ; + assign IRQ_P2F_CTI = \ ; + assign IRQ_P2F_DMAC0 = \ ; + assign IRQ_P2F_DMAC1 = \ ; + assign IRQ_P2F_DMAC2 = \ ; + assign IRQ_P2F_DMAC3 = \ ; + assign IRQ_P2F_DMAC4 = \ ; + assign IRQ_P2F_DMAC5 = \ ; + assign IRQ_P2F_DMAC6 = \ ; + assign IRQ_P2F_DMAC7 = \ ; + assign IRQ_P2F_DMAC_ABORT = \ ; + assign IRQ_P2F_ENET0 = \ ; + assign IRQ_P2F_ENET1 = \ ; + assign IRQ_P2F_ENET_WAKE0 = \ ; + assign IRQ_P2F_ENET_WAKE1 = \ ; + assign IRQ_P2F_GPIO = \ ; + assign IRQ_P2F_I2C0 = \ ; + assign IRQ_P2F_I2C1 = \ ; + assign IRQ_P2F_QSPI = \ ; + assign IRQ_P2F_SDIO0 = \ ; + assign IRQ_P2F_SDIO1 = \ ; + assign IRQ_P2F_SMC = \ ; + assign IRQ_P2F_SPI0 = \ ; + assign IRQ_P2F_SPI1 = \ ; + assign IRQ_P2F_UART0 = \ ; + assign IRQ_P2F_UART1 = \ ; + assign IRQ_P2F_USB0 = \ ; + assign IRQ_P2F_USB1 = \ ; + assign M_AXI_GP0_ARCACHE[3:2] = \^M_AXI_GP0_ARCACHE [3:2]; + assign M_AXI_GP0_ARCACHE[1] = \ ; + assign M_AXI_GP0_ARCACHE[0] = \^M_AXI_GP0_ARCACHE [0]; + assign M_AXI_GP0_ARESETN = \ ; + assign M_AXI_GP0_ARSIZE[2] = \ ; + assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0]; + assign M_AXI_GP0_AWCACHE[3:2] = \^M_AXI_GP0_AWCACHE [3:2]; + assign M_AXI_GP0_AWCACHE[1] = \ ; + assign M_AXI_GP0_AWCACHE[0] = \^M_AXI_GP0_AWCACHE [0]; + assign M_AXI_GP0_AWSIZE[2] = \ ; + assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0]; + assign M_AXI_GP1_ARADDR[31] = \ ; + assign M_AXI_GP1_ARADDR[30] = \ ; + assign M_AXI_GP1_ARADDR[29] = \ ; + assign M_AXI_GP1_ARADDR[28] = \ ; + assign M_AXI_GP1_ARADDR[27] = \ ; + assign M_AXI_GP1_ARADDR[26] = \ ; + assign M_AXI_GP1_ARADDR[25] = \ ; + assign M_AXI_GP1_ARADDR[24] = \ ; + assign M_AXI_GP1_ARADDR[23] = \ ; + assign M_AXI_GP1_ARADDR[22] = \ ; + assign M_AXI_GP1_ARADDR[21] = \ ; + assign M_AXI_GP1_ARADDR[20] = \ ; + assign M_AXI_GP1_ARADDR[19] = \ ; + assign M_AXI_GP1_ARADDR[18] = \ ; + assign M_AXI_GP1_ARADDR[17] = \ ; + assign M_AXI_GP1_ARADDR[16] = \ ; + assign M_AXI_GP1_ARADDR[15] = \ ; + assign M_AXI_GP1_ARADDR[14] = \ ; + assign M_AXI_GP1_ARADDR[13] = \ ; + assign M_AXI_GP1_ARADDR[12] = \ ; + assign M_AXI_GP1_ARADDR[11] = \ ; + assign M_AXI_GP1_ARADDR[10] = \ ; + assign M_AXI_GP1_ARADDR[9] = \ ; + assign M_AXI_GP1_ARADDR[8] = \ ; + assign M_AXI_GP1_ARADDR[7] = \ ; + assign M_AXI_GP1_ARADDR[6] = \ ; + assign M_AXI_GP1_ARADDR[5] = \ ; + assign M_AXI_GP1_ARADDR[4] = \ ; + assign M_AXI_GP1_ARADDR[3] = \ ; + assign M_AXI_GP1_ARADDR[2] = \ ; + assign M_AXI_GP1_ARADDR[1] = \ ; + assign M_AXI_GP1_ARADDR[0] = \ ; + assign M_AXI_GP1_ARBURST[1] = \ ; + assign M_AXI_GP1_ARBURST[0] = \ ; + assign M_AXI_GP1_ARCACHE[3] = \ ; + assign M_AXI_GP1_ARCACHE[2] = \ ; + assign M_AXI_GP1_ARCACHE[1] = \ ; + assign M_AXI_GP1_ARCACHE[0] = \ ; + assign M_AXI_GP1_ARESETN = \ ; + assign M_AXI_GP1_ARID[11] = \ ; + assign M_AXI_GP1_ARID[10] = \ ; + assign M_AXI_GP1_ARID[9] = \ ; + assign M_AXI_GP1_ARID[8] = \ ; + assign M_AXI_GP1_ARID[7] = \ ; + assign M_AXI_GP1_ARID[6] = \ ; + assign M_AXI_GP1_ARID[5] = \ ; + assign M_AXI_GP1_ARID[4] = \ ; + assign M_AXI_GP1_ARID[3] = \ ; + assign M_AXI_GP1_ARID[2] = \ ; + assign M_AXI_GP1_ARID[1] = \ ; + assign M_AXI_GP1_ARID[0] = \ ; + assign M_AXI_GP1_ARLEN[3] = \ ; + assign M_AXI_GP1_ARLEN[2] = \ ; + assign M_AXI_GP1_ARLEN[1] = \ ; + assign M_AXI_GP1_ARLEN[0] = \ ; + assign M_AXI_GP1_ARLOCK[1] = \ ; + assign M_AXI_GP1_ARLOCK[0] = \ ; + assign M_AXI_GP1_ARPROT[2] = \ ; + assign M_AXI_GP1_ARPROT[1] = \ ; + assign M_AXI_GP1_ARPROT[0] = \ ; + assign M_AXI_GP1_ARQOS[3] = \ ; + assign M_AXI_GP1_ARQOS[2] = \ ; + assign M_AXI_GP1_ARQOS[1] = \ ; + assign M_AXI_GP1_ARQOS[0] = \ ; + assign M_AXI_GP1_ARSIZE[2] = \ ; + assign M_AXI_GP1_ARSIZE[1] = \ ; + assign M_AXI_GP1_ARSIZE[0] = \ ; + assign M_AXI_GP1_ARVALID = \ ; + assign M_AXI_GP1_AWADDR[31] = \ ; + assign M_AXI_GP1_AWADDR[30] = \ ; + assign M_AXI_GP1_AWADDR[29] = \ ; + assign M_AXI_GP1_AWADDR[28] = \ ; + assign M_AXI_GP1_AWADDR[27] = \ ; + assign M_AXI_GP1_AWADDR[26] = \ ; + assign M_AXI_GP1_AWADDR[25] = \ ; + assign M_AXI_GP1_AWADDR[24] = \ ; + assign M_AXI_GP1_AWADDR[23] = \ ; + assign M_AXI_GP1_AWADDR[22] = \ ; + assign M_AXI_GP1_AWADDR[21] = \ ; + assign M_AXI_GP1_AWADDR[20] = \ ; + assign M_AXI_GP1_AWADDR[19] = \ ; + assign M_AXI_GP1_AWADDR[18] = \ ; + assign M_AXI_GP1_AWADDR[17] = \ ; + assign M_AXI_GP1_AWADDR[16] = \ ; + assign M_AXI_GP1_AWADDR[15] = \ ; + assign M_AXI_GP1_AWADDR[14] = \ ; + assign M_AXI_GP1_AWADDR[13] = \ ; + assign M_AXI_GP1_AWADDR[12] = \ ; + assign M_AXI_GP1_AWADDR[11] = \ ; + assign M_AXI_GP1_AWADDR[10] = \ ; + assign M_AXI_GP1_AWADDR[9] = \ ; + assign M_AXI_GP1_AWADDR[8] = \ ; + assign M_AXI_GP1_AWADDR[7] = \ ; + assign M_AXI_GP1_AWADDR[6] = \ ; + assign M_AXI_GP1_AWADDR[5] = \ ; + assign M_AXI_GP1_AWADDR[4] = \ ; + assign M_AXI_GP1_AWADDR[3] = \ ; + assign M_AXI_GP1_AWADDR[2] = \ ; + assign M_AXI_GP1_AWADDR[1] = \ ; + assign M_AXI_GP1_AWADDR[0] = \ ; + assign M_AXI_GP1_AWBURST[1] = \ ; + assign M_AXI_GP1_AWBURST[0] = \ ; + assign M_AXI_GP1_AWCACHE[3] = \ ; + assign M_AXI_GP1_AWCACHE[2] = \ ; + assign M_AXI_GP1_AWCACHE[1] = \ ; + assign M_AXI_GP1_AWCACHE[0] = \ ; + assign M_AXI_GP1_AWID[11] = \ ; + assign M_AXI_GP1_AWID[10] = \ ; + assign M_AXI_GP1_AWID[9] = \ ; + assign M_AXI_GP1_AWID[8] = \ ; + assign M_AXI_GP1_AWID[7] = \ ; + assign M_AXI_GP1_AWID[6] = \ ; + assign M_AXI_GP1_AWID[5] = \ ; + assign M_AXI_GP1_AWID[4] = \ ; + assign M_AXI_GP1_AWID[3] = \ ; + assign M_AXI_GP1_AWID[2] = \ ; + assign M_AXI_GP1_AWID[1] = \ ; + assign M_AXI_GP1_AWID[0] = \ ; + assign M_AXI_GP1_AWLEN[3] = \ ; + assign M_AXI_GP1_AWLEN[2] = \ ; + assign M_AXI_GP1_AWLEN[1] = \ ; + assign M_AXI_GP1_AWLEN[0] = \ ; + assign M_AXI_GP1_AWLOCK[1] = \ ; + assign M_AXI_GP1_AWLOCK[0] = \ ; + assign M_AXI_GP1_AWPROT[2] = \ ; + assign M_AXI_GP1_AWPROT[1] = \ ; + assign M_AXI_GP1_AWPROT[0] = \ ; + assign M_AXI_GP1_AWQOS[3] = \ ; + assign M_AXI_GP1_AWQOS[2] = \ ; + assign M_AXI_GP1_AWQOS[1] = \ ; + assign M_AXI_GP1_AWQOS[0] = \ ; + assign M_AXI_GP1_AWSIZE[2] = \ ; + assign M_AXI_GP1_AWSIZE[1] = \ ; + assign M_AXI_GP1_AWSIZE[0] = \ ; + assign M_AXI_GP1_AWVALID = \ ; + assign M_AXI_GP1_BREADY = \ ; + assign M_AXI_GP1_RREADY = \ ; + assign M_AXI_GP1_WDATA[31] = \ ; + assign M_AXI_GP1_WDATA[30] = \ ; + assign M_AXI_GP1_WDATA[29] = \ ; + assign M_AXI_GP1_WDATA[28] = \ ; + assign M_AXI_GP1_WDATA[27] = \ ; + assign M_AXI_GP1_WDATA[26] = \ ; + assign M_AXI_GP1_WDATA[25] = \ ; + assign M_AXI_GP1_WDATA[24] = \ ; + assign M_AXI_GP1_WDATA[23] = \ ; + assign M_AXI_GP1_WDATA[22] = \ ; + assign M_AXI_GP1_WDATA[21] = \ ; + assign M_AXI_GP1_WDATA[20] = \ ; + assign M_AXI_GP1_WDATA[19] = \ ; + assign M_AXI_GP1_WDATA[18] = \ ; + assign M_AXI_GP1_WDATA[17] = \ ; + assign M_AXI_GP1_WDATA[16] = \ ; + assign M_AXI_GP1_WDATA[15] = \ ; + assign M_AXI_GP1_WDATA[14] = \ ; + assign M_AXI_GP1_WDATA[13] = \ ; + assign M_AXI_GP1_WDATA[12] = \ ; + assign M_AXI_GP1_WDATA[11] = \ ; + assign M_AXI_GP1_WDATA[10] = \ ; + assign M_AXI_GP1_WDATA[9] = \ ; + assign M_AXI_GP1_WDATA[8] = \ ; + assign M_AXI_GP1_WDATA[7] = \ ; + assign M_AXI_GP1_WDATA[6] = \ ; + assign M_AXI_GP1_WDATA[5] = \ ; + assign M_AXI_GP1_WDATA[4] = \ ; + assign M_AXI_GP1_WDATA[3] = \ ; + assign M_AXI_GP1_WDATA[2] = \ ; + assign M_AXI_GP1_WDATA[1] = \ ; + assign M_AXI_GP1_WDATA[0] = \ ; + assign M_AXI_GP1_WID[11] = \ ; + assign M_AXI_GP1_WID[10] = \ ; + assign M_AXI_GP1_WID[9] = \ ; + assign M_AXI_GP1_WID[8] = \ ; + assign M_AXI_GP1_WID[7] = \ ; + assign M_AXI_GP1_WID[6] = \ ; + assign M_AXI_GP1_WID[5] = \ ; + assign M_AXI_GP1_WID[4] = \ ; + assign M_AXI_GP1_WID[3] = \ ; + assign M_AXI_GP1_WID[2] = \ ; + assign M_AXI_GP1_WID[1] = \ ; + assign M_AXI_GP1_WID[0] = \ ; + assign M_AXI_GP1_WLAST = \ ; + assign M_AXI_GP1_WSTRB[3] = \ ; + assign M_AXI_GP1_WSTRB[2] = \ ; + assign M_AXI_GP1_WSTRB[1] = \ ; + assign M_AXI_GP1_WSTRB[0] = \ ; + assign M_AXI_GP1_WVALID = \ ; + assign PJTAG_TDO = \ ; + assign SDIO0_BUSPOW = \ ; + assign SDIO0_BUSVOLT[2] = \ ; + assign SDIO0_BUSVOLT[1] = \ ; + assign SDIO0_BUSVOLT[0] = \ ; + assign SDIO0_CLK = \ ; + assign SDIO0_CMD_O = \ ; + assign SDIO0_CMD_T = \ ; + assign SDIO0_DATA_O[3] = \ ; + assign SDIO0_DATA_O[2] = \ ; + assign SDIO0_DATA_O[1] = \ ; + assign SDIO0_DATA_O[0] = \ ; + assign SDIO0_DATA_T[3] = \ ; + assign SDIO0_DATA_T[2] = \ ; + assign SDIO0_DATA_T[1] = \ ; + assign SDIO0_DATA_T[0] = \ ; + assign SDIO0_LED = \ ; + assign SDIO1_BUSPOW = \ ; + assign SDIO1_BUSVOLT[2] = \ ; + assign SDIO1_BUSVOLT[1] = \ ; + assign SDIO1_BUSVOLT[0] = \ ; + assign SDIO1_CLK = \ ; + assign SDIO1_CMD_O = \ ; + assign SDIO1_CMD_T = \ ; + assign SDIO1_DATA_O[3] = \ ; + assign SDIO1_DATA_O[2] = \ ; + assign SDIO1_DATA_O[1] = \ ; + assign SDIO1_DATA_O[0] = \ ; + assign SDIO1_DATA_T[3] = \ ; + assign SDIO1_DATA_T[2] = \ ; + assign SDIO1_DATA_T[1] = \ ; + assign SDIO1_DATA_T[0] = \ ; + assign SDIO1_LED = \ ; + assign SPI0_MISO_O = \ ; + assign SPI0_MISO_T = \ ; + assign SPI0_MOSI_O = \ ; + assign SPI0_MOSI_T = \ ; + assign SPI0_SCLK_O = \ ; + assign SPI0_SCLK_T = \ ; + assign SPI0_SS1_O = \ ; + assign SPI0_SS2_O = \ ; + assign SPI0_SS_O = \ ; + assign SPI0_SS_T = \ ; + assign SPI1_MISO_O = \ ; + assign SPI1_MISO_T = \ ; + assign SPI1_MOSI_O = \ ; + assign SPI1_MOSI_T = \ ; + assign SPI1_SCLK_O = \ ; + assign SPI1_SCLK_T = \ ; + assign SPI1_SS1_O = \ ; + assign SPI1_SS2_O = \ ; + assign SPI1_SS_O = \ ; + assign SPI1_SS_T = \ ; + assign S_AXI_ACP_ARESETN = \ ; + assign S_AXI_ACP_ARREADY = \ ; + assign S_AXI_ACP_AWREADY = \ ; + assign S_AXI_ACP_BID[2] = \ ; + assign S_AXI_ACP_BID[1] = \ ; + assign S_AXI_ACP_BID[0] = \ ; + assign S_AXI_ACP_BRESP[1] = \ ; + assign S_AXI_ACP_BRESP[0] = \ ; + assign S_AXI_ACP_BVALID = \ ; + assign S_AXI_ACP_RDATA[63] = \ ; + assign S_AXI_ACP_RDATA[62] = \ ; + assign S_AXI_ACP_RDATA[61] = \ ; + assign S_AXI_ACP_RDATA[60] = \ ; + assign S_AXI_ACP_RDATA[59] = \ ; + assign S_AXI_ACP_RDATA[58] = \ ; + assign S_AXI_ACP_RDATA[57] = \ ; + assign S_AXI_ACP_RDATA[56] = \ ; + assign S_AXI_ACP_RDATA[55] = \ ; + assign S_AXI_ACP_RDATA[54] = \ ; + assign S_AXI_ACP_RDATA[53] = \ ; + assign S_AXI_ACP_RDATA[52] = \ ; + assign S_AXI_ACP_RDATA[51] = \ ; + assign S_AXI_ACP_RDATA[50] = \ ; + assign S_AXI_ACP_RDATA[49] = \ ; + assign S_AXI_ACP_RDATA[48] = \ ; + assign S_AXI_ACP_RDATA[47] = \ ; + assign S_AXI_ACP_RDATA[46] = \ ; + assign S_AXI_ACP_RDATA[45] = \ ; + assign S_AXI_ACP_RDATA[44] = \ ; + assign S_AXI_ACP_RDATA[43] = \ ; + assign S_AXI_ACP_RDATA[42] = \ ; + assign S_AXI_ACP_RDATA[41] = \ ; + assign S_AXI_ACP_RDATA[40] = \ ; + assign S_AXI_ACP_RDATA[39] = \ ; + assign S_AXI_ACP_RDATA[38] = \ ; + assign S_AXI_ACP_RDATA[37] = \ ; + assign S_AXI_ACP_RDATA[36] = \ ; + assign S_AXI_ACP_RDATA[35] = \ ; + assign S_AXI_ACP_RDATA[34] = \ ; + assign S_AXI_ACP_RDATA[33] = \ ; + assign S_AXI_ACP_RDATA[32] = \ ; + assign S_AXI_ACP_RDATA[31] = \ ; + assign S_AXI_ACP_RDATA[30] = \ ; + assign S_AXI_ACP_RDATA[29] = \ ; + assign S_AXI_ACP_RDATA[28] = \ ; + assign S_AXI_ACP_RDATA[27] = \ ; + assign S_AXI_ACP_RDATA[26] = \ ; + assign S_AXI_ACP_RDATA[25] = \ ; + assign S_AXI_ACP_RDATA[24] = \ ; + assign S_AXI_ACP_RDATA[23] = \ ; + assign S_AXI_ACP_RDATA[22] = \ ; + assign S_AXI_ACP_RDATA[21] = \ ; + assign S_AXI_ACP_RDATA[20] = \ ; + assign S_AXI_ACP_RDATA[19] = \ ; + assign S_AXI_ACP_RDATA[18] = \ ; + assign S_AXI_ACP_RDATA[17] = \ ; + assign S_AXI_ACP_RDATA[16] = \ ; + assign S_AXI_ACP_RDATA[15] = \ ; + assign S_AXI_ACP_RDATA[14] = \ ; + assign S_AXI_ACP_RDATA[13] = \ ; + assign S_AXI_ACP_RDATA[12] = \ ; + assign S_AXI_ACP_RDATA[11] = \ ; + assign S_AXI_ACP_RDATA[10] = \ ; + assign S_AXI_ACP_RDATA[9] = \ ; + assign S_AXI_ACP_RDATA[8] = \ ; + assign S_AXI_ACP_RDATA[7] = \ ; + assign S_AXI_ACP_RDATA[6] = \ ; + assign S_AXI_ACP_RDATA[5] = \ ; + assign S_AXI_ACP_RDATA[4] = \ ; + assign S_AXI_ACP_RDATA[3] = \ ; + assign S_AXI_ACP_RDATA[2] = \ ; + assign S_AXI_ACP_RDATA[1] = \ ; + assign S_AXI_ACP_RDATA[0] = \ ; + assign S_AXI_ACP_RID[2] = \ ; + assign S_AXI_ACP_RID[1] = \ ; + assign S_AXI_ACP_RID[0] = \ ; + assign S_AXI_ACP_RLAST = \ ; + assign S_AXI_ACP_RRESP[1] = \ ; + assign S_AXI_ACP_RRESP[0] = \ ; + assign S_AXI_ACP_RVALID = \ ; + assign S_AXI_ACP_WREADY = \ ; + assign S_AXI_GP0_ARESETN = \ ; + assign S_AXI_GP0_ARREADY = \ ; + assign S_AXI_GP0_AWREADY = \ ; + assign S_AXI_GP0_BID[5] = \ ; + assign S_AXI_GP0_BID[4] = \ ; + assign S_AXI_GP0_BID[3] = \ ; + assign S_AXI_GP0_BID[2] = \ ; + assign S_AXI_GP0_BID[1] = \ ; + assign S_AXI_GP0_BID[0] = \ ; + assign S_AXI_GP0_BRESP[1] = \ ; + assign S_AXI_GP0_BRESP[0] = \ ; + assign S_AXI_GP0_BVALID = \ ; + assign S_AXI_GP0_RDATA[31] = \ ; + assign S_AXI_GP0_RDATA[30] = \ ; + assign S_AXI_GP0_RDATA[29] = \ ; + assign S_AXI_GP0_RDATA[28] = \ ; + assign S_AXI_GP0_RDATA[27] = \ ; + assign S_AXI_GP0_RDATA[26] = \ ; + assign S_AXI_GP0_RDATA[25] = \ ; + assign S_AXI_GP0_RDATA[24] = \ ; + assign S_AXI_GP0_RDATA[23] = \ ; + assign S_AXI_GP0_RDATA[22] = \ ; + assign S_AXI_GP0_RDATA[21] = \ ; + assign S_AXI_GP0_RDATA[20] = \ ; + assign S_AXI_GP0_RDATA[19] = \ ; + assign S_AXI_GP0_RDATA[18] = \ ; + assign S_AXI_GP0_RDATA[17] = \ ; + assign S_AXI_GP0_RDATA[16] = \ ; + assign S_AXI_GP0_RDATA[15] = \ ; + assign S_AXI_GP0_RDATA[14] = \ ; + assign S_AXI_GP0_RDATA[13] = \ ; + assign S_AXI_GP0_RDATA[12] = \ ; + assign S_AXI_GP0_RDATA[11] = \ ; + assign S_AXI_GP0_RDATA[10] = \ ; + assign S_AXI_GP0_RDATA[9] = \ ; + assign S_AXI_GP0_RDATA[8] = \ ; + assign S_AXI_GP0_RDATA[7] = \ ; + assign S_AXI_GP0_RDATA[6] = \ ; + assign S_AXI_GP0_RDATA[5] = \ ; + assign S_AXI_GP0_RDATA[4] = \ ; + assign S_AXI_GP0_RDATA[3] = \ ; + assign S_AXI_GP0_RDATA[2] = \ ; + assign S_AXI_GP0_RDATA[1] = \ ; + assign S_AXI_GP0_RDATA[0] = \ ; + assign S_AXI_GP0_RID[5] = \ ; + assign S_AXI_GP0_RID[4] = \ ; + assign S_AXI_GP0_RID[3] = \ ; + assign S_AXI_GP0_RID[2] = \ ; + assign S_AXI_GP0_RID[1] = \ ; + assign S_AXI_GP0_RID[0] = \ ; + assign S_AXI_GP0_RLAST = \ ; + assign S_AXI_GP0_RRESP[1] = \ ; + assign S_AXI_GP0_RRESP[0] = \ ; + assign S_AXI_GP0_RVALID = \ ; + assign S_AXI_GP0_WREADY = \ ; + assign S_AXI_GP1_ARESETN = \ ; + assign S_AXI_GP1_ARREADY = \ ; + assign S_AXI_GP1_AWREADY = \ ; + assign S_AXI_GP1_BID[5] = \ ; + assign S_AXI_GP1_BID[4] = \ ; + assign S_AXI_GP1_BID[3] = \ ; + assign S_AXI_GP1_BID[2] = \ ; + assign S_AXI_GP1_BID[1] = \ ; + assign S_AXI_GP1_BID[0] = \ ; + assign S_AXI_GP1_BRESP[1] = \ ; + assign S_AXI_GP1_BRESP[0] = \ ; + assign S_AXI_GP1_BVALID = \ ; + assign S_AXI_GP1_RDATA[31] = \ ; + assign S_AXI_GP1_RDATA[30] = \ ; + assign S_AXI_GP1_RDATA[29] = \ ; + assign S_AXI_GP1_RDATA[28] = \ ; + assign S_AXI_GP1_RDATA[27] = \ ; + assign S_AXI_GP1_RDATA[26] = \ ; + assign S_AXI_GP1_RDATA[25] = \ ; + assign S_AXI_GP1_RDATA[24] = \ ; + assign S_AXI_GP1_RDATA[23] = \ ; + assign S_AXI_GP1_RDATA[22] = \ ; + assign S_AXI_GP1_RDATA[21] = \ ; + assign S_AXI_GP1_RDATA[20] = \ ; + assign S_AXI_GP1_RDATA[19] = \ ; + assign S_AXI_GP1_RDATA[18] = \ ; + assign S_AXI_GP1_RDATA[17] = \ ; + assign S_AXI_GP1_RDATA[16] = \ ; + assign S_AXI_GP1_RDATA[15] = \ ; + assign S_AXI_GP1_RDATA[14] = \ ; + assign S_AXI_GP1_RDATA[13] = \ ; + assign S_AXI_GP1_RDATA[12] = \ ; + assign S_AXI_GP1_RDATA[11] = \ ; + assign S_AXI_GP1_RDATA[10] = \ ; + assign S_AXI_GP1_RDATA[9] = \ ; + assign S_AXI_GP1_RDATA[8] = \ ; + assign S_AXI_GP1_RDATA[7] = \ ; + assign S_AXI_GP1_RDATA[6] = \ ; + assign S_AXI_GP1_RDATA[5] = \ ; + assign S_AXI_GP1_RDATA[4] = \ ; + assign S_AXI_GP1_RDATA[3] = \ ; + assign S_AXI_GP1_RDATA[2] = \ ; + assign S_AXI_GP1_RDATA[1] = \ ; + assign S_AXI_GP1_RDATA[0] = \ ; + assign S_AXI_GP1_RID[5] = \ ; + assign S_AXI_GP1_RID[4] = \ ; + assign S_AXI_GP1_RID[3] = \ ; + assign S_AXI_GP1_RID[2] = \ ; + assign S_AXI_GP1_RID[1] = \ ; + assign S_AXI_GP1_RID[0] = \ ; + assign S_AXI_GP1_RLAST = \ ; + assign S_AXI_GP1_RRESP[1] = \ ; + assign S_AXI_GP1_RRESP[0] = \ ; + assign S_AXI_GP1_RVALID = \ ; + assign S_AXI_GP1_WREADY = \ ; + assign S_AXI_HP0_ARESETN = \ ; + assign S_AXI_HP0_ARREADY = \ ; + assign S_AXI_HP0_AWREADY = \ ; + assign S_AXI_HP0_BID[5] = \ ; + assign S_AXI_HP0_BID[4] = \ ; + assign S_AXI_HP0_BID[3] = \ ; + assign S_AXI_HP0_BID[2] = \ ; + assign S_AXI_HP0_BID[1] = \ ; + assign S_AXI_HP0_BID[0] = \ ; + assign S_AXI_HP0_BRESP[1] = \ ; + assign S_AXI_HP0_BRESP[0] = \ ; + assign S_AXI_HP0_BVALID = \ ; + assign S_AXI_HP0_RACOUNT[2] = \ ; + assign S_AXI_HP0_RACOUNT[1] = \ ; + assign S_AXI_HP0_RACOUNT[0] = \ ; + assign S_AXI_HP0_RCOUNT[7] = \ ; + assign S_AXI_HP0_RCOUNT[6] = \ ; + assign S_AXI_HP0_RCOUNT[5] = \ ; + assign S_AXI_HP0_RCOUNT[4] = \ ; + assign S_AXI_HP0_RCOUNT[3] = \ ; + assign S_AXI_HP0_RCOUNT[2] = \ ; + assign S_AXI_HP0_RCOUNT[1] = \ ; + assign S_AXI_HP0_RCOUNT[0] = \ ; + assign S_AXI_HP0_RDATA[63] = \ ; + assign S_AXI_HP0_RDATA[62] = \ ; + assign S_AXI_HP0_RDATA[61] = \ ; + assign S_AXI_HP0_RDATA[60] = \ ; + assign S_AXI_HP0_RDATA[59] = \ ; + assign S_AXI_HP0_RDATA[58] = \ ; + assign S_AXI_HP0_RDATA[57] = \ ; + assign S_AXI_HP0_RDATA[56] = \ ; + assign S_AXI_HP0_RDATA[55] = \ ; + assign S_AXI_HP0_RDATA[54] = \ ; + assign S_AXI_HP0_RDATA[53] = \ ; + assign S_AXI_HP0_RDATA[52] = \ ; + assign S_AXI_HP0_RDATA[51] = \ ; + assign S_AXI_HP0_RDATA[50] = \ ; + assign S_AXI_HP0_RDATA[49] = \ ; + assign S_AXI_HP0_RDATA[48] = \ ; + assign S_AXI_HP0_RDATA[47] = \ ; + assign S_AXI_HP0_RDATA[46] = \ ; + assign S_AXI_HP0_RDATA[45] = \ ; + assign S_AXI_HP0_RDATA[44] = \ ; + assign S_AXI_HP0_RDATA[43] = \ ; + assign S_AXI_HP0_RDATA[42] = \ ; + assign S_AXI_HP0_RDATA[41] = \ ; + assign S_AXI_HP0_RDATA[40] = \ ; + assign S_AXI_HP0_RDATA[39] = \ ; + assign S_AXI_HP0_RDATA[38] = \ ; + assign S_AXI_HP0_RDATA[37] = \ ; + assign S_AXI_HP0_RDATA[36] = \ ; + assign S_AXI_HP0_RDATA[35] = \ ; + assign S_AXI_HP0_RDATA[34] = \ ; + assign S_AXI_HP0_RDATA[33] = \ ; + assign S_AXI_HP0_RDATA[32] = \ ; + assign S_AXI_HP0_RDATA[31] = \ ; + assign S_AXI_HP0_RDATA[30] = \ ; + assign S_AXI_HP0_RDATA[29] = \ ; + assign S_AXI_HP0_RDATA[28] = \ ; + assign S_AXI_HP0_RDATA[27] = \ ; + assign S_AXI_HP0_RDATA[26] = \ ; + assign S_AXI_HP0_RDATA[25] = \ ; + assign S_AXI_HP0_RDATA[24] = \ ; + assign S_AXI_HP0_RDATA[23] = \ ; + assign S_AXI_HP0_RDATA[22] = \ ; + assign S_AXI_HP0_RDATA[21] = \ ; + assign S_AXI_HP0_RDATA[20] = \ ; + assign S_AXI_HP0_RDATA[19] = \ ; + assign S_AXI_HP0_RDATA[18] = \ ; + assign S_AXI_HP0_RDATA[17] = \ ; + assign S_AXI_HP0_RDATA[16] = \ ; + assign S_AXI_HP0_RDATA[15] = \ ; + assign S_AXI_HP0_RDATA[14] = \ ; + assign S_AXI_HP0_RDATA[13] = \ ; + assign S_AXI_HP0_RDATA[12] = \ ; + assign S_AXI_HP0_RDATA[11] = \ ; + assign S_AXI_HP0_RDATA[10] = \ ; + assign S_AXI_HP0_RDATA[9] = \ ; + assign S_AXI_HP0_RDATA[8] = \ ; + assign S_AXI_HP0_RDATA[7] = \ ; + assign S_AXI_HP0_RDATA[6] = \ ; + assign S_AXI_HP0_RDATA[5] = \ ; + assign S_AXI_HP0_RDATA[4] = \ ; + assign S_AXI_HP0_RDATA[3] = \ ; + assign S_AXI_HP0_RDATA[2] = \ ; + assign S_AXI_HP0_RDATA[1] = \ ; + assign S_AXI_HP0_RDATA[0] = \ ; + assign S_AXI_HP0_RID[5] = \ ; + assign S_AXI_HP0_RID[4] = \ ; + assign S_AXI_HP0_RID[3] = \ ; + assign S_AXI_HP0_RID[2] = \ ; + assign S_AXI_HP0_RID[1] = \ ; + assign S_AXI_HP0_RID[0] = \ ; + assign S_AXI_HP0_RLAST = \ ; + assign S_AXI_HP0_RRESP[1] = \ ; + assign S_AXI_HP0_RRESP[0] = \ ; + assign S_AXI_HP0_RVALID = \ ; + assign S_AXI_HP0_WACOUNT[5] = \ ; + assign S_AXI_HP0_WACOUNT[4] = \ ; + assign S_AXI_HP0_WACOUNT[3] = \ ; + assign S_AXI_HP0_WACOUNT[2] = \ ; + assign S_AXI_HP0_WACOUNT[1] = \ ; + assign S_AXI_HP0_WACOUNT[0] = \ ; + assign S_AXI_HP0_WCOUNT[7] = \ ; + assign S_AXI_HP0_WCOUNT[6] = \ ; + assign S_AXI_HP0_WCOUNT[5] = \ ; + assign S_AXI_HP0_WCOUNT[4] = \ ; + assign S_AXI_HP0_WCOUNT[3] = \ ; + assign S_AXI_HP0_WCOUNT[2] = \ ; + assign S_AXI_HP0_WCOUNT[1] = \ ; + assign S_AXI_HP0_WCOUNT[0] = \ ; + assign S_AXI_HP0_WREADY = \ ; + assign S_AXI_HP1_ARESETN = \ ; + assign S_AXI_HP1_ARREADY = \ ; + assign S_AXI_HP1_AWREADY = \ ; + assign S_AXI_HP1_BID[5] = \ ; + assign S_AXI_HP1_BID[4] = \ ; + assign S_AXI_HP1_BID[3] = \ ; + assign S_AXI_HP1_BID[2] = \ ; + assign S_AXI_HP1_BID[1] = \ ; + assign S_AXI_HP1_BID[0] = \ ; + assign S_AXI_HP1_BRESP[1] = \ ; + assign S_AXI_HP1_BRESP[0] = \ ; + assign S_AXI_HP1_BVALID = \ ; + assign S_AXI_HP1_RACOUNT[2] = \ ; + assign S_AXI_HP1_RACOUNT[1] = \ ; + assign S_AXI_HP1_RACOUNT[0] = \ ; + assign S_AXI_HP1_RCOUNT[7] = \ ; + assign S_AXI_HP1_RCOUNT[6] = \ ; + assign S_AXI_HP1_RCOUNT[5] = \ ; + assign S_AXI_HP1_RCOUNT[4] = \ ; + assign S_AXI_HP1_RCOUNT[3] = \ ; + assign S_AXI_HP1_RCOUNT[2] = \ ; + assign S_AXI_HP1_RCOUNT[1] = \ ; + assign S_AXI_HP1_RCOUNT[0] = \ ; + assign S_AXI_HP1_RDATA[63] = \ ; + assign S_AXI_HP1_RDATA[62] = \ ; + assign S_AXI_HP1_RDATA[61] = \ ; + assign S_AXI_HP1_RDATA[60] = \ ; + assign S_AXI_HP1_RDATA[59] = \ ; + assign S_AXI_HP1_RDATA[58] = \ ; + assign S_AXI_HP1_RDATA[57] = \ ; + assign S_AXI_HP1_RDATA[56] = \ ; + assign S_AXI_HP1_RDATA[55] = \ ; + assign S_AXI_HP1_RDATA[54] = \ ; + assign S_AXI_HP1_RDATA[53] = \ ; + assign S_AXI_HP1_RDATA[52] = \ ; + assign S_AXI_HP1_RDATA[51] = \ ; + assign S_AXI_HP1_RDATA[50] = \ ; + assign S_AXI_HP1_RDATA[49] = \ ; + assign S_AXI_HP1_RDATA[48] = \ ; + assign S_AXI_HP1_RDATA[47] = \ ; + assign S_AXI_HP1_RDATA[46] = \ ; + assign S_AXI_HP1_RDATA[45] = \ ; + assign S_AXI_HP1_RDATA[44] = \ ; + assign S_AXI_HP1_RDATA[43] = \ ; + assign S_AXI_HP1_RDATA[42] = \ ; + assign S_AXI_HP1_RDATA[41] = \ ; + assign S_AXI_HP1_RDATA[40] = \ ; + assign S_AXI_HP1_RDATA[39] = \ ; + assign S_AXI_HP1_RDATA[38] = \ ; + assign S_AXI_HP1_RDATA[37] = \ ; + assign S_AXI_HP1_RDATA[36] = \ ; + assign S_AXI_HP1_RDATA[35] = \ ; + assign S_AXI_HP1_RDATA[34] = \ ; + assign S_AXI_HP1_RDATA[33] = \ ; + assign S_AXI_HP1_RDATA[32] = \ ; + assign S_AXI_HP1_RDATA[31] = \ ; + assign S_AXI_HP1_RDATA[30] = \ ; + assign S_AXI_HP1_RDATA[29] = \ ; + assign S_AXI_HP1_RDATA[28] = \ ; + assign S_AXI_HP1_RDATA[27] = \ ; + assign S_AXI_HP1_RDATA[26] = \ ; + assign S_AXI_HP1_RDATA[25] = \ ; + assign S_AXI_HP1_RDATA[24] = \ ; + assign S_AXI_HP1_RDATA[23] = \ ; + assign S_AXI_HP1_RDATA[22] = \ ; + assign S_AXI_HP1_RDATA[21] = \ ; + assign S_AXI_HP1_RDATA[20] = \ ; + assign S_AXI_HP1_RDATA[19] = \ ; + assign S_AXI_HP1_RDATA[18] = \ ; + assign S_AXI_HP1_RDATA[17] = \ ; + assign S_AXI_HP1_RDATA[16] = \ ; + assign S_AXI_HP1_RDATA[15] = \ ; + assign S_AXI_HP1_RDATA[14] = \ ; + assign S_AXI_HP1_RDATA[13] = \ ; + assign S_AXI_HP1_RDATA[12] = \ ; + assign S_AXI_HP1_RDATA[11] = \ ; + assign S_AXI_HP1_RDATA[10] = \ ; + assign S_AXI_HP1_RDATA[9] = \ ; + assign S_AXI_HP1_RDATA[8] = \ ; + assign S_AXI_HP1_RDATA[7] = \ ; + assign S_AXI_HP1_RDATA[6] = \ ; + assign S_AXI_HP1_RDATA[5] = \ ; + assign S_AXI_HP1_RDATA[4] = \ ; + assign S_AXI_HP1_RDATA[3] = \ ; + assign S_AXI_HP1_RDATA[2] = \ ; + assign S_AXI_HP1_RDATA[1] = \ ; + assign S_AXI_HP1_RDATA[0] = \ ; + assign S_AXI_HP1_RID[5] = \ ; + assign S_AXI_HP1_RID[4] = \ ; + assign S_AXI_HP1_RID[3] = \ ; + assign S_AXI_HP1_RID[2] = \ ; + assign S_AXI_HP1_RID[1] = \ ; + assign S_AXI_HP1_RID[0] = \ ; + assign S_AXI_HP1_RLAST = \ ; + assign S_AXI_HP1_RRESP[1] = \ ; + assign S_AXI_HP1_RRESP[0] = \ ; + assign S_AXI_HP1_RVALID = \ ; + assign S_AXI_HP1_WACOUNT[5] = \ ; + assign S_AXI_HP1_WACOUNT[4] = \ ; + assign S_AXI_HP1_WACOUNT[3] = \ ; + assign S_AXI_HP1_WACOUNT[2] = \ ; + assign S_AXI_HP1_WACOUNT[1] = \ ; + assign S_AXI_HP1_WACOUNT[0] = \ ; + assign S_AXI_HP1_WCOUNT[7] = \ ; + assign S_AXI_HP1_WCOUNT[6] = \ ; + assign S_AXI_HP1_WCOUNT[5] = \ ; + assign S_AXI_HP1_WCOUNT[4] = \ ; + assign S_AXI_HP1_WCOUNT[3] = \ ; + assign S_AXI_HP1_WCOUNT[2] = \ ; + assign S_AXI_HP1_WCOUNT[1] = \ ; + assign S_AXI_HP1_WCOUNT[0] = \ ; + assign S_AXI_HP1_WREADY = \ ; + assign S_AXI_HP2_ARESETN = \ ; + assign S_AXI_HP2_ARREADY = \ ; + assign S_AXI_HP2_AWREADY = \ ; + assign S_AXI_HP2_BID[5] = \ ; + assign S_AXI_HP2_BID[4] = \ ; + assign S_AXI_HP2_BID[3] = \ ; + assign S_AXI_HP2_BID[2] = \ ; + assign S_AXI_HP2_BID[1] = \ ; + assign S_AXI_HP2_BID[0] = \ ; + assign S_AXI_HP2_BRESP[1] = \ ; + assign S_AXI_HP2_BRESP[0] = \ ; + assign S_AXI_HP2_BVALID = \ ; + assign S_AXI_HP2_RACOUNT[2] = \ ; + assign S_AXI_HP2_RACOUNT[1] = \ ; + assign S_AXI_HP2_RACOUNT[0] = \ ; + assign S_AXI_HP2_RCOUNT[7] = \ ; + assign S_AXI_HP2_RCOUNT[6] = \ ; + assign S_AXI_HP2_RCOUNT[5] = \ ; + assign S_AXI_HP2_RCOUNT[4] = \ ; + assign S_AXI_HP2_RCOUNT[3] = \ ; + assign S_AXI_HP2_RCOUNT[2] = \ ; + assign S_AXI_HP2_RCOUNT[1] = \ ; + assign S_AXI_HP2_RCOUNT[0] = \ ; + assign S_AXI_HP2_RDATA[63] = \ ; + assign S_AXI_HP2_RDATA[62] = \ ; + assign S_AXI_HP2_RDATA[61] = \ ; + assign S_AXI_HP2_RDATA[60] = \ ; + assign S_AXI_HP2_RDATA[59] = \ ; + assign S_AXI_HP2_RDATA[58] = \ ; + assign S_AXI_HP2_RDATA[57] = \ ; + assign S_AXI_HP2_RDATA[56] = \ ; + assign S_AXI_HP2_RDATA[55] = \ ; + assign S_AXI_HP2_RDATA[54] = \ ; + assign S_AXI_HP2_RDATA[53] = \ ; + assign S_AXI_HP2_RDATA[52] = \ ; + assign S_AXI_HP2_RDATA[51] = \ ; + assign S_AXI_HP2_RDATA[50] = \ ; + assign S_AXI_HP2_RDATA[49] = \ ; + assign S_AXI_HP2_RDATA[48] = \ ; + assign S_AXI_HP2_RDATA[47] = \ ; + assign S_AXI_HP2_RDATA[46] = \ ; + assign S_AXI_HP2_RDATA[45] = \ ; + assign S_AXI_HP2_RDATA[44] = \ ; + assign S_AXI_HP2_RDATA[43] = \ ; + assign S_AXI_HP2_RDATA[42] = \ ; + assign S_AXI_HP2_RDATA[41] = \ ; + assign S_AXI_HP2_RDATA[40] = \ ; + assign S_AXI_HP2_RDATA[39] = \ ; + assign S_AXI_HP2_RDATA[38] = \ ; + assign S_AXI_HP2_RDATA[37] = \ ; + assign S_AXI_HP2_RDATA[36] = \ ; + assign S_AXI_HP2_RDATA[35] = \ ; + assign S_AXI_HP2_RDATA[34] = \ ; + assign S_AXI_HP2_RDATA[33] = \ ; + assign S_AXI_HP2_RDATA[32] = \ ; + assign S_AXI_HP2_RDATA[31] = \ ; + assign S_AXI_HP2_RDATA[30] = \ ; + assign S_AXI_HP2_RDATA[29] = \ ; + assign S_AXI_HP2_RDATA[28] = \ ; + assign S_AXI_HP2_RDATA[27] = \ ; + assign S_AXI_HP2_RDATA[26] = \ ; + assign S_AXI_HP2_RDATA[25] = \ ; + assign S_AXI_HP2_RDATA[24] = \ ; + assign S_AXI_HP2_RDATA[23] = \ ; + assign S_AXI_HP2_RDATA[22] = \ ; + assign S_AXI_HP2_RDATA[21] = \ ; + assign S_AXI_HP2_RDATA[20] = \ ; + assign S_AXI_HP2_RDATA[19] = \ ; + assign S_AXI_HP2_RDATA[18] = \ ; + assign S_AXI_HP2_RDATA[17] = \ ; + assign S_AXI_HP2_RDATA[16] = \ ; + assign S_AXI_HP2_RDATA[15] = \ ; + assign S_AXI_HP2_RDATA[14] = \ ; + assign S_AXI_HP2_RDATA[13] = \ ; + assign S_AXI_HP2_RDATA[12] = \ ; + assign S_AXI_HP2_RDATA[11] = \ ; + assign S_AXI_HP2_RDATA[10] = \ ; + assign S_AXI_HP2_RDATA[9] = \ ; + assign S_AXI_HP2_RDATA[8] = \ ; + assign S_AXI_HP2_RDATA[7] = \ ; + assign S_AXI_HP2_RDATA[6] = \ ; + assign S_AXI_HP2_RDATA[5] = \ ; + assign S_AXI_HP2_RDATA[4] = \ ; + assign S_AXI_HP2_RDATA[3] = \ ; + assign S_AXI_HP2_RDATA[2] = \ ; + assign S_AXI_HP2_RDATA[1] = \ ; + assign S_AXI_HP2_RDATA[0] = \ ; + assign S_AXI_HP2_RID[5] = \ ; + assign S_AXI_HP2_RID[4] = \ ; + assign S_AXI_HP2_RID[3] = \ ; + assign S_AXI_HP2_RID[2] = \ ; + assign S_AXI_HP2_RID[1] = \ ; + assign S_AXI_HP2_RID[0] = \ ; + assign S_AXI_HP2_RLAST = \ ; + assign S_AXI_HP2_RRESP[1] = \ ; + assign S_AXI_HP2_RRESP[0] = \ ; + assign S_AXI_HP2_RVALID = \ ; + assign S_AXI_HP2_WACOUNT[5] = \ ; + assign S_AXI_HP2_WACOUNT[4] = \ ; + assign S_AXI_HP2_WACOUNT[3] = \ ; + assign S_AXI_HP2_WACOUNT[2] = \ ; + assign S_AXI_HP2_WACOUNT[1] = \ ; + assign S_AXI_HP2_WACOUNT[0] = \ ; + assign S_AXI_HP2_WCOUNT[7] = \ ; + assign S_AXI_HP2_WCOUNT[6] = \ ; + assign S_AXI_HP2_WCOUNT[5] = \ ; + assign S_AXI_HP2_WCOUNT[4] = \ ; + assign S_AXI_HP2_WCOUNT[3] = \ ; + assign S_AXI_HP2_WCOUNT[2] = \ ; + assign S_AXI_HP2_WCOUNT[1] = \ ; + assign S_AXI_HP2_WCOUNT[0] = \ ; + assign S_AXI_HP2_WREADY = \ ; + assign S_AXI_HP3_ARESETN = \ ; + assign S_AXI_HP3_ARREADY = \ ; + assign S_AXI_HP3_AWREADY = \ ; + assign S_AXI_HP3_BID[5] = \ ; + assign S_AXI_HP3_BID[4] = \ ; + assign S_AXI_HP3_BID[3] = \ ; + assign S_AXI_HP3_BID[2] = \ ; + assign S_AXI_HP3_BID[1] = \ ; + assign S_AXI_HP3_BID[0] = \ ; + assign S_AXI_HP3_BRESP[1] = \ ; + assign S_AXI_HP3_BRESP[0] = \ ; + assign S_AXI_HP3_BVALID = \ ; + assign S_AXI_HP3_RACOUNT[2] = \ ; + assign S_AXI_HP3_RACOUNT[1] = \ ; + assign S_AXI_HP3_RACOUNT[0] = \ ; + assign S_AXI_HP3_RCOUNT[7] = \ ; + assign S_AXI_HP3_RCOUNT[6] = \ ; + assign S_AXI_HP3_RCOUNT[5] = \ ; + assign S_AXI_HP3_RCOUNT[4] = \ ; + assign S_AXI_HP3_RCOUNT[3] = \ ; + assign S_AXI_HP3_RCOUNT[2] = \ ; + assign S_AXI_HP3_RCOUNT[1] = \ ; + assign S_AXI_HP3_RCOUNT[0] = \ ; + assign S_AXI_HP3_RDATA[63] = \ ; + assign S_AXI_HP3_RDATA[62] = \ ; + assign S_AXI_HP3_RDATA[61] = \ ; + assign S_AXI_HP3_RDATA[60] = \ ; + assign S_AXI_HP3_RDATA[59] = \ ; + assign S_AXI_HP3_RDATA[58] = \ ; + assign S_AXI_HP3_RDATA[57] = \ ; + assign S_AXI_HP3_RDATA[56] = \ ; + assign S_AXI_HP3_RDATA[55] = \ ; + assign S_AXI_HP3_RDATA[54] = \ ; + assign S_AXI_HP3_RDATA[53] = \ ; + assign S_AXI_HP3_RDATA[52] = \ ; + assign S_AXI_HP3_RDATA[51] = \ ; + assign S_AXI_HP3_RDATA[50] = \ ; + assign S_AXI_HP3_RDATA[49] = \ ; + assign S_AXI_HP3_RDATA[48] = \ ; + assign S_AXI_HP3_RDATA[47] = \ ; + assign S_AXI_HP3_RDATA[46] = \ ; + assign S_AXI_HP3_RDATA[45] = \ ; + assign S_AXI_HP3_RDATA[44] = \ ; + assign S_AXI_HP3_RDATA[43] = \ ; + assign S_AXI_HP3_RDATA[42] = \ ; + assign S_AXI_HP3_RDATA[41] = \ ; + assign S_AXI_HP3_RDATA[40] = \ ; + assign S_AXI_HP3_RDATA[39] = \ ; + assign S_AXI_HP3_RDATA[38] = \ ; + assign S_AXI_HP3_RDATA[37] = \ ; + assign S_AXI_HP3_RDATA[36] = \ ; + assign S_AXI_HP3_RDATA[35] = \ ; + assign S_AXI_HP3_RDATA[34] = \ ; + assign S_AXI_HP3_RDATA[33] = \ ; + assign S_AXI_HP3_RDATA[32] = \ ; + assign S_AXI_HP3_RDATA[31] = \ ; + assign S_AXI_HP3_RDATA[30] = \ ; + assign S_AXI_HP3_RDATA[29] = \ ; + assign S_AXI_HP3_RDATA[28] = \ ; + assign S_AXI_HP3_RDATA[27] = \ ; + assign S_AXI_HP3_RDATA[26] = \ ; + assign S_AXI_HP3_RDATA[25] = \ ; + assign S_AXI_HP3_RDATA[24] = \ ; + assign S_AXI_HP3_RDATA[23] = \ ; + assign S_AXI_HP3_RDATA[22] = \ ; + assign S_AXI_HP3_RDATA[21] = \ ; + assign S_AXI_HP3_RDATA[20] = \ ; + assign S_AXI_HP3_RDATA[19] = \ ; + assign S_AXI_HP3_RDATA[18] = \ ; + assign S_AXI_HP3_RDATA[17] = \ ; + assign S_AXI_HP3_RDATA[16] = \ ; + assign S_AXI_HP3_RDATA[15] = \ ; + assign S_AXI_HP3_RDATA[14] = \ ; + assign S_AXI_HP3_RDATA[13] = \ ; + assign S_AXI_HP3_RDATA[12] = \ ; + assign S_AXI_HP3_RDATA[11] = \ ; + assign S_AXI_HP3_RDATA[10] = \ ; + assign S_AXI_HP3_RDATA[9] = \ ; + assign S_AXI_HP3_RDATA[8] = \ ; + assign S_AXI_HP3_RDATA[7] = \ ; + assign S_AXI_HP3_RDATA[6] = \ ; + assign S_AXI_HP3_RDATA[5] = \ ; + assign S_AXI_HP3_RDATA[4] = \ ; + assign S_AXI_HP3_RDATA[3] = \ ; + assign S_AXI_HP3_RDATA[2] = \ ; + assign S_AXI_HP3_RDATA[1] = \ ; + assign S_AXI_HP3_RDATA[0] = \ ; + assign S_AXI_HP3_RID[5] = \ ; + assign S_AXI_HP3_RID[4] = \ ; + assign S_AXI_HP3_RID[3] = \ ; + assign S_AXI_HP3_RID[2] = \ ; + assign S_AXI_HP3_RID[1] = \ ; + assign S_AXI_HP3_RID[0] = \ ; + assign S_AXI_HP3_RLAST = \ ; + assign S_AXI_HP3_RRESP[1] = \ ; + assign S_AXI_HP3_RRESP[0] = \ ; + assign S_AXI_HP3_RVALID = \ ; + assign S_AXI_HP3_WACOUNT[5] = \ ; + assign S_AXI_HP3_WACOUNT[4] = \ ; + assign S_AXI_HP3_WACOUNT[3] = \ ; + assign S_AXI_HP3_WACOUNT[2] = \ ; + assign S_AXI_HP3_WACOUNT[1] = \ ; + assign S_AXI_HP3_WACOUNT[0] = \ ; + assign S_AXI_HP3_WCOUNT[7] = \ ; + assign S_AXI_HP3_WCOUNT[6] = \ ; + assign S_AXI_HP3_WCOUNT[5] = \ ; + assign S_AXI_HP3_WCOUNT[4] = \ ; + assign S_AXI_HP3_WCOUNT[3] = \ ; + assign S_AXI_HP3_WCOUNT[2] = \ ; + assign S_AXI_HP3_WCOUNT[1] = \ ; + assign S_AXI_HP3_WCOUNT[0] = \ ; + assign S_AXI_HP3_WREADY = \ ; + assign TRACE_CLK_OUT = \ ; + assign TRACE_CTL = \TRACE_CTL_PIPE[0] ; + assign TRACE_DATA[1:0] = \TRACE_DATA_PIPE[0] ; + assign TTC0_WAVE0_OUT = \ ; + assign TTC0_WAVE1_OUT = \ ; + assign TTC0_WAVE2_OUT = \ ; + assign TTC1_WAVE0_OUT = \ ; + assign TTC1_WAVE1_OUT = \ ; + assign TTC1_WAVE2_OUT = \ ; + assign UART0_DTRN = \ ; + assign UART0_RTSN = \ ; + assign UART0_TX = \ ; + assign UART1_DTRN = \ ; + assign UART1_RTSN = \ ; + assign UART1_TX = \ ; + assign USB0_PORT_INDCTL[1] = \ ; + assign USB0_PORT_INDCTL[0] = \ ; + assign USB0_VBUS_PWRSELECT = \ ; + assign USB1_PORT_INDCTL[1] = \ ; + assign USB1_PORT_INDCTL[0] = \ ; + assign USB1_VBUS_PWRSELECT = \ ; + assign WDT_RST_OUT = \ ; + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_CAS_n_BIBUF + (.IO(buffered_DDR_CAS_n), + .PAD(DDR_CAS_n)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_CKE_BIBUF + (.IO(buffered_DDR_CKE), + .PAD(DDR_CKE)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_CS_n_BIBUF + (.IO(buffered_DDR_CS_n), + .PAD(DDR_CS_n)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_Clk_BIBUF + (.IO(buffered_DDR_Clk), + .PAD(DDR_Clk)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_Clk_n_BIBUF + (.IO(buffered_DDR_Clk_n), + .PAD(DDR_Clk_n)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_DRSTB_BIBUF + (.IO(buffered_DDR_DRSTB), + .PAD(DDR_DRSTB)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_ODT_BIBUF + (.IO(buffered_DDR_ODT), + .PAD(DDR_ODT)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_RAS_n_BIBUF + (.IO(buffered_DDR_RAS_n), + .PAD(DDR_RAS_n)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_VRN_BIBUF + (.IO(buffered_DDR_VRN), + .PAD(DDR_VRN)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_VRP_BIBUF + (.IO(buffered_DDR_VRP), + .PAD(DDR_VRP)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_WEB_BIBUF + (.IO(buffered_DDR_WEB), + .PAD(DDR_WEB)); + GND GND + (.G(\ )); + (* BOX_TYPE = "PRIMITIVE" *) + PS7 PS7_i + (.DDRA(buffered_DDR_Addr), + .DDRARB({1'b0,1'b0,1'b0,1'b0}), + .DDRBA(buffered_DDR_BankAddr), + .DDRCASB(buffered_DDR_CAS_n), + .DDRCKE(buffered_DDR_CKE), + .DDRCKN(buffered_DDR_Clk_n), + .DDRCKP(buffered_DDR_Clk), + .DDRCSB(buffered_DDR_CS_n), + .DDRDM(buffered_DDR_DM), + .DDRDQ(buffered_DDR_DQ), + .DDRDQSN(buffered_DDR_DQS_n), + .DDRDQSP(buffered_DDR_DQS), + .DDRDRSTB(buffered_DDR_DRSTB), + .DDRODT(buffered_DDR_ODT), + .DDRRASB(buffered_DDR_RAS_n), + .DDRVRN(buffered_DDR_VRN), + .DDRVRP(buffered_DDR_VRP), + .DDRWEB(buffered_DDR_WEB), + .DMA0ACLK(1'b0), + .DMA0DAREADY(1'b0), + .DMA0DATYPE({PS7_i_n_224,PS7_i_n_225}), + .DMA0DAVALID(PS7_i_n_0), + .DMA0DRLAST(1'b0), + .DMA0DRREADY(PS7_i_n_1), + .DMA0DRTYPE({1'b0,1'b0}), + .DMA0DRVALID(1'b0), + .DMA0RSTN(PS7_i_n_2), + .DMA1ACLK(1'b0), + .DMA1DAREADY(1'b0), + .DMA1DATYPE({PS7_i_n_226,PS7_i_n_227}), + .DMA1DAVALID(PS7_i_n_3), + .DMA1DRLAST(1'b0), + .DMA1DRREADY(PS7_i_n_4), + .DMA1DRTYPE({1'b0,1'b0}), + .DMA1DRVALID(1'b0), + .DMA1RSTN(PS7_i_n_5), + .DMA2ACLK(1'b0), + .DMA2DAREADY(1'b0), + .DMA2DATYPE({PS7_i_n_228,PS7_i_n_229}), + .DMA2DAVALID(PS7_i_n_6), + .DMA2DRLAST(1'b0), + .DMA2DRREADY(PS7_i_n_7), + .DMA2DRTYPE({1'b0,1'b0}), + .DMA2DRVALID(1'b0), + .DMA2RSTN(PS7_i_n_8), + .DMA3ACLK(1'b0), + .DMA3DAREADY(1'b0), + .DMA3DATYPE({PS7_i_n_230,PS7_i_n_231}), + .DMA3DAVALID(PS7_i_n_9), + .DMA3DRLAST(1'b0), + .DMA3DRREADY(PS7_i_n_10), + .DMA3DRTYPE({1'b0,1'b0}), + .DMA3DRVALID(1'b0), + .DMA3RSTN(PS7_i_n_11), + .EMIOCAN0PHYRX(1'b0), + .EMIOCAN0PHYTX(PS7_i_n_12), + .EMIOCAN1PHYRX(1'b0), + .EMIOCAN1PHYTX(PS7_i_n_13), + .EMIOENET0EXTINTIN(1'b0), + .EMIOENET0GMIICOL(1'b0), + .EMIOENET0GMIICRS(1'b0), + .EMIOENET0GMIIRXCLK(1'b0), + .EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .EMIOENET0GMIIRXDV(1'b0), + .EMIOENET0GMIIRXER(1'b0), + .EMIOENET0GMIITXCLK(1'b0), + .EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]), + .EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED), + .EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED), + .EMIOENET0MDIOI(1'b0), + .EMIOENET0MDIOMDC(PS7_i_n_16), + .EMIOENET0MDIOO(PS7_i_n_17), + .EMIOENET0MDIOTN(ENET0_MDIO_T_n), + .EMIOENET0PTPDELAYREQRX(PS7_i_n_19), + .EMIOENET0PTPDELAYREQTX(PS7_i_n_20), + .EMIOENET0PTPPDELAYREQRX(PS7_i_n_21), + .EMIOENET0PTPPDELAYREQTX(PS7_i_n_22), + .EMIOENET0PTPPDELAYRESPRX(PS7_i_n_23), + .EMIOENET0PTPPDELAYRESPTX(PS7_i_n_24), + .EMIOENET0PTPSYNCFRAMERX(PS7_i_n_25), + .EMIOENET0PTPSYNCFRAMETX(PS7_i_n_26), + .EMIOENET0SOFRX(PS7_i_n_27), + .EMIOENET0SOFTX(PS7_i_n_28), + .EMIOENET1EXTINTIN(1'b0), + .EMIOENET1GMIICOL(1'b0), + .EMIOENET1GMIICRS(1'b0), + .EMIOENET1GMIIRXCLK(1'b0), + .EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .EMIOENET1GMIIRXDV(1'b0), + .EMIOENET1GMIIRXER(1'b0), + .EMIOENET1GMIITXCLK(1'b0), + .EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]), + .EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED), + .EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED), + .EMIOENET1MDIOI(1'b0), + .EMIOENET1MDIOMDC(PS7_i_n_31), + .EMIOENET1MDIOO(PS7_i_n_32), + .EMIOENET1MDIOTN(ENET1_MDIO_T_n), + .EMIOENET1PTPDELAYREQRX(PS7_i_n_34), + .EMIOENET1PTPDELAYREQTX(PS7_i_n_35), + .EMIOENET1PTPPDELAYREQRX(PS7_i_n_36), + .EMIOENET1PTPPDELAYREQTX(PS7_i_n_37), + .EMIOENET1PTPPDELAYRESPRX(PS7_i_n_38), + .EMIOENET1PTPPDELAYRESPTX(PS7_i_n_39), + .EMIOENET1PTPSYNCFRAMERX(PS7_i_n_40), + .EMIOENET1PTPSYNCFRAMETX(PS7_i_n_41), + .EMIOENET1SOFRX(PS7_i_n_42), + .EMIOENET1SOFTX(PS7_i_n_43), + .EMIOGPIOI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .EMIOGPIOO({PS7_i_n_873,PS7_i_n_874,PS7_i_n_875,PS7_i_n_876,PS7_i_n_877,PS7_i_n_878,PS7_i_n_879,PS7_i_n_880,PS7_i_n_881,PS7_i_n_882,PS7_i_n_883,PS7_i_n_884,PS7_i_n_885,PS7_i_n_886,PS7_i_n_887,PS7_i_n_888,PS7_i_n_889,PS7_i_n_890,PS7_i_n_891,PS7_i_n_892,PS7_i_n_893,PS7_i_n_894,PS7_i_n_895,PS7_i_n_896,PS7_i_n_897,PS7_i_n_898,PS7_i_n_899,PS7_i_n_900,PS7_i_n_901,PS7_i_n_902,PS7_i_n_903,PS7_i_n_904,PS7_i_n_905,PS7_i_n_906,PS7_i_n_907,PS7_i_n_908,PS7_i_n_909,PS7_i_n_910,PS7_i_n_911,PS7_i_n_912,PS7_i_n_913,PS7_i_n_914,PS7_i_n_915,PS7_i_n_916,PS7_i_n_917,PS7_i_n_918,PS7_i_n_919,PS7_i_n_920,PS7_i_n_921,PS7_i_n_922,PS7_i_n_923,PS7_i_n_924,PS7_i_n_925,PS7_i_n_926,PS7_i_n_927,PS7_i_n_928,PS7_i_n_929,PS7_i_n_930,PS7_i_n_931,PS7_i_n_932,PS7_i_n_933,PS7_i_n_934,PS7_i_n_935,PS7_i_n_936}), + .EMIOGPIOTN(gpio_out_t_n), + .EMIOI2C0SCLI(1'b0), + .EMIOI2C0SCLO(PS7_i_n_44), + .EMIOI2C0SCLTN(I2C0_SCL_T_n), + .EMIOI2C0SDAI(1'b0), + .EMIOI2C0SDAO(PS7_i_n_46), + .EMIOI2C0SDATN(I2C0_SDA_T_n), + .EMIOI2C1SCLI(1'b0), + .EMIOI2C1SCLO(PS7_i_n_48), + .EMIOI2C1SCLTN(I2C1_SCL_T_n), + .EMIOI2C1SDAI(1'b0), + .EMIOI2C1SDAO(PS7_i_n_50), + .EMIOI2C1SDATN(I2C1_SDA_T_n), + .EMIOPJTAGTCK(1'b0), + .EMIOPJTAGTDI(1'b0), + .EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED), + .EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED), + .EMIOPJTAGTMS(1'b0), + .EMIOSDIO0BUSPOW(PS7_i_n_54), + .EMIOSDIO0BUSVOLT({PS7_i_n_321,PS7_i_n_322,PS7_i_n_323}), + .EMIOSDIO0CDN(1'b0), + .EMIOSDIO0CLK(PS7_i_n_55), + .EMIOSDIO0CLKFB(1'b0), + .EMIOSDIO0CMDI(1'b0), + .EMIOSDIO0CMDO(PS7_i_n_56), + .EMIOSDIO0CMDTN(SDIO0_CMD_T_n), + .EMIOSDIO0DATAI({1'b0,1'b0,1'b0,1'b0}), + .EMIOSDIO0DATAO({PS7_i_n_689,PS7_i_n_690,PS7_i_n_691,PS7_i_n_692}), + .EMIOSDIO0DATATN(SDIO0_DATA_T_n), + .EMIOSDIO0LED(PS7_i_n_58), + .EMIOSDIO0WP(1'b0), + .EMIOSDIO1BUSPOW(PS7_i_n_59), + .EMIOSDIO1BUSVOLT({PS7_i_n_324,PS7_i_n_325,PS7_i_n_326}), + .EMIOSDIO1CDN(1'b0), + .EMIOSDIO1CLK(PS7_i_n_60), + .EMIOSDIO1CLKFB(1'b0), + .EMIOSDIO1CMDI(1'b0), + .EMIOSDIO1CMDO(PS7_i_n_61), + .EMIOSDIO1CMDTN(SDIO1_CMD_T_n), + .EMIOSDIO1DATAI({1'b0,1'b0,1'b0,1'b0}), + .EMIOSDIO1DATAO({PS7_i_n_697,PS7_i_n_698,PS7_i_n_699,PS7_i_n_700}), + .EMIOSDIO1DATATN(SDIO1_DATA_T_n), + .EMIOSDIO1LED(PS7_i_n_63), + .EMIOSDIO1WP(1'b0), + .EMIOSPI0MI(1'b0), + .EMIOSPI0MO(PS7_i_n_64), + .EMIOSPI0MOTN(SPI0_MOSI_T_n), + .EMIOSPI0SCLKI(1'b0), + .EMIOSPI0SCLKO(PS7_i_n_66), + .EMIOSPI0SCLKTN(SPI0_SCLK_T_n), + .EMIOSPI0SI(1'b0), + .EMIOSPI0SO(PS7_i_n_68), + .EMIOSPI0SSIN(1'b0), + .EMIOSPI0SSNTN(SPI0_SS_T_n), + .EMIOSPI0SSON({PS7_i_n_327,PS7_i_n_328,PS7_i_n_329}), + .EMIOSPI0STN(SPI0_MISO_T_n), + .EMIOSPI1MI(1'b0), + .EMIOSPI1MO(PS7_i_n_71), + .EMIOSPI1MOTN(SPI1_MOSI_T_n), + .EMIOSPI1SCLKI(1'b0), + .EMIOSPI1SCLKO(PS7_i_n_73), + .EMIOSPI1SCLKTN(SPI1_SCLK_T_n), + .EMIOSPI1SI(1'b0), + .EMIOSPI1SO(PS7_i_n_75), + .EMIOSPI1SSIN(1'b0), + .EMIOSPI1SSNTN(SPI1_SS_T_n), + .EMIOSPI1SSON({PS7_i_n_330,PS7_i_n_331,PS7_i_n_332}), + .EMIOSPI1STN(SPI1_MISO_T_n), + .EMIOSRAMINTIN(1'b0), + .EMIOTRACECLK(1'b0), + .EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED), + .EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]), + .EMIOTTC0CLKI({1'b0,1'b0,1'b0}), + .EMIOTTC0WAVEO({PS7_i_n_333,PS7_i_n_334,PS7_i_n_335}), + .EMIOTTC1CLKI({1'b0,1'b0,1'b0}), + .EMIOTTC1WAVEO({PS7_i_n_336,PS7_i_n_337,PS7_i_n_338}), + .EMIOUART0CTSN(1'b0), + .EMIOUART0DCDN(1'b0), + .EMIOUART0DSRN(1'b0), + .EMIOUART0DTRN(PS7_i_n_79), + .EMIOUART0RIN(1'b0), + .EMIOUART0RTSN(PS7_i_n_80), + .EMIOUART0RX(1'b1), + .EMIOUART0TX(PS7_i_n_81), + .EMIOUART1CTSN(1'b0), + .EMIOUART1DCDN(1'b0), + .EMIOUART1DSRN(1'b0), + .EMIOUART1DTRN(PS7_i_n_82), + .EMIOUART1RIN(1'b0), + .EMIOUART1RTSN(PS7_i_n_83), + .EMIOUART1RX(1'b1), + .EMIOUART1TX(PS7_i_n_84), + .EMIOUSB0PORTINDCTL({PS7_i_n_232,PS7_i_n_233}), + .EMIOUSB0VBUSPWRFAULT(1'b0), + .EMIOUSB0VBUSPWRSELECT(PS7_i_n_85), + .EMIOUSB1PORTINDCTL({PS7_i_n_234,PS7_i_n_235}), + .EMIOUSB1VBUSPWRFAULT(1'b0), + .EMIOUSB1VBUSPWRSELECT(PS7_i_n_86), + .EMIOWDTCLKI(1'b0), + .EMIOWDTRSTO(PS7_i_n_87), + .EVENTEVENTI(1'b0), + .EVENTEVENTO(PS7_i_n_88), + .EVENTSTANDBYWFE({PS7_i_n_236,PS7_i_n_237}), + .EVENTSTANDBYWFI({PS7_i_n_238,PS7_i_n_239}), + .FCLKCLK(FCLK_CLK_unbuffered), + .FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}), + .FCLKRESETN({PS7_i_n_709,PS7_i_n_710,PS7_i_n_711,FCLK_RESET0_N}), + .FPGAIDLEN(1'b0), + .FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}), + .FTMDTRACEINCLOCK(1'b0), + .FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .FTMDTRACEINVALID(1'b0), + .FTMTF2PDEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .FTMTF2PTRIG({1'b0,1'b0,1'b0,1'b0}), + .FTMTF2PTRIGACK({PS7_i_n_713,PS7_i_n_714,PS7_i_n_715,PS7_i_n_716}), + .FTMTP2FDEBUG({PS7_i_n_401,PS7_i_n_402,PS7_i_n_403,PS7_i_n_404,PS7_i_n_405,PS7_i_n_406,PS7_i_n_407,PS7_i_n_408,PS7_i_n_409,PS7_i_n_410,PS7_i_n_411,PS7_i_n_412,PS7_i_n_413,PS7_i_n_414,PS7_i_n_415,PS7_i_n_416,PS7_i_n_417,PS7_i_n_418,PS7_i_n_419,PS7_i_n_420,PS7_i_n_421,PS7_i_n_422,PS7_i_n_423,PS7_i_n_424,PS7_i_n_425,PS7_i_n_426,PS7_i_n_427,PS7_i_n_428,PS7_i_n_429,PS7_i_n_430,PS7_i_n_431,PS7_i_n_432}), + .FTMTP2FTRIG({PS7_i_n_717,PS7_i_n_718,PS7_i_n_719,PS7_i_n_720}), + .FTMTP2FTRIGACK({1'b0,1'b0,1'b0,1'b0}), + .IRQF2P({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .IRQP2F({PS7_i_n_292,PS7_i_n_293,PS7_i_n_294,PS7_i_n_295,PS7_i_n_296,PS7_i_n_297,PS7_i_n_298,PS7_i_n_299,PS7_i_n_300,PS7_i_n_301,PS7_i_n_302,PS7_i_n_303,PS7_i_n_304,PS7_i_n_305,PS7_i_n_306,PS7_i_n_307,PS7_i_n_308,PS7_i_n_309,PS7_i_n_310,PS7_i_n_311,PS7_i_n_312,PS7_i_n_313,PS7_i_n_314,PS7_i_n_315,PS7_i_n_316,PS7_i_n_317,PS7_i_n_318,PS7_i_n_319,PS7_i_n_320}), + .MAXIGP0ACLK(M_AXI_GP0_ACLK), + .MAXIGP0ARADDR(M_AXI_GP0_ARADDR), + .MAXIGP0ARBURST(M_AXI_GP0_ARBURST), + .MAXIGP0ARCACHE(\^M_AXI_GP0_ARCACHE ), + .MAXIGP0ARESETN(PS7_i_n_89), + .MAXIGP0ARID(M_AXI_GP0_ARID), + .MAXIGP0ARLEN(M_AXI_GP0_ARLEN), + .MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK), + .MAXIGP0ARPROT(M_AXI_GP0_ARPROT), + .MAXIGP0ARQOS(M_AXI_GP0_ARQOS), + .MAXIGP0ARREADY(M_AXI_GP0_ARREADY), + .MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ), + .MAXIGP0ARVALID(M_AXI_GP0_ARVALID), + .MAXIGP0AWADDR(M_AXI_GP0_AWADDR), + .MAXIGP0AWBURST(M_AXI_GP0_AWBURST), + .MAXIGP0AWCACHE(\^M_AXI_GP0_AWCACHE ), + .MAXIGP0AWID(M_AXI_GP0_AWID), + .MAXIGP0AWLEN(M_AXI_GP0_AWLEN), + .MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK), + .MAXIGP0AWPROT(M_AXI_GP0_AWPROT), + .MAXIGP0AWQOS(M_AXI_GP0_AWQOS), + .MAXIGP0AWREADY(M_AXI_GP0_AWREADY), + .MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ), + .MAXIGP0AWVALID(M_AXI_GP0_AWVALID), + .MAXIGP0BID(M_AXI_GP0_BID), + .MAXIGP0BREADY(M_AXI_GP0_BREADY), + .MAXIGP0BRESP(M_AXI_GP0_BRESP), + .MAXIGP0BVALID(M_AXI_GP0_BVALID), + .MAXIGP0RDATA(M_AXI_GP0_RDATA), + .MAXIGP0RID(M_AXI_GP0_RID), + .MAXIGP0RLAST(M_AXI_GP0_RLAST), + .MAXIGP0RREADY(M_AXI_GP0_RREADY), + .MAXIGP0RRESP(M_AXI_GP0_RRESP), + .MAXIGP0RVALID(M_AXI_GP0_RVALID), + .MAXIGP0WDATA(M_AXI_GP0_WDATA), + .MAXIGP0WID(M_AXI_GP0_WID), + .MAXIGP0WLAST(M_AXI_GP0_WLAST), + .MAXIGP0WREADY(M_AXI_GP0_WREADY), + .MAXIGP0WSTRB(M_AXI_GP0_WSTRB), + .MAXIGP0WVALID(M_AXI_GP0_WVALID), + .MAXIGP1ACLK(1'b0), + .MAXIGP1ARADDR({PS7_i_n_529,PS7_i_n_530,PS7_i_n_531,PS7_i_n_532,PS7_i_n_533,PS7_i_n_534,PS7_i_n_535,PS7_i_n_536,PS7_i_n_537,PS7_i_n_538,PS7_i_n_539,PS7_i_n_540,PS7_i_n_541,PS7_i_n_542,PS7_i_n_543,PS7_i_n_544,PS7_i_n_545,PS7_i_n_546,PS7_i_n_547,PS7_i_n_548,PS7_i_n_549,PS7_i_n_550,PS7_i_n_551,PS7_i_n_552,PS7_i_n_553,PS7_i_n_554,PS7_i_n_555,PS7_i_n_556,PS7_i_n_557,PS7_i_n_558,PS7_i_n_559,PS7_i_n_560}), + .MAXIGP1ARBURST({PS7_i_n_252,PS7_i_n_253}), + .MAXIGP1ARCACHE({PS7_i_n_749,PS7_i_n_750,NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED[1],PS7_i_n_752}), + .MAXIGP1ARESETN(PS7_i_n_96), + .MAXIGP1ARID({PS7_i_n_188,PS7_i_n_189,PS7_i_n_190,PS7_i_n_191,PS7_i_n_192,PS7_i_n_193,PS7_i_n_194,PS7_i_n_195,PS7_i_n_196,PS7_i_n_197,PS7_i_n_198,PS7_i_n_199}), + .MAXIGP1ARLEN({PS7_i_n_753,PS7_i_n_754,PS7_i_n_755,PS7_i_n_756}), + .MAXIGP1ARLOCK({PS7_i_n_254,PS7_i_n_255}), + .MAXIGP1ARPROT({PS7_i_n_345,PS7_i_n_346,PS7_i_n_347}), + .MAXIGP1ARQOS({PS7_i_n_757,PS7_i_n_758,PS7_i_n_759,PS7_i_n_760}), + .MAXIGP1ARREADY(1'b0), + .MAXIGP1ARSIZE({PS7_i_n_256,PS7_i_n_257}), + .MAXIGP1ARVALID(PS7_i_n_97), + .MAXIGP1AWADDR({PS7_i_n_561,PS7_i_n_562,PS7_i_n_563,PS7_i_n_564,PS7_i_n_565,PS7_i_n_566,PS7_i_n_567,PS7_i_n_568,PS7_i_n_569,PS7_i_n_570,PS7_i_n_571,PS7_i_n_572,PS7_i_n_573,PS7_i_n_574,PS7_i_n_575,PS7_i_n_576,PS7_i_n_577,PS7_i_n_578,PS7_i_n_579,PS7_i_n_580,PS7_i_n_581,PS7_i_n_582,PS7_i_n_583,PS7_i_n_584,PS7_i_n_585,PS7_i_n_586,PS7_i_n_587,PS7_i_n_588,PS7_i_n_589,PS7_i_n_590,PS7_i_n_591,PS7_i_n_592}), + .MAXIGP1AWBURST({PS7_i_n_258,PS7_i_n_259}), + .MAXIGP1AWCACHE({PS7_i_n_761,PS7_i_n_762,NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED[1],PS7_i_n_764}), + .MAXIGP1AWID({PS7_i_n_200,PS7_i_n_201,PS7_i_n_202,PS7_i_n_203,PS7_i_n_204,PS7_i_n_205,PS7_i_n_206,PS7_i_n_207,PS7_i_n_208,PS7_i_n_209,PS7_i_n_210,PS7_i_n_211}), + .MAXIGP1AWLEN({PS7_i_n_765,PS7_i_n_766,PS7_i_n_767,PS7_i_n_768}), + .MAXIGP1AWLOCK({PS7_i_n_260,PS7_i_n_261}), + .MAXIGP1AWPROT({PS7_i_n_348,PS7_i_n_349,PS7_i_n_350}), + .MAXIGP1AWQOS({PS7_i_n_769,PS7_i_n_770,PS7_i_n_771,PS7_i_n_772}), + .MAXIGP1AWREADY(1'b0), + .MAXIGP1AWSIZE({PS7_i_n_262,PS7_i_n_263}), + .MAXIGP1AWVALID(PS7_i_n_98), + .MAXIGP1BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .MAXIGP1BREADY(PS7_i_n_99), + .MAXIGP1BRESP({1'b0,1'b0}), + .MAXIGP1BVALID(1'b0), + .MAXIGP1RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .MAXIGP1RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .MAXIGP1RLAST(1'b0), + .MAXIGP1RREADY(PS7_i_n_100), + .MAXIGP1RRESP({1'b0,1'b0}), + .MAXIGP1RVALID(1'b0), + .MAXIGP1WDATA({PS7_i_n_593,PS7_i_n_594,PS7_i_n_595,PS7_i_n_596,PS7_i_n_597,PS7_i_n_598,PS7_i_n_599,PS7_i_n_600,PS7_i_n_601,PS7_i_n_602,PS7_i_n_603,PS7_i_n_604,PS7_i_n_605,PS7_i_n_606,PS7_i_n_607,PS7_i_n_608,PS7_i_n_609,PS7_i_n_610,PS7_i_n_611,PS7_i_n_612,PS7_i_n_613,PS7_i_n_614,PS7_i_n_615,PS7_i_n_616,PS7_i_n_617,PS7_i_n_618,PS7_i_n_619,PS7_i_n_620,PS7_i_n_621,PS7_i_n_622,PS7_i_n_623,PS7_i_n_624}), + .MAXIGP1WID({PS7_i_n_212,PS7_i_n_213,PS7_i_n_214,PS7_i_n_215,PS7_i_n_216,PS7_i_n_217,PS7_i_n_218,PS7_i_n_219,PS7_i_n_220,PS7_i_n_221,PS7_i_n_222,PS7_i_n_223}), + .MAXIGP1WLAST(PS7_i_n_101), + .MAXIGP1WREADY(1'b0), + .MAXIGP1WSTRB({PS7_i_n_773,PS7_i_n_774,PS7_i_n_775,PS7_i_n_776}), + .MAXIGP1WVALID(PS7_i_n_102), + .MIO(buffered_MIO), + .PSCLK(buffered_PS_CLK), + .PSPORB(buffered_PS_PORB), + .PSSRSTB(buffered_PS_SRSTB), + .SAXIACPACLK(1'b0), + .SAXIACPARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIACPARBURST({1'b0,1'b0}), + .SAXIACPARCACHE({1'b0,1'b0,1'b0,1'b0}), + .SAXIACPARESETN(PS7_i_n_103), + .SAXIACPARID({1'b0,1'b0,1'b0}), + .SAXIACPARLEN({1'b0,1'b0,1'b0,1'b0}), + .SAXIACPARLOCK({1'b0,1'b0}), + .SAXIACPARPROT({1'b0,1'b0,1'b0}), + .SAXIACPARQOS({1'b0,1'b0,1'b0,1'b0}), + .SAXIACPARREADY(PS7_i_n_104), + .SAXIACPARSIZE({1'b0,1'b0}), + .SAXIACPARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIACPARVALID(1'b0), + .SAXIACPAWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIACPAWBURST({1'b0,1'b0}), + .SAXIACPAWCACHE({1'b0,1'b0,1'b0,1'b0}), + .SAXIACPAWID({1'b0,1'b0,1'b0}), + .SAXIACPAWLEN({1'b0,1'b0,1'b0,1'b0}), + .SAXIACPAWLOCK({1'b0,1'b0}), + .SAXIACPAWPROT({1'b0,1'b0,1'b0}), + .SAXIACPAWQOS({1'b0,1'b0,1'b0,1'b0}), + .SAXIACPAWREADY(PS7_i_n_105), + .SAXIACPAWSIZE({1'b0,1'b0}), + .SAXIACPAWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIACPAWVALID(1'b0), + .SAXIACPBID({PS7_i_n_351,PS7_i_n_352,PS7_i_n_353}), + .SAXIACPBREADY(1'b0), + .SAXIACPBRESP({PS7_i_n_264,PS7_i_n_265}), + .SAXIACPBVALID(PS7_i_n_106), + .SAXIACPRDATA({PS7_i_n_1001,PS7_i_n_1002,PS7_i_n_1003,PS7_i_n_1004,PS7_i_n_1005,PS7_i_n_1006,PS7_i_n_1007,PS7_i_n_1008,PS7_i_n_1009,PS7_i_n_1010,PS7_i_n_1011,PS7_i_n_1012,PS7_i_n_1013,PS7_i_n_1014,PS7_i_n_1015,PS7_i_n_1016,PS7_i_n_1017,PS7_i_n_1018,PS7_i_n_1019,PS7_i_n_1020,PS7_i_n_1021,PS7_i_n_1022,PS7_i_n_1023,PS7_i_n_1024,PS7_i_n_1025,PS7_i_n_1026,PS7_i_n_1027,PS7_i_n_1028,PS7_i_n_1029,PS7_i_n_1030,PS7_i_n_1031,PS7_i_n_1032,PS7_i_n_1033,PS7_i_n_1034,PS7_i_n_1035,PS7_i_n_1036,PS7_i_n_1037,PS7_i_n_1038,PS7_i_n_1039,PS7_i_n_1040,PS7_i_n_1041,PS7_i_n_1042,PS7_i_n_1043,PS7_i_n_1044,PS7_i_n_1045,PS7_i_n_1046,PS7_i_n_1047,PS7_i_n_1048,PS7_i_n_1049,PS7_i_n_1050,PS7_i_n_1051,PS7_i_n_1052,PS7_i_n_1053,PS7_i_n_1054,PS7_i_n_1055,PS7_i_n_1056,PS7_i_n_1057,PS7_i_n_1058,PS7_i_n_1059,PS7_i_n_1060,PS7_i_n_1061,PS7_i_n_1062,PS7_i_n_1063,PS7_i_n_1064}), + .SAXIACPRID({PS7_i_n_354,PS7_i_n_355,PS7_i_n_356}), + .SAXIACPRLAST(PS7_i_n_107), + .SAXIACPRREADY(1'b0), + .SAXIACPRRESP({PS7_i_n_266,PS7_i_n_267}), + .SAXIACPRVALID(PS7_i_n_108), + .SAXIACPWDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIACPWID({1'b0,1'b0,1'b0}), + .SAXIACPWLAST(1'b0), + .SAXIACPWREADY(PS7_i_n_109), + .SAXIACPWSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIACPWVALID(1'b0), + .SAXIGP0ACLK(1'b0), + .SAXIGP0ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIGP0ARBURST({1'b0,1'b0}), + .SAXIGP0ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .SAXIGP0ARESETN(PS7_i_n_110), + .SAXIGP0ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIGP0ARLEN({1'b0,1'b0,1'b0,1'b0}), + .SAXIGP0ARLOCK({1'b0,1'b0}), + .SAXIGP0ARPROT({1'b0,1'b0,1'b0}), + .SAXIGP0ARQOS({1'b0,1'b0,1'b0,1'b0}), + .SAXIGP0ARREADY(PS7_i_n_111), + .SAXIGP0ARSIZE({1'b0,1'b0}), + .SAXIGP0ARVALID(1'b0), + .SAXIGP0AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIGP0AWBURST({1'b0,1'b0}), + .SAXIGP0AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .SAXIGP0AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIGP0AWLEN({1'b0,1'b0,1'b0,1'b0}), + .SAXIGP0AWLOCK({1'b0,1'b0}), + .SAXIGP0AWPROT({1'b0,1'b0,1'b0}), + .SAXIGP0AWQOS({1'b0,1'b0,1'b0,1'b0}), + .SAXIGP0AWREADY(PS7_i_n_112), + .SAXIGP0AWSIZE({1'b0,1'b0}), + .SAXIGP0AWVALID(1'b0), + .SAXIGP0BID({PS7_i_n_777,PS7_i_n_778,PS7_i_n_779,PS7_i_n_780,PS7_i_n_781,PS7_i_n_782}), + .SAXIGP0BREADY(1'b0), + .SAXIGP0BRESP({PS7_i_n_268,PS7_i_n_269}), + .SAXIGP0BVALID(PS7_i_n_113), + .SAXIGP0RDATA({PS7_i_n_625,PS7_i_n_626,PS7_i_n_627,PS7_i_n_628,PS7_i_n_629,PS7_i_n_630,PS7_i_n_631,PS7_i_n_632,PS7_i_n_633,PS7_i_n_634,PS7_i_n_635,PS7_i_n_636,PS7_i_n_637,PS7_i_n_638,PS7_i_n_639,PS7_i_n_640,PS7_i_n_641,PS7_i_n_642,PS7_i_n_643,PS7_i_n_644,PS7_i_n_645,PS7_i_n_646,PS7_i_n_647,PS7_i_n_648,PS7_i_n_649,PS7_i_n_650,PS7_i_n_651,PS7_i_n_652,PS7_i_n_653,PS7_i_n_654,PS7_i_n_655,PS7_i_n_656}), + .SAXIGP0RID({PS7_i_n_783,PS7_i_n_784,PS7_i_n_785,PS7_i_n_786,PS7_i_n_787,PS7_i_n_788}), + .SAXIGP0RLAST(PS7_i_n_114), + .SAXIGP0RREADY(1'b0), + .SAXIGP0RRESP({PS7_i_n_270,PS7_i_n_271}), + .SAXIGP0RVALID(PS7_i_n_115), + .SAXIGP0WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIGP0WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIGP0WLAST(1'b0), + .SAXIGP0WREADY(PS7_i_n_116), + .SAXIGP0WSTRB({1'b0,1'b0,1'b0,1'b0}), + .SAXIGP0WVALID(1'b0), + .SAXIGP1ACLK(1'b0), + .SAXIGP1ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIGP1ARBURST({1'b0,1'b0}), + .SAXIGP1ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .SAXIGP1ARESETN(PS7_i_n_117), + .SAXIGP1ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIGP1ARLEN({1'b0,1'b0,1'b0,1'b0}), + .SAXIGP1ARLOCK({1'b0,1'b0}), + .SAXIGP1ARPROT({1'b0,1'b0,1'b0}), + .SAXIGP1ARQOS({1'b0,1'b0,1'b0,1'b0}), + .SAXIGP1ARREADY(PS7_i_n_118), + .SAXIGP1ARSIZE({1'b0,1'b0}), + .SAXIGP1ARVALID(1'b0), + .SAXIGP1AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIGP1AWBURST({1'b0,1'b0}), + .SAXIGP1AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .SAXIGP1AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIGP1AWLEN({1'b0,1'b0,1'b0,1'b0}), + .SAXIGP1AWLOCK({1'b0,1'b0}), + .SAXIGP1AWPROT({1'b0,1'b0,1'b0}), + .SAXIGP1AWQOS({1'b0,1'b0,1'b0,1'b0}), + .SAXIGP1AWREADY(PS7_i_n_119), + .SAXIGP1AWSIZE({1'b0,1'b0}), + .SAXIGP1AWVALID(1'b0), + .SAXIGP1BID({PS7_i_n_789,PS7_i_n_790,PS7_i_n_791,PS7_i_n_792,PS7_i_n_793,PS7_i_n_794}), + .SAXIGP1BREADY(1'b0), + .SAXIGP1BRESP({PS7_i_n_272,PS7_i_n_273}), + .SAXIGP1BVALID(PS7_i_n_120), + .SAXIGP1RDATA({PS7_i_n_657,PS7_i_n_658,PS7_i_n_659,PS7_i_n_660,PS7_i_n_661,PS7_i_n_662,PS7_i_n_663,PS7_i_n_664,PS7_i_n_665,PS7_i_n_666,PS7_i_n_667,PS7_i_n_668,PS7_i_n_669,PS7_i_n_670,PS7_i_n_671,PS7_i_n_672,PS7_i_n_673,PS7_i_n_674,PS7_i_n_675,PS7_i_n_676,PS7_i_n_677,PS7_i_n_678,PS7_i_n_679,PS7_i_n_680,PS7_i_n_681,PS7_i_n_682,PS7_i_n_683,PS7_i_n_684,PS7_i_n_685,PS7_i_n_686,PS7_i_n_687,PS7_i_n_688}), + .SAXIGP1RID({PS7_i_n_795,PS7_i_n_796,PS7_i_n_797,PS7_i_n_798,PS7_i_n_799,PS7_i_n_800}), + .SAXIGP1RLAST(PS7_i_n_121), + .SAXIGP1RREADY(1'b0), + .SAXIGP1RRESP({PS7_i_n_274,PS7_i_n_275}), + .SAXIGP1RVALID(PS7_i_n_122), + .SAXIGP1WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIGP1WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIGP1WLAST(1'b0), + .SAXIGP1WREADY(PS7_i_n_123), + .SAXIGP1WSTRB({1'b0,1'b0,1'b0,1'b0}), + .SAXIGP1WVALID(1'b0), + .SAXIHP0ACLK(1'b0), + .SAXIHP0ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIHP0ARBURST({1'b0,1'b0}), + .SAXIHP0ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .SAXIHP0ARESETN(PS7_i_n_124), + .SAXIHP0ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIHP0ARLEN({1'b0,1'b0,1'b0,1'b0}), + .SAXIHP0ARLOCK({1'b0,1'b0}), + .SAXIHP0ARPROT({1'b0,1'b0,1'b0}), + .SAXIHP0ARQOS({1'b0,1'b0,1'b0,1'b0}), + .SAXIHP0ARREADY(PS7_i_n_125), + .SAXIHP0ARSIZE({1'b0,1'b0}), + .SAXIHP0ARVALID(1'b0), + .SAXIHP0AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIHP0AWBURST({1'b0,1'b0}), + .SAXIHP0AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .SAXIHP0AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIHP0AWLEN({1'b0,1'b0,1'b0,1'b0}), + .SAXIHP0AWLOCK({1'b0,1'b0}), + .SAXIHP0AWPROT({1'b0,1'b0,1'b0}), + .SAXIHP0AWQOS({1'b0,1'b0,1'b0,1'b0}), + .SAXIHP0AWREADY(PS7_i_n_126), + .SAXIHP0AWSIZE({1'b0,1'b0}), + .SAXIHP0AWVALID(1'b0), + .SAXIHP0BID({PS7_i_n_801,PS7_i_n_802,PS7_i_n_803,PS7_i_n_804,PS7_i_n_805,PS7_i_n_806}), + .SAXIHP0BREADY(1'b0), + .SAXIHP0BRESP({PS7_i_n_276,PS7_i_n_277}), + .SAXIHP0BVALID(PS7_i_n_127), + .SAXIHP0RACOUNT({PS7_i_n_357,PS7_i_n_358,PS7_i_n_359}), + .SAXIHP0RCOUNT({PS7_i_n_1337,PS7_i_n_1338,PS7_i_n_1339,PS7_i_n_1340,PS7_i_n_1341,PS7_i_n_1342,PS7_i_n_1343,PS7_i_n_1344}), + .SAXIHP0RDATA({PS7_i_n_1065,PS7_i_n_1066,PS7_i_n_1067,PS7_i_n_1068,PS7_i_n_1069,PS7_i_n_1070,PS7_i_n_1071,PS7_i_n_1072,PS7_i_n_1073,PS7_i_n_1074,PS7_i_n_1075,PS7_i_n_1076,PS7_i_n_1077,PS7_i_n_1078,PS7_i_n_1079,PS7_i_n_1080,PS7_i_n_1081,PS7_i_n_1082,PS7_i_n_1083,PS7_i_n_1084,PS7_i_n_1085,PS7_i_n_1086,PS7_i_n_1087,PS7_i_n_1088,PS7_i_n_1089,PS7_i_n_1090,PS7_i_n_1091,PS7_i_n_1092,PS7_i_n_1093,PS7_i_n_1094,PS7_i_n_1095,PS7_i_n_1096,PS7_i_n_1097,PS7_i_n_1098,PS7_i_n_1099,PS7_i_n_1100,PS7_i_n_1101,PS7_i_n_1102,PS7_i_n_1103,PS7_i_n_1104,PS7_i_n_1105,PS7_i_n_1106,PS7_i_n_1107,PS7_i_n_1108,PS7_i_n_1109,PS7_i_n_1110,PS7_i_n_1111,PS7_i_n_1112,PS7_i_n_1113,PS7_i_n_1114,PS7_i_n_1115,PS7_i_n_1116,PS7_i_n_1117,PS7_i_n_1118,PS7_i_n_1119,PS7_i_n_1120,PS7_i_n_1121,PS7_i_n_1122,PS7_i_n_1123,PS7_i_n_1124,PS7_i_n_1125,PS7_i_n_1126,PS7_i_n_1127,PS7_i_n_1128}), + .SAXIHP0RDISSUECAP1EN(1'b0), + .SAXIHP0RID({PS7_i_n_807,PS7_i_n_808,PS7_i_n_809,PS7_i_n_810,PS7_i_n_811,PS7_i_n_812}), + .SAXIHP0RLAST(PS7_i_n_128), + .SAXIHP0RREADY(1'b0), + .SAXIHP0RRESP({PS7_i_n_278,PS7_i_n_279}), + .SAXIHP0RVALID(PS7_i_n_129), + .SAXIHP0WACOUNT({PS7_i_n_813,PS7_i_n_814,PS7_i_n_815,PS7_i_n_816,PS7_i_n_817,PS7_i_n_818}), + .SAXIHP0WCOUNT({PS7_i_n_1345,PS7_i_n_1346,PS7_i_n_1347,PS7_i_n_1348,PS7_i_n_1349,PS7_i_n_1350,PS7_i_n_1351,PS7_i_n_1352}), + .SAXIHP0WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIHP0WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIHP0WLAST(1'b0), + .SAXIHP0WREADY(PS7_i_n_130), + .SAXIHP0WRISSUECAP1EN(1'b0), + .SAXIHP0WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIHP0WVALID(1'b0), + .SAXIHP1ACLK(1'b0), + .SAXIHP1ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIHP1ARBURST({1'b0,1'b0}), + .SAXIHP1ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .SAXIHP1ARESETN(PS7_i_n_131), + .SAXIHP1ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIHP1ARLEN({1'b0,1'b0,1'b0,1'b0}), + .SAXIHP1ARLOCK({1'b0,1'b0}), + .SAXIHP1ARPROT({1'b0,1'b0,1'b0}), + .SAXIHP1ARQOS({1'b0,1'b0,1'b0,1'b0}), + .SAXIHP1ARREADY(PS7_i_n_132), + .SAXIHP1ARSIZE({1'b0,1'b0}), + .SAXIHP1ARVALID(1'b0), + .SAXIHP1AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIHP1AWBURST({1'b0,1'b0}), + .SAXIHP1AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .SAXIHP1AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIHP1AWLEN({1'b0,1'b0,1'b0,1'b0}), + .SAXIHP1AWLOCK({1'b0,1'b0}), + .SAXIHP1AWPROT({1'b0,1'b0,1'b0}), + .SAXIHP1AWQOS({1'b0,1'b0,1'b0,1'b0}), + .SAXIHP1AWREADY(PS7_i_n_133), + .SAXIHP1AWSIZE({1'b0,1'b0}), + .SAXIHP1AWVALID(1'b0), + .SAXIHP1BID({PS7_i_n_819,PS7_i_n_820,PS7_i_n_821,PS7_i_n_822,PS7_i_n_823,PS7_i_n_824}), + .SAXIHP1BREADY(1'b0), + .SAXIHP1BRESP({PS7_i_n_280,PS7_i_n_281}), + .SAXIHP1BVALID(PS7_i_n_134), + .SAXIHP1RACOUNT({PS7_i_n_360,PS7_i_n_361,PS7_i_n_362}), + .SAXIHP1RCOUNT({PS7_i_n_1353,PS7_i_n_1354,PS7_i_n_1355,PS7_i_n_1356,PS7_i_n_1357,PS7_i_n_1358,PS7_i_n_1359,PS7_i_n_1360}), + .SAXIHP1RDATA({PS7_i_n_1129,PS7_i_n_1130,PS7_i_n_1131,PS7_i_n_1132,PS7_i_n_1133,PS7_i_n_1134,PS7_i_n_1135,PS7_i_n_1136,PS7_i_n_1137,PS7_i_n_1138,PS7_i_n_1139,PS7_i_n_1140,PS7_i_n_1141,PS7_i_n_1142,PS7_i_n_1143,PS7_i_n_1144,PS7_i_n_1145,PS7_i_n_1146,PS7_i_n_1147,PS7_i_n_1148,PS7_i_n_1149,PS7_i_n_1150,PS7_i_n_1151,PS7_i_n_1152,PS7_i_n_1153,PS7_i_n_1154,PS7_i_n_1155,PS7_i_n_1156,PS7_i_n_1157,PS7_i_n_1158,PS7_i_n_1159,PS7_i_n_1160,PS7_i_n_1161,PS7_i_n_1162,PS7_i_n_1163,PS7_i_n_1164,PS7_i_n_1165,PS7_i_n_1166,PS7_i_n_1167,PS7_i_n_1168,PS7_i_n_1169,PS7_i_n_1170,PS7_i_n_1171,PS7_i_n_1172,PS7_i_n_1173,PS7_i_n_1174,PS7_i_n_1175,PS7_i_n_1176,PS7_i_n_1177,PS7_i_n_1178,PS7_i_n_1179,PS7_i_n_1180,PS7_i_n_1181,PS7_i_n_1182,PS7_i_n_1183,PS7_i_n_1184,PS7_i_n_1185,PS7_i_n_1186,PS7_i_n_1187,PS7_i_n_1188,PS7_i_n_1189,PS7_i_n_1190,PS7_i_n_1191,PS7_i_n_1192}), + .SAXIHP1RDISSUECAP1EN(1'b0), + .SAXIHP1RID({PS7_i_n_825,PS7_i_n_826,PS7_i_n_827,PS7_i_n_828,PS7_i_n_829,PS7_i_n_830}), + .SAXIHP1RLAST(PS7_i_n_135), + .SAXIHP1RREADY(1'b0), + .SAXIHP1RRESP({PS7_i_n_282,PS7_i_n_283}), + .SAXIHP1RVALID(PS7_i_n_136), + .SAXIHP1WACOUNT({PS7_i_n_831,PS7_i_n_832,PS7_i_n_833,PS7_i_n_834,PS7_i_n_835,PS7_i_n_836}), + .SAXIHP1WCOUNT({PS7_i_n_1361,PS7_i_n_1362,PS7_i_n_1363,PS7_i_n_1364,PS7_i_n_1365,PS7_i_n_1366,PS7_i_n_1367,PS7_i_n_1368}), + .SAXIHP1WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIHP1WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIHP1WLAST(1'b0), + .SAXIHP1WREADY(PS7_i_n_137), + .SAXIHP1WRISSUECAP1EN(1'b0), + .SAXIHP1WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIHP1WVALID(1'b0), + .SAXIHP2ACLK(1'b0), + .SAXIHP2ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIHP2ARBURST({1'b0,1'b0}), + .SAXIHP2ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .SAXIHP2ARESETN(PS7_i_n_138), + .SAXIHP2ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIHP2ARLEN({1'b0,1'b0,1'b0,1'b0}), + .SAXIHP2ARLOCK({1'b0,1'b0}), + .SAXIHP2ARPROT({1'b0,1'b0,1'b0}), + .SAXIHP2ARQOS({1'b0,1'b0,1'b0,1'b0}), + .SAXIHP2ARREADY(PS7_i_n_139), + .SAXIHP2ARSIZE({1'b0,1'b0}), + .SAXIHP2ARVALID(1'b0), + .SAXIHP2AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIHP2AWBURST({1'b0,1'b0}), + .SAXIHP2AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .SAXIHP2AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIHP2AWLEN({1'b0,1'b0,1'b0,1'b0}), + .SAXIHP2AWLOCK({1'b0,1'b0}), + .SAXIHP2AWPROT({1'b0,1'b0,1'b0}), + .SAXIHP2AWQOS({1'b0,1'b0,1'b0,1'b0}), + .SAXIHP2AWREADY(PS7_i_n_140), + .SAXIHP2AWSIZE({1'b0,1'b0}), + .SAXIHP2AWVALID(1'b0), + .SAXIHP2BID({PS7_i_n_837,PS7_i_n_838,PS7_i_n_839,PS7_i_n_840,PS7_i_n_841,PS7_i_n_842}), + .SAXIHP2BREADY(1'b0), + .SAXIHP2BRESP({PS7_i_n_284,PS7_i_n_285}), + .SAXIHP2BVALID(PS7_i_n_141), + .SAXIHP2RACOUNT({PS7_i_n_363,PS7_i_n_364,PS7_i_n_365}), + .SAXIHP2RCOUNT({PS7_i_n_1369,PS7_i_n_1370,PS7_i_n_1371,PS7_i_n_1372,PS7_i_n_1373,PS7_i_n_1374,PS7_i_n_1375,PS7_i_n_1376}), + .SAXIHP2RDATA({PS7_i_n_1193,PS7_i_n_1194,PS7_i_n_1195,PS7_i_n_1196,PS7_i_n_1197,PS7_i_n_1198,PS7_i_n_1199,PS7_i_n_1200,PS7_i_n_1201,PS7_i_n_1202,PS7_i_n_1203,PS7_i_n_1204,PS7_i_n_1205,PS7_i_n_1206,PS7_i_n_1207,PS7_i_n_1208,PS7_i_n_1209,PS7_i_n_1210,PS7_i_n_1211,PS7_i_n_1212,PS7_i_n_1213,PS7_i_n_1214,PS7_i_n_1215,PS7_i_n_1216,PS7_i_n_1217,PS7_i_n_1218,PS7_i_n_1219,PS7_i_n_1220,PS7_i_n_1221,PS7_i_n_1222,PS7_i_n_1223,PS7_i_n_1224,PS7_i_n_1225,PS7_i_n_1226,PS7_i_n_1227,PS7_i_n_1228,PS7_i_n_1229,PS7_i_n_1230,PS7_i_n_1231,PS7_i_n_1232,PS7_i_n_1233,PS7_i_n_1234,PS7_i_n_1235,PS7_i_n_1236,PS7_i_n_1237,PS7_i_n_1238,PS7_i_n_1239,PS7_i_n_1240,PS7_i_n_1241,PS7_i_n_1242,PS7_i_n_1243,PS7_i_n_1244,PS7_i_n_1245,PS7_i_n_1246,PS7_i_n_1247,PS7_i_n_1248,PS7_i_n_1249,PS7_i_n_1250,PS7_i_n_1251,PS7_i_n_1252,PS7_i_n_1253,PS7_i_n_1254,PS7_i_n_1255,PS7_i_n_1256}), + .SAXIHP2RDISSUECAP1EN(1'b0), + .SAXIHP2RID({PS7_i_n_843,PS7_i_n_844,PS7_i_n_845,PS7_i_n_846,PS7_i_n_847,PS7_i_n_848}), + .SAXIHP2RLAST(PS7_i_n_142), + .SAXIHP2RREADY(1'b0), + .SAXIHP2RRESP({PS7_i_n_286,PS7_i_n_287}), + .SAXIHP2RVALID(PS7_i_n_143), + .SAXIHP2WACOUNT({PS7_i_n_849,PS7_i_n_850,PS7_i_n_851,PS7_i_n_852,PS7_i_n_853,PS7_i_n_854}), + .SAXIHP2WCOUNT({PS7_i_n_1377,PS7_i_n_1378,PS7_i_n_1379,PS7_i_n_1380,PS7_i_n_1381,PS7_i_n_1382,PS7_i_n_1383,PS7_i_n_1384}), + .SAXIHP2WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIHP2WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIHP2WLAST(1'b0), + .SAXIHP2WREADY(PS7_i_n_144), + .SAXIHP2WRISSUECAP1EN(1'b0), + .SAXIHP2WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIHP2WVALID(1'b0), + .SAXIHP3ACLK(1'b0), + .SAXIHP3ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIHP3ARBURST({1'b0,1'b0}), + .SAXIHP3ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .SAXIHP3ARESETN(PS7_i_n_145), + .SAXIHP3ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIHP3ARLEN({1'b0,1'b0,1'b0,1'b0}), + .SAXIHP3ARLOCK({1'b0,1'b0}), + .SAXIHP3ARPROT({1'b0,1'b0,1'b0}), + .SAXIHP3ARQOS({1'b0,1'b0,1'b0,1'b0}), + .SAXIHP3ARREADY(PS7_i_n_146), + .SAXIHP3ARSIZE({1'b0,1'b0}), + .SAXIHP3ARVALID(1'b0), + .SAXIHP3AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIHP3AWBURST({1'b0,1'b0}), + .SAXIHP3AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .SAXIHP3AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIHP3AWLEN({1'b0,1'b0,1'b0,1'b0}), + .SAXIHP3AWLOCK({1'b0,1'b0}), + .SAXIHP3AWPROT({1'b0,1'b0,1'b0}), + .SAXIHP3AWQOS({1'b0,1'b0,1'b0,1'b0}), + .SAXIHP3AWREADY(PS7_i_n_147), + .SAXIHP3AWSIZE({1'b0,1'b0}), + .SAXIHP3AWVALID(1'b0), + .SAXIHP3BID({PS7_i_n_855,PS7_i_n_856,PS7_i_n_857,PS7_i_n_858,PS7_i_n_859,PS7_i_n_860}), + .SAXIHP3BREADY(1'b0), + .SAXIHP3BRESP({PS7_i_n_288,PS7_i_n_289}), + .SAXIHP3BVALID(PS7_i_n_148), + .SAXIHP3RACOUNT({PS7_i_n_366,PS7_i_n_367,PS7_i_n_368}), + .SAXIHP3RCOUNT({PS7_i_n_1385,PS7_i_n_1386,PS7_i_n_1387,PS7_i_n_1388,PS7_i_n_1389,PS7_i_n_1390,PS7_i_n_1391,PS7_i_n_1392}), + .SAXIHP3RDATA({PS7_i_n_1257,PS7_i_n_1258,PS7_i_n_1259,PS7_i_n_1260,PS7_i_n_1261,PS7_i_n_1262,PS7_i_n_1263,PS7_i_n_1264,PS7_i_n_1265,PS7_i_n_1266,PS7_i_n_1267,PS7_i_n_1268,PS7_i_n_1269,PS7_i_n_1270,PS7_i_n_1271,PS7_i_n_1272,PS7_i_n_1273,PS7_i_n_1274,PS7_i_n_1275,PS7_i_n_1276,PS7_i_n_1277,PS7_i_n_1278,PS7_i_n_1279,PS7_i_n_1280,PS7_i_n_1281,PS7_i_n_1282,PS7_i_n_1283,PS7_i_n_1284,PS7_i_n_1285,PS7_i_n_1286,PS7_i_n_1287,PS7_i_n_1288,PS7_i_n_1289,PS7_i_n_1290,PS7_i_n_1291,PS7_i_n_1292,PS7_i_n_1293,PS7_i_n_1294,PS7_i_n_1295,PS7_i_n_1296,PS7_i_n_1297,PS7_i_n_1298,PS7_i_n_1299,PS7_i_n_1300,PS7_i_n_1301,PS7_i_n_1302,PS7_i_n_1303,PS7_i_n_1304,PS7_i_n_1305,PS7_i_n_1306,PS7_i_n_1307,PS7_i_n_1308,PS7_i_n_1309,PS7_i_n_1310,PS7_i_n_1311,PS7_i_n_1312,PS7_i_n_1313,PS7_i_n_1314,PS7_i_n_1315,PS7_i_n_1316,PS7_i_n_1317,PS7_i_n_1318,PS7_i_n_1319,PS7_i_n_1320}), + .SAXIHP3RDISSUECAP1EN(1'b0), + .SAXIHP3RID({PS7_i_n_861,PS7_i_n_862,PS7_i_n_863,PS7_i_n_864,PS7_i_n_865,PS7_i_n_866}), + .SAXIHP3RLAST(PS7_i_n_149), + .SAXIHP3RREADY(1'b0), + .SAXIHP3RRESP({PS7_i_n_290,PS7_i_n_291}), + .SAXIHP3RVALID(PS7_i_n_150), + .SAXIHP3WACOUNT({PS7_i_n_867,PS7_i_n_868,PS7_i_n_869,PS7_i_n_870,PS7_i_n_871,PS7_i_n_872}), + .SAXIHP3WCOUNT({PS7_i_n_1393,PS7_i_n_1394,PS7_i_n_1395,PS7_i_n_1396,PS7_i_n_1397,PS7_i_n_1398,PS7_i_n_1399,PS7_i_n_1400}), + .SAXIHP3WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIHP3WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIHP3WLAST(1'b0), + .SAXIHP3WREADY(PS7_i_n_151), + .SAXIHP3WRISSUECAP1EN(1'b0), + .SAXIHP3WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .SAXIHP3WVALID(1'b0)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF PS_CLK_BIBUF + (.IO(buffered_PS_CLK), + .PAD(PS_CLK)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF PS_PORB_BIBUF + (.IO(buffered_PS_PORB), + .PAD(PS_PORB)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF PS_SRSTB_BIBUF + (.IO(buffered_PS_SRSTB), + .PAD(PS_SRSTB)); + (* BOX_TYPE = "PRIMITIVE" *) + BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG + (.I(FCLK_CLK_unbuffered[0]), + .O(FCLK_CLK0)); + (* BOX_TYPE = "PRIMITIVE" *) + BUFG \buffer_fclk_clk_1.FCLK_CLK_1_BUFG + (.I(FCLK_CLK_unbuffered[1]), + .O(FCLK_CLK1)); + (* BOX_TYPE = "PRIMITIVE" *) + BUFG \buffer_fclk_clk_2.FCLK_CLK_2_BUFG + (.I(FCLK_CLK_unbuffered[2]), + .O(FCLK_CLK2)); + (* BOX_TYPE = "PRIMITIVE" *) + BUFG \buffer_fclk_clk_3.FCLK_CLK_3_BUFG + (.I(FCLK_CLK_unbuffered[3]), + .O(FCLK_CLK3)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[0].MIO_BIBUF + (.IO(buffered_MIO[0]), + .PAD(MIO[0])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[10].MIO_BIBUF + (.IO(buffered_MIO[10]), + .PAD(MIO[10])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[11].MIO_BIBUF + (.IO(buffered_MIO[11]), + .PAD(MIO[11])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[12].MIO_BIBUF + (.IO(buffered_MIO[12]), + .PAD(MIO[12])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[13].MIO_BIBUF + (.IO(buffered_MIO[13]), + .PAD(MIO[13])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[14].MIO_BIBUF + (.IO(buffered_MIO[14]), + .PAD(MIO[14])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[15].MIO_BIBUF + (.IO(buffered_MIO[15]), + .PAD(MIO[15])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[16].MIO_BIBUF + (.IO(buffered_MIO[16]), + .PAD(MIO[16])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[17].MIO_BIBUF + (.IO(buffered_MIO[17]), + .PAD(MIO[17])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[18].MIO_BIBUF + (.IO(buffered_MIO[18]), + .PAD(MIO[18])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[19].MIO_BIBUF + (.IO(buffered_MIO[19]), + .PAD(MIO[19])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[1].MIO_BIBUF + (.IO(buffered_MIO[1]), + .PAD(MIO[1])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[20].MIO_BIBUF + (.IO(buffered_MIO[20]), + .PAD(MIO[20])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[21].MIO_BIBUF + (.IO(buffered_MIO[21]), + .PAD(MIO[21])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[22].MIO_BIBUF + (.IO(buffered_MIO[22]), + .PAD(MIO[22])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[23].MIO_BIBUF + (.IO(buffered_MIO[23]), + .PAD(MIO[23])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[24].MIO_BIBUF + (.IO(buffered_MIO[24]), + .PAD(MIO[24])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[25].MIO_BIBUF + (.IO(buffered_MIO[25]), + .PAD(MIO[25])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[26].MIO_BIBUF + (.IO(buffered_MIO[26]), + .PAD(MIO[26])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[27].MIO_BIBUF + (.IO(buffered_MIO[27]), + .PAD(MIO[27])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[28].MIO_BIBUF + (.IO(buffered_MIO[28]), + .PAD(MIO[28])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[29].MIO_BIBUF + (.IO(buffered_MIO[29]), + .PAD(MIO[29])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[2].MIO_BIBUF + (.IO(buffered_MIO[2]), + .PAD(MIO[2])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[30].MIO_BIBUF + (.IO(buffered_MIO[30]), + .PAD(MIO[30])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[31].MIO_BIBUF + (.IO(buffered_MIO[31]), + .PAD(MIO[31])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[32].MIO_BIBUF + (.IO(buffered_MIO[32]), + .PAD(MIO[32])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[33].MIO_BIBUF + (.IO(buffered_MIO[33]), + .PAD(MIO[33])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[34].MIO_BIBUF + (.IO(buffered_MIO[34]), + .PAD(MIO[34])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[35].MIO_BIBUF + (.IO(buffered_MIO[35]), + .PAD(MIO[35])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[36].MIO_BIBUF + (.IO(buffered_MIO[36]), + .PAD(MIO[36])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[37].MIO_BIBUF + (.IO(buffered_MIO[37]), + .PAD(MIO[37])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[38].MIO_BIBUF + (.IO(buffered_MIO[38]), + .PAD(MIO[38])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[39].MIO_BIBUF + (.IO(buffered_MIO[39]), + .PAD(MIO[39])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[3].MIO_BIBUF + (.IO(buffered_MIO[3]), + .PAD(MIO[3])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[40].MIO_BIBUF + (.IO(buffered_MIO[40]), + .PAD(MIO[40])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[41].MIO_BIBUF + (.IO(buffered_MIO[41]), + .PAD(MIO[41])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[42].MIO_BIBUF + (.IO(buffered_MIO[42]), + .PAD(MIO[42])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[43].MIO_BIBUF + (.IO(buffered_MIO[43]), + .PAD(MIO[43])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[44].MIO_BIBUF + (.IO(buffered_MIO[44]), + .PAD(MIO[44])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[45].MIO_BIBUF + (.IO(buffered_MIO[45]), + .PAD(MIO[45])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[46].MIO_BIBUF + (.IO(buffered_MIO[46]), + .PAD(MIO[46])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[47].MIO_BIBUF + (.IO(buffered_MIO[47]), + .PAD(MIO[47])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[48].MIO_BIBUF + (.IO(buffered_MIO[48]), + .PAD(MIO[48])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[49].MIO_BIBUF + (.IO(buffered_MIO[49]), + .PAD(MIO[49])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[4].MIO_BIBUF + (.IO(buffered_MIO[4]), + .PAD(MIO[4])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[50].MIO_BIBUF + (.IO(buffered_MIO[50]), + .PAD(MIO[50])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[51].MIO_BIBUF + (.IO(buffered_MIO[51]), + .PAD(MIO[51])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[52].MIO_BIBUF + (.IO(buffered_MIO[52]), + .PAD(MIO[52])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[53].MIO_BIBUF + (.IO(buffered_MIO[53]), + .PAD(MIO[53])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[5].MIO_BIBUF + (.IO(buffered_MIO[5]), + .PAD(MIO[5])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[6].MIO_BIBUF + (.IO(buffered_MIO[6]), + .PAD(MIO[6])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[7].MIO_BIBUF + (.IO(buffered_MIO[7]), + .PAD(MIO[7])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[8].MIO_BIBUF + (.IO(buffered_MIO[8]), + .PAD(MIO[8])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[9].MIO_BIBUF + (.IO(buffered_MIO[9]), + .PAD(MIO[9])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk14[0].DDR_BankAddr_BIBUF + (.IO(buffered_DDR_BankAddr[0]), + .PAD(DDR_BankAddr[0])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk14[1].DDR_BankAddr_BIBUF + (.IO(buffered_DDR_BankAddr[1]), + .PAD(DDR_BankAddr[1])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk14[2].DDR_BankAddr_BIBUF + (.IO(buffered_DDR_BankAddr[2]), + .PAD(DDR_BankAddr[2])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[0].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[0]), + .PAD(DDR_Addr[0])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[10].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[10]), + .PAD(DDR_Addr[10])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[11].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[11]), + .PAD(DDR_Addr[11])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[12].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[12]), + .PAD(DDR_Addr[12])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[13].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[13]), + .PAD(DDR_Addr[13])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[14].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[14]), + .PAD(DDR_Addr[14])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[1].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[1]), + .PAD(DDR_Addr[1])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[2].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[2]), + .PAD(DDR_Addr[2])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[3].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[3]), + .PAD(DDR_Addr[3])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[4].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[4]), + .PAD(DDR_Addr[4])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[5].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[5]), + .PAD(DDR_Addr[5])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[6].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[6]), + .PAD(DDR_Addr[6])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[7].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[7]), + .PAD(DDR_Addr[7])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[8].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[8]), + .PAD(DDR_Addr[8])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[9].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[9]), + .PAD(DDR_Addr[9])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk16[0].DDR_DM_BIBUF + (.IO(buffered_DDR_DM[0]), + .PAD(DDR_DM[0])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk16[1].DDR_DM_BIBUF + (.IO(buffered_DDR_DM[1]), + .PAD(DDR_DM[1])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk16[2].DDR_DM_BIBUF + (.IO(buffered_DDR_DM[2]), + .PAD(DDR_DM[2])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk16[3].DDR_DM_BIBUF + (.IO(buffered_DDR_DM[3]), + .PAD(DDR_DM[3])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[0].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[0]), + .PAD(DDR_DQ[0])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[10].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[10]), + .PAD(DDR_DQ[10])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[11].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[11]), + .PAD(DDR_DQ[11])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[12].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[12]), + .PAD(DDR_DQ[12])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[13].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[13]), + .PAD(DDR_DQ[13])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[14].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[14]), + .PAD(DDR_DQ[14])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[15].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[15]), + .PAD(DDR_DQ[15])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[16].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[16]), + .PAD(DDR_DQ[16])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[17].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[17]), + .PAD(DDR_DQ[17])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[18].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[18]), + .PAD(DDR_DQ[18])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[19].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[19]), + .PAD(DDR_DQ[19])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[1].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[1]), + .PAD(DDR_DQ[1])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[20].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[20]), + .PAD(DDR_DQ[20])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[21].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[21]), + .PAD(DDR_DQ[21])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[22].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[22]), + .PAD(DDR_DQ[22])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[23].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[23]), + .PAD(DDR_DQ[23])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[24].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[24]), + .PAD(DDR_DQ[24])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[25].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[25]), + .PAD(DDR_DQ[25])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[26].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[26]), + .PAD(DDR_DQ[26])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[27].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[27]), + .PAD(DDR_DQ[27])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[28].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[28]), + .PAD(DDR_DQ[28])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[29].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[29]), + .PAD(DDR_DQ[29])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[2].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[2]), + .PAD(DDR_DQ[2])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[30].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[30]), + .PAD(DDR_DQ[30])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[31].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[31]), + .PAD(DDR_DQ[31])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[3].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[3]), + .PAD(DDR_DQ[3])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[4].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[4]), + .PAD(DDR_DQ[4])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[5].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[5]), + .PAD(DDR_DQ[5])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[6].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[6]), + .PAD(DDR_DQ[6])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[7].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[7]), + .PAD(DDR_DQ[7])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[8].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[8]), + .PAD(DDR_DQ[8])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[9].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[9]), + .PAD(DDR_DQ[9])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk18[0].DDR_DQS_n_BIBUF + (.IO(buffered_DDR_DQS_n[0]), + .PAD(DDR_DQS_n[0])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk18[1].DDR_DQS_n_BIBUF + (.IO(buffered_DDR_DQS_n[1]), + .PAD(DDR_DQS_n[1])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk18[2].DDR_DQS_n_BIBUF + (.IO(buffered_DDR_DQS_n[2]), + .PAD(DDR_DQS_n[2])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk18[3].DDR_DQS_n_BIBUF + (.IO(buffered_DDR_DQS_n[3]), + .PAD(DDR_DQS_n[3])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk19[0].DDR_DQS_BIBUF + (.IO(buffered_DDR_DQS[0]), + .PAD(DDR_DQS[0])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk19[1].DDR_DQS_BIBUF + (.IO(buffered_DDR_DQS[1]), + .PAD(DDR_DQS[1])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk19[2].DDR_DQS_BIBUF + (.IO(buffered_DDR_DQS[2]), + .PAD(DDR_DQS[2])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk19[3].DDR_DQS_BIBUF + (.IO(buffered_DDR_DQS[3]), + .PAD(DDR_DQS[3])); + LUT1 #( + .INIT(2'h2)) + i_0 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[0] )); + LUT1 #( + .INIT(2'h2)) + i_1 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[0] [1])); + LUT1 #( + .INIT(2'h2)) + i_10 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[7] [1])); + LUT1 #( + .INIT(2'h2)) + i_11 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[7] [0])); + LUT1 #( + .INIT(2'h2)) + i_12 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[6] [1])); + LUT1 #( + .INIT(2'h2)) + i_13 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[6] [0])); + LUT1 #( + .INIT(2'h2)) + i_14 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[5] [1])); + LUT1 #( + .INIT(2'h2)) + i_15 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[5] [0])); + LUT1 #( + .INIT(2'h2)) + i_16 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[4] [1])); + LUT1 #( + .INIT(2'h2)) + i_17 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[4] [0])); + LUT1 #( + .INIT(2'h2)) + i_18 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[3] [1])); + LUT1 #( + .INIT(2'h2)) + i_19 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[3] [0])); + LUT1 #( + .INIT(2'h2)) + i_2 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[0] [0])); + LUT1 #( + .INIT(2'h2)) + i_20 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[2] [1])); + LUT1 #( + .INIT(2'h2)) + i_21 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[2] [0])); + LUT1 #( + .INIT(2'h2)) + i_22 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[1] [1])); + LUT1 #( + .INIT(2'h2)) + i_23 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[1] [0])); + LUT1 #( + .INIT(2'h2)) + i_3 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[7] )); + LUT1 #( + .INIT(2'h2)) + i_4 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[6] )); + LUT1 #( + .INIT(2'h2)) + i_5 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[5] )); + LUT1 #( + .INIT(2'h2)) + i_6 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[4] )); + LUT1 #( + .INIT(2'h2)) + i_7 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[3] )); + LUT1 #( + .INIT(2'h2)) + i_8 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[2] )); + LUT1 #( + .INIT(2'h2)) + i_9 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[1] )); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0_sim_netlist.vhdl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0_sim_netlist.vhdl new file mode 100644 index 0000000..c2dbec2 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0_sim_netlist.vhdl @@ -0,0 +1,6952 @@ +-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +-- Date : Fri May 15 15:27:00 2026 +-- Host : mkb running 64-bit unknown +-- Command : write_vhdl -force -mode funcsim +-- /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0_sim_netlist.vhdl +-- Design : NewExtInst_TOP_processing_system7_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z035ffg676-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 is + port ( + CAN0_PHY_TX : out STD_LOGIC; + CAN0_PHY_RX : in STD_LOGIC; + CAN1_PHY_TX : out STD_LOGIC; + CAN1_PHY_RX : in STD_LOGIC; + ENET0_GMII_TX_EN : out STD_LOGIC; + ENET0_GMII_TX_ER : out STD_LOGIC; + ENET0_MDIO_MDC : out STD_LOGIC; + ENET0_MDIO_O : out STD_LOGIC; + ENET0_MDIO_T : out STD_LOGIC; + ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC; + ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC; + ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC; + ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC; + ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC; + ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC; + ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC; + ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC; + ENET0_SOF_RX : out STD_LOGIC; + ENET0_SOF_TX : out STD_LOGIC; + ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 ); + ENET0_GMII_COL : in STD_LOGIC; + ENET0_GMII_CRS : in STD_LOGIC; + ENET0_GMII_RX_CLK : in STD_LOGIC; + ENET0_GMII_RX_DV : in STD_LOGIC; + ENET0_GMII_RX_ER : in STD_LOGIC; + ENET0_GMII_TX_CLK : in STD_LOGIC; + ENET0_MDIO_I : in STD_LOGIC; + ENET0_EXT_INTIN : in STD_LOGIC; + ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 ); + ENET1_GMII_TX_EN : out STD_LOGIC; + ENET1_GMII_TX_ER : out STD_LOGIC; + ENET1_MDIO_MDC : out STD_LOGIC; + ENET1_MDIO_O : out STD_LOGIC; + ENET1_MDIO_T : out STD_LOGIC; + ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC; + ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC; + ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC; + ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC; + ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC; + ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC; + ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC; + ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC; + ENET1_SOF_RX : out STD_LOGIC; + ENET1_SOF_TX : out STD_LOGIC; + ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 ); + ENET1_GMII_COL : in STD_LOGIC; + ENET1_GMII_CRS : in STD_LOGIC; + ENET1_GMII_RX_CLK : in STD_LOGIC; + ENET1_GMII_RX_DV : in STD_LOGIC; + ENET1_GMII_RX_ER : in STD_LOGIC; + ENET1_GMII_TX_CLK : in STD_LOGIC; + ENET1_MDIO_I : in STD_LOGIC; + ENET1_EXT_INTIN : in STD_LOGIC; + ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 ); + GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 ); + GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 ); + GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 ); + I2C0_SDA_I : in STD_LOGIC; + I2C0_SDA_O : out STD_LOGIC; + I2C0_SDA_T : out STD_LOGIC; + I2C0_SCL_I : in STD_LOGIC; + I2C0_SCL_O : out STD_LOGIC; + I2C0_SCL_T : out STD_LOGIC; + I2C1_SDA_I : in STD_LOGIC; + I2C1_SDA_O : out STD_LOGIC; + I2C1_SDA_T : out STD_LOGIC; + I2C1_SCL_I : in STD_LOGIC; + I2C1_SCL_O : out STD_LOGIC; + I2C1_SCL_T : out STD_LOGIC; + PJTAG_TCK : in STD_LOGIC; + PJTAG_TMS : in STD_LOGIC; + PJTAG_TDI : in STD_LOGIC; + PJTAG_TDO : out STD_LOGIC; + SDIO0_CLK : out STD_LOGIC; + SDIO0_CLK_FB : in STD_LOGIC; + SDIO0_CMD_O : out STD_LOGIC; + SDIO0_CMD_I : in STD_LOGIC; + SDIO0_CMD_T : out STD_LOGIC; + SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 ); + SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 ); + SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 ); + SDIO0_LED : out STD_LOGIC; + SDIO0_CDN : in STD_LOGIC; + SDIO0_WP : in STD_LOGIC; + SDIO0_BUSPOW : out STD_LOGIC; + SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + SDIO1_CLK : out STD_LOGIC; + SDIO1_CLK_FB : in STD_LOGIC; + SDIO1_CMD_O : out STD_LOGIC; + SDIO1_CMD_I : in STD_LOGIC; + SDIO1_CMD_T : out STD_LOGIC; + SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 ); + SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 ); + SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 ); + SDIO1_LED : out STD_LOGIC; + SDIO1_CDN : in STD_LOGIC; + SDIO1_WP : in STD_LOGIC; + SDIO1_BUSPOW : out STD_LOGIC; + SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + SPI0_SCLK_I : in STD_LOGIC; + SPI0_SCLK_O : out STD_LOGIC; + SPI0_SCLK_T : out STD_LOGIC; + SPI0_MOSI_I : in STD_LOGIC; + SPI0_MOSI_O : out STD_LOGIC; + SPI0_MOSI_T : out STD_LOGIC; + SPI0_MISO_I : in STD_LOGIC; + SPI0_MISO_O : out STD_LOGIC; + SPI0_MISO_T : out STD_LOGIC; + SPI0_SS_I : in STD_LOGIC; + SPI0_SS_O : out STD_LOGIC; + SPI0_SS1_O : out STD_LOGIC; + SPI0_SS2_O : out STD_LOGIC; + SPI0_SS_T : out STD_LOGIC; + SPI1_SCLK_I : in STD_LOGIC; + SPI1_SCLK_O : out STD_LOGIC; + SPI1_SCLK_T : out STD_LOGIC; + SPI1_MOSI_I : in STD_LOGIC; + SPI1_MOSI_O : out STD_LOGIC; + SPI1_MOSI_T : out STD_LOGIC; + SPI1_MISO_I : in STD_LOGIC; + SPI1_MISO_O : out STD_LOGIC; + SPI1_MISO_T : out STD_LOGIC; + SPI1_SS_I : in STD_LOGIC; + SPI1_SS_O : out STD_LOGIC; + SPI1_SS1_O : out STD_LOGIC; + SPI1_SS2_O : out STD_LOGIC; + SPI1_SS_T : out STD_LOGIC; + UART0_DTRN : out STD_LOGIC; + UART0_RTSN : out STD_LOGIC; + UART0_TX : out STD_LOGIC; + UART0_CTSN : in STD_LOGIC; + UART0_DCDN : in STD_LOGIC; + UART0_DSRN : in STD_LOGIC; + UART0_RIN : in STD_LOGIC; + UART0_RX : in STD_LOGIC; + UART1_DTRN : out STD_LOGIC; + UART1_RTSN : out STD_LOGIC; + UART1_TX : out STD_LOGIC; + UART1_CTSN : in STD_LOGIC; + UART1_DCDN : in STD_LOGIC; + UART1_DSRN : in STD_LOGIC; + UART1_RIN : in STD_LOGIC; + UART1_RX : in STD_LOGIC; + TTC0_WAVE0_OUT : out STD_LOGIC; + TTC0_WAVE1_OUT : out STD_LOGIC; + TTC0_WAVE2_OUT : out STD_LOGIC; + TTC0_CLK0_IN : in STD_LOGIC; + TTC0_CLK1_IN : in STD_LOGIC; + TTC0_CLK2_IN : in STD_LOGIC; + TTC1_WAVE0_OUT : out STD_LOGIC; + TTC1_WAVE1_OUT : out STD_LOGIC; + TTC1_WAVE2_OUT : out STD_LOGIC; + TTC1_CLK0_IN : in STD_LOGIC; + TTC1_CLK1_IN : in STD_LOGIC; + TTC1_CLK2_IN : in STD_LOGIC; + WDT_CLK_IN : in STD_LOGIC; + WDT_RST_OUT : out STD_LOGIC; + TRACE_CLK : in STD_LOGIC; + TRACE_CTL : out STD_LOGIC; + TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 ); + TRACE_CLK_OUT : out STD_LOGIC; + USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); + USB0_VBUS_PWRSELECT : out STD_LOGIC; + USB0_VBUS_PWRFAULT : in STD_LOGIC; + USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); + USB1_VBUS_PWRSELECT : out STD_LOGIC; + USB1_VBUS_PWRFAULT : in STD_LOGIC; + SRAM_INTIN : in STD_LOGIC; + M_AXI_GP0_ARESETN : out STD_LOGIC; + M_AXI_GP0_ARVALID : out STD_LOGIC; + M_AXI_GP0_AWVALID : out STD_LOGIC; + M_AXI_GP0_BREADY : out STD_LOGIC; + M_AXI_GP0_RREADY : out STD_LOGIC; + M_AXI_GP0_WLAST : out STD_LOGIC; + M_AXI_GP0_WVALID : out STD_LOGIC; + M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_ACLK : in STD_LOGIC; + M_AXI_GP0_ARREADY : in STD_LOGIC; + M_AXI_GP0_AWREADY : in STD_LOGIC; + M_AXI_GP0_BVALID : in STD_LOGIC; + M_AXI_GP0_RLAST : in STD_LOGIC; + M_AXI_GP0_RVALID : in STD_LOGIC; + M_AXI_GP0_WREADY : in STD_LOGIC; + M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP1_ARESETN : out STD_LOGIC; + M_AXI_GP1_ARVALID : out STD_LOGIC; + M_AXI_GP1_AWVALID : out STD_LOGIC; + M_AXI_GP1_BREADY : out STD_LOGIC; + M_AXI_GP1_RREADY : out STD_LOGIC; + M_AXI_GP1_WLAST : out STD_LOGIC; + M_AXI_GP1_WVALID : out STD_LOGIC; + M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP1_ACLK : in STD_LOGIC; + M_AXI_GP1_ARREADY : in STD_LOGIC; + M_AXI_GP1_AWREADY : in STD_LOGIC; + M_AXI_GP1_BVALID : in STD_LOGIC; + M_AXI_GP1_RLAST : in STD_LOGIC; + M_AXI_GP1_RVALID : in STD_LOGIC; + M_AXI_GP1_WREADY : in STD_LOGIC; + M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_GP0_ARESETN : out STD_LOGIC; + S_AXI_GP0_ARREADY : out STD_LOGIC; + S_AXI_GP0_AWREADY : out STD_LOGIC; + S_AXI_GP0_BVALID : out STD_LOGIC; + S_AXI_GP0_RLAST : out STD_LOGIC; + S_AXI_GP0_RVALID : out STD_LOGIC; + S_AXI_GP0_WREADY : out STD_LOGIC; + S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_GP0_ACLK : in STD_LOGIC; + S_AXI_GP0_ARVALID : in STD_LOGIC; + S_AXI_GP0_AWVALID : in STD_LOGIC; + S_AXI_GP0_BREADY : in STD_LOGIC; + S_AXI_GP0_RREADY : in STD_LOGIC; + S_AXI_GP0_WLAST : in STD_LOGIC; + S_AXI_GP0_WVALID : in STD_LOGIC; + S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_GP1_ARESETN : out STD_LOGIC; + S_AXI_GP1_ARREADY : out STD_LOGIC; + S_AXI_GP1_AWREADY : out STD_LOGIC; + S_AXI_GP1_BVALID : out STD_LOGIC; + S_AXI_GP1_RLAST : out STD_LOGIC; + S_AXI_GP1_RVALID : out STD_LOGIC; + S_AXI_GP1_WREADY : out STD_LOGIC; + S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_GP1_ACLK : in STD_LOGIC; + S_AXI_GP1_ARVALID : in STD_LOGIC; + S_AXI_GP1_AWVALID : in STD_LOGIC; + S_AXI_GP1_BREADY : in STD_LOGIC; + S_AXI_GP1_RREADY : in STD_LOGIC; + S_AXI_GP1_WLAST : in STD_LOGIC; + S_AXI_GP1_WVALID : in STD_LOGIC; + S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_ACP_ARESETN : out STD_LOGIC; + S_AXI_ACP_ARREADY : out STD_LOGIC; + S_AXI_ACP_AWREADY : out STD_LOGIC; + S_AXI_ACP_BVALID : out STD_LOGIC; + S_AXI_ACP_RLAST : out STD_LOGIC; + S_AXI_ACP_RVALID : out STD_LOGIC; + S_AXI_ACP_WREADY : out STD_LOGIC; + S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_ACP_ACLK : in STD_LOGIC; + S_AXI_ACP_ARVALID : in STD_LOGIC; + S_AXI_ACP_AWVALID : in STD_LOGIC; + S_AXI_ACP_BREADY : in STD_LOGIC; + S_AXI_ACP_RREADY : in STD_LOGIC; + S_AXI_ACP_WLAST : in STD_LOGIC; + S_AXI_ACP_WVALID : in STD_LOGIC; + S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 ); + S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 ); + S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP0_ARESETN : out STD_LOGIC; + S_AXI_HP0_ARREADY : out STD_LOGIC; + S_AXI_HP0_AWREADY : out STD_LOGIC; + S_AXI_HP0_BVALID : out STD_LOGIC; + S_AXI_HP0_RLAST : out STD_LOGIC; + S_AXI_HP0_RVALID : out STD_LOGIC; + S_AXI_HP0_WREADY : out STD_LOGIC; + S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_ACLK : in STD_LOGIC; + S_AXI_HP0_ARVALID : in STD_LOGIC; + S_AXI_HP0_AWVALID : in STD_LOGIC; + S_AXI_HP0_BREADY : in STD_LOGIC; + S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC; + S_AXI_HP0_RREADY : in STD_LOGIC; + S_AXI_HP0_WLAST : in STD_LOGIC; + S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC; + S_AXI_HP0_WVALID : in STD_LOGIC; + S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP1_ARESETN : out STD_LOGIC; + S_AXI_HP1_ARREADY : out STD_LOGIC; + S_AXI_HP1_AWREADY : out STD_LOGIC; + S_AXI_HP1_BVALID : out STD_LOGIC; + S_AXI_HP1_RLAST : out STD_LOGIC; + S_AXI_HP1_RVALID : out STD_LOGIC; + S_AXI_HP1_WREADY : out STD_LOGIC; + S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP1_ACLK : in STD_LOGIC; + S_AXI_HP1_ARVALID : in STD_LOGIC; + S_AXI_HP1_AWVALID : in STD_LOGIC; + S_AXI_HP1_BREADY : in STD_LOGIC; + S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC; + S_AXI_HP1_RREADY : in STD_LOGIC; + S_AXI_HP1_WLAST : in STD_LOGIC; + S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC; + S_AXI_HP1_WVALID : in STD_LOGIC; + S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP2_ARESETN : out STD_LOGIC; + S_AXI_HP2_ARREADY : out STD_LOGIC; + S_AXI_HP2_AWREADY : out STD_LOGIC; + S_AXI_HP2_BVALID : out STD_LOGIC; + S_AXI_HP2_RLAST : out STD_LOGIC; + S_AXI_HP2_RVALID : out STD_LOGIC; + S_AXI_HP2_WREADY : out STD_LOGIC; + S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP2_ACLK : in STD_LOGIC; + S_AXI_HP2_ARVALID : in STD_LOGIC; + S_AXI_HP2_AWVALID : in STD_LOGIC; + S_AXI_HP2_BREADY : in STD_LOGIC; + S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC; + S_AXI_HP2_RREADY : in STD_LOGIC; + S_AXI_HP2_WLAST : in STD_LOGIC; + S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC; + S_AXI_HP2_WVALID : in STD_LOGIC; + S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP3_ARESETN : out STD_LOGIC; + S_AXI_HP3_ARREADY : out STD_LOGIC; + S_AXI_HP3_AWREADY : out STD_LOGIC; + S_AXI_HP3_BVALID : out STD_LOGIC; + S_AXI_HP3_RLAST : out STD_LOGIC; + S_AXI_HP3_RVALID : out STD_LOGIC; + S_AXI_HP3_WREADY : out STD_LOGIC; + S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP3_ACLK : in STD_LOGIC; + S_AXI_HP3_ARVALID : in STD_LOGIC; + S_AXI_HP3_AWVALID : in STD_LOGIC; + S_AXI_HP3_BREADY : in STD_LOGIC; + S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC; + S_AXI_HP3_RREADY : in STD_LOGIC; + S_AXI_HP3_WLAST : in STD_LOGIC; + S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC; + S_AXI_HP3_WVALID : in STD_LOGIC; + S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); + IRQ_P2F_DMAC_ABORT : out STD_LOGIC; + IRQ_P2F_DMAC0 : out STD_LOGIC; + IRQ_P2F_DMAC1 : out STD_LOGIC; + IRQ_P2F_DMAC2 : out STD_LOGIC; + IRQ_P2F_DMAC3 : out STD_LOGIC; + IRQ_P2F_DMAC4 : out STD_LOGIC; + IRQ_P2F_DMAC5 : out STD_LOGIC; + IRQ_P2F_DMAC6 : out STD_LOGIC; + IRQ_P2F_DMAC7 : out STD_LOGIC; + IRQ_P2F_SMC : out STD_LOGIC; + IRQ_P2F_QSPI : out STD_LOGIC; + IRQ_P2F_CTI : out STD_LOGIC; + IRQ_P2F_GPIO : out STD_LOGIC; + IRQ_P2F_USB0 : out STD_LOGIC; + IRQ_P2F_ENET0 : out STD_LOGIC; + IRQ_P2F_ENET_WAKE0 : out STD_LOGIC; + IRQ_P2F_SDIO0 : out STD_LOGIC; + IRQ_P2F_I2C0 : out STD_LOGIC; + IRQ_P2F_SPI0 : out STD_LOGIC; + IRQ_P2F_UART0 : out STD_LOGIC; + IRQ_P2F_CAN0 : out STD_LOGIC; + IRQ_P2F_USB1 : out STD_LOGIC; + IRQ_P2F_ENET1 : out STD_LOGIC; + IRQ_P2F_ENET_WAKE1 : out STD_LOGIC; + IRQ_P2F_SDIO1 : out STD_LOGIC; + IRQ_P2F_I2C1 : out STD_LOGIC; + IRQ_P2F_SPI1 : out STD_LOGIC; + IRQ_P2F_UART1 : out STD_LOGIC; + IRQ_P2F_CAN1 : out STD_LOGIC; + IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 ); + Core0_nFIQ : in STD_LOGIC; + Core0_nIRQ : in STD_LOGIC; + Core1_nFIQ : in STD_LOGIC; + Core1_nIRQ : in STD_LOGIC; + DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); + DMA0_DAVALID : out STD_LOGIC; + DMA0_DRREADY : out STD_LOGIC; + DMA0_RSTN : out STD_LOGIC; + DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); + DMA1_DAVALID : out STD_LOGIC; + DMA1_DRREADY : out STD_LOGIC; + DMA1_RSTN : out STD_LOGIC; + DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); + DMA2_DAVALID : out STD_LOGIC; + DMA2_DRREADY : out STD_LOGIC; + DMA2_RSTN : out STD_LOGIC; + DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); + DMA3_DAVALID : out STD_LOGIC; + DMA3_DRREADY : out STD_LOGIC; + DMA3_RSTN : out STD_LOGIC; + DMA0_ACLK : in STD_LOGIC; + DMA0_DAREADY : in STD_LOGIC; + DMA0_DRLAST : in STD_LOGIC; + DMA0_DRVALID : in STD_LOGIC; + DMA1_ACLK : in STD_LOGIC; + DMA1_DAREADY : in STD_LOGIC; + DMA1_DRLAST : in STD_LOGIC; + DMA1_DRVALID : in STD_LOGIC; + DMA2_ACLK : in STD_LOGIC; + DMA2_DAREADY : in STD_LOGIC; + DMA2_DRLAST : in STD_LOGIC; + DMA2_DRVALID : in STD_LOGIC; + DMA3_ACLK : in STD_LOGIC; + DMA3_DAREADY : in STD_LOGIC; + DMA3_DRLAST : in STD_LOGIC; + DMA3_DRVALID : in STD_LOGIC; + DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); + DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); + DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); + DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); + FCLK_CLK3 : out STD_LOGIC; + FCLK_CLK2 : out STD_LOGIC; + FCLK_CLK1 : out STD_LOGIC; + FCLK_CLK0 : out STD_LOGIC; + FCLK_CLKTRIG3_N : in STD_LOGIC; + FCLK_CLKTRIG2_N : in STD_LOGIC; + FCLK_CLKTRIG1_N : in STD_LOGIC; + FCLK_CLKTRIG0_N : in STD_LOGIC; + FCLK_RESET3_N : out STD_LOGIC; + FCLK_RESET2_N : out STD_LOGIC; + FCLK_RESET1_N : out STD_LOGIC; + FCLK_RESET0_N : out STD_LOGIC; + FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + FTMD_TRACEIN_VALID : in STD_LOGIC; + FTMD_TRACEIN_CLK : in STD_LOGIC; + FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 ); + FTMT_F2P_TRIG_0 : in STD_LOGIC; + FTMT_F2P_TRIGACK_0 : out STD_LOGIC; + FTMT_F2P_TRIG_1 : in STD_LOGIC; + FTMT_F2P_TRIGACK_1 : out STD_LOGIC; + FTMT_F2P_TRIG_2 : in STD_LOGIC; + FTMT_F2P_TRIGACK_2 : out STD_LOGIC; + FTMT_F2P_TRIG_3 : in STD_LOGIC; + FTMT_F2P_TRIGACK_3 : out STD_LOGIC; + FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 ); + FTMT_P2F_TRIGACK_0 : in STD_LOGIC; + FTMT_P2F_TRIG_0 : out STD_LOGIC; + FTMT_P2F_TRIGACK_1 : in STD_LOGIC; + FTMT_P2F_TRIG_1 : out STD_LOGIC; + FTMT_P2F_TRIGACK_2 : in STD_LOGIC; + FTMT_P2F_TRIG_2 : out STD_LOGIC; + FTMT_P2F_TRIGACK_3 : in STD_LOGIC; + FTMT_P2F_TRIG_3 : out STD_LOGIC; + FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 ); + FPGA_IDLE_N : in STD_LOGIC; + EVENT_EVENTO : out STD_LOGIC; + EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 ); + EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 ); + EVENT_EVENTI : in STD_LOGIC; + DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 ); + MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); + DDR_CAS_n : inout STD_LOGIC; + DDR_CKE : inout STD_LOGIC; + DDR_Clk_n : inout STD_LOGIC; + DDR_Clk : inout STD_LOGIC; + DDR_CS_n : inout STD_LOGIC; + DDR_DRSTB : inout STD_LOGIC; + DDR_ODT : inout STD_LOGIC; + DDR_RAS_n : inout STD_LOGIC; + DDR_WEB : inout STD_LOGIC; + DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); + DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); + DDR_VRN : inout STD_LOGIC; + DDR_VRP : inout STD_LOGIC; + DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); + DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + PS_SRSTB : inout STD_LOGIC; + PS_CLK : inout STD_LOGIC; + PS_PORB : inout STD_LOGIC + ); + attribute C_DM_WIDTH : integer; + attribute C_DM_WIDTH of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4; + attribute C_DQS_WIDTH : integer; + attribute C_DQS_WIDTH of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4; + attribute C_DQ_WIDTH : integer; + attribute C_DQ_WIDTH of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 32; + attribute C_EMIO_GPIO_WIDTH : integer; + attribute C_EMIO_GPIO_WIDTH of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64; + attribute C_EN_EMIO_ENET0 : integer; + attribute C_EN_EMIO_ENET0 of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_EN_EMIO_ENET1 : integer; + attribute C_EN_EMIO_ENET1 of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_EN_EMIO_PJTAG : integer; + attribute C_EN_EMIO_PJTAG of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_EN_EMIO_TRACE : integer; + attribute C_EN_EMIO_TRACE of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_FCLK_CLK0_BUF : string; + attribute C_FCLK_CLK0_BUF of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "TRUE"; + attribute C_FCLK_CLK1_BUF : string; + attribute C_FCLK_CLK1_BUF of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "TRUE"; + attribute C_FCLK_CLK2_BUF : string; + attribute C_FCLK_CLK2_BUF of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "TRUE"; + attribute C_FCLK_CLK3_BUF : string; + attribute C_FCLK_CLK3_BUF of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "TRUE"; + attribute C_GP0_EN_MODIFIABLE_TXN : integer; + attribute C_GP0_EN_MODIFIABLE_TXN of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1; + attribute C_GP1_EN_MODIFIABLE_TXN : integer; + attribute C_GP1_EN_MODIFIABLE_TXN of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1; + attribute C_INCLUDE_ACP_TRANS_CHECK : integer; + attribute C_INCLUDE_ACP_TRANS_CHECK of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_INCLUDE_TRACE_BUFFER : integer; + attribute C_INCLUDE_TRACE_BUFFER of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_IRQ_F2P_MODE : string; + attribute C_IRQ_F2P_MODE of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "DIRECT"; + attribute C_MIO_PRIMITIVE : integer; + attribute C_MIO_PRIMITIVE of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 54; + attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer; + attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_M_AXI_GP0_ID_WIDTH : integer; + attribute C_M_AXI_GP0_ID_WIDTH of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12; + attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer; + attribute C_M_AXI_GP0_THREAD_ID_WIDTH of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12; + attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer; + attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_M_AXI_GP1_ID_WIDTH : integer; + attribute C_M_AXI_GP1_ID_WIDTH of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12; + attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer; + attribute C_M_AXI_GP1_THREAD_ID_WIDTH of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12; + attribute C_NUM_F2P_INTR_INPUTS : integer; + attribute C_NUM_F2P_INTR_INPUTS of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1; + attribute C_PACKAGE_NAME : string; + attribute C_PACKAGE_NAME of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "ffg676"; + attribute C_PS7_SI_REV : string; + attribute C_PS7_SI_REV of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION"; + attribute C_S_AXI_ACP_ARUSER_VAL : integer; + attribute C_S_AXI_ACP_ARUSER_VAL of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31; + attribute C_S_AXI_ACP_AWUSER_VAL : integer; + attribute C_S_AXI_ACP_AWUSER_VAL of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31; + attribute C_S_AXI_ACP_ID_WIDTH : integer; + attribute C_S_AXI_ACP_ID_WIDTH of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 3; + attribute C_S_AXI_GP0_ID_WIDTH : integer; + attribute C_S_AXI_GP0_ID_WIDTH of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6; + attribute C_S_AXI_GP1_ID_WIDTH : integer; + attribute C_S_AXI_GP1_ID_WIDTH of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6; + attribute C_S_AXI_HP0_DATA_WIDTH : integer; + attribute C_S_AXI_HP0_DATA_WIDTH of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64; + attribute C_S_AXI_HP0_ID_WIDTH : integer; + attribute C_S_AXI_HP0_ID_WIDTH of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6; + attribute C_S_AXI_HP1_DATA_WIDTH : integer; + attribute C_S_AXI_HP1_DATA_WIDTH of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64; + attribute C_S_AXI_HP1_ID_WIDTH : integer; + attribute C_S_AXI_HP1_ID_WIDTH of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6; + attribute C_S_AXI_HP2_DATA_WIDTH : integer; + attribute C_S_AXI_HP2_DATA_WIDTH of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64; + attribute C_S_AXI_HP2_ID_WIDTH : integer; + attribute C_S_AXI_HP2_ID_WIDTH of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6; + attribute C_S_AXI_HP3_DATA_WIDTH : integer; + attribute C_S_AXI_HP3_DATA_WIDTH of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64; + attribute C_S_AXI_HP3_ID_WIDTH : integer; + attribute C_S_AXI_HP3_ID_WIDTH of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6; + attribute C_TRACE_BUFFER_CLOCK_DELAY : integer; + attribute C_TRACE_BUFFER_CLOCK_DELAY of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12; + attribute C_TRACE_BUFFER_FIFO_SIZE : integer; + attribute C_TRACE_BUFFER_FIFO_SIZE of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 128; + attribute C_TRACE_INTERNAL_WIDTH : integer; + attribute C_TRACE_INTERNAL_WIDTH of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 2; + attribute C_TRACE_PIPELINE_WIDTH : integer; + attribute C_TRACE_PIPELINE_WIDTH of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 8; + attribute C_USE_AXI_NONSECURE : integer; + attribute C_USE_AXI_NONSECURE of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_USE_DEFAULT_ACP_USER_VAL : integer; + attribute C_USE_DEFAULT_ACP_USER_VAL of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_USE_M_AXI_GP0 : integer; + attribute C_USE_M_AXI_GP0 of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1; + attribute C_USE_M_AXI_GP1 : integer; + attribute C_USE_M_AXI_GP1 of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_USE_S_AXI_ACP : integer; + attribute C_USE_S_AXI_ACP of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_USE_S_AXI_GP0 : integer; + attribute C_USE_S_AXI_GP0 of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_USE_S_AXI_GP1 : integer; + attribute C_USE_S_AXI_GP1 of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_USE_S_AXI_HP0 : integer; + attribute C_USE_S_AXI_HP0 of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_USE_S_AXI_HP1 : integer; + attribute C_USE_S_AXI_HP1 of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_USE_S_AXI_HP2 : integer; + attribute C_USE_S_AXI_HP2 of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_USE_S_AXI_HP3 : integer; + attribute C_USE_S_AXI_HP3 of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0; + attribute HW_HANDOFF : string; + attribute HW_HANDOFF of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "NewExtInst_TOP_processing_system7_0_0.hwdef"; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "processing_system7_v5_5_processing_system7"; + attribute POWER : string; + attribute POWER of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "/>"; + attribute USE_TRACE_DATA_EDGE_DETECTOR : integer; + attribute USE_TRACE_DATA_EDGE_DETECTOR of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0; +end NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7; + +architecture STRUCTURE of NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 is + signal \\ : STD_LOGIC; + signal ENET0_MDIO_T_n : STD_LOGIC; + signal ENET1_MDIO_T_n : STD_LOGIC; + signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal I2C0_SCL_T_n : STD_LOGIC; + signal I2C0_SDA_T_n : STD_LOGIC; + signal I2C1_SCL_T_n : STD_LOGIC; + signal I2C1_SDA_T_n : STD_LOGIC; + signal \^m_axi_gp0_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^m_axi_gp0_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal PS7_i_n_0 : STD_LOGIC; + signal PS7_i_n_1 : STD_LOGIC; + signal PS7_i_n_10 : STD_LOGIC; + signal PS7_i_n_100 : STD_LOGIC; + signal PS7_i_n_1001 : STD_LOGIC; + signal PS7_i_n_1002 : STD_LOGIC; + signal PS7_i_n_1003 : STD_LOGIC; + signal PS7_i_n_1004 : STD_LOGIC; + signal PS7_i_n_1005 : STD_LOGIC; + signal PS7_i_n_1006 : STD_LOGIC; + signal PS7_i_n_1007 : STD_LOGIC; + signal PS7_i_n_1008 : STD_LOGIC; + signal PS7_i_n_1009 : STD_LOGIC; + signal PS7_i_n_101 : STD_LOGIC; + signal PS7_i_n_1010 : STD_LOGIC; + signal PS7_i_n_1011 : STD_LOGIC; + signal PS7_i_n_1012 : STD_LOGIC; + signal PS7_i_n_1013 : STD_LOGIC; + signal PS7_i_n_1014 : STD_LOGIC; + signal PS7_i_n_1015 : STD_LOGIC; + signal PS7_i_n_1016 : STD_LOGIC; + signal PS7_i_n_1017 : STD_LOGIC; + signal PS7_i_n_1018 : STD_LOGIC; + signal PS7_i_n_1019 : STD_LOGIC; + signal PS7_i_n_102 : STD_LOGIC; + signal PS7_i_n_1020 : STD_LOGIC; + signal PS7_i_n_1021 : STD_LOGIC; + signal PS7_i_n_1022 : STD_LOGIC; + signal PS7_i_n_1023 : STD_LOGIC; + signal PS7_i_n_1024 : STD_LOGIC; + signal PS7_i_n_1025 : STD_LOGIC; + signal PS7_i_n_1026 : STD_LOGIC; + signal PS7_i_n_1027 : STD_LOGIC; + signal PS7_i_n_1028 : STD_LOGIC; + signal PS7_i_n_1029 : STD_LOGIC; + signal PS7_i_n_103 : STD_LOGIC; + signal PS7_i_n_1030 : STD_LOGIC; + signal PS7_i_n_1031 : STD_LOGIC; + signal PS7_i_n_1032 : STD_LOGIC; + signal PS7_i_n_1033 : STD_LOGIC; + signal PS7_i_n_1034 : STD_LOGIC; + signal PS7_i_n_1035 : STD_LOGIC; + signal PS7_i_n_1036 : STD_LOGIC; + signal PS7_i_n_1037 : STD_LOGIC; + signal PS7_i_n_1038 : STD_LOGIC; + signal PS7_i_n_1039 : STD_LOGIC; + signal PS7_i_n_104 : STD_LOGIC; + signal PS7_i_n_1040 : STD_LOGIC; + signal PS7_i_n_1041 : STD_LOGIC; + signal PS7_i_n_1042 : STD_LOGIC; + signal PS7_i_n_1043 : STD_LOGIC; + signal PS7_i_n_1044 : STD_LOGIC; + signal PS7_i_n_1045 : STD_LOGIC; + signal PS7_i_n_1046 : STD_LOGIC; + signal PS7_i_n_1047 : STD_LOGIC; + signal PS7_i_n_1048 : STD_LOGIC; + signal PS7_i_n_1049 : STD_LOGIC; + signal PS7_i_n_105 : STD_LOGIC; + signal PS7_i_n_1050 : STD_LOGIC; + signal PS7_i_n_1051 : STD_LOGIC; + signal PS7_i_n_1052 : STD_LOGIC; + signal PS7_i_n_1053 : STD_LOGIC; + signal PS7_i_n_1054 : STD_LOGIC; + signal PS7_i_n_1055 : STD_LOGIC; + signal PS7_i_n_1056 : STD_LOGIC; + signal PS7_i_n_1057 : STD_LOGIC; + signal PS7_i_n_1058 : STD_LOGIC; + signal PS7_i_n_1059 : STD_LOGIC; + signal PS7_i_n_106 : STD_LOGIC; + signal PS7_i_n_1060 : STD_LOGIC; + signal PS7_i_n_1061 : STD_LOGIC; + signal PS7_i_n_1062 : STD_LOGIC; + signal PS7_i_n_1063 : STD_LOGIC; + signal PS7_i_n_1064 : STD_LOGIC; + signal PS7_i_n_1065 : STD_LOGIC; + signal PS7_i_n_1066 : STD_LOGIC; + signal PS7_i_n_1067 : STD_LOGIC; + signal PS7_i_n_1068 : STD_LOGIC; + signal PS7_i_n_1069 : STD_LOGIC; + signal PS7_i_n_107 : STD_LOGIC; + signal PS7_i_n_1070 : STD_LOGIC; + signal PS7_i_n_1071 : STD_LOGIC; + signal PS7_i_n_1072 : STD_LOGIC; + signal PS7_i_n_1073 : STD_LOGIC; + signal PS7_i_n_1074 : STD_LOGIC; + signal PS7_i_n_1075 : STD_LOGIC; + signal PS7_i_n_1076 : STD_LOGIC; + signal PS7_i_n_1077 : STD_LOGIC; + signal PS7_i_n_1078 : STD_LOGIC; + signal PS7_i_n_1079 : STD_LOGIC; + signal PS7_i_n_108 : STD_LOGIC; + signal PS7_i_n_1080 : STD_LOGIC; + signal PS7_i_n_1081 : STD_LOGIC; + signal PS7_i_n_1082 : STD_LOGIC; + signal PS7_i_n_1083 : STD_LOGIC; + signal PS7_i_n_1084 : STD_LOGIC; + signal PS7_i_n_1085 : STD_LOGIC; + signal PS7_i_n_1086 : STD_LOGIC; + signal PS7_i_n_1087 : STD_LOGIC; + signal PS7_i_n_1088 : STD_LOGIC; + signal PS7_i_n_1089 : STD_LOGIC; + signal PS7_i_n_109 : STD_LOGIC; + signal PS7_i_n_1090 : STD_LOGIC; + signal PS7_i_n_1091 : STD_LOGIC; + signal PS7_i_n_1092 : STD_LOGIC; + signal PS7_i_n_1093 : STD_LOGIC; + signal PS7_i_n_1094 : STD_LOGIC; + signal PS7_i_n_1095 : STD_LOGIC; + signal PS7_i_n_1096 : STD_LOGIC; + signal PS7_i_n_1097 : STD_LOGIC; + signal PS7_i_n_1098 : STD_LOGIC; + signal PS7_i_n_1099 : STD_LOGIC; + signal PS7_i_n_11 : STD_LOGIC; + signal PS7_i_n_110 : STD_LOGIC; + signal PS7_i_n_1100 : STD_LOGIC; + signal PS7_i_n_1101 : STD_LOGIC; + signal PS7_i_n_1102 : STD_LOGIC; + signal PS7_i_n_1103 : STD_LOGIC; + signal PS7_i_n_1104 : STD_LOGIC; + signal PS7_i_n_1105 : STD_LOGIC; + signal PS7_i_n_1106 : STD_LOGIC; + signal PS7_i_n_1107 : STD_LOGIC; + signal PS7_i_n_1108 : STD_LOGIC; + signal PS7_i_n_1109 : STD_LOGIC; + signal PS7_i_n_111 : STD_LOGIC; + signal PS7_i_n_1110 : STD_LOGIC; + signal PS7_i_n_1111 : STD_LOGIC; + signal PS7_i_n_1112 : STD_LOGIC; + signal PS7_i_n_1113 : STD_LOGIC; + signal PS7_i_n_1114 : STD_LOGIC; + signal PS7_i_n_1115 : STD_LOGIC; + signal PS7_i_n_1116 : STD_LOGIC; + signal PS7_i_n_1117 : STD_LOGIC; + signal PS7_i_n_1118 : STD_LOGIC; + signal PS7_i_n_1119 : STD_LOGIC; + signal PS7_i_n_112 : STD_LOGIC; + signal PS7_i_n_1120 : STD_LOGIC; + signal PS7_i_n_1121 : STD_LOGIC; + signal PS7_i_n_1122 : STD_LOGIC; + signal PS7_i_n_1123 : STD_LOGIC; + signal PS7_i_n_1124 : STD_LOGIC; + signal PS7_i_n_1125 : STD_LOGIC; + signal PS7_i_n_1126 : STD_LOGIC; + signal PS7_i_n_1127 : STD_LOGIC; + signal PS7_i_n_1128 : STD_LOGIC; + signal PS7_i_n_1129 : STD_LOGIC; + signal PS7_i_n_113 : STD_LOGIC; + signal PS7_i_n_1130 : STD_LOGIC; + signal PS7_i_n_1131 : STD_LOGIC; + signal PS7_i_n_1132 : STD_LOGIC; + signal PS7_i_n_1133 : STD_LOGIC; + signal PS7_i_n_1134 : STD_LOGIC; + signal PS7_i_n_1135 : STD_LOGIC; + signal PS7_i_n_1136 : STD_LOGIC; + signal PS7_i_n_1137 : STD_LOGIC; + signal PS7_i_n_1138 : STD_LOGIC; + signal PS7_i_n_1139 : STD_LOGIC; + signal PS7_i_n_114 : STD_LOGIC; + signal PS7_i_n_1140 : STD_LOGIC; + signal PS7_i_n_1141 : STD_LOGIC; + signal PS7_i_n_1142 : STD_LOGIC; + signal PS7_i_n_1143 : STD_LOGIC; + signal PS7_i_n_1144 : STD_LOGIC; + signal PS7_i_n_1145 : STD_LOGIC; + signal PS7_i_n_1146 : STD_LOGIC; + signal PS7_i_n_1147 : STD_LOGIC; + signal PS7_i_n_1148 : STD_LOGIC; + signal PS7_i_n_1149 : STD_LOGIC; + signal PS7_i_n_115 : STD_LOGIC; + signal PS7_i_n_1150 : STD_LOGIC; + signal PS7_i_n_1151 : STD_LOGIC; + signal PS7_i_n_1152 : STD_LOGIC; + signal PS7_i_n_1153 : STD_LOGIC; + signal PS7_i_n_1154 : STD_LOGIC; + signal PS7_i_n_1155 : STD_LOGIC; + signal PS7_i_n_1156 : STD_LOGIC; + signal PS7_i_n_1157 : STD_LOGIC; + signal PS7_i_n_1158 : STD_LOGIC; + signal PS7_i_n_1159 : STD_LOGIC; + signal PS7_i_n_116 : STD_LOGIC; + signal PS7_i_n_1160 : STD_LOGIC; + signal PS7_i_n_1161 : STD_LOGIC; + signal PS7_i_n_1162 : STD_LOGIC; + signal PS7_i_n_1163 : STD_LOGIC; + signal PS7_i_n_1164 : STD_LOGIC; + signal PS7_i_n_1165 : STD_LOGIC; + signal PS7_i_n_1166 : STD_LOGIC; + signal PS7_i_n_1167 : STD_LOGIC; + signal PS7_i_n_1168 : STD_LOGIC; + signal PS7_i_n_1169 : STD_LOGIC; + signal PS7_i_n_117 : STD_LOGIC; + signal PS7_i_n_1170 : STD_LOGIC; + signal PS7_i_n_1171 : STD_LOGIC; + signal PS7_i_n_1172 : STD_LOGIC; + signal PS7_i_n_1173 : STD_LOGIC; + signal PS7_i_n_1174 : STD_LOGIC; + signal PS7_i_n_1175 : STD_LOGIC; + signal PS7_i_n_1176 : STD_LOGIC; + signal PS7_i_n_1177 : STD_LOGIC; + signal PS7_i_n_1178 : STD_LOGIC; + signal PS7_i_n_1179 : STD_LOGIC; + signal PS7_i_n_118 : STD_LOGIC; + signal PS7_i_n_1180 : STD_LOGIC; + signal PS7_i_n_1181 : STD_LOGIC; + signal PS7_i_n_1182 : STD_LOGIC; + signal PS7_i_n_1183 : STD_LOGIC; + signal PS7_i_n_1184 : STD_LOGIC; + signal PS7_i_n_1185 : STD_LOGIC; + signal PS7_i_n_1186 : STD_LOGIC; + signal PS7_i_n_1187 : STD_LOGIC; + signal PS7_i_n_1188 : STD_LOGIC; + signal PS7_i_n_1189 : STD_LOGIC; + signal PS7_i_n_119 : STD_LOGIC; + signal PS7_i_n_1190 : STD_LOGIC; + signal PS7_i_n_1191 : STD_LOGIC; + signal PS7_i_n_1192 : STD_LOGIC; + signal PS7_i_n_1193 : STD_LOGIC; + signal PS7_i_n_1194 : STD_LOGIC; + signal PS7_i_n_1195 : STD_LOGIC; + signal PS7_i_n_1196 : STD_LOGIC; + signal PS7_i_n_1197 : STD_LOGIC; + signal PS7_i_n_1198 : STD_LOGIC; + signal PS7_i_n_1199 : STD_LOGIC; + signal PS7_i_n_12 : STD_LOGIC; + signal PS7_i_n_120 : STD_LOGIC; + signal PS7_i_n_1200 : STD_LOGIC; + signal PS7_i_n_1201 : STD_LOGIC; + signal PS7_i_n_1202 : STD_LOGIC; + signal PS7_i_n_1203 : STD_LOGIC; + signal PS7_i_n_1204 : STD_LOGIC; + signal PS7_i_n_1205 : STD_LOGIC; + signal PS7_i_n_1206 : STD_LOGIC; + signal PS7_i_n_1207 : STD_LOGIC; + signal PS7_i_n_1208 : STD_LOGIC; + signal PS7_i_n_1209 : STD_LOGIC; + signal PS7_i_n_121 : STD_LOGIC; + signal PS7_i_n_1210 : STD_LOGIC; + signal PS7_i_n_1211 : STD_LOGIC; + signal PS7_i_n_1212 : STD_LOGIC; + signal PS7_i_n_1213 : STD_LOGIC; + signal PS7_i_n_1214 : STD_LOGIC; + signal PS7_i_n_1215 : STD_LOGIC; + signal PS7_i_n_1216 : STD_LOGIC; + signal PS7_i_n_1217 : STD_LOGIC; + signal PS7_i_n_1218 : STD_LOGIC; + signal PS7_i_n_1219 : STD_LOGIC; + signal PS7_i_n_122 : STD_LOGIC; + signal PS7_i_n_1220 : STD_LOGIC; + signal PS7_i_n_1221 : STD_LOGIC; + signal PS7_i_n_1222 : STD_LOGIC; + signal PS7_i_n_1223 : STD_LOGIC; + signal PS7_i_n_1224 : STD_LOGIC; + signal PS7_i_n_1225 : STD_LOGIC; + signal PS7_i_n_1226 : STD_LOGIC; + signal PS7_i_n_1227 : STD_LOGIC; + signal PS7_i_n_1228 : STD_LOGIC; + signal PS7_i_n_1229 : STD_LOGIC; + signal PS7_i_n_123 : STD_LOGIC; + signal PS7_i_n_1230 : STD_LOGIC; + signal PS7_i_n_1231 : STD_LOGIC; + signal PS7_i_n_1232 : STD_LOGIC; + signal PS7_i_n_1233 : STD_LOGIC; + signal PS7_i_n_1234 : STD_LOGIC; + signal PS7_i_n_1235 : STD_LOGIC; + signal PS7_i_n_1236 : STD_LOGIC; + signal PS7_i_n_1237 : STD_LOGIC; + signal PS7_i_n_1238 : STD_LOGIC; + signal PS7_i_n_1239 : STD_LOGIC; + signal PS7_i_n_124 : STD_LOGIC; + signal PS7_i_n_1240 : STD_LOGIC; + signal PS7_i_n_1241 : STD_LOGIC; + signal PS7_i_n_1242 : STD_LOGIC; + signal PS7_i_n_1243 : STD_LOGIC; + signal PS7_i_n_1244 : STD_LOGIC; + signal PS7_i_n_1245 : STD_LOGIC; + signal PS7_i_n_1246 : STD_LOGIC; + signal PS7_i_n_1247 : STD_LOGIC; + signal PS7_i_n_1248 : STD_LOGIC; + signal PS7_i_n_1249 : STD_LOGIC; + signal PS7_i_n_125 : STD_LOGIC; + signal PS7_i_n_1250 : STD_LOGIC; + signal PS7_i_n_1251 : STD_LOGIC; + signal PS7_i_n_1252 : STD_LOGIC; + signal PS7_i_n_1253 : STD_LOGIC; + signal PS7_i_n_1254 : STD_LOGIC; + signal PS7_i_n_1255 : STD_LOGIC; + signal PS7_i_n_1256 : STD_LOGIC; + signal PS7_i_n_1257 : STD_LOGIC; + signal PS7_i_n_1258 : STD_LOGIC; + signal PS7_i_n_1259 : STD_LOGIC; + signal PS7_i_n_126 : STD_LOGIC; + signal PS7_i_n_1260 : STD_LOGIC; + signal PS7_i_n_1261 : STD_LOGIC; + signal PS7_i_n_1262 : STD_LOGIC; + signal PS7_i_n_1263 : STD_LOGIC; + signal PS7_i_n_1264 : STD_LOGIC; + signal PS7_i_n_1265 : STD_LOGIC; + signal PS7_i_n_1266 : STD_LOGIC; + signal PS7_i_n_1267 : STD_LOGIC; + signal PS7_i_n_1268 : STD_LOGIC; + signal PS7_i_n_1269 : STD_LOGIC; + signal PS7_i_n_127 : STD_LOGIC; + signal PS7_i_n_1270 : STD_LOGIC; + signal PS7_i_n_1271 : STD_LOGIC; + signal PS7_i_n_1272 : STD_LOGIC; + signal PS7_i_n_1273 : STD_LOGIC; + signal PS7_i_n_1274 : STD_LOGIC; + signal PS7_i_n_1275 : STD_LOGIC; + signal PS7_i_n_1276 : STD_LOGIC; + signal PS7_i_n_1277 : STD_LOGIC; + signal PS7_i_n_1278 : STD_LOGIC; + signal PS7_i_n_1279 : STD_LOGIC; + signal PS7_i_n_128 : STD_LOGIC; + signal PS7_i_n_1280 : STD_LOGIC; + signal PS7_i_n_1281 : STD_LOGIC; + signal PS7_i_n_1282 : STD_LOGIC; + signal PS7_i_n_1283 : STD_LOGIC; + signal PS7_i_n_1284 : STD_LOGIC; + signal PS7_i_n_1285 : STD_LOGIC; + signal PS7_i_n_1286 : STD_LOGIC; + signal PS7_i_n_1287 : STD_LOGIC; + signal PS7_i_n_1288 : STD_LOGIC; + signal PS7_i_n_1289 : STD_LOGIC; + signal PS7_i_n_129 : STD_LOGIC; + signal PS7_i_n_1290 : STD_LOGIC; + signal PS7_i_n_1291 : STD_LOGIC; + signal PS7_i_n_1292 : STD_LOGIC; + signal PS7_i_n_1293 : STD_LOGIC; + signal PS7_i_n_1294 : STD_LOGIC; + signal PS7_i_n_1295 : STD_LOGIC; + signal PS7_i_n_1296 : STD_LOGIC; + signal PS7_i_n_1297 : STD_LOGIC; + signal PS7_i_n_1298 : STD_LOGIC; + signal PS7_i_n_1299 : STD_LOGIC; + signal PS7_i_n_13 : STD_LOGIC; + signal PS7_i_n_130 : STD_LOGIC; + signal PS7_i_n_1300 : STD_LOGIC; + signal PS7_i_n_1301 : STD_LOGIC; + signal PS7_i_n_1302 : STD_LOGIC; + signal PS7_i_n_1303 : STD_LOGIC; + signal PS7_i_n_1304 : STD_LOGIC; + signal PS7_i_n_1305 : STD_LOGIC; + signal PS7_i_n_1306 : STD_LOGIC; + signal PS7_i_n_1307 : STD_LOGIC; + signal PS7_i_n_1308 : STD_LOGIC; + signal PS7_i_n_1309 : STD_LOGIC; + signal PS7_i_n_131 : STD_LOGIC; + signal PS7_i_n_1310 : STD_LOGIC; + signal PS7_i_n_1311 : STD_LOGIC; + signal PS7_i_n_1312 : STD_LOGIC; + signal PS7_i_n_1313 : STD_LOGIC; + signal PS7_i_n_1314 : STD_LOGIC; + signal PS7_i_n_1315 : STD_LOGIC; + signal PS7_i_n_1316 : STD_LOGIC; + signal PS7_i_n_1317 : STD_LOGIC; + signal PS7_i_n_1318 : STD_LOGIC; + signal PS7_i_n_1319 : STD_LOGIC; + signal PS7_i_n_132 : STD_LOGIC; + signal PS7_i_n_1320 : STD_LOGIC; + signal PS7_i_n_133 : STD_LOGIC; + signal PS7_i_n_1337 : STD_LOGIC; + signal PS7_i_n_1338 : STD_LOGIC; + signal PS7_i_n_1339 : STD_LOGIC; + signal PS7_i_n_134 : STD_LOGIC; + signal PS7_i_n_1340 : STD_LOGIC; + signal PS7_i_n_1341 : STD_LOGIC; + signal PS7_i_n_1342 : STD_LOGIC; + signal PS7_i_n_1343 : STD_LOGIC; + signal PS7_i_n_1344 : STD_LOGIC; + signal PS7_i_n_1345 : STD_LOGIC; + signal PS7_i_n_1346 : STD_LOGIC; + signal PS7_i_n_1347 : STD_LOGIC; + signal PS7_i_n_1348 : STD_LOGIC; + signal PS7_i_n_1349 : STD_LOGIC; + signal PS7_i_n_135 : STD_LOGIC; + signal PS7_i_n_1350 : STD_LOGIC; + signal PS7_i_n_1351 : STD_LOGIC; + signal PS7_i_n_1352 : STD_LOGIC; + signal PS7_i_n_1353 : STD_LOGIC; + signal PS7_i_n_1354 : STD_LOGIC; + signal PS7_i_n_1355 : STD_LOGIC; + signal PS7_i_n_1356 : STD_LOGIC; + signal PS7_i_n_1357 : STD_LOGIC; + signal PS7_i_n_1358 : STD_LOGIC; + signal PS7_i_n_1359 : STD_LOGIC; + signal PS7_i_n_136 : STD_LOGIC; + signal PS7_i_n_1360 : STD_LOGIC; + signal PS7_i_n_1361 : STD_LOGIC; + signal PS7_i_n_1362 : STD_LOGIC; + signal PS7_i_n_1363 : STD_LOGIC; + signal PS7_i_n_1364 : STD_LOGIC; + signal PS7_i_n_1365 : STD_LOGIC; + signal PS7_i_n_1366 : STD_LOGIC; + signal PS7_i_n_1367 : STD_LOGIC; + signal PS7_i_n_1368 : STD_LOGIC; + signal PS7_i_n_1369 : STD_LOGIC; + signal PS7_i_n_137 : STD_LOGIC; + signal PS7_i_n_1370 : STD_LOGIC; + signal PS7_i_n_1371 : STD_LOGIC; + signal PS7_i_n_1372 : STD_LOGIC; + signal PS7_i_n_1373 : STD_LOGIC; + signal PS7_i_n_1374 : STD_LOGIC; + signal PS7_i_n_1375 : STD_LOGIC; + signal PS7_i_n_1376 : STD_LOGIC; + signal PS7_i_n_1377 : STD_LOGIC; + signal PS7_i_n_1378 : STD_LOGIC; + signal PS7_i_n_1379 : STD_LOGIC; + signal PS7_i_n_138 : STD_LOGIC; + signal PS7_i_n_1380 : STD_LOGIC; + signal PS7_i_n_1381 : STD_LOGIC; + signal PS7_i_n_1382 : STD_LOGIC; + signal PS7_i_n_1383 : STD_LOGIC; + signal PS7_i_n_1384 : STD_LOGIC; + signal PS7_i_n_1385 : STD_LOGIC; + signal PS7_i_n_1386 : STD_LOGIC; + signal PS7_i_n_1387 : STD_LOGIC; + signal PS7_i_n_1388 : STD_LOGIC; + signal PS7_i_n_1389 : STD_LOGIC; + signal PS7_i_n_139 : STD_LOGIC; + signal PS7_i_n_1390 : STD_LOGIC; + signal PS7_i_n_1391 : STD_LOGIC; + signal PS7_i_n_1392 : STD_LOGIC; + signal PS7_i_n_1393 : STD_LOGIC; + signal PS7_i_n_1394 : STD_LOGIC; + signal PS7_i_n_1395 : STD_LOGIC; + signal PS7_i_n_1396 : STD_LOGIC; + signal PS7_i_n_1397 : STD_LOGIC; + signal PS7_i_n_1398 : STD_LOGIC; + signal PS7_i_n_1399 : STD_LOGIC; + signal PS7_i_n_140 : STD_LOGIC; + signal PS7_i_n_1400 : STD_LOGIC; + signal PS7_i_n_141 : STD_LOGIC; + signal PS7_i_n_142 : STD_LOGIC; + signal PS7_i_n_143 : STD_LOGIC; + signal PS7_i_n_144 : STD_LOGIC; + signal PS7_i_n_145 : STD_LOGIC; + signal PS7_i_n_146 : STD_LOGIC; + signal PS7_i_n_147 : STD_LOGIC; + signal PS7_i_n_148 : STD_LOGIC; + signal PS7_i_n_149 : STD_LOGIC; + signal PS7_i_n_150 : STD_LOGIC; + signal PS7_i_n_151 : STD_LOGIC; + signal PS7_i_n_16 : STD_LOGIC; + signal PS7_i_n_17 : STD_LOGIC; + signal PS7_i_n_188 : STD_LOGIC; + signal PS7_i_n_189 : STD_LOGIC; + signal PS7_i_n_19 : STD_LOGIC; + signal PS7_i_n_190 : STD_LOGIC; + signal PS7_i_n_191 : STD_LOGIC; + signal PS7_i_n_192 : STD_LOGIC; + signal PS7_i_n_193 : STD_LOGIC; + signal PS7_i_n_194 : STD_LOGIC; + signal PS7_i_n_195 : STD_LOGIC; + signal PS7_i_n_196 : STD_LOGIC; + signal PS7_i_n_197 : STD_LOGIC; + signal PS7_i_n_198 : STD_LOGIC; + signal PS7_i_n_199 : STD_LOGIC; + signal PS7_i_n_2 : STD_LOGIC; + signal PS7_i_n_20 : STD_LOGIC; + signal PS7_i_n_200 : STD_LOGIC; + signal PS7_i_n_201 : STD_LOGIC; + signal PS7_i_n_202 : STD_LOGIC; + signal PS7_i_n_203 : STD_LOGIC; + signal PS7_i_n_204 : STD_LOGIC; + signal PS7_i_n_205 : STD_LOGIC; + signal PS7_i_n_206 : STD_LOGIC; + signal PS7_i_n_207 : STD_LOGIC; + signal PS7_i_n_208 : STD_LOGIC; + signal PS7_i_n_209 : STD_LOGIC; + signal PS7_i_n_21 : STD_LOGIC; + signal PS7_i_n_210 : STD_LOGIC; + signal PS7_i_n_211 : STD_LOGIC; + signal PS7_i_n_212 : STD_LOGIC; + signal PS7_i_n_213 : STD_LOGIC; + signal PS7_i_n_214 : STD_LOGIC; + signal PS7_i_n_215 : STD_LOGIC; + signal PS7_i_n_216 : STD_LOGIC; + signal PS7_i_n_217 : STD_LOGIC; + signal PS7_i_n_218 : STD_LOGIC; + signal PS7_i_n_219 : STD_LOGIC; + signal PS7_i_n_22 : STD_LOGIC; + signal PS7_i_n_220 : STD_LOGIC; + signal PS7_i_n_221 : STD_LOGIC; + signal PS7_i_n_222 : STD_LOGIC; + signal PS7_i_n_223 : STD_LOGIC; + signal PS7_i_n_224 : STD_LOGIC; + signal PS7_i_n_225 : STD_LOGIC; + signal PS7_i_n_226 : STD_LOGIC; + signal PS7_i_n_227 : STD_LOGIC; + signal PS7_i_n_228 : STD_LOGIC; + signal PS7_i_n_229 : STD_LOGIC; + signal PS7_i_n_23 : STD_LOGIC; + signal PS7_i_n_230 : STD_LOGIC; + signal PS7_i_n_231 : STD_LOGIC; + signal PS7_i_n_232 : STD_LOGIC; + signal PS7_i_n_233 : STD_LOGIC; + signal PS7_i_n_234 : STD_LOGIC; + signal PS7_i_n_235 : STD_LOGIC; + signal PS7_i_n_236 : STD_LOGIC; + signal PS7_i_n_237 : STD_LOGIC; + signal PS7_i_n_238 : STD_LOGIC; + signal PS7_i_n_239 : STD_LOGIC; + signal PS7_i_n_24 : STD_LOGIC; + signal PS7_i_n_25 : STD_LOGIC; + signal PS7_i_n_252 : STD_LOGIC; + signal PS7_i_n_253 : STD_LOGIC; + signal PS7_i_n_254 : STD_LOGIC; + signal PS7_i_n_255 : STD_LOGIC; + signal PS7_i_n_256 : STD_LOGIC; + signal PS7_i_n_257 : STD_LOGIC; + signal PS7_i_n_258 : STD_LOGIC; + signal PS7_i_n_259 : STD_LOGIC; + signal PS7_i_n_26 : STD_LOGIC; + signal PS7_i_n_260 : STD_LOGIC; + signal PS7_i_n_261 : STD_LOGIC; + signal PS7_i_n_262 : STD_LOGIC; + signal PS7_i_n_263 : STD_LOGIC; + signal PS7_i_n_264 : STD_LOGIC; + signal PS7_i_n_265 : STD_LOGIC; + signal PS7_i_n_266 : STD_LOGIC; + signal PS7_i_n_267 : STD_LOGIC; + signal PS7_i_n_268 : STD_LOGIC; + signal PS7_i_n_269 : STD_LOGIC; + signal PS7_i_n_27 : STD_LOGIC; + signal PS7_i_n_270 : STD_LOGIC; + signal PS7_i_n_271 : STD_LOGIC; + signal PS7_i_n_272 : STD_LOGIC; + signal PS7_i_n_273 : STD_LOGIC; + signal PS7_i_n_274 : STD_LOGIC; + signal PS7_i_n_275 : STD_LOGIC; + signal PS7_i_n_276 : STD_LOGIC; + signal PS7_i_n_277 : STD_LOGIC; + signal PS7_i_n_278 : STD_LOGIC; + signal PS7_i_n_279 : STD_LOGIC; + signal PS7_i_n_28 : STD_LOGIC; + signal PS7_i_n_280 : STD_LOGIC; + signal PS7_i_n_281 : STD_LOGIC; + signal PS7_i_n_282 : STD_LOGIC; + signal PS7_i_n_283 : STD_LOGIC; + signal PS7_i_n_284 : STD_LOGIC; + signal PS7_i_n_285 : STD_LOGIC; + signal PS7_i_n_286 : STD_LOGIC; + signal PS7_i_n_287 : STD_LOGIC; + signal PS7_i_n_288 : STD_LOGIC; + signal PS7_i_n_289 : STD_LOGIC; + signal PS7_i_n_290 : STD_LOGIC; + signal PS7_i_n_291 : STD_LOGIC; + signal PS7_i_n_292 : STD_LOGIC; + signal PS7_i_n_293 : STD_LOGIC; + signal PS7_i_n_294 : STD_LOGIC; + signal PS7_i_n_295 : STD_LOGIC; + signal PS7_i_n_296 : STD_LOGIC; + signal PS7_i_n_297 : STD_LOGIC; + signal PS7_i_n_298 : STD_LOGIC; + signal PS7_i_n_299 : STD_LOGIC; + signal PS7_i_n_3 : STD_LOGIC; + signal PS7_i_n_300 : STD_LOGIC; + signal PS7_i_n_301 : STD_LOGIC; + signal PS7_i_n_302 : STD_LOGIC; + signal PS7_i_n_303 : STD_LOGIC; + signal PS7_i_n_304 : STD_LOGIC; + signal PS7_i_n_305 : STD_LOGIC; + signal PS7_i_n_306 : STD_LOGIC; + signal PS7_i_n_307 : STD_LOGIC; + signal PS7_i_n_308 : STD_LOGIC; + signal PS7_i_n_309 : STD_LOGIC; + signal PS7_i_n_31 : STD_LOGIC; + signal PS7_i_n_310 : STD_LOGIC; + signal PS7_i_n_311 : STD_LOGIC; + signal PS7_i_n_312 : STD_LOGIC; + signal PS7_i_n_313 : STD_LOGIC; + signal PS7_i_n_314 : STD_LOGIC; + signal PS7_i_n_315 : STD_LOGIC; + signal PS7_i_n_316 : STD_LOGIC; + signal PS7_i_n_317 : STD_LOGIC; + signal PS7_i_n_318 : STD_LOGIC; + signal PS7_i_n_319 : STD_LOGIC; + signal PS7_i_n_32 : STD_LOGIC; + signal PS7_i_n_320 : STD_LOGIC; + signal PS7_i_n_321 : STD_LOGIC; + signal PS7_i_n_322 : STD_LOGIC; + signal PS7_i_n_323 : STD_LOGIC; + signal PS7_i_n_324 : STD_LOGIC; + signal PS7_i_n_325 : STD_LOGIC; + signal PS7_i_n_326 : STD_LOGIC; + signal PS7_i_n_327 : STD_LOGIC; + signal PS7_i_n_328 : STD_LOGIC; + signal PS7_i_n_329 : STD_LOGIC; + signal PS7_i_n_330 : STD_LOGIC; + signal PS7_i_n_331 : STD_LOGIC; + signal PS7_i_n_332 : STD_LOGIC; + signal PS7_i_n_333 : STD_LOGIC; + signal PS7_i_n_334 : STD_LOGIC; + signal PS7_i_n_335 : STD_LOGIC; + signal PS7_i_n_336 : STD_LOGIC; + signal PS7_i_n_337 : STD_LOGIC; + signal PS7_i_n_338 : STD_LOGIC; + signal PS7_i_n_34 : STD_LOGIC; + signal PS7_i_n_345 : STD_LOGIC; + signal PS7_i_n_346 : STD_LOGIC; + signal PS7_i_n_347 : STD_LOGIC; + signal PS7_i_n_348 : STD_LOGIC; + signal PS7_i_n_349 : STD_LOGIC; + signal PS7_i_n_35 : STD_LOGIC; + signal PS7_i_n_350 : STD_LOGIC; + signal PS7_i_n_351 : STD_LOGIC; + signal PS7_i_n_352 : STD_LOGIC; + signal PS7_i_n_353 : STD_LOGIC; + signal PS7_i_n_354 : STD_LOGIC; + signal PS7_i_n_355 : STD_LOGIC; + signal PS7_i_n_356 : STD_LOGIC; + signal PS7_i_n_357 : STD_LOGIC; + signal PS7_i_n_358 : STD_LOGIC; + signal PS7_i_n_359 : STD_LOGIC; + signal PS7_i_n_36 : STD_LOGIC; + signal PS7_i_n_360 : STD_LOGIC; + signal PS7_i_n_361 : STD_LOGIC; + signal PS7_i_n_362 : STD_LOGIC; + signal PS7_i_n_363 : STD_LOGIC; + signal PS7_i_n_364 : STD_LOGIC; + signal PS7_i_n_365 : STD_LOGIC; + signal PS7_i_n_366 : STD_LOGIC; + signal PS7_i_n_367 : STD_LOGIC; + signal PS7_i_n_368 : STD_LOGIC; + signal PS7_i_n_37 : STD_LOGIC; + signal PS7_i_n_38 : STD_LOGIC; + signal PS7_i_n_39 : STD_LOGIC; + signal PS7_i_n_4 : STD_LOGIC; + signal PS7_i_n_40 : STD_LOGIC; + signal PS7_i_n_401 : STD_LOGIC; + signal PS7_i_n_402 : STD_LOGIC; + signal PS7_i_n_403 : STD_LOGIC; + signal PS7_i_n_404 : STD_LOGIC; + signal PS7_i_n_405 : STD_LOGIC; + signal PS7_i_n_406 : STD_LOGIC; + signal PS7_i_n_407 : STD_LOGIC; + signal PS7_i_n_408 : STD_LOGIC; + signal PS7_i_n_409 : STD_LOGIC; + signal PS7_i_n_41 : STD_LOGIC; + signal PS7_i_n_410 : STD_LOGIC; + signal PS7_i_n_411 : STD_LOGIC; + signal PS7_i_n_412 : STD_LOGIC; + signal PS7_i_n_413 : STD_LOGIC; + signal PS7_i_n_414 : STD_LOGIC; + signal PS7_i_n_415 : STD_LOGIC; + signal PS7_i_n_416 : STD_LOGIC; + signal PS7_i_n_417 : STD_LOGIC; + signal PS7_i_n_418 : STD_LOGIC; + signal PS7_i_n_419 : STD_LOGIC; + signal PS7_i_n_42 : STD_LOGIC; + signal PS7_i_n_420 : STD_LOGIC; + signal PS7_i_n_421 : STD_LOGIC; + signal PS7_i_n_422 : STD_LOGIC; + signal PS7_i_n_423 : STD_LOGIC; + signal PS7_i_n_424 : STD_LOGIC; + signal PS7_i_n_425 : STD_LOGIC; + signal PS7_i_n_426 : STD_LOGIC; + signal PS7_i_n_427 : STD_LOGIC; + signal PS7_i_n_428 : STD_LOGIC; + signal PS7_i_n_429 : STD_LOGIC; + signal PS7_i_n_43 : STD_LOGIC; + signal PS7_i_n_430 : STD_LOGIC; + signal PS7_i_n_431 : STD_LOGIC; + signal PS7_i_n_432 : STD_LOGIC; + signal PS7_i_n_44 : STD_LOGIC; + signal PS7_i_n_46 : STD_LOGIC; + signal PS7_i_n_48 : STD_LOGIC; + signal PS7_i_n_5 : STD_LOGIC; + signal PS7_i_n_50 : STD_LOGIC; + signal PS7_i_n_529 : STD_LOGIC; + signal PS7_i_n_530 : STD_LOGIC; + signal PS7_i_n_531 : STD_LOGIC; + signal PS7_i_n_532 : STD_LOGIC; + signal PS7_i_n_533 : STD_LOGIC; + signal PS7_i_n_534 : STD_LOGIC; + signal PS7_i_n_535 : STD_LOGIC; + signal PS7_i_n_536 : STD_LOGIC; + signal PS7_i_n_537 : STD_LOGIC; + signal PS7_i_n_538 : STD_LOGIC; + signal PS7_i_n_539 : STD_LOGIC; + signal PS7_i_n_54 : STD_LOGIC; + signal PS7_i_n_540 : STD_LOGIC; + signal PS7_i_n_541 : STD_LOGIC; + signal PS7_i_n_542 : STD_LOGIC; + signal PS7_i_n_543 : STD_LOGIC; + signal PS7_i_n_544 : STD_LOGIC; + signal PS7_i_n_545 : STD_LOGIC; + signal PS7_i_n_546 : STD_LOGIC; + signal PS7_i_n_547 : STD_LOGIC; + signal PS7_i_n_548 : STD_LOGIC; + signal PS7_i_n_549 : STD_LOGIC; + signal PS7_i_n_55 : STD_LOGIC; + signal PS7_i_n_550 : STD_LOGIC; + signal PS7_i_n_551 : STD_LOGIC; + signal PS7_i_n_552 : STD_LOGIC; + signal PS7_i_n_553 : STD_LOGIC; + signal PS7_i_n_554 : STD_LOGIC; + signal PS7_i_n_555 : STD_LOGIC; + signal PS7_i_n_556 : STD_LOGIC; + signal PS7_i_n_557 : STD_LOGIC; + signal PS7_i_n_558 : STD_LOGIC; + signal PS7_i_n_559 : STD_LOGIC; + signal PS7_i_n_56 : STD_LOGIC; + signal PS7_i_n_560 : STD_LOGIC; + signal PS7_i_n_561 : STD_LOGIC; + signal PS7_i_n_562 : STD_LOGIC; + signal PS7_i_n_563 : STD_LOGIC; + signal PS7_i_n_564 : STD_LOGIC; + signal PS7_i_n_565 : STD_LOGIC; + signal PS7_i_n_566 : STD_LOGIC; + signal PS7_i_n_567 : STD_LOGIC; + signal PS7_i_n_568 : STD_LOGIC; + signal PS7_i_n_569 : STD_LOGIC; + signal PS7_i_n_570 : STD_LOGIC; + signal PS7_i_n_571 : STD_LOGIC; + signal PS7_i_n_572 : STD_LOGIC; + signal PS7_i_n_573 : STD_LOGIC; + signal PS7_i_n_574 : STD_LOGIC; + signal PS7_i_n_575 : STD_LOGIC; + signal PS7_i_n_576 : STD_LOGIC; + signal PS7_i_n_577 : STD_LOGIC; + signal PS7_i_n_578 : STD_LOGIC; + signal PS7_i_n_579 : STD_LOGIC; + signal PS7_i_n_58 : STD_LOGIC; + signal PS7_i_n_580 : STD_LOGIC; + signal PS7_i_n_581 : STD_LOGIC; + signal PS7_i_n_582 : STD_LOGIC; + signal PS7_i_n_583 : STD_LOGIC; + signal PS7_i_n_584 : STD_LOGIC; + signal PS7_i_n_585 : STD_LOGIC; + signal PS7_i_n_586 : STD_LOGIC; + signal PS7_i_n_587 : STD_LOGIC; + signal PS7_i_n_588 : STD_LOGIC; + signal PS7_i_n_589 : STD_LOGIC; + signal PS7_i_n_59 : STD_LOGIC; + signal PS7_i_n_590 : STD_LOGIC; + signal PS7_i_n_591 : STD_LOGIC; + signal PS7_i_n_592 : STD_LOGIC; + signal PS7_i_n_593 : STD_LOGIC; + signal PS7_i_n_594 : STD_LOGIC; + signal PS7_i_n_595 : STD_LOGIC; + signal PS7_i_n_596 : STD_LOGIC; + signal PS7_i_n_597 : STD_LOGIC; + signal PS7_i_n_598 : STD_LOGIC; + signal PS7_i_n_599 : STD_LOGIC; + signal PS7_i_n_6 : STD_LOGIC; + signal PS7_i_n_60 : STD_LOGIC; + signal PS7_i_n_600 : STD_LOGIC; + signal PS7_i_n_601 : STD_LOGIC; + signal PS7_i_n_602 : STD_LOGIC; + signal PS7_i_n_603 : STD_LOGIC; + signal PS7_i_n_604 : STD_LOGIC; + signal PS7_i_n_605 : STD_LOGIC; + signal PS7_i_n_606 : STD_LOGIC; + signal PS7_i_n_607 : STD_LOGIC; + signal PS7_i_n_608 : STD_LOGIC; + signal PS7_i_n_609 : STD_LOGIC; + signal PS7_i_n_61 : STD_LOGIC; + signal PS7_i_n_610 : STD_LOGIC; + signal PS7_i_n_611 : STD_LOGIC; + signal PS7_i_n_612 : STD_LOGIC; + signal PS7_i_n_613 : STD_LOGIC; + signal PS7_i_n_614 : STD_LOGIC; + signal PS7_i_n_615 : STD_LOGIC; + signal PS7_i_n_616 : STD_LOGIC; + signal PS7_i_n_617 : STD_LOGIC; + signal PS7_i_n_618 : STD_LOGIC; + signal PS7_i_n_619 : STD_LOGIC; + signal PS7_i_n_620 : STD_LOGIC; + signal PS7_i_n_621 : STD_LOGIC; + signal PS7_i_n_622 : STD_LOGIC; + signal PS7_i_n_623 : STD_LOGIC; + signal PS7_i_n_624 : STD_LOGIC; + signal PS7_i_n_625 : STD_LOGIC; + signal PS7_i_n_626 : STD_LOGIC; + signal PS7_i_n_627 : STD_LOGIC; + signal PS7_i_n_628 : STD_LOGIC; + signal PS7_i_n_629 : STD_LOGIC; + signal PS7_i_n_63 : STD_LOGIC; + signal PS7_i_n_630 : STD_LOGIC; + signal PS7_i_n_631 : STD_LOGIC; + signal PS7_i_n_632 : STD_LOGIC; + signal PS7_i_n_633 : STD_LOGIC; + signal PS7_i_n_634 : STD_LOGIC; + signal PS7_i_n_635 : STD_LOGIC; + signal PS7_i_n_636 : STD_LOGIC; + signal PS7_i_n_637 : STD_LOGIC; + signal PS7_i_n_638 : STD_LOGIC; + signal PS7_i_n_639 : STD_LOGIC; + signal PS7_i_n_64 : STD_LOGIC; + signal PS7_i_n_640 : STD_LOGIC; + signal PS7_i_n_641 : STD_LOGIC; + signal PS7_i_n_642 : STD_LOGIC; + signal PS7_i_n_643 : STD_LOGIC; + signal PS7_i_n_644 : STD_LOGIC; + signal PS7_i_n_645 : STD_LOGIC; + signal PS7_i_n_646 : STD_LOGIC; + signal PS7_i_n_647 : STD_LOGIC; + signal PS7_i_n_648 : STD_LOGIC; + signal PS7_i_n_649 : STD_LOGIC; + signal PS7_i_n_650 : STD_LOGIC; + signal PS7_i_n_651 : STD_LOGIC; + signal PS7_i_n_652 : STD_LOGIC; + signal PS7_i_n_653 : STD_LOGIC; + signal PS7_i_n_654 : STD_LOGIC; + signal PS7_i_n_655 : STD_LOGIC; + signal PS7_i_n_656 : STD_LOGIC; + signal PS7_i_n_657 : STD_LOGIC; + signal PS7_i_n_658 : STD_LOGIC; + signal PS7_i_n_659 : STD_LOGIC; + signal PS7_i_n_66 : STD_LOGIC; + signal PS7_i_n_660 : STD_LOGIC; + signal PS7_i_n_661 : STD_LOGIC; + signal PS7_i_n_662 : STD_LOGIC; + signal PS7_i_n_663 : STD_LOGIC; + signal PS7_i_n_664 : STD_LOGIC; + signal PS7_i_n_665 : STD_LOGIC; + signal PS7_i_n_666 : STD_LOGIC; + signal PS7_i_n_667 : STD_LOGIC; + signal PS7_i_n_668 : STD_LOGIC; + signal PS7_i_n_669 : STD_LOGIC; + signal PS7_i_n_670 : STD_LOGIC; + signal PS7_i_n_671 : STD_LOGIC; + signal PS7_i_n_672 : STD_LOGIC; + signal PS7_i_n_673 : STD_LOGIC; + signal PS7_i_n_674 : STD_LOGIC; + signal PS7_i_n_675 : STD_LOGIC; + signal PS7_i_n_676 : STD_LOGIC; + signal PS7_i_n_677 : STD_LOGIC; + signal PS7_i_n_678 : STD_LOGIC; + signal PS7_i_n_679 : STD_LOGIC; + signal PS7_i_n_68 : STD_LOGIC; + signal PS7_i_n_680 : STD_LOGIC; + signal PS7_i_n_681 : STD_LOGIC; + signal PS7_i_n_682 : STD_LOGIC; + signal PS7_i_n_683 : STD_LOGIC; + signal PS7_i_n_684 : STD_LOGIC; + signal PS7_i_n_685 : STD_LOGIC; + signal PS7_i_n_686 : STD_LOGIC; + signal PS7_i_n_687 : STD_LOGIC; + signal PS7_i_n_688 : STD_LOGIC; + signal PS7_i_n_689 : STD_LOGIC; + signal PS7_i_n_690 : STD_LOGIC; + signal PS7_i_n_691 : STD_LOGIC; + signal PS7_i_n_692 : STD_LOGIC; + signal PS7_i_n_697 : STD_LOGIC; + signal PS7_i_n_698 : STD_LOGIC; + signal PS7_i_n_699 : STD_LOGIC; + signal PS7_i_n_7 : STD_LOGIC; + signal PS7_i_n_700 : STD_LOGIC; + signal PS7_i_n_709 : STD_LOGIC; + signal PS7_i_n_71 : STD_LOGIC; + signal PS7_i_n_710 : STD_LOGIC; + signal PS7_i_n_711 : STD_LOGIC; + signal PS7_i_n_713 : STD_LOGIC; + signal PS7_i_n_714 : STD_LOGIC; + signal PS7_i_n_715 : STD_LOGIC; + signal PS7_i_n_716 : STD_LOGIC; + signal PS7_i_n_717 : STD_LOGIC; + signal PS7_i_n_718 : STD_LOGIC; + signal PS7_i_n_719 : STD_LOGIC; + signal PS7_i_n_720 : STD_LOGIC; + signal PS7_i_n_73 : STD_LOGIC; + signal PS7_i_n_749 : STD_LOGIC; + signal PS7_i_n_75 : STD_LOGIC; + signal PS7_i_n_750 : STD_LOGIC; + signal PS7_i_n_752 : STD_LOGIC; + signal PS7_i_n_753 : STD_LOGIC; + signal PS7_i_n_754 : STD_LOGIC; + signal PS7_i_n_755 : STD_LOGIC; + signal PS7_i_n_756 : STD_LOGIC; + signal PS7_i_n_757 : STD_LOGIC; + signal PS7_i_n_758 : STD_LOGIC; + signal PS7_i_n_759 : STD_LOGIC; + signal PS7_i_n_760 : STD_LOGIC; + signal PS7_i_n_761 : STD_LOGIC; + signal PS7_i_n_762 : STD_LOGIC; + signal PS7_i_n_764 : STD_LOGIC; + signal PS7_i_n_765 : STD_LOGIC; + signal PS7_i_n_766 : STD_LOGIC; + signal PS7_i_n_767 : STD_LOGIC; + signal PS7_i_n_768 : STD_LOGIC; + signal PS7_i_n_769 : STD_LOGIC; + signal PS7_i_n_770 : STD_LOGIC; + signal PS7_i_n_771 : STD_LOGIC; + signal PS7_i_n_772 : STD_LOGIC; + signal PS7_i_n_773 : STD_LOGIC; + signal PS7_i_n_774 : STD_LOGIC; + signal PS7_i_n_775 : STD_LOGIC; + signal PS7_i_n_776 : STD_LOGIC; + signal PS7_i_n_777 : STD_LOGIC; + signal PS7_i_n_778 : STD_LOGIC; + signal PS7_i_n_779 : STD_LOGIC; + signal PS7_i_n_780 : STD_LOGIC; + signal PS7_i_n_781 : STD_LOGIC; + signal PS7_i_n_782 : STD_LOGIC; + signal PS7_i_n_783 : STD_LOGIC; + signal PS7_i_n_784 : STD_LOGIC; + signal PS7_i_n_785 : STD_LOGIC; + signal PS7_i_n_786 : STD_LOGIC; + signal PS7_i_n_787 : STD_LOGIC; + signal PS7_i_n_788 : STD_LOGIC; + signal PS7_i_n_789 : STD_LOGIC; + signal PS7_i_n_79 : STD_LOGIC; + signal PS7_i_n_790 : STD_LOGIC; + signal PS7_i_n_791 : STD_LOGIC; + signal PS7_i_n_792 : STD_LOGIC; + signal PS7_i_n_793 : STD_LOGIC; + signal PS7_i_n_794 : STD_LOGIC; + signal PS7_i_n_795 : STD_LOGIC; + signal PS7_i_n_796 : STD_LOGIC; + signal PS7_i_n_797 : STD_LOGIC; + signal PS7_i_n_798 : STD_LOGIC; + signal PS7_i_n_799 : STD_LOGIC; + signal PS7_i_n_8 : STD_LOGIC; + signal PS7_i_n_80 : STD_LOGIC; + signal PS7_i_n_800 : STD_LOGIC; + signal PS7_i_n_801 : STD_LOGIC; + signal PS7_i_n_802 : STD_LOGIC; + signal PS7_i_n_803 : STD_LOGIC; + signal PS7_i_n_804 : STD_LOGIC; + signal PS7_i_n_805 : STD_LOGIC; + signal PS7_i_n_806 : STD_LOGIC; + signal PS7_i_n_807 : STD_LOGIC; + signal PS7_i_n_808 : STD_LOGIC; + signal PS7_i_n_809 : STD_LOGIC; + signal PS7_i_n_81 : STD_LOGIC; + signal PS7_i_n_810 : STD_LOGIC; + signal PS7_i_n_811 : STD_LOGIC; + signal PS7_i_n_812 : STD_LOGIC; + signal PS7_i_n_813 : STD_LOGIC; + signal PS7_i_n_814 : STD_LOGIC; + signal PS7_i_n_815 : STD_LOGIC; + signal PS7_i_n_816 : STD_LOGIC; + signal PS7_i_n_817 : STD_LOGIC; + signal PS7_i_n_818 : STD_LOGIC; + signal PS7_i_n_819 : STD_LOGIC; + signal PS7_i_n_82 : STD_LOGIC; + signal PS7_i_n_820 : STD_LOGIC; + signal PS7_i_n_821 : STD_LOGIC; + signal PS7_i_n_822 : STD_LOGIC; + signal PS7_i_n_823 : STD_LOGIC; + signal PS7_i_n_824 : STD_LOGIC; + signal PS7_i_n_825 : STD_LOGIC; + signal PS7_i_n_826 : STD_LOGIC; + signal PS7_i_n_827 : STD_LOGIC; + signal PS7_i_n_828 : STD_LOGIC; + signal PS7_i_n_829 : STD_LOGIC; + signal PS7_i_n_83 : STD_LOGIC; + signal PS7_i_n_830 : STD_LOGIC; + signal PS7_i_n_831 : STD_LOGIC; + signal PS7_i_n_832 : STD_LOGIC; + signal PS7_i_n_833 : STD_LOGIC; + signal PS7_i_n_834 : STD_LOGIC; + signal PS7_i_n_835 : STD_LOGIC; + signal PS7_i_n_836 : STD_LOGIC; + signal PS7_i_n_837 : STD_LOGIC; + signal PS7_i_n_838 : STD_LOGIC; + signal PS7_i_n_839 : STD_LOGIC; + signal PS7_i_n_84 : STD_LOGIC; + signal PS7_i_n_840 : STD_LOGIC; + signal PS7_i_n_841 : STD_LOGIC; + signal PS7_i_n_842 : STD_LOGIC; + signal PS7_i_n_843 : STD_LOGIC; + signal PS7_i_n_844 : STD_LOGIC; + signal PS7_i_n_845 : STD_LOGIC; + signal PS7_i_n_846 : STD_LOGIC; + signal PS7_i_n_847 : STD_LOGIC; + signal PS7_i_n_848 : STD_LOGIC; + signal PS7_i_n_849 : STD_LOGIC; + signal PS7_i_n_85 : STD_LOGIC; + signal PS7_i_n_850 : STD_LOGIC; + signal PS7_i_n_851 : STD_LOGIC; + signal PS7_i_n_852 : STD_LOGIC; + signal PS7_i_n_853 : STD_LOGIC; + signal PS7_i_n_854 : STD_LOGIC; + signal PS7_i_n_855 : STD_LOGIC; + signal PS7_i_n_856 : STD_LOGIC; + signal PS7_i_n_857 : STD_LOGIC; + signal PS7_i_n_858 : STD_LOGIC; + signal PS7_i_n_859 : STD_LOGIC; + signal PS7_i_n_86 : STD_LOGIC; + signal PS7_i_n_860 : STD_LOGIC; + signal PS7_i_n_861 : STD_LOGIC; + signal PS7_i_n_862 : STD_LOGIC; + signal PS7_i_n_863 : STD_LOGIC; + signal PS7_i_n_864 : STD_LOGIC; + signal PS7_i_n_865 : STD_LOGIC; + signal PS7_i_n_866 : STD_LOGIC; + signal PS7_i_n_867 : STD_LOGIC; + signal PS7_i_n_868 : STD_LOGIC; + signal PS7_i_n_869 : STD_LOGIC; + signal PS7_i_n_87 : STD_LOGIC; + signal PS7_i_n_870 : STD_LOGIC; + signal PS7_i_n_871 : STD_LOGIC; + signal PS7_i_n_872 : STD_LOGIC; + signal PS7_i_n_873 : STD_LOGIC; + signal PS7_i_n_874 : STD_LOGIC; + signal PS7_i_n_875 : STD_LOGIC; + signal PS7_i_n_876 : STD_LOGIC; + signal PS7_i_n_877 : STD_LOGIC; + signal PS7_i_n_878 : STD_LOGIC; + signal PS7_i_n_879 : STD_LOGIC; + signal PS7_i_n_88 : STD_LOGIC; + signal PS7_i_n_880 : STD_LOGIC; + signal PS7_i_n_881 : STD_LOGIC; + signal PS7_i_n_882 : STD_LOGIC; + signal PS7_i_n_883 : STD_LOGIC; + signal PS7_i_n_884 : STD_LOGIC; + signal PS7_i_n_885 : STD_LOGIC; + signal PS7_i_n_886 : STD_LOGIC; + signal PS7_i_n_887 : STD_LOGIC; + signal PS7_i_n_888 : STD_LOGIC; + signal PS7_i_n_889 : STD_LOGIC; + signal PS7_i_n_89 : STD_LOGIC; + signal PS7_i_n_890 : STD_LOGIC; + signal PS7_i_n_891 : STD_LOGIC; + signal PS7_i_n_892 : STD_LOGIC; + signal PS7_i_n_893 : STD_LOGIC; + signal PS7_i_n_894 : STD_LOGIC; + signal PS7_i_n_895 : STD_LOGIC; + signal PS7_i_n_896 : STD_LOGIC; + signal PS7_i_n_897 : STD_LOGIC; + signal PS7_i_n_898 : STD_LOGIC; + signal PS7_i_n_899 : STD_LOGIC; + signal PS7_i_n_9 : STD_LOGIC; + signal PS7_i_n_900 : STD_LOGIC; + signal PS7_i_n_901 : STD_LOGIC; + signal PS7_i_n_902 : STD_LOGIC; + signal PS7_i_n_903 : STD_LOGIC; + signal PS7_i_n_904 : STD_LOGIC; + signal PS7_i_n_905 : STD_LOGIC; + signal PS7_i_n_906 : STD_LOGIC; + signal PS7_i_n_907 : STD_LOGIC; + signal PS7_i_n_908 : STD_LOGIC; + signal PS7_i_n_909 : STD_LOGIC; + signal PS7_i_n_910 : STD_LOGIC; + signal PS7_i_n_911 : STD_LOGIC; + signal PS7_i_n_912 : STD_LOGIC; + signal PS7_i_n_913 : STD_LOGIC; + signal PS7_i_n_914 : STD_LOGIC; + signal PS7_i_n_915 : STD_LOGIC; + signal PS7_i_n_916 : STD_LOGIC; + signal PS7_i_n_917 : STD_LOGIC; + signal PS7_i_n_918 : STD_LOGIC; + signal PS7_i_n_919 : STD_LOGIC; + signal PS7_i_n_920 : STD_LOGIC; + signal PS7_i_n_921 : STD_LOGIC; + signal PS7_i_n_922 : STD_LOGIC; + signal PS7_i_n_923 : STD_LOGIC; + signal PS7_i_n_924 : STD_LOGIC; + signal PS7_i_n_925 : STD_LOGIC; + signal PS7_i_n_926 : STD_LOGIC; + signal PS7_i_n_927 : STD_LOGIC; + signal PS7_i_n_928 : STD_LOGIC; + signal PS7_i_n_929 : STD_LOGIC; + signal PS7_i_n_930 : STD_LOGIC; + signal PS7_i_n_931 : STD_LOGIC; + signal PS7_i_n_932 : STD_LOGIC; + signal PS7_i_n_933 : STD_LOGIC; + signal PS7_i_n_934 : STD_LOGIC; + signal PS7_i_n_935 : STD_LOGIC; + signal PS7_i_n_936 : STD_LOGIC; + signal PS7_i_n_96 : STD_LOGIC; + signal PS7_i_n_97 : STD_LOGIC; + signal PS7_i_n_98 : STD_LOGIC; + signal PS7_i_n_99 : STD_LOGIC; + signal SDIO0_CMD_T_n : STD_LOGIC; + signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal SDIO1_CMD_T_n : STD_LOGIC; + signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal SPI0_MISO_T_n : STD_LOGIC; + signal SPI0_MOSI_T_n : STD_LOGIC; + signal SPI0_SCLK_T_n : STD_LOGIC; + signal SPI0_SS_T_n : STD_LOGIC; + signal SPI1_MISO_T_n : STD_LOGIC; + signal SPI1_MOSI_T_n : STD_LOGIC; + signal SPI1_SCLK_T_n : STD_LOGIC; + signal SPI1_SS_T_n : STD_LOGIC; + signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC; + attribute RTL_KEEP : string; + attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true"; + signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC; + attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true"; + signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC; + attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true"; + signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC; + attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true"; + signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC; + attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true"; + signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC; + attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true"; + signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC; + attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true"; + signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC; + attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true"; + signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true"; + signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true"; + signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true"; + signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true"; + signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true"; + signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true"; + signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true"; + signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true"; + signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 ); + signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal buffered_DDR_CAS_n : STD_LOGIC; + signal buffered_DDR_CKE : STD_LOGIC; + signal buffered_DDR_CS_n : STD_LOGIC; + signal buffered_DDR_Clk : STD_LOGIC; + signal buffered_DDR_Clk_n : STD_LOGIC; + signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal buffered_DDR_DRSTB : STD_LOGIC; + signal buffered_DDR_ODT : STD_LOGIC; + signal buffered_DDR_RAS_n : STD_LOGIC; + signal buffered_DDR_VRN : STD_LOGIC; + signal buffered_DDR_VRP : STD_LOGIC; + signal buffered_DDR_WEB : STD_LOGIC; + signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 ); + signal buffered_PS_CLK : STD_LOGIC; + signal buffered_PS_PORB : STD_LOGIC; + signal buffered_PS_SRSTB : STD_LOGIC; + signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC; + signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC; + signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC; + signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC; + signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC; + signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC; + signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC; + signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); + signal NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); + signal NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); + signal NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of PS7_i : label is "PRIMITIVE"; + attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \buffer_fclk_clk_1.FCLK_CLK_1_BUFG\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \buffer_fclk_clk_2.FCLK_CLK_2_BUFG\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \buffer_fclk_clk_3.FCLK_CLK_3_BUFG\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; +begin + CAN0_PHY_TX <= \\; + CAN1_PHY_TX <= \\; + DMA0_DATYPE(1) <= \\; + DMA0_DATYPE(0) <= \\; + DMA0_DAVALID <= \\; + DMA0_DRREADY <= \\; + DMA0_RSTN <= \\; + DMA1_DATYPE(1) <= \\; + DMA1_DATYPE(0) <= \\; + DMA1_DAVALID <= \\; + DMA1_DRREADY <= \\; + DMA1_RSTN <= \\; + DMA2_DATYPE(1) <= \\; + DMA2_DATYPE(0) <= \\; + DMA2_DAVALID <= \\; + DMA2_DRREADY <= \\; + DMA2_RSTN <= \\; + DMA3_DATYPE(1) <= \\; + DMA3_DATYPE(0) <= \\; + DMA3_DAVALID <= \\; + DMA3_DRREADY <= \\; + DMA3_RSTN <= \\; + ENET0_GMII_TXD(7) <= \\; + ENET0_GMII_TXD(6) <= \\; + ENET0_GMII_TXD(5) <= \\; + ENET0_GMII_TXD(4) <= \\; + ENET0_GMII_TXD(3) <= \\; + ENET0_GMII_TXD(2) <= \\; + ENET0_GMII_TXD(1) <= \\; + ENET0_GMII_TXD(0) <= \\; + ENET0_GMII_TX_EN <= \\; + ENET0_GMII_TX_ER <= \\; + ENET0_MDIO_MDC <= \\; + ENET0_MDIO_O <= \\; + ENET0_MDIO_T <= \\; + ENET0_PTP_DELAY_REQ_RX <= \\; + ENET0_PTP_DELAY_REQ_TX <= \\; + ENET0_PTP_PDELAY_REQ_RX <= \\; + ENET0_PTP_PDELAY_REQ_TX <= \\; + ENET0_PTP_PDELAY_RESP_RX <= \\; + ENET0_PTP_PDELAY_RESP_TX <= \\; + ENET0_PTP_SYNC_FRAME_RX <= \\; + ENET0_PTP_SYNC_FRAME_TX <= \\; + ENET0_SOF_RX <= \\; + ENET0_SOF_TX <= \\; + ENET1_GMII_TXD(7) <= \\; + ENET1_GMII_TXD(6) <= \\; + ENET1_GMII_TXD(5) <= \\; + ENET1_GMII_TXD(4) <= \\; + ENET1_GMII_TXD(3) <= \\; + ENET1_GMII_TXD(2) <= \\; + ENET1_GMII_TXD(1) <= \\; + ENET1_GMII_TXD(0) <= \\; + ENET1_GMII_TX_EN <= \\; + ENET1_GMII_TX_ER <= \\; + ENET1_MDIO_MDC <= \\; + ENET1_MDIO_O <= \\; + ENET1_MDIO_T <= \\; + ENET1_PTP_DELAY_REQ_RX <= \\; + ENET1_PTP_DELAY_REQ_TX <= \\; + ENET1_PTP_PDELAY_REQ_RX <= \\; + ENET1_PTP_PDELAY_REQ_TX <= \\; + ENET1_PTP_PDELAY_RESP_RX <= \\; + ENET1_PTP_PDELAY_RESP_TX <= \\; + ENET1_PTP_SYNC_FRAME_RX <= \\; + ENET1_PTP_SYNC_FRAME_TX <= \\; + ENET1_SOF_RX <= \\; + ENET1_SOF_TX <= \\; + EVENT_EVENTO <= \\; + EVENT_STANDBYWFE(1) <= \\; + EVENT_STANDBYWFE(0) <= \\; + EVENT_STANDBYWFI(1) <= \\; + EVENT_STANDBYWFI(0) <= \\; + FCLK_RESET1_N <= \\; + FCLK_RESET2_N <= \\; + FCLK_RESET3_N <= \\; + FTMT_F2P_TRIGACK_0 <= \\; + FTMT_F2P_TRIGACK_1 <= \\; + FTMT_F2P_TRIGACK_2 <= \\; + FTMT_F2P_TRIGACK_3 <= \\; + FTMT_P2F_DEBUG(31) <= \\; + FTMT_P2F_DEBUG(30) <= \\; + FTMT_P2F_DEBUG(29) <= \\; + FTMT_P2F_DEBUG(28) <= \\; + FTMT_P2F_DEBUG(27) <= \\; + FTMT_P2F_DEBUG(26) <= \\; + FTMT_P2F_DEBUG(25) <= \\; + FTMT_P2F_DEBUG(24) <= \\; + FTMT_P2F_DEBUG(23) <= \\; + FTMT_P2F_DEBUG(22) <= \\; + FTMT_P2F_DEBUG(21) <= \\; + FTMT_P2F_DEBUG(20) <= \\; + FTMT_P2F_DEBUG(19) <= \\; + FTMT_P2F_DEBUG(18) <= \\; + FTMT_P2F_DEBUG(17) <= \\; + FTMT_P2F_DEBUG(16) <= \\; + FTMT_P2F_DEBUG(15) <= \\; + FTMT_P2F_DEBUG(14) <= \\; + FTMT_P2F_DEBUG(13) <= \\; + FTMT_P2F_DEBUG(12) <= \\; + FTMT_P2F_DEBUG(11) <= \\; + FTMT_P2F_DEBUG(10) <= \\; + FTMT_P2F_DEBUG(9) <= \\; + FTMT_P2F_DEBUG(8) <= \\; + FTMT_P2F_DEBUG(7) <= \\; + FTMT_P2F_DEBUG(6) <= \\; + FTMT_P2F_DEBUG(5) <= \\; + FTMT_P2F_DEBUG(4) <= \\; + FTMT_P2F_DEBUG(3) <= \\; + FTMT_P2F_DEBUG(2) <= \\; + FTMT_P2F_DEBUG(1) <= \\; + FTMT_P2F_DEBUG(0) <= \\; + FTMT_P2F_TRIG_0 <= \\; + FTMT_P2F_TRIG_1 <= \\; + FTMT_P2F_TRIG_2 <= \\; + FTMT_P2F_TRIG_3 <= \\; + GPIO_O(63) <= \\; + GPIO_O(62) <= \\; + GPIO_O(61) <= \\; + GPIO_O(60) <= \\; + GPIO_O(59) <= \\; + GPIO_O(58) <= \\; + GPIO_O(57) <= \\; + GPIO_O(56) <= \\; + GPIO_O(55) <= \\; + GPIO_O(54) <= \\; + GPIO_O(53) <= \\; + GPIO_O(52) <= \\; + GPIO_O(51) <= \\; + GPIO_O(50) <= \\; + GPIO_O(49) <= \\; + GPIO_O(48) <= \\; + GPIO_O(47) <= \\; + GPIO_O(46) <= \\; + GPIO_O(45) <= \\; + GPIO_O(44) <= \\; + GPIO_O(43) <= \\; + GPIO_O(42) <= \\; + GPIO_O(41) <= \\; + GPIO_O(40) <= \\; + GPIO_O(39) <= \\; + GPIO_O(38) <= \\; + GPIO_O(37) <= \\; + GPIO_O(36) <= \\; + GPIO_O(35) <= \\; + GPIO_O(34) <= \\; + GPIO_O(33) <= \\; + GPIO_O(32) <= \\; + GPIO_O(31) <= \\; + GPIO_O(30) <= \\; + GPIO_O(29) <= \\; + GPIO_O(28) <= \\; + GPIO_O(27) <= \\; + GPIO_O(26) <= \\; + GPIO_O(25) <= \\; + GPIO_O(24) <= \\; + GPIO_O(23) <= \\; + GPIO_O(22) <= \\; + GPIO_O(21) <= \\; + GPIO_O(20) <= \\; + GPIO_O(19) <= \\; + GPIO_O(18) <= \\; + GPIO_O(17) <= \\; + GPIO_O(16) <= \\; + GPIO_O(15) <= \\; + GPIO_O(14) <= \\; + GPIO_O(13) <= \\; + GPIO_O(12) <= \\; + GPIO_O(11) <= \\; + GPIO_O(10) <= \\; + GPIO_O(9) <= \\; + GPIO_O(8) <= \\; + GPIO_O(7) <= \\; + GPIO_O(6) <= \\; + GPIO_O(5) <= \\; + GPIO_O(4) <= \\; + GPIO_O(3) <= \\; + GPIO_O(2) <= \\; + GPIO_O(1) <= \\; + GPIO_O(0) <= \\; + GPIO_T(63) <= \\; + GPIO_T(62) <= \\; + GPIO_T(61) <= \\; + GPIO_T(60) <= \\; + GPIO_T(59) <= \\; + GPIO_T(58) <= \\; + GPIO_T(57) <= \\; + GPIO_T(56) <= \\; + GPIO_T(55) <= \\; + GPIO_T(54) <= \\; + GPIO_T(53) <= \\; + GPIO_T(52) <= \\; + GPIO_T(51) <= \\; + GPIO_T(50) <= \\; + GPIO_T(49) <= \\; + GPIO_T(48) <= \\; + GPIO_T(47) <= \\; + GPIO_T(46) <= \\; + GPIO_T(45) <= \\; + GPIO_T(44) <= \\; + GPIO_T(43) <= \\; + GPIO_T(42) <= \\; + GPIO_T(41) <= \\; + GPIO_T(40) <= \\; + GPIO_T(39) <= \\; + GPIO_T(38) <= \\; + GPIO_T(37) <= \\; + GPIO_T(36) <= \\; + GPIO_T(35) <= \\; + GPIO_T(34) <= \\; + GPIO_T(33) <= \\; + GPIO_T(32) <= \\; + GPIO_T(31) <= \\; + GPIO_T(30) <= \\; + GPIO_T(29) <= \\; + GPIO_T(28) <= \\; + GPIO_T(27) <= \\; + GPIO_T(26) <= \\; + GPIO_T(25) <= \\; + GPIO_T(24) <= \\; + GPIO_T(23) <= \\; + GPIO_T(22) <= \\; + GPIO_T(21) <= \\; + GPIO_T(20) <= \\; + GPIO_T(19) <= \\; + GPIO_T(18) <= \\; + GPIO_T(17) <= \\; + GPIO_T(16) <= \\; + GPIO_T(15) <= \\; + GPIO_T(14) <= \\; + GPIO_T(13) <= \\; + GPIO_T(12) <= \\; + GPIO_T(11) <= \\; + GPIO_T(10) <= \\; + GPIO_T(9) <= \\; + GPIO_T(8) <= \\; + GPIO_T(7) <= \\; + GPIO_T(6) <= \\; + GPIO_T(5) <= \\; + GPIO_T(4) <= \\; + GPIO_T(3) <= \\; + GPIO_T(2) <= \\; + GPIO_T(1) <= \\; + GPIO_T(0) <= \\; + I2C0_SCL_O <= \\; + I2C0_SCL_T <= \\; + I2C0_SDA_O <= \\; + I2C0_SDA_T <= \\; + I2C1_SCL_O <= \\; + I2C1_SCL_T <= \\; + I2C1_SDA_O <= \\; + I2C1_SDA_T <= \\; + IRQ_P2F_CAN0 <= \\; + IRQ_P2F_CAN1 <= \\; + IRQ_P2F_CTI <= \\; + IRQ_P2F_DMAC0 <= \\; + IRQ_P2F_DMAC1 <= \\; + IRQ_P2F_DMAC2 <= \\; + IRQ_P2F_DMAC3 <= \\; + IRQ_P2F_DMAC4 <= \\; + IRQ_P2F_DMAC5 <= \\; + IRQ_P2F_DMAC6 <= \\; + IRQ_P2F_DMAC7 <= \\; + IRQ_P2F_DMAC_ABORT <= \\; + IRQ_P2F_ENET0 <= \\; + IRQ_P2F_ENET1 <= \\; + IRQ_P2F_ENET_WAKE0 <= \\; + IRQ_P2F_ENET_WAKE1 <= \\; + IRQ_P2F_GPIO <= \\; + IRQ_P2F_I2C0 <= \\; + IRQ_P2F_I2C1 <= \\; + IRQ_P2F_QSPI <= \\; + IRQ_P2F_SDIO0 <= \\; + IRQ_P2F_SDIO1 <= \\; + IRQ_P2F_SMC <= \\; + IRQ_P2F_SPI0 <= \\; + IRQ_P2F_SPI1 <= \\; + IRQ_P2F_UART0 <= \\; + IRQ_P2F_UART1 <= \\; + IRQ_P2F_USB0 <= \\; + IRQ_P2F_USB1 <= \\; + M_AXI_GP0_ARCACHE(3 downto 2) <= \^m_axi_gp0_arcache\(3 downto 2); + M_AXI_GP0_ARCACHE(1) <= \\; + M_AXI_GP0_ARCACHE(0) <= \^m_axi_gp0_arcache\(0); + M_AXI_GP0_ARESETN <= \\; + M_AXI_GP0_ARSIZE(2) <= \\; + M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0); + M_AXI_GP0_AWCACHE(3 downto 2) <= \^m_axi_gp0_awcache\(3 downto 2); + M_AXI_GP0_AWCACHE(1) <= \\; + M_AXI_GP0_AWCACHE(0) <= \^m_axi_gp0_awcache\(0); + M_AXI_GP0_AWSIZE(2) <= \\; + M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0); + M_AXI_GP1_ARADDR(31) <= \\; + M_AXI_GP1_ARADDR(30) <= \\; + M_AXI_GP1_ARADDR(29) <= \\; + M_AXI_GP1_ARADDR(28) <= \\; + M_AXI_GP1_ARADDR(27) <= \\; + M_AXI_GP1_ARADDR(26) <= \\; + M_AXI_GP1_ARADDR(25) <= \\; + M_AXI_GP1_ARADDR(24) <= \\; + M_AXI_GP1_ARADDR(23) <= \\; + M_AXI_GP1_ARADDR(22) <= \\; + M_AXI_GP1_ARADDR(21) <= \\; + M_AXI_GP1_ARADDR(20) <= \\; + M_AXI_GP1_ARADDR(19) <= \\; + M_AXI_GP1_ARADDR(18) <= \\; + M_AXI_GP1_ARADDR(17) <= \\; + M_AXI_GP1_ARADDR(16) <= \\; + M_AXI_GP1_ARADDR(15) <= \\; + M_AXI_GP1_ARADDR(14) <= \\; + M_AXI_GP1_ARADDR(13) <= \\; + M_AXI_GP1_ARADDR(12) <= \\; + M_AXI_GP1_ARADDR(11) <= \\; + M_AXI_GP1_ARADDR(10) <= \\; + M_AXI_GP1_ARADDR(9) <= \\; + M_AXI_GP1_ARADDR(8) <= \\; + M_AXI_GP1_ARADDR(7) <= \\; + M_AXI_GP1_ARADDR(6) <= \\; + M_AXI_GP1_ARADDR(5) <= \\; + M_AXI_GP1_ARADDR(4) <= \\; + M_AXI_GP1_ARADDR(3) <= \\; + M_AXI_GP1_ARADDR(2) <= \\; + M_AXI_GP1_ARADDR(1) <= \\; + M_AXI_GP1_ARADDR(0) <= \\; + M_AXI_GP1_ARBURST(1) <= \\; + M_AXI_GP1_ARBURST(0) <= \\; + M_AXI_GP1_ARCACHE(3) <= \\; + M_AXI_GP1_ARCACHE(2) <= \\; + M_AXI_GP1_ARCACHE(1) <= \\; + M_AXI_GP1_ARCACHE(0) <= \\; + M_AXI_GP1_ARESETN <= \\; + M_AXI_GP1_ARID(11) <= \\; + M_AXI_GP1_ARID(10) <= \\; + M_AXI_GP1_ARID(9) <= \\; + M_AXI_GP1_ARID(8) <= \\; + M_AXI_GP1_ARID(7) <= \\; + M_AXI_GP1_ARID(6) <= \\; + M_AXI_GP1_ARID(5) <= \\; + M_AXI_GP1_ARID(4) <= \\; + M_AXI_GP1_ARID(3) <= \\; + M_AXI_GP1_ARID(2) <= \\; + M_AXI_GP1_ARID(1) <= \\; + M_AXI_GP1_ARID(0) <= \\; + M_AXI_GP1_ARLEN(3) <= \\; + M_AXI_GP1_ARLEN(2) <= \\; + M_AXI_GP1_ARLEN(1) <= \\; + M_AXI_GP1_ARLEN(0) <= \\; + M_AXI_GP1_ARLOCK(1) <= \\; + M_AXI_GP1_ARLOCK(0) <= \\; + M_AXI_GP1_ARPROT(2) <= \\; + M_AXI_GP1_ARPROT(1) <= \\; + M_AXI_GP1_ARPROT(0) <= \\; + M_AXI_GP1_ARQOS(3) <= \\; + M_AXI_GP1_ARQOS(2) <= \\; + M_AXI_GP1_ARQOS(1) <= \\; + M_AXI_GP1_ARQOS(0) <= \\; + M_AXI_GP1_ARSIZE(2) <= \\; + M_AXI_GP1_ARSIZE(1) <= \\; + M_AXI_GP1_ARSIZE(0) <= \\; + M_AXI_GP1_ARVALID <= \\; + M_AXI_GP1_AWADDR(31) <= \\; + M_AXI_GP1_AWADDR(30) <= \\; + M_AXI_GP1_AWADDR(29) <= \\; + M_AXI_GP1_AWADDR(28) <= \\; + M_AXI_GP1_AWADDR(27) <= \\; + M_AXI_GP1_AWADDR(26) <= \\; + M_AXI_GP1_AWADDR(25) <= \\; + M_AXI_GP1_AWADDR(24) <= \\; + M_AXI_GP1_AWADDR(23) <= \\; + M_AXI_GP1_AWADDR(22) <= \\; + M_AXI_GP1_AWADDR(21) <= \\; + M_AXI_GP1_AWADDR(20) <= \\; + M_AXI_GP1_AWADDR(19) <= \\; + M_AXI_GP1_AWADDR(18) <= \\; + M_AXI_GP1_AWADDR(17) <= \\; + M_AXI_GP1_AWADDR(16) <= \\; + M_AXI_GP1_AWADDR(15) <= \\; + M_AXI_GP1_AWADDR(14) <= \\; + M_AXI_GP1_AWADDR(13) <= \\; + M_AXI_GP1_AWADDR(12) <= \\; + M_AXI_GP1_AWADDR(11) <= \\; + M_AXI_GP1_AWADDR(10) <= \\; + M_AXI_GP1_AWADDR(9) <= \\; + M_AXI_GP1_AWADDR(8) <= \\; + M_AXI_GP1_AWADDR(7) <= \\; + M_AXI_GP1_AWADDR(6) <= \\; + M_AXI_GP1_AWADDR(5) <= \\; + M_AXI_GP1_AWADDR(4) <= \\; + M_AXI_GP1_AWADDR(3) <= \\; + M_AXI_GP1_AWADDR(2) <= \\; + M_AXI_GP1_AWADDR(1) <= \\; + M_AXI_GP1_AWADDR(0) <= \\; + M_AXI_GP1_AWBURST(1) <= \\; + M_AXI_GP1_AWBURST(0) <= \\; + M_AXI_GP1_AWCACHE(3) <= \\; + M_AXI_GP1_AWCACHE(2) <= \\; + M_AXI_GP1_AWCACHE(1) <= \\; + M_AXI_GP1_AWCACHE(0) <= \\; + M_AXI_GP1_AWID(11) <= \\; + M_AXI_GP1_AWID(10) <= \\; + M_AXI_GP1_AWID(9) <= \\; + M_AXI_GP1_AWID(8) <= \\; + M_AXI_GP1_AWID(7) <= \\; + M_AXI_GP1_AWID(6) <= \\; + M_AXI_GP1_AWID(5) <= \\; + M_AXI_GP1_AWID(4) <= \\; + M_AXI_GP1_AWID(3) <= \\; + M_AXI_GP1_AWID(2) <= \\; + M_AXI_GP1_AWID(1) <= \\; + M_AXI_GP1_AWID(0) <= \\; + M_AXI_GP1_AWLEN(3) <= \\; + M_AXI_GP1_AWLEN(2) <= \\; + M_AXI_GP1_AWLEN(1) <= \\; + M_AXI_GP1_AWLEN(0) <= \\; + M_AXI_GP1_AWLOCK(1) <= \\; + M_AXI_GP1_AWLOCK(0) <= \\; + M_AXI_GP1_AWPROT(2) <= \\; + M_AXI_GP1_AWPROT(1) <= \\; + M_AXI_GP1_AWPROT(0) <= \\; + M_AXI_GP1_AWQOS(3) <= \\; + M_AXI_GP1_AWQOS(2) <= \\; + M_AXI_GP1_AWQOS(1) <= \\; + M_AXI_GP1_AWQOS(0) <= \\; + M_AXI_GP1_AWSIZE(2) <= \\; + M_AXI_GP1_AWSIZE(1) <= \\; + M_AXI_GP1_AWSIZE(0) <= \\; + M_AXI_GP1_AWVALID <= \\; + M_AXI_GP1_BREADY <= \\; + M_AXI_GP1_RREADY <= \\; + M_AXI_GP1_WDATA(31) <= \\; + M_AXI_GP1_WDATA(30) <= \\; + M_AXI_GP1_WDATA(29) <= \\; + M_AXI_GP1_WDATA(28) <= \\; + M_AXI_GP1_WDATA(27) <= \\; + M_AXI_GP1_WDATA(26) <= \\; + M_AXI_GP1_WDATA(25) <= \\; + M_AXI_GP1_WDATA(24) <= \\; + M_AXI_GP1_WDATA(23) <= \\; + M_AXI_GP1_WDATA(22) <= \\; + M_AXI_GP1_WDATA(21) <= \\; + M_AXI_GP1_WDATA(20) <= \\; + M_AXI_GP1_WDATA(19) <= \\; + M_AXI_GP1_WDATA(18) <= \\; + M_AXI_GP1_WDATA(17) <= \\; + M_AXI_GP1_WDATA(16) <= \\; + M_AXI_GP1_WDATA(15) <= \\; + M_AXI_GP1_WDATA(14) <= \\; + M_AXI_GP1_WDATA(13) <= \\; + M_AXI_GP1_WDATA(12) <= \\; + M_AXI_GP1_WDATA(11) <= \\; + M_AXI_GP1_WDATA(10) <= \\; + M_AXI_GP1_WDATA(9) <= \\; + M_AXI_GP1_WDATA(8) <= \\; + M_AXI_GP1_WDATA(7) <= \\; + M_AXI_GP1_WDATA(6) <= \\; + M_AXI_GP1_WDATA(5) <= \\; + M_AXI_GP1_WDATA(4) <= \\; + M_AXI_GP1_WDATA(3) <= \\; + M_AXI_GP1_WDATA(2) <= \\; + M_AXI_GP1_WDATA(1) <= \\; + M_AXI_GP1_WDATA(0) <= \\; + M_AXI_GP1_WID(11) <= \\; + M_AXI_GP1_WID(10) <= \\; + M_AXI_GP1_WID(9) <= \\; + M_AXI_GP1_WID(8) <= \\; + M_AXI_GP1_WID(7) <= \\; + M_AXI_GP1_WID(6) <= \\; + M_AXI_GP1_WID(5) <= \\; + M_AXI_GP1_WID(4) <= \\; + M_AXI_GP1_WID(3) <= \\; + M_AXI_GP1_WID(2) <= \\; + M_AXI_GP1_WID(1) <= \\; + M_AXI_GP1_WID(0) <= \\; + M_AXI_GP1_WLAST <= \\; + M_AXI_GP1_WSTRB(3) <= \\; + M_AXI_GP1_WSTRB(2) <= \\; + M_AXI_GP1_WSTRB(1) <= \\; + M_AXI_GP1_WSTRB(0) <= \\; + M_AXI_GP1_WVALID <= \\; + PJTAG_TDO <= \\; + SDIO0_BUSPOW <= \\; + SDIO0_BUSVOLT(2) <= \\; + SDIO0_BUSVOLT(1) <= \\; + SDIO0_BUSVOLT(0) <= \\; + SDIO0_CLK <= \\; + SDIO0_CMD_O <= \\; + SDIO0_CMD_T <= \\; + SDIO0_DATA_O(3) <= \\; + SDIO0_DATA_O(2) <= \\; + SDIO0_DATA_O(1) <= \\; + SDIO0_DATA_O(0) <= \\; + SDIO0_DATA_T(3) <= \\; + SDIO0_DATA_T(2) <= \\; + SDIO0_DATA_T(1) <= \\; + SDIO0_DATA_T(0) <= \\; + SDIO0_LED <= \\; + SDIO1_BUSPOW <= \\; + SDIO1_BUSVOLT(2) <= \\; + SDIO1_BUSVOLT(1) <= \\; + SDIO1_BUSVOLT(0) <= \\; + SDIO1_CLK <= \\; + SDIO1_CMD_O <= \\; + SDIO1_CMD_T <= \\; + SDIO1_DATA_O(3) <= \\; + SDIO1_DATA_O(2) <= \\; + SDIO1_DATA_O(1) <= \\; + SDIO1_DATA_O(0) <= \\; + SDIO1_DATA_T(3) <= \\; + SDIO1_DATA_T(2) <= \\; + SDIO1_DATA_T(1) <= \\; + SDIO1_DATA_T(0) <= \\; + SDIO1_LED <= \\; + SPI0_MISO_O <= \\; + SPI0_MISO_T <= \\; + SPI0_MOSI_O <= \\; + SPI0_MOSI_T <= \\; + SPI0_SCLK_O <= \\; + SPI0_SCLK_T <= \\; + SPI0_SS1_O <= \\; + SPI0_SS2_O <= \\; + SPI0_SS_O <= \\; + SPI0_SS_T <= \\; + SPI1_MISO_O <= \\; + SPI1_MISO_T <= \\; + SPI1_MOSI_O <= \\; + SPI1_MOSI_T <= \\; + SPI1_SCLK_O <= \\; + SPI1_SCLK_T <= \\; + SPI1_SS1_O <= \\; + SPI1_SS2_O <= \\; + SPI1_SS_O <= \\; + SPI1_SS_T <= \\; + S_AXI_ACP_ARESETN <= \\; + S_AXI_ACP_ARREADY <= \\; + S_AXI_ACP_AWREADY <= \\; + S_AXI_ACP_BID(2) <= \\; + S_AXI_ACP_BID(1) <= \\; + S_AXI_ACP_BID(0) <= \\; + S_AXI_ACP_BRESP(1) <= \\; + S_AXI_ACP_BRESP(0) <= \\; + S_AXI_ACP_BVALID <= \\; + S_AXI_ACP_RDATA(63) <= \\; + S_AXI_ACP_RDATA(62) <= \\; + S_AXI_ACP_RDATA(61) <= \\; + S_AXI_ACP_RDATA(60) <= \\; + S_AXI_ACP_RDATA(59) <= \\; + S_AXI_ACP_RDATA(58) <= \\; + S_AXI_ACP_RDATA(57) <= \\; + S_AXI_ACP_RDATA(56) <= \\; + S_AXI_ACP_RDATA(55) <= \\; + S_AXI_ACP_RDATA(54) <= \\; + S_AXI_ACP_RDATA(53) <= \\; + S_AXI_ACP_RDATA(52) <= \\; + S_AXI_ACP_RDATA(51) <= \\; + S_AXI_ACP_RDATA(50) <= \\; + S_AXI_ACP_RDATA(49) <= \\; + S_AXI_ACP_RDATA(48) <= \\; + S_AXI_ACP_RDATA(47) <= \\; + S_AXI_ACP_RDATA(46) <= \\; + S_AXI_ACP_RDATA(45) <= \\; + S_AXI_ACP_RDATA(44) <= \\; + S_AXI_ACP_RDATA(43) <= \\; + S_AXI_ACP_RDATA(42) <= \\; + S_AXI_ACP_RDATA(41) <= \\; + S_AXI_ACP_RDATA(40) <= \\; + S_AXI_ACP_RDATA(39) <= \\; + S_AXI_ACP_RDATA(38) <= \\; + S_AXI_ACP_RDATA(37) <= \\; + S_AXI_ACP_RDATA(36) <= \\; + S_AXI_ACP_RDATA(35) <= \\; + S_AXI_ACP_RDATA(34) <= \\; + S_AXI_ACP_RDATA(33) <= \\; + S_AXI_ACP_RDATA(32) <= \\; + S_AXI_ACP_RDATA(31) <= \\; + S_AXI_ACP_RDATA(30) <= \\; + S_AXI_ACP_RDATA(29) <= \\; + S_AXI_ACP_RDATA(28) <= \\; + S_AXI_ACP_RDATA(27) <= \\; + S_AXI_ACP_RDATA(26) <= \\; + S_AXI_ACP_RDATA(25) <= \\; + S_AXI_ACP_RDATA(24) <= \\; + S_AXI_ACP_RDATA(23) <= \\; + S_AXI_ACP_RDATA(22) <= \\; + S_AXI_ACP_RDATA(21) <= \\; + S_AXI_ACP_RDATA(20) <= \\; + S_AXI_ACP_RDATA(19) <= \\; + S_AXI_ACP_RDATA(18) <= \\; + S_AXI_ACP_RDATA(17) <= \\; + S_AXI_ACP_RDATA(16) <= \\; + S_AXI_ACP_RDATA(15) <= \\; + S_AXI_ACP_RDATA(14) <= \\; + S_AXI_ACP_RDATA(13) <= \\; + S_AXI_ACP_RDATA(12) <= \\; + S_AXI_ACP_RDATA(11) <= \\; + S_AXI_ACP_RDATA(10) <= \\; + S_AXI_ACP_RDATA(9) <= \\; + S_AXI_ACP_RDATA(8) <= \\; + S_AXI_ACP_RDATA(7) <= \\; + S_AXI_ACP_RDATA(6) <= \\; + S_AXI_ACP_RDATA(5) <= \\; + S_AXI_ACP_RDATA(4) <= \\; + S_AXI_ACP_RDATA(3) <= \\; + S_AXI_ACP_RDATA(2) <= \\; + S_AXI_ACP_RDATA(1) <= \\; + S_AXI_ACP_RDATA(0) <= \\; + S_AXI_ACP_RID(2) <= \\; + S_AXI_ACP_RID(1) <= \\; + S_AXI_ACP_RID(0) <= \\; + S_AXI_ACP_RLAST <= \\; + S_AXI_ACP_RRESP(1) <= \\; + S_AXI_ACP_RRESP(0) <= \\; + S_AXI_ACP_RVALID <= \\; + S_AXI_ACP_WREADY <= \\; + S_AXI_GP0_ARESETN <= \\; + S_AXI_GP0_ARREADY <= \\; + S_AXI_GP0_AWREADY <= \\; + S_AXI_GP0_BID(5) <= \\; + S_AXI_GP0_BID(4) <= \\; + S_AXI_GP0_BID(3) <= \\; + S_AXI_GP0_BID(2) <= \\; + S_AXI_GP0_BID(1) <= \\; + S_AXI_GP0_BID(0) <= \\; + S_AXI_GP0_BRESP(1) <= \\; + S_AXI_GP0_BRESP(0) <= \\; + S_AXI_GP0_BVALID <= \\; + S_AXI_GP0_RDATA(31) <= \\; + S_AXI_GP0_RDATA(30) <= \\; + S_AXI_GP0_RDATA(29) <= \\; + S_AXI_GP0_RDATA(28) <= \\; + S_AXI_GP0_RDATA(27) <= \\; + S_AXI_GP0_RDATA(26) <= \\; + S_AXI_GP0_RDATA(25) <= \\; + S_AXI_GP0_RDATA(24) <= \\; + S_AXI_GP0_RDATA(23) <= \\; + S_AXI_GP0_RDATA(22) <= \\; + S_AXI_GP0_RDATA(21) <= \\; + S_AXI_GP0_RDATA(20) <= \\; + S_AXI_GP0_RDATA(19) <= \\; + S_AXI_GP0_RDATA(18) <= \\; + S_AXI_GP0_RDATA(17) <= \\; + S_AXI_GP0_RDATA(16) <= \\; + S_AXI_GP0_RDATA(15) <= \\; + S_AXI_GP0_RDATA(14) <= \\; + S_AXI_GP0_RDATA(13) <= \\; + S_AXI_GP0_RDATA(12) <= \\; + S_AXI_GP0_RDATA(11) <= \\; + S_AXI_GP0_RDATA(10) <= \\; + S_AXI_GP0_RDATA(9) <= \\; + S_AXI_GP0_RDATA(8) <= \\; + S_AXI_GP0_RDATA(7) <= \\; + S_AXI_GP0_RDATA(6) <= \\; + S_AXI_GP0_RDATA(5) <= \\; + S_AXI_GP0_RDATA(4) <= \\; + S_AXI_GP0_RDATA(3) <= \\; + S_AXI_GP0_RDATA(2) <= \\; + S_AXI_GP0_RDATA(1) <= \\; + S_AXI_GP0_RDATA(0) <= \\; + S_AXI_GP0_RID(5) <= \\; + S_AXI_GP0_RID(4) <= \\; + S_AXI_GP0_RID(3) <= \\; + S_AXI_GP0_RID(2) <= \\; + S_AXI_GP0_RID(1) <= \\; + S_AXI_GP0_RID(0) <= \\; + S_AXI_GP0_RLAST <= \\; + S_AXI_GP0_RRESP(1) <= \\; + S_AXI_GP0_RRESP(0) <= \\; + S_AXI_GP0_RVALID <= \\; + S_AXI_GP0_WREADY <= \\; + S_AXI_GP1_ARESETN <= \\; + S_AXI_GP1_ARREADY <= \\; + S_AXI_GP1_AWREADY <= \\; + S_AXI_GP1_BID(5) <= \\; + S_AXI_GP1_BID(4) <= \\; + S_AXI_GP1_BID(3) <= \\; + S_AXI_GP1_BID(2) <= \\; + S_AXI_GP1_BID(1) <= \\; + S_AXI_GP1_BID(0) <= \\; + S_AXI_GP1_BRESP(1) <= \\; + S_AXI_GP1_BRESP(0) <= \\; + S_AXI_GP1_BVALID <= \\; + S_AXI_GP1_RDATA(31) <= \\; + S_AXI_GP1_RDATA(30) <= \\; + S_AXI_GP1_RDATA(29) <= \\; + S_AXI_GP1_RDATA(28) <= \\; + S_AXI_GP1_RDATA(27) <= \\; + S_AXI_GP1_RDATA(26) <= \\; + S_AXI_GP1_RDATA(25) <= \\; + S_AXI_GP1_RDATA(24) <= \\; + S_AXI_GP1_RDATA(23) <= \\; + S_AXI_GP1_RDATA(22) <= \\; + S_AXI_GP1_RDATA(21) <= \\; + S_AXI_GP1_RDATA(20) <= \\; + S_AXI_GP1_RDATA(19) <= \\; + S_AXI_GP1_RDATA(18) <= \\; + S_AXI_GP1_RDATA(17) <= \\; + S_AXI_GP1_RDATA(16) <= \\; + S_AXI_GP1_RDATA(15) <= \\; + S_AXI_GP1_RDATA(14) <= \\; + S_AXI_GP1_RDATA(13) <= \\; + S_AXI_GP1_RDATA(12) <= \\; + S_AXI_GP1_RDATA(11) <= \\; + S_AXI_GP1_RDATA(10) <= \\; + S_AXI_GP1_RDATA(9) <= \\; + S_AXI_GP1_RDATA(8) <= \\; + S_AXI_GP1_RDATA(7) <= \\; + S_AXI_GP1_RDATA(6) <= \\; + S_AXI_GP1_RDATA(5) <= \\; + S_AXI_GP1_RDATA(4) <= \\; + S_AXI_GP1_RDATA(3) <= \\; + S_AXI_GP1_RDATA(2) <= \\; + S_AXI_GP1_RDATA(1) <= \\; + S_AXI_GP1_RDATA(0) <= \\; + S_AXI_GP1_RID(5) <= \\; + S_AXI_GP1_RID(4) <= \\; + S_AXI_GP1_RID(3) <= \\; + S_AXI_GP1_RID(2) <= \\; + S_AXI_GP1_RID(1) <= \\; + S_AXI_GP1_RID(0) <= \\; + S_AXI_GP1_RLAST <= \\; + S_AXI_GP1_RRESP(1) <= \\; + S_AXI_GP1_RRESP(0) <= \\; + S_AXI_GP1_RVALID <= \\; + S_AXI_GP1_WREADY <= \\; + S_AXI_HP0_ARESETN <= \\; + S_AXI_HP0_ARREADY <= \\; + S_AXI_HP0_AWREADY <= \\; + S_AXI_HP0_BID(5) <= \\; + S_AXI_HP0_BID(4) <= \\; + S_AXI_HP0_BID(3) <= \\; + S_AXI_HP0_BID(2) <= \\; + S_AXI_HP0_BID(1) <= \\; + S_AXI_HP0_BID(0) <= \\; + S_AXI_HP0_BRESP(1) <= \\; + S_AXI_HP0_BRESP(0) <= \\; + S_AXI_HP0_BVALID <= \\; + S_AXI_HP0_RACOUNT(2) <= \\; + S_AXI_HP0_RACOUNT(1) <= \\; + S_AXI_HP0_RACOUNT(0) <= \\; + S_AXI_HP0_RCOUNT(7) <= \\; + S_AXI_HP0_RCOUNT(6) <= \\; + S_AXI_HP0_RCOUNT(5) <= \\; + S_AXI_HP0_RCOUNT(4) <= \\; + S_AXI_HP0_RCOUNT(3) <= \\; + S_AXI_HP0_RCOUNT(2) <= \\; + S_AXI_HP0_RCOUNT(1) <= \\; + S_AXI_HP0_RCOUNT(0) <= \\; + S_AXI_HP0_RDATA(63) <= \\; + S_AXI_HP0_RDATA(62) <= \\; + S_AXI_HP0_RDATA(61) <= \\; + S_AXI_HP0_RDATA(60) <= \\; + S_AXI_HP0_RDATA(59) <= \\; + S_AXI_HP0_RDATA(58) <= \\; + S_AXI_HP0_RDATA(57) <= \\; + S_AXI_HP0_RDATA(56) <= \\; + S_AXI_HP0_RDATA(55) <= \\; + S_AXI_HP0_RDATA(54) <= \\; + S_AXI_HP0_RDATA(53) <= \\; + S_AXI_HP0_RDATA(52) <= \\; + S_AXI_HP0_RDATA(51) <= \\; + S_AXI_HP0_RDATA(50) <= \\; + S_AXI_HP0_RDATA(49) <= \\; + S_AXI_HP0_RDATA(48) <= \\; + S_AXI_HP0_RDATA(47) <= \\; + S_AXI_HP0_RDATA(46) <= \\; + S_AXI_HP0_RDATA(45) <= \\; + S_AXI_HP0_RDATA(44) <= \\; + S_AXI_HP0_RDATA(43) <= \\; + S_AXI_HP0_RDATA(42) <= \\; + S_AXI_HP0_RDATA(41) <= \\; + S_AXI_HP0_RDATA(40) <= \\; + S_AXI_HP0_RDATA(39) <= \\; + S_AXI_HP0_RDATA(38) <= \\; + S_AXI_HP0_RDATA(37) <= \\; + S_AXI_HP0_RDATA(36) <= \\; + S_AXI_HP0_RDATA(35) <= \\; + S_AXI_HP0_RDATA(34) <= \\; + S_AXI_HP0_RDATA(33) <= \\; + S_AXI_HP0_RDATA(32) <= \\; + S_AXI_HP0_RDATA(31) <= \\; + S_AXI_HP0_RDATA(30) <= \\; + S_AXI_HP0_RDATA(29) <= \\; + S_AXI_HP0_RDATA(28) <= \\; + S_AXI_HP0_RDATA(27) <= \\; + S_AXI_HP0_RDATA(26) <= \\; + S_AXI_HP0_RDATA(25) <= \\; + S_AXI_HP0_RDATA(24) <= \\; + S_AXI_HP0_RDATA(23) <= \\; + S_AXI_HP0_RDATA(22) <= \\; + S_AXI_HP0_RDATA(21) <= \\; + S_AXI_HP0_RDATA(20) <= \\; + S_AXI_HP0_RDATA(19) <= \\; + S_AXI_HP0_RDATA(18) <= \\; + S_AXI_HP0_RDATA(17) <= \\; + S_AXI_HP0_RDATA(16) <= \\; + S_AXI_HP0_RDATA(15) <= \\; + S_AXI_HP0_RDATA(14) <= \\; + S_AXI_HP0_RDATA(13) <= \\; + S_AXI_HP0_RDATA(12) <= \\; + S_AXI_HP0_RDATA(11) <= \\; + S_AXI_HP0_RDATA(10) <= \\; + S_AXI_HP0_RDATA(9) <= \\; + S_AXI_HP0_RDATA(8) <= \\; + S_AXI_HP0_RDATA(7) <= \\; + S_AXI_HP0_RDATA(6) <= \\; + S_AXI_HP0_RDATA(5) <= \\; + S_AXI_HP0_RDATA(4) <= \\; + S_AXI_HP0_RDATA(3) <= \\; + S_AXI_HP0_RDATA(2) <= \\; + S_AXI_HP0_RDATA(1) <= \\; + S_AXI_HP0_RDATA(0) <= \\; + S_AXI_HP0_RID(5) <= \\; + S_AXI_HP0_RID(4) <= \\; + S_AXI_HP0_RID(3) <= \\; + S_AXI_HP0_RID(2) <= \\; + S_AXI_HP0_RID(1) <= \\; + S_AXI_HP0_RID(0) <= \\; + S_AXI_HP0_RLAST <= \\; + S_AXI_HP0_RRESP(1) <= \\; + S_AXI_HP0_RRESP(0) <= \\; + S_AXI_HP0_RVALID <= \\; + S_AXI_HP0_WACOUNT(5) <= \\; + S_AXI_HP0_WACOUNT(4) <= \\; + S_AXI_HP0_WACOUNT(3) <= \\; + S_AXI_HP0_WACOUNT(2) <= \\; + S_AXI_HP0_WACOUNT(1) <= \\; + S_AXI_HP0_WACOUNT(0) <= \\; + S_AXI_HP0_WCOUNT(7) <= \\; + S_AXI_HP0_WCOUNT(6) <= \\; + S_AXI_HP0_WCOUNT(5) <= \\; + S_AXI_HP0_WCOUNT(4) <= \\; + S_AXI_HP0_WCOUNT(3) <= \\; + S_AXI_HP0_WCOUNT(2) <= \\; + S_AXI_HP0_WCOUNT(1) <= \\; + S_AXI_HP0_WCOUNT(0) <= \\; + S_AXI_HP0_WREADY <= \\; + S_AXI_HP1_ARESETN <= \\; + S_AXI_HP1_ARREADY <= \\; + S_AXI_HP1_AWREADY <= \\; + S_AXI_HP1_BID(5) <= \\; + S_AXI_HP1_BID(4) <= \\; + S_AXI_HP1_BID(3) <= \\; + S_AXI_HP1_BID(2) <= \\; + S_AXI_HP1_BID(1) <= \\; + S_AXI_HP1_BID(0) <= \\; + S_AXI_HP1_BRESP(1) <= \\; + S_AXI_HP1_BRESP(0) <= \\; + S_AXI_HP1_BVALID <= \\; + S_AXI_HP1_RACOUNT(2) <= \\; + S_AXI_HP1_RACOUNT(1) <= \\; + S_AXI_HP1_RACOUNT(0) <= \\; + S_AXI_HP1_RCOUNT(7) <= \\; + S_AXI_HP1_RCOUNT(6) <= \\; + S_AXI_HP1_RCOUNT(5) <= \\; + S_AXI_HP1_RCOUNT(4) <= \\; + S_AXI_HP1_RCOUNT(3) <= \\; + S_AXI_HP1_RCOUNT(2) <= \\; + S_AXI_HP1_RCOUNT(1) <= \\; + S_AXI_HP1_RCOUNT(0) <= \\; + S_AXI_HP1_RDATA(63) <= \\; + S_AXI_HP1_RDATA(62) <= \\; + S_AXI_HP1_RDATA(61) <= \\; + S_AXI_HP1_RDATA(60) <= \\; + S_AXI_HP1_RDATA(59) <= \\; + S_AXI_HP1_RDATA(58) <= \\; + S_AXI_HP1_RDATA(57) <= \\; + S_AXI_HP1_RDATA(56) <= \\; + S_AXI_HP1_RDATA(55) <= \\; + S_AXI_HP1_RDATA(54) <= \\; + S_AXI_HP1_RDATA(53) <= \\; + S_AXI_HP1_RDATA(52) <= \\; + S_AXI_HP1_RDATA(51) <= \\; + S_AXI_HP1_RDATA(50) <= \\; + S_AXI_HP1_RDATA(49) <= \\; + S_AXI_HP1_RDATA(48) <= \\; + S_AXI_HP1_RDATA(47) <= \\; + S_AXI_HP1_RDATA(46) <= \\; + S_AXI_HP1_RDATA(45) <= \\; + S_AXI_HP1_RDATA(44) <= \\; + S_AXI_HP1_RDATA(43) <= \\; + S_AXI_HP1_RDATA(42) <= \\; + S_AXI_HP1_RDATA(41) <= \\; + S_AXI_HP1_RDATA(40) <= \\; + S_AXI_HP1_RDATA(39) <= \\; + S_AXI_HP1_RDATA(38) <= \\; + S_AXI_HP1_RDATA(37) <= \\; + S_AXI_HP1_RDATA(36) <= \\; + S_AXI_HP1_RDATA(35) <= \\; + S_AXI_HP1_RDATA(34) <= \\; + S_AXI_HP1_RDATA(33) <= \\; + S_AXI_HP1_RDATA(32) <= \\; + S_AXI_HP1_RDATA(31) <= \\; + S_AXI_HP1_RDATA(30) <= \\; + S_AXI_HP1_RDATA(29) <= \\; + S_AXI_HP1_RDATA(28) <= \\; + S_AXI_HP1_RDATA(27) <= \\; + S_AXI_HP1_RDATA(26) <= \\; + S_AXI_HP1_RDATA(25) <= \\; + S_AXI_HP1_RDATA(24) <= \\; + S_AXI_HP1_RDATA(23) <= \\; + S_AXI_HP1_RDATA(22) <= \\; + S_AXI_HP1_RDATA(21) <= \\; + S_AXI_HP1_RDATA(20) <= \\; + S_AXI_HP1_RDATA(19) <= \\; + S_AXI_HP1_RDATA(18) <= \\; + S_AXI_HP1_RDATA(17) <= \\; + S_AXI_HP1_RDATA(16) <= \\; + S_AXI_HP1_RDATA(15) <= \\; + S_AXI_HP1_RDATA(14) <= \\; + S_AXI_HP1_RDATA(13) <= \\; + S_AXI_HP1_RDATA(12) <= \\; + S_AXI_HP1_RDATA(11) <= \\; + S_AXI_HP1_RDATA(10) <= \\; + S_AXI_HP1_RDATA(9) <= \\; + S_AXI_HP1_RDATA(8) <= \\; + S_AXI_HP1_RDATA(7) <= \\; + S_AXI_HP1_RDATA(6) <= \\; + S_AXI_HP1_RDATA(5) <= \\; + S_AXI_HP1_RDATA(4) <= \\; + S_AXI_HP1_RDATA(3) <= \\; + S_AXI_HP1_RDATA(2) <= \\; + S_AXI_HP1_RDATA(1) <= \\; + S_AXI_HP1_RDATA(0) <= \\; + S_AXI_HP1_RID(5) <= \\; + S_AXI_HP1_RID(4) <= \\; + S_AXI_HP1_RID(3) <= \\; + S_AXI_HP1_RID(2) <= \\; + S_AXI_HP1_RID(1) <= \\; + S_AXI_HP1_RID(0) <= \\; + S_AXI_HP1_RLAST <= \\; + S_AXI_HP1_RRESP(1) <= \\; + S_AXI_HP1_RRESP(0) <= \\; + S_AXI_HP1_RVALID <= \\; + S_AXI_HP1_WACOUNT(5) <= \\; + S_AXI_HP1_WACOUNT(4) <= \\; + S_AXI_HP1_WACOUNT(3) <= \\; + S_AXI_HP1_WACOUNT(2) <= \\; + S_AXI_HP1_WACOUNT(1) <= \\; + S_AXI_HP1_WACOUNT(0) <= \\; + S_AXI_HP1_WCOUNT(7) <= \\; + S_AXI_HP1_WCOUNT(6) <= \\; + S_AXI_HP1_WCOUNT(5) <= \\; + S_AXI_HP1_WCOUNT(4) <= \\; + S_AXI_HP1_WCOUNT(3) <= \\; + S_AXI_HP1_WCOUNT(2) <= \\; + S_AXI_HP1_WCOUNT(1) <= \\; + S_AXI_HP1_WCOUNT(0) <= \\; + S_AXI_HP1_WREADY <= \\; + S_AXI_HP2_ARESETN <= \\; + S_AXI_HP2_ARREADY <= \\; + S_AXI_HP2_AWREADY <= \\; + S_AXI_HP2_BID(5) <= \\; + S_AXI_HP2_BID(4) <= \\; + S_AXI_HP2_BID(3) <= \\; + S_AXI_HP2_BID(2) <= \\; + S_AXI_HP2_BID(1) <= \\; + S_AXI_HP2_BID(0) <= \\; + S_AXI_HP2_BRESP(1) <= \\; + S_AXI_HP2_BRESP(0) <= \\; + S_AXI_HP2_BVALID <= \\; + S_AXI_HP2_RACOUNT(2) <= \\; + S_AXI_HP2_RACOUNT(1) <= \\; + S_AXI_HP2_RACOUNT(0) <= \\; + S_AXI_HP2_RCOUNT(7) <= \\; + S_AXI_HP2_RCOUNT(6) <= \\; + S_AXI_HP2_RCOUNT(5) <= \\; + S_AXI_HP2_RCOUNT(4) <= \\; + S_AXI_HP2_RCOUNT(3) <= \\; + S_AXI_HP2_RCOUNT(2) <= \\; + S_AXI_HP2_RCOUNT(1) <= \\; + S_AXI_HP2_RCOUNT(0) <= \\; + S_AXI_HP2_RDATA(63) <= \\; + S_AXI_HP2_RDATA(62) <= \\; + S_AXI_HP2_RDATA(61) <= \\; + S_AXI_HP2_RDATA(60) <= \\; + S_AXI_HP2_RDATA(59) <= \\; + S_AXI_HP2_RDATA(58) <= \\; + S_AXI_HP2_RDATA(57) <= \\; + S_AXI_HP2_RDATA(56) <= \\; + S_AXI_HP2_RDATA(55) <= \\; + S_AXI_HP2_RDATA(54) <= \\; + S_AXI_HP2_RDATA(53) <= \\; + S_AXI_HP2_RDATA(52) <= \\; + S_AXI_HP2_RDATA(51) <= \\; + S_AXI_HP2_RDATA(50) <= \\; + S_AXI_HP2_RDATA(49) <= \\; + S_AXI_HP2_RDATA(48) <= \\; + S_AXI_HP2_RDATA(47) <= \\; + S_AXI_HP2_RDATA(46) <= \\; + S_AXI_HP2_RDATA(45) <= \\; + S_AXI_HP2_RDATA(44) <= \\; + S_AXI_HP2_RDATA(43) <= \\; + S_AXI_HP2_RDATA(42) <= \\; + S_AXI_HP2_RDATA(41) <= \\; + S_AXI_HP2_RDATA(40) <= \\; + S_AXI_HP2_RDATA(39) <= \\; + S_AXI_HP2_RDATA(38) <= \\; + S_AXI_HP2_RDATA(37) <= \\; + S_AXI_HP2_RDATA(36) <= \\; + S_AXI_HP2_RDATA(35) <= \\; + S_AXI_HP2_RDATA(34) <= \\; + S_AXI_HP2_RDATA(33) <= \\; + S_AXI_HP2_RDATA(32) <= \\; + S_AXI_HP2_RDATA(31) <= \\; + S_AXI_HP2_RDATA(30) <= \\; + S_AXI_HP2_RDATA(29) <= \\; + S_AXI_HP2_RDATA(28) <= \\; + S_AXI_HP2_RDATA(27) <= \\; + S_AXI_HP2_RDATA(26) <= \\; + S_AXI_HP2_RDATA(25) <= \\; + S_AXI_HP2_RDATA(24) <= \\; + S_AXI_HP2_RDATA(23) <= \\; + S_AXI_HP2_RDATA(22) <= \\; + S_AXI_HP2_RDATA(21) <= \\; + S_AXI_HP2_RDATA(20) <= \\; + S_AXI_HP2_RDATA(19) <= \\; + S_AXI_HP2_RDATA(18) <= \\; + S_AXI_HP2_RDATA(17) <= \\; + S_AXI_HP2_RDATA(16) <= \\; + S_AXI_HP2_RDATA(15) <= \\; + S_AXI_HP2_RDATA(14) <= \\; + S_AXI_HP2_RDATA(13) <= \\; + S_AXI_HP2_RDATA(12) <= \\; + S_AXI_HP2_RDATA(11) <= \\; + S_AXI_HP2_RDATA(10) <= \\; + S_AXI_HP2_RDATA(9) <= \\; + S_AXI_HP2_RDATA(8) <= \\; + S_AXI_HP2_RDATA(7) <= \\; + S_AXI_HP2_RDATA(6) <= \\; + S_AXI_HP2_RDATA(5) <= \\; + S_AXI_HP2_RDATA(4) <= \\; + S_AXI_HP2_RDATA(3) <= \\; + S_AXI_HP2_RDATA(2) <= \\; + S_AXI_HP2_RDATA(1) <= \\; + S_AXI_HP2_RDATA(0) <= \\; + S_AXI_HP2_RID(5) <= \\; + S_AXI_HP2_RID(4) <= \\; + S_AXI_HP2_RID(3) <= \\; + S_AXI_HP2_RID(2) <= \\; + S_AXI_HP2_RID(1) <= \\; + S_AXI_HP2_RID(0) <= \\; + S_AXI_HP2_RLAST <= \\; + S_AXI_HP2_RRESP(1) <= \\; + S_AXI_HP2_RRESP(0) <= \\; + S_AXI_HP2_RVALID <= \\; + S_AXI_HP2_WACOUNT(5) <= \\; + S_AXI_HP2_WACOUNT(4) <= \\; + S_AXI_HP2_WACOUNT(3) <= \\; + S_AXI_HP2_WACOUNT(2) <= \\; + S_AXI_HP2_WACOUNT(1) <= \\; + S_AXI_HP2_WACOUNT(0) <= \\; + S_AXI_HP2_WCOUNT(7) <= \\; + S_AXI_HP2_WCOUNT(6) <= \\; + S_AXI_HP2_WCOUNT(5) <= \\; + S_AXI_HP2_WCOUNT(4) <= \\; + S_AXI_HP2_WCOUNT(3) <= \\; + S_AXI_HP2_WCOUNT(2) <= \\; + S_AXI_HP2_WCOUNT(1) <= \\; + S_AXI_HP2_WCOUNT(0) <= \\; + S_AXI_HP2_WREADY <= \\; + S_AXI_HP3_ARESETN <= \\; + S_AXI_HP3_ARREADY <= \\; + S_AXI_HP3_AWREADY <= \\; + S_AXI_HP3_BID(5) <= \\; + S_AXI_HP3_BID(4) <= \\; + S_AXI_HP3_BID(3) <= \\; + S_AXI_HP3_BID(2) <= \\; + S_AXI_HP3_BID(1) <= \\; + S_AXI_HP3_BID(0) <= \\; + S_AXI_HP3_BRESP(1) <= \\; + S_AXI_HP3_BRESP(0) <= \\; + S_AXI_HP3_BVALID <= \\; + S_AXI_HP3_RACOUNT(2) <= \\; + S_AXI_HP3_RACOUNT(1) <= \\; + S_AXI_HP3_RACOUNT(0) <= \\; + S_AXI_HP3_RCOUNT(7) <= \\; + S_AXI_HP3_RCOUNT(6) <= \\; + S_AXI_HP3_RCOUNT(5) <= \\; + S_AXI_HP3_RCOUNT(4) <= \\; + S_AXI_HP3_RCOUNT(3) <= \\; + S_AXI_HP3_RCOUNT(2) <= \\; + S_AXI_HP3_RCOUNT(1) <= \\; + S_AXI_HP3_RCOUNT(0) <= \\; + S_AXI_HP3_RDATA(63) <= \\; + S_AXI_HP3_RDATA(62) <= \\; + S_AXI_HP3_RDATA(61) <= \\; + S_AXI_HP3_RDATA(60) <= \\; + S_AXI_HP3_RDATA(59) <= \\; + S_AXI_HP3_RDATA(58) <= \\; + S_AXI_HP3_RDATA(57) <= \\; + S_AXI_HP3_RDATA(56) <= \\; + S_AXI_HP3_RDATA(55) <= \\; + S_AXI_HP3_RDATA(54) <= \\; + S_AXI_HP3_RDATA(53) <= \\; + S_AXI_HP3_RDATA(52) <= \\; + S_AXI_HP3_RDATA(51) <= \\; + S_AXI_HP3_RDATA(50) <= \\; + S_AXI_HP3_RDATA(49) <= \\; + S_AXI_HP3_RDATA(48) <= \\; + S_AXI_HP3_RDATA(47) <= \\; + S_AXI_HP3_RDATA(46) <= \\; + S_AXI_HP3_RDATA(45) <= \\; + S_AXI_HP3_RDATA(44) <= \\; + S_AXI_HP3_RDATA(43) <= \\; + S_AXI_HP3_RDATA(42) <= \\; + S_AXI_HP3_RDATA(41) <= \\; + S_AXI_HP3_RDATA(40) <= \\; + S_AXI_HP3_RDATA(39) <= \\; + S_AXI_HP3_RDATA(38) <= \\; + S_AXI_HP3_RDATA(37) <= \\; + S_AXI_HP3_RDATA(36) <= \\; + S_AXI_HP3_RDATA(35) <= \\; + S_AXI_HP3_RDATA(34) <= \\; + S_AXI_HP3_RDATA(33) <= \\; + S_AXI_HP3_RDATA(32) <= \\; + S_AXI_HP3_RDATA(31) <= \\; + S_AXI_HP3_RDATA(30) <= \\; + S_AXI_HP3_RDATA(29) <= \\; + S_AXI_HP3_RDATA(28) <= \\; + S_AXI_HP3_RDATA(27) <= \\; + S_AXI_HP3_RDATA(26) <= \\; + S_AXI_HP3_RDATA(25) <= \\; + S_AXI_HP3_RDATA(24) <= \\; + S_AXI_HP3_RDATA(23) <= \\; + S_AXI_HP3_RDATA(22) <= \\; + S_AXI_HP3_RDATA(21) <= \\; + S_AXI_HP3_RDATA(20) <= \\; + S_AXI_HP3_RDATA(19) <= \\; + S_AXI_HP3_RDATA(18) <= \\; + S_AXI_HP3_RDATA(17) <= \\; + S_AXI_HP3_RDATA(16) <= \\; + S_AXI_HP3_RDATA(15) <= \\; + S_AXI_HP3_RDATA(14) <= \\; + S_AXI_HP3_RDATA(13) <= \\; + S_AXI_HP3_RDATA(12) <= \\; + S_AXI_HP3_RDATA(11) <= \\; + S_AXI_HP3_RDATA(10) <= \\; + S_AXI_HP3_RDATA(9) <= \\; + S_AXI_HP3_RDATA(8) <= \\; + S_AXI_HP3_RDATA(7) <= \\; + S_AXI_HP3_RDATA(6) <= \\; + S_AXI_HP3_RDATA(5) <= \\; + S_AXI_HP3_RDATA(4) <= \\; + S_AXI_HP3_RDATA(3) <= \\; + S_AXI_HP3_RDATA(2) <= \\; + S_AXI_HP3_RDATA(1) <= \\; + S_AXI_HP3_RDATA(0) <= \\; + S_AXI_HP3_RID(5) <= \\; + S_AXI_HP3_RID(4) <= \\; + S_AXI_HP3_RID(3) <= \\; + S_AXI_HP3_RID(2) <= \\; + S_AXI_HP3_RID(1) <= \\; + S_AXI_HP3_RID(0) <= \\; + S_AXI_HP3_RLAST <= \\; + S_AXI_HP3_RRESP(1) <= \\; + S_AXI_HP3_RRESP(0) <= \\; + S_AXI_HP3_RVALID <= \\; + S_AXI_HP3_WACOUNT(5) <= \\; + S_AXI_HP3_WACOUNT(4) <= \\; + S_AXI_HP3_WACOUNT(3) <= \\; + S_AXI_HP3_WACOUNT(2) <= \\; + S_AXI_HP3_WACOUNT(1) <= \\; + S_AXI_HP3_WACOUNT(0) <= \\; + S_AXI_HP3_WCOUNT(7) <= \\; + S_AXI_HP3_WCOUNT(6) <= \\; + S_AXI_HP3_WCOUNT(5) <= \\; + S_AXI_HP3_WCOUNT(4) <= \\; + S_AXI_HP3_WCOUNT(3) <= \\; + S_AXI_HP3_WCOUNT(2) <= \\; + S_AXI_HP3_WCOUNT(1) <= \\; + S_AXI_HP3_WCOUNT(0) <= \\; + S_AXI_HP3_WREADY <= \\; + TRACE_CLK_OUT <= \\; + TRACE_CTL <= \TRACE_CTL_PIPE[0]\; + TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0); + TTC0_WAVE0_OUT <= \\; + TTC0_WAVE1_OUT <= \\; + TTC0_WAVE2_OUT <= \\; + TTC1_WAVE0_OUT <= \\; + TTC1_WAVE1_OUT <= \\; + TTC1_WAVE2_OUT <= \\; + UART0_DTRN <= \\; + UART0_RTSN <= \\; + UART0_TX <= \\; + UART1_DTRN <= \\; + UART1_RTSN <= \\; + UART1_TX <= \\; + USB0_PORT_INDCTL(1) <= \\; + USB0_PORT_INDCTL(0) <= \\; + USB0_VBUS_PWRSELECT <= \\; + USB1_PORT_INDCTL(1) <= \\; + USB1_PORT_INDCTL(0) <= \\; + USB1_VBUS_PWRSELECT <= \\; + WDT_RST_OUT <= \\; +DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_CAS_n, + PAD => DDR_CAS_n + ); +DDR_CKE_BIBUF: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_CKE, + PAD => DDR_CKE + ); +DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_CS_n, + PAD => DDR_CS_n + ); +DDR_Clk_BIBUF: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Clk, + PAD => DDR_Clk + ); +DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Clk_n, + PAD => DDR_Clk_n + ); +DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DRSTB, + PAD => DDR_DRSTB + ); +DDR_ODT_BIBUF: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_ODT, + PAD => DDR_ODT + ); +DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_RAS_n, + PAD => DDR_RAS_n + ); +DDR_VRN_BIBUF: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_VRN, + PAD => DDR_VRN + ); +DDR_VRP_BIBUF: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_VRP, + PAD => DDR_VRP + ); +DDR_WEB_BIBUF: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_WEB, + PAD => DDR_WEB + ); +GND: unisim.vcomponents.GND + port map ( + G => \\ + ); +PS7_i: unisim.vcomponents.PS7 + port map ( + DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0), + DDRARB(3 downto 0) => B"0000", + DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0), + DDRCASB => buffered_DDR_CAS_n, + DDRCKE => buffered_DDR_CKE, + DDRCKN => buffered_DDR_Clk_n, + DDRCKP => buffered_DDR_Clk, + DDRCSB => buffered_DDR_CS_n, + DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0), + DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0), + DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0), + DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0), + DDRDRSTB => buffered_DDR_DRSTB, + DDRODT => buffered_DDR_ODT, + DDRRASB => buffered_DDR_RAS_n, + DDRVRN => buffered_DDR_VRN, + DDRVRP => buffered_DDR_VRP, + DDRWEB => buffered_DDR_WEB, + DMA0ACLK => '0', + DMA0DAREADY => '0', + DMA0DATYPE(1) => PS7_i_n_224, + DMA0DATYPE(0) => PS7_i_n_225, + DMA0DAVALID => PS7_i_n_0, + DMA0DRLAST => '0', + DMA0DRREADY => PS7_i_n_1, + DMA0DRTYPE(1 downto 0) => B"00", + DMA0DRVALID => '0', + DMA0RSTN => PS7_i_n_2, + DMA1ACLK => '0', + DMA1DAREADY => '0', + DMA1DATYPE(1) => PS7_i_n_226, + DMA1DATYPE(0) => PS7_i_n_227, + DMA1DAVALID => PS7_i_n_3, + DMA1DRLAST => '0', + DMA1DRREADY => PS7_i_n_4, + DMA1DRTYPE(1 downto 0) => B"00", + DMA1DRVALID => '0', + DMA1RSTN => PS7_i_n_5, + DMA2ACLK => '0', + DMA2DAREADY => '0', + DMA2DATYPE(1) => PS7_i_n_228, + DMA2DATYPE(0) => PS7_i_n_229, + DMA2DAVALID => PS7_i_n_6, + DMA2DRLAST => '0', + DMA2DRREADY => PS7_i_n_7, + DMA2DRTYPE(1 downto 0) => B"00", + DMA2DRVALID => '0', + DMA2RSTN => PS7_i_n_8, + DMA3ACLK => '0', + DMA3DAREADY => '0', + DMA3DATYPE(1) => PS7_i_n_230, + DMA3DATYPE(0) => PS7_i_n_231, + DMA3DAVALID => PS7_i_n_9, + DMA3DRLAST => '0', + DMA3DRREADY => PS7_i_n_10, + DMA3DRTYPE(1 downto 0) => B"00", + DMA3DRVALID => '0', + DMA3RSTN => PS7_i_n_11, + EMIOCAN0PHYRX => '0', + EMIOCAN0PHYTX => PS7_i_n_12, + EMIOCAN1PHYRX => '0', + EMIOCAN1PHYTX => PS7_i_n_13, + EMIOENET0EXTINTIN => '0', + EMIOENET0GMIICOL => '0', + EMIOENET0GMIICRS => '0', + EMIOENET0GMIIRXCLK => '0', + EMIOENET0GMIIRXD(7 downto 0) => B"00000000", + EMIOENET0GMIIRXDV => '0', + EMIOENET0GMIIRXER => '0', + EMIOENET0GMIITXCLK => '0', + EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0), + EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED, + EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED, + EMIOENET0MDIOI => '0', + EMIOENET0MDIOMDC => PS7_i_n_16, + EMIOENET0MDIOO => PS7_i_n_17, + EMIOENET0MDIOTN => ENET0_MDIO_T_n, + EMIOENET0PTPDELAYREQRX => PS7_i_n_19, + EMIOENET0PTPDELAYREQTX => PS7_i_n_20, + EMIOENET0PTPPDELAYREQRX => PS7_i_n_21, + EMIOENET0PTPPDELAYREQTX => PS7_i_n_22, + EMIOENET0PTPPDELAYRESPRX => PS7_i_n_23, + EMIOENET0PTPPDELAYRESPTX => PS7_i_n_24, + EMIOENET0PTPSYNCFRAMERX => PS7_i_n_25, + EMIOENET0PTPSYNCFRAMETX => PS7_i_n_26, + EMIOENET0SOFRX => PS7_i_n_27, + EMIOENET0SOFTX => PS7_i_n_28, + EMIOENET1EXTINTIN => '0', + EMIOENET1GMIICOL => '0', + EMIOENET1GMIICRS => '0', + EMIOENET1GMIIRXCLK => '0', + EMIOENET1GMIIRXD(7 downto 0) => B"00000000", + EMIOENET1GMIIRXDV => '0', + EMIOENET1GMIIRXER => '0', + EMIOENET1GMIITXCLK => '0', + EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0), + EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED, + EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED, + EMIOENET1MDIOI => '0', + EMIOENET1MDIOMDC => PS7_i_n_31, + EMIOENET1MDIOO => PS7_i_n_32, + EMIOENET1MDIOTN => ENET1_MDIO_T_n, + EMIOENET1PTPDELAYREQRX => PS7_i_n_34, + EMIOENET1PTPDELAYREQTX => PS7_i_n_35, + EMIOENET1PTPPDELAYREQRX => PS7_i_n_36, + EMIOENET1PTPPDELAYREQTX => PS7_i_n_37, + EMIOENET1PTPPDELAYRESPRX => PS7_i_n_38, + EMIOENET1PTPPDELAYRESPTX => PS7_i_n_39, + EMIOENET1PTPSYNCFRAMERX => PS7_i_n_40, + EMIOENET1PTPSYNCFRAMETX => PS7_i_n_41, + EMIOENET1SOFRX => PS7_i_n_42, + EMIOENET1SOFTX => PS7_i_n_43, + EMIOGPIOI(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + EMIOGPIOO(63) => PS7_i_n_873, + EMIOGPIOO(62) => PS7_i_n_874, + EMIOGPIOO(61) => PS7_i_n_875, + EMIOGPIOO(60) => PS7_i_n_876, + EMIOGPIOO(59) => PS7_i_n_877, + EMIOGPIOO(58) => PS7_i_n_878, + EMIOGPIOO(57) => PS7_i_n_879, + EMIOGPIOO(56) => PS7_i_n_880, + EMIOGPIOO(55) => PS7_i_n_881, + EMIOGPIOO(54) => PS7_i_n_882, + EMIOGPIOO(53) => PS7_i_n_883, + EMIOGPIOO(52) => PS7_i_n_884, + EMIOGPIOO(51) => PS7_i_n_885, + EMIOGPIOO(50) => PS7_i_n_886, + EMIOGPIOO(49) => PS7_i_n_887, + EMIOGPIOO(48) => PS7_i_n_888, + EMIOGPIOO(47) => PS7_i_n_889, + EMIOGPIOO(46) => PS7_i_n_890, + EMIOGPIOO(45) => PS7_i_n_891, + EMIOGPIOO(44) => PS7_i_n_892, + EMIOGPIOO(43) => PS7_i_n_893, + EMIOGPIOO(42) => PS7_i_n_894, + EMIOGPIOO(41) => PS7_i_n_895, + EMIOGPIOO(40) => PS7_i_n_896, + EMIOGPIOO(39) => PS7_i_n_897, + EMIOGPIOO(38) => PS7_i_n_898, + EMIOGPIOO(37) => PS7_i_n_899, + EMIOGPIOO(36) => PS7_i_n_900, + EMIOGPIOO(35) => PS7_i_n_901, + EMIOGPIOO(34) => PS7_i_n_902, + EMIOGPIOO(33) => PS7_i_n_903, + EMIOGPIOO(32) => PS7_i_n_904, + EMIOGPIOO(31) => PS7_i_n_905, + EMIOGPIOO(30) => PS7_i_n_906, + EMIOGPIOO(29) => PS7_i_n_907, + EMIOGPIOO(28) => PS7_i_n_908, + EMIOGPIOO(27) => PS7_i_n_909, + EMIOGPIOO(26) => PS7_i_n_910, + EMIOGPIOO(25) => PS7_i_n_911, + EMIOGPIOO(24) => PS7_i_n_912, + EMIOGPIOO(23) => PS7_i_n_913, + EMIOGPIOO(22) => PS7_i_n_914, + EMIOGPIOO(21) => PS7_i_n_915, + EMIOGPIOO(20) => PS7_i_n_916, + EMIOGPIOO(19) => PS7_i_n_917, + EMIOGPIOO(18) => PS7_i_n_918, + EMIOGPIOO(17) => PS7_i_n_919, + EMIOGPIOO(16) => PS7_i_n_920, + EMIOGPIOO(15) => PS7_i_n_921, + EMIOGPIOO(14) => PS7_i_n_922, + EMIOGPIOO(13) => PS7_i_n_923, + EMIOGPIOO(12) => PS7_i_n_924, + EMIOGPIOO(11) => PS7_i_n_925, + EMIOGPIOO(10) => PS7_i_n_926, + EMIOGPIOO(9) => PS7_i_n_927, + EMIOGPIOO(8) => PS7_i_n_928, + EMIOGPIOO(7) => PS7_i_n_929, + EMIOGPIOO(6) => PS7_i_n_930, + EMIOGPIOO(5) => PS7_i_n_931, + EMIOGPIOO(4) => PS7_i_n_932, + EMIOGPIOO(3) => PS7_i_n_933, + EMIOGPIOO(2) => PS7_i_n_934, + EMIOGPIOO(1) => PS7_i_n_935, + EMIOGPIOO(0) => PS7_i_n_936, + EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0), + EMIOI2C0SCLI => '0', + EMIOI2C0SCLO => PS7_i_n_44, + EMIOI2C0SCLTN => I2C0_SCL_T_n, + EMIOI2C0SDAI => '0', + EMIOI2C0SDAO => PS7_i_n_46, + EMIOI2C0SDATN => I2C0_SDA_T_n, + EMIOI2C1SCLI => '0', + EMIOI2C1SCLO => PS7_i_n_48, + EMIOI2C1SCLTN => I2C1_SCL_T_n, + EMIOI2C1SDAI => '0', + EMIOI2C1SDAO => PS7_i_n_50, + EMIOI2C1SDATN => I2C1_SDA_T_n, + EMIOPJTAGTCK => '0', + EMIOPJTAGTDI => '0', + EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED, + EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED, + EMIOPJTAGTMS => '0', + EMIOSDIO0BUSPOW => PS7_i_n_54, + EMIOSDIO0BUSVOLT(2) => PS7_i_n_321, + EMIOSDIO0BUSVOLT(1) => PS7_i_n_322, + EMIOSDIO0BUSVOLT(0) => PS7_i_n_323, + EMIOSDIO0CDN => '0', + EMIOSDIO0CLK => PS7_i_n_55, + EMIOSDIO0CLKFB => '0', + EMIOSDIO0CMDI => '0', + EMIOSDIO0CMDO => PS7_i_n_56, + EMIOSDIO0CMDTN => SDIO0_CMD_T_n, + EMIOSDIO0DATAI(3 downto 0) => B"0000", + EMIOSDIO0DATAO(3) => PS7_i_n_689, + EMIOSDIO0DATAO(2) => PS7_i_n_690, + EMIOSDIO0DATAO(1) => PS7_i_n_691, + EMIOSDIO0DATAO(0) => PS7_i_n_692, + EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0), + EMIOSDIO0LED => PS7_i_n_58, + EMIOSDIO0WP => '0', + EMIOSDIO1BUSPOW => PS7_i_n_59, + EMIOSDIO1BUSVOLT(2) => PS7_i_n_324, + EMIOSDIO1BUSVOLT(1) => PS7_i_n_325, + EMIOSDIO1BUSVOLT(0) => PS7_i_n_326, + EMIOSDIO1CDN => '0', + EMIOSDIO1CLK => PS7_i_n_60, + EMIOSDIO1CLKFB => '0', + EMIOSDIO1CMDI => '0', + EMIOSDIO1CMDO => PS7_i_n_61, + EMIOSDIO1CMDTN => SDIO1_CMD_T_n, + EMIOSDIO1DATAI(3 downto 0) => B"0000", + EMIOSDIO1DATAO(3) => PS7_i_n_697, + EMIOSDIO1DATAO(2) => PS7_i_n_698, + EMIOSDIO1DATAO(1) => PS7_i_n_699, + EMIOSDIO1DATAO(0) => PS7_i_n_700, + EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0), + EMIOSDIO1LED => PS7_i_n_63, + EMIOSDIO1WP => '0', + EMIOSPI0MI => '0', + EMIOSPI0MO => PS7_i_n_64, + EMIOSPI0MOTN => SPI0_MOSI_T_n, + EMIOSPI0SCLKI => '0', + EMIOSPI0SCLKO => PS7_i_n_66, + EMIOSPI0SCLKTN => SPI0_SCLK_T_n, + EMIOSPI0SI => '0', + EMIOSPI0SO => PS7_i_n_68, + EMIOSPI0SSIN => '0', + EMIOSPI0SSNTN => SPI0_SS_T_n, + EMIOSPI0SSON(2) => PS7_i_n_327, + EMIOSPI0SSON(1) => PS7_i_n_328, + EMIOSPI0SSON(0) => PS7_i_n_329, + EMIOSPI0STN => SPI0_MISO_T_n, + EMIOSPI1MI => '0', + EMIOSPI1MO => PS7_i_n_71, + EMIOSPI1MOTN => SPI1_MOSI_T_n, + EMIOSPI1SCLKI => '0', + EMIOSPI1SCLKO => PS7_i_n_73, + EMIOSPI1SCLKTN => SPI1_SCLK_T_n, + EMIOSPI1SI => '0', + EMIOSPI1SO => PS7_i_n_75, + EMIOSPI1SSIN => '0', + EMIOSPI1SSNTN => SPI1_SS_T_n, + EMIOSPI1SSON(2) => PS7_i_n_330, + EMIOSPI1SSON(1) => PS7_i_n_331, + EMIOSPI1SSON(0) => PS7_i_n_332, + EMIOSPI1STN => SPI1_MISO_T_n, + EMIOSRAMINTIN => '0', + EMIOTRACECLK => '0', + EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED, + EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0), + EMIOTTC0CLKI(2 downto 0) => B"000", + EMIOTTC0WAVEO(2) => PS7_i_n_333, + EMIOTTC0WAVEO(1) => PS7_i_n_334, + EMIOTTC0WAVEO(0) => PS7_i_n_335, + EMIOTTC1CLKI(2 downto 0) => B"000", + EMIOTTC1WAVEO(2) => PS7_i_n_336, + EMIOTTC1WAVEO(1) => PS7_i_n_337, + EMIOTTC1WAVEO(0) => PS7_i_n_338, + EMIOUART0CTSN => '0', + EMIOUART0DCDN => '0', + EMIOUART0DSRN => '0', + EMIOUART0DTRN => PS7_i_n_79, + EMIOUART0RIN => '0', + EMIOUART0RTSN => PS7_i_n_80, + EMIOUART0RX => '1', + EMIOUART0TX => PS7_i_n_81, + EMIOUART1CTSN => '0', + EMIOUART1DCDN => '0', + EMIOUART1DSRN => '0', + EMIOUART1DTRN => PS7_i_n_82, + EMIOUART1RIN => '0', + EMIOUART1RTSN => PS7_i_n_83, + EMIOUART1RX => '1', + EMIOUART1TX => PS7_i_n_84, + EMIOUSB0PORTINDCTL(1) => PS7_i_n_232, + EMIOUSB0PORTINDCTL(0) => PS7_i_n_233, + EMIOUSB0VBUSPWRFAULT => '0', + EMIOUSB0VBUSPWRSELECT => PS7_i_n_85, + EMIOUSB1PORTINDCTL(1) => PS7_i_n_234, + EMIOUSB1PORTINDCTL(0) => PS7_i_n_235, + EMIOUSB1VBUSPWRFAULT => '0', + EMIOUSB1VBUSPWRSELECT => PS7_i_n_86, + EMIOWDTCLKI => '0', + EMIOWDTRSTO => PS7_i_n_87, + EVENTEVENTI => '0', + EVENTEVENTO => PS7_i_n_88, + EVENTSTANDBYWFE(1) => PS7_i_n_236, + EVENTSTANDBYWFE(0) => PS7_i_n_237, + EVENTSTANDBYWFI(1) => PS7_i_n_238, + EVENTSTANDBYWFI(0) => PS7_i_n_239, + FCLKCLK(3 downto 0) => FCLK_CLK_unbuffered(3 downto 0), + FCLKCLKTRIGN(3 downto 0) => B"0000", + FCLKRESETN(3) => PS7_i_n_709, + FCLKRESETN(2) => PS7_i_n_710, + FCLKRESETN(1) => PS7_i_n_711, + FCLKRESETN(0) => FCLK_RESET0_N, + FPGAIDLEN => '0', + FTMDTRACEINATID(3 downto 0) => B"0000", + FTMDTRACEINCLOCK => '0', + FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000", + FTMDTRACEINVALID => '0', + FTMTF2PDEBUG(31 downto 0) => B"00000000000000000000000000000000", + FTMTF2PTRIG(3 downto 0) => B"0000", + FTMTF2PTRIGACK(3) => PS7_i_n_713, + FTMTF2PTRIGACK(2) => PS7_i_n_714, + FTMTF2PTRIGACK(1) => PS7_i_n_715, + FTMTF2PTRIGACK(0) => PS7_i_n_716, + FTMTP2FDEBUG(31) => PS7_i_n_401, + FTMTP2FDEBUG(30) => PS7_i_n_402, + FTMTP2FDEBUG(29) => PS7_i_n_403, + FTMTP2FDEBUG(28) => PS7_i_n_404, + FTMTP2FDEBUG(27) => PS7_i_n_405, + FTMTP2FDEBUG(26) => PS7_i_n_406, + FTMTP2FDEBUG(25) => PS7_i_n_407, + FTMTP2FDEBUG(24) => PS7_i_n_408, + FTMTP2FDEBUG(23) => PS7_i_n_409, + FTMTP2FDEBUG(22) => PS7_i_n_410, + FTMTP2FDEBUG(21) => PS7_i_n_411, + FTMTP2FDEBUG(20) => PS7_i_n_412, + FTMTP2FDEBUG(19) => PS7_i_n_413, + FTMTP2FDEBUG(18) => PS7_i_n_414, + FTMTP2FDEBUG(17) => PS7_i_n_415, + FTMTP2FDEBUG(16) => PS7_i_n_416, + FTMTP2FDEBUG(15) => PS7_i_n_417, + FTMTP2FDEBUG(14) => PS7_i_n_418, + FTMTP2FDEBUG(13) => PS7_i_n_419, + FTMTP2FDEBUG(12) => PS7_i_n_420, + FTMTP2FDEBUG(11) => PS7_i_n_421, + FTMTP2FDEBUG(10) => PS7_i_n_422, + FTMTP2FDEBUG(9) => PS7_i_n_423, + FTMTP2FDEBUG(8) => PS7_i_n_424, + FTMTP2FDEBUG(7) => PS7_i_n_425, + FTMTP2FDEBUG(6) => PS7_i_n_426, + FTMTP2FDEBUG(5) => PS7_i_n_427, + FTMTP2FDEBUG(4) => PS7_i_n_428, + FTMTP2FDEBUG(3) => PS7_i_n_429, + FTMTP2FDEBUG(2) => PS7_i_n_430, + FTMTP2FDEBUG(1) => PS7_i_n_431, + FTMTP2FDEBUG(0) => PS7_i_n_432, + FTMTP2FTRIG(3) => PS7_i_n_717, + FTMTP2FTRIG(2) => PS7_i_n_718, + FTMTP2FTRIG(1) => PS7_i_n_719, + FTMTP2FTRIG(0) => PS7_i_n_720, + FTMTP2FTRIGACK(3 downto 0) => B"0000", + IRQF2P(19 downto 0) => B"00000000000000000000", + IRQP2F(28) => PS7_i_n_292, + IRQP2F(27) => PS7_i_n_293, + IRQP2F(26) => PS7_i_n_294, + IRQP2F(25) => PS7_i_n_295, + IRQP2F(24) => PS7_i_n_296, + IRQP2F(23) => PS7_i_n_297, + IRQP2F(22) => PS7_i_n_298, + IRQP2F(21) => PS7_i_n_299, + IRQP2F(20) => PS7_i_n_300, + IRQP2F(19) => PS7_i_n_301, + IRQP2F(18) => PS7_i_n_302, + IRQP2F(17) => PS7_i_n_303, + IRQP2F(16) => PS7_i_n_304, + IRQP2F(15) => PS7_i_n_305, + IRQP2F(14) => PS7_i_n_306, + IRQP2F(13) => PS7_i_n_307, + IRQP2F(12) => PS7_i_n_308, + IRQP2F(11) => PS7_i_n_309, + IRQP2F(10) => PS7_i_n_310, + IRQP2F(9) => PS7_i_n_311, + IRQP2F(8) => PS7_i_n_312, + IRQP2F(7) => PS7_i_n_313, + IRQP2F(6) => PS7_i_n_314, + IRQP2F(5) => PS7_i_n_315, + IRQP2F(4) => PS7_i_n_316, + IRQP2F(3) => PS7_i_n_317, + IRQP2F(2) => PS7_i_n_318, + IRQP2F(1) => PS7_i_n_319, + IRQP2F(0) => PS7_i_n_320, + MAXIGP0ACLK => M_AXI_GP0_ACLK, + MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0), + MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0), + MAXIGP0ARCACHE(3 downto 2) => \^m_axi_gp0_arcache\(3 downto 2), + MAXIGP0ARCACHE(1) => NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED(1), + MAXIGP0ARCACHE(0) => \^m_axi_gp0_arcache\(0), + MAXIGP0ARESETN => PS7_i_n_89, + MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0), + MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0), + MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0), + MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0), + MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0), + MAXIGP0ARREADY => M_AXI_GP0_ARREADY, + MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0), + MAXIGP0ARVALID => M_AXI_GP0_ARVALID, + MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0), + MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0), + MAXIGP0AWCACHE(3 downto 2) => \^m_axi_gp0_awcache\(3 downto 2), + MAXIGP0AWCACHE(1) => NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED(1), + MAXIGP0AWCACHE(0) => \^m_axi_gp0_awcache\(0), + MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0), + MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0), + MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0), + MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0), + MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0), + MAXIGP0AWREADY => M_AXI_GP0_AWREADY, + MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0), + MAXIGP0AWVALID => M_AXI_GP0_AWVALID, + MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0), + MAXIGP0BREADY => M_AXI_GP0_BREADY, + MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0), + MAXIGP0BVALID => M_AXI_GP0_BVALID, + MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0), + MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0), + MAXIGP0RLAST => M_AXI_GP0_RLAST, + MAXIGP0RREADY => M_AXI_GP0_RREADY, + MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0), + MAXIGP0RVALID => M_AXI_GP0_RVALID, + MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0), + MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0), + MAXIGP0WLAST => M_AXI_GP0_WLAST, + MAXIGP0WREADY => M_AXI_GP0_WREADY, + MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0), + MAXIGP0WVALID => M_AXI_GP0_WVALID, + MAXIGP1ACLK => '0', + MAXIGP1ARADDR(31) => PS7_i_n_529, + MAXIGP1ARADDR(30) => PS7_i_n_530, + MAXIGP1ARADDR(29) => PS7_i_n_531, + MAXIGP1ARADDR(28) => PS7_i_n_532, + MAXIGP1ARADDR(27) => PS7_i_n_533, + MAXIGP1ARADDR(26) => PS7_i_n_534, + MAXIGP1ARADDR(25) => PS7_i_n_535, + MAXIGP1ARADDR(24) => PS7_i_n_536, + MAXIGP1ARADDR(23) => PS7_i_n_537, + MAXIGP1ARADDR(22) => PS7_i_n_538, + MAXIGP1ARADDR(21) => PS7_i_n_539, + MAXIGP1ARADDR(20) => PS7_i_n_540, + MAXIGP1ARADDR(19) => PS7_i_n_541, + MAXIGP1ARADDR(18) => PS7_i_n_542, + MAXIGP1ARADDR(17) => PS7_i_n_543, + MAXIGP1ARADDR(16) => PS7_i_n_544, + MAXIGP1ARADDR(15) => PS7_i_n_545, + MAXIGP1ARADDR(14) => PS7_i_n_546, + MAXIGP1ARADDR(13) => PS7_i_n_547, + MAXIGP1ARADDR(12) => PS7_i_n_548, + MAXIGP1ARADDR(11) => PS7_i_n_549, + MAXIGP1ARADDR(10) => PS7_i_n_550, + MAXIGP1ARADDR(9) => PS7_i_n_551, + MAXIGP1ARADDR(8) => PS7_i_n_552, + MAXIGP1ARADDR(7) => PS7_i_n_553, + MAXIGP1ARADDR(6) => PS7_i_n_554, + MAXIGP1ARADDR(5) => PS7_i_n_555, + MAXIGP1ARADDR(4) => PS7_i_n_556, + MAXIGP1ARADDR(3) => PS7_i_n_557, + MAXIGP1ARADDR(2) => PS7_i_n_558, + MAXIGP1ARADDR(1) => PS7_i_n_559, + MAXIGP1ARADDR(0) => PS7_i_n_560, + MAXIGP1ARBURST(1) => PS7_i_n_252, + MAXIGP1ARBURST(0) => PS7_i_n_253, + MAXIGP1ARCACHE(3) => PS7_i_n_749, + MAXIGP1ARCACHE(2) => PS7_i_n_750, + MAXIGP1ARCACHE(1) => NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED(1), + MAXIGP1ARCACHE(0) => PS7_i_n_752, + MAXIGP1ARESETN => PS7_i_n_96, + MAXIGP1ARID(11) => PS7_i_n_188, + MAXIGP1ARID(10) => PS7_i_n_189, + MAXIGP1ARID(9) => PS7_i_n_190, + MAXIGP1ARID(8) => PS7_i_n_191, + MAXIGP1ARID(7) => PS7_i_n_192, + MAXIGP1ARID(6) => PS7_i_n_193, + MAXIGP1ARID(5) => PS7_i_n_194, + MAXIGP1ARID(4) => PS7_i_n_195, + MAXIGP1ARID(3) => PS7_i_n_196, + MAXIGP1ARID(2) => PS7_i_n_197, + MAXIGP1ARID(1) => PS7_i_n_198, + MAXIGP1ARID(0) => PS7_i_n_199, + MAXIGP1ARLEN(3) => PS7_i_n_753, + MAXIGP1ARLEN(2) => PS7_i_n_754, + MAXIGP1ARLEN(1) => PS7_i_n_755, + MAXIGP1ARLEN(0) => PS7_i_n_756, + MAXIGP1ARLOCK(1) => PS7_i_n_254, + MAXIGP1ARLOCK(0) => PS7_i_n_255, + MAXIGP1ARPROT(2) => PS7_i_n_345, + MAXIGP1ARPROT(1) => PS7_i_n_346, + MAXIGP1ARPROT(0) => PS7_i_n_347, + MAXIGP1ARQOS(3) => PS7_i_n_757, + MAXIGP1ARQOS(2) => PS7_i_n_758, + MAXIGP1ARQOS(1) => PS7_i_n_759, + MAXIGP1ARQOS(0) => PS7_i_n_760, + MAXIGP1ARREADY => '0', + MAXIGP1ARSIZE(1) => PS7_i_n_256, + MAXIGP1ARSIZE(0) => PS7_i_n_257, + MAXIGP1ARVALID => PS7_i_n_97, + MAXIGP1AWADDR(31) => PS7_i_n_561, + MAXIGP1AWADDR(30) => PS7_i_n_562, + MAXIGP1AWADDR(29) => PS7_i_n_563, + MAXIGP1AWADDR(28) => PS7_i_n_564, + MAXIGP1AWADDR(27) => PS7_i_n_565, + MAXIGP1AWADDR(26) => PS7_i_n_566, + MAXIGP1AWADDR(25) => PS7_i_n_567, + MAXIGP1AWADDR(24) => PS7_i_n_568, + MAXIGP1AWADDR(23) => PS7_i_n_569, + MAXIGP1AWADDR(22) => PS7_i_n_570, + MAXIGP1AWADDR(21) => PS7_i_n_571, + MAXIGP1AWADDR(20) => PS7_i_n_572, + MAXIGP1AWADDR(19) => PS7_i_n_573, + MAXIGP1AWADDR(18) => PS7_i_n_574, + MAXIGP1AWADDR(17) => PS7_i_n_575, + MAXIGP1AWADDR(16) => PS7_i_n_576, + MAXIGP1AWADDR(15) => PS7_i_n_577, + MAXIGP1AWADDR(14) => PS7_i_n_578, + MAXIGP1AWADDR(13) => PS7_i_n_579, + MAXIGP1AWADDR(12) => PS7_i_n_580, + MAXIGP1AWADDR(11) => PS7_i_n_581, + MAXIGP1AWADDR(10) => PS7_i_n_582, + MAXIGP1AWADDR(9) => PS7_i_n_583, + MAXIGP1AWADDR(8) => PS7_i_n_584, + MAXIGP1AWADDR(7) => PS7_i_n_585, + MAXIGP1AWADDR(6) => PS7_i_n_586, + MAXIGP1AWADDR(5) => PS7_i_n_587, + MAXIGP1AWADDR(4) => PS7_i_n_588, + MAXIGP1AWADDR(3) => PS7_i_n_589, + MAXIGP1AWADDR(2) => PS7_i_n_590, + MAXIGP1AWADDR(1) => PS7_i_n_591, + MAXIGP1AWADDR(0) => PS7_i_n_592, + MAXIGP1AWBURST(1) => PS7_i_n_258, + MAXIGP1AWBURST(0) => PS7_i_n_259, + MAXIGP1AWCACHE(3) => PS7_i_n_761, + MAXIGP1AWCACHE(2) => PS7_i_n_762, + MAXIGP1AWCACHE(1) => NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED(1), + MAXIGP1AWCACHE(0) => PS7_i_n_764, + MAXIGP1AWID(11) => PS7_i_n_200, + MAXIGP1AWID(10) => PS7_i_n_201, + MAXIGP1AWID(9) => PS7_i_n_202, + MAXIGP1AWID(8) => PS7_i_n_203, + MAXIGP1AWID(7) => PS7_i_n_204, + MAXIGP1AWID(6) => PS7_i_n_205, + MAXIGP1AWID(5) => PS7_i_n_206, + MAXIGP1AWID(4) => PS7_i_n_207, + MAXIGP1AWID(3) => PS7_i_n_208, + MAXIGP1AWID(2) => PS7_i_n_209, + MAXIGP1AWID(1) => PS7_i_n_210, + MAXIGP1AWID(0) => PS7_i_n_211, + MAXIGP1AWLEN(3) => PS7_i_n_765, + MAXIGP1AWLEN(2) => PS7_i_n_766, + MAXIGP1AWLEN(1) => PS7_i_n_767, + MAXIGP1AWLEN(0) => PS7_i_n_768, + MAXIGP1AWLOCK(1) => PS7_i_n_260, + MAXIGP1AWLOCK(0) => PS7_i_n_261, + MAXIGP1AWPROT(2) => PS7_i_n_348, + MAXIGP1AWPROT(1) => PS7_i_n_349, + MAXIGP1AWPROT(0) => PS7_i_n_350, + MAXIGP1AWQOS(3) => PS7_i_n_769, + MAXIGP1AWQOS(2) => PS7_i_n_770, + MAXIGP1AWQOS(1) => PS7_i_n_771, + MAXIGP1AWQOS(0) => PS7_i_n_772, + MAXIGP1AWREADY => '0', + MAXIGP1AWSIZE(1) => PS7_i_n_262, + MAXIGP1AWSIZE(0) => PS7_i_n_263, + MAXIGP1AWVALID => PS7_i_n_98, + MAXIGP1BID(11 downto 0) => B"000000000000", + MAXIGP1BREADY => PS7_i_n_99, + MAXIGP1BRESP(1 downto 0) => B"00", + MAXIGP1BVALID => '0', + MAXIGP1RDATA(31 downto 0) => B"00000000000000000000000000000000", + MAXIGP1RID(11 downto 0) => B"000000000000", + MAXIGP1RLAST => '0', + MAXIGP1RREADY => PS7_i_n_100, + MAXIGP1RRESP(1 downto 0) => B"00", + MAXIGP1RVALID => '0', + MAXIGP1WDATA(31) => PS7_i_n_593, + MAXIGP1WDATA(30) => PS7_i_n_594, + MAXIGP1WDATA(29) => PS7_i_n_595, + MAXIGP1WDATA(28) => PS7_i_n_596, + MAXIGP1WDATA(27) => PS7_i_n_597, + MAXIGP1WDATA(26) => PS7_i_n_598, + MAXIGP1WDATA(25) => PS7_i_n_599, + MAXIGP1WDATA(24) => PS7_i_n_600, + MAXIGP1WDATA(23) => PS7_i_n_601, + MAXIGP1WDATA(22) => PS7_i_n_602, + MAXIGP1WDATA(21) => PS7_i_n_603, + MAXIGP1WDATA(20) => PS7_i_n_604, + MAXIGP1WDATA(19) => PS7_i_n_605, + MAXIGP1WDATA(18) => PS7_i_n_606, + MAXIGP1WDATA(17) => PS7_i_n_607, + MAXIGP1WDATA(16) => PS7_i_n_608, + MAXIGP1WDATA(15) => PS7_i_n_609, + MAXIGP1WDATA(14) => PS7_i_n_610, + MAXIGP1WDATA(13) => PS7_i_n_611, + MAXIGP1WDATA(12) => PS7_i_n_612, + MAXIGP1WDATA(11) => PS7_i_n_613, + MAXIGP1WDATA(10) => PS7_i_n_614, + MAXIGP1WDATA(9) => PS7_i_n_615, + MAXIGP1WDATA(8) => PS7_i_n_616, + MAXIGP1WDATA(7) => PS7_i_n_617, + MAXIGP1WDATA(6) => PS7_i_n_618, + MAXIGP1WDATA(5) => PS7_i_n_619, + MAXIGP1WDATA(4) => PS7_i_n_620, + MAXIGP1WDATA(3) => PS7_i_n_621, + MAXIGP1WDATA(2) => PS7_i_n_622, + MAXIGP1WDATA(1) => PS7_i_n_623, + MAXIGP1WDATA(0) => PS7_i_n_624, + MAXIGP1WID(11) => PS7_i_n_212, + MAXIGP1WID(10) => PS7_i_n_213, + MAXIGP1WID(9) => PS7_i_n_214, + MAXIGP1WID(8) => PS7_i_n_215, + MAXIGP1WID(7) => PS7_i_n_216, + MAXIGP1WID(6) => PS7_i_n_217, + MAXIGP1WID(5) => PS7_i_n_218, + MAXIGP1WID(4) => PS7_i_n_219, + MAXIGP1WID(3) => PS7_i_n_220, + MAXIGP1WID(2) => PS7_i_n_221, + MAXIGP1WID(1) => PS7_i_n_222, + MAXIGP1WID(0) => PS7_i_n_223, + MAXIGP1WLAST => PS7_i_n_101, + MAXIGP1WREADY => '0', + MAXIGP1WSTRB(3) => PS7_i_n_773, + MAXIGP1WSTRB(2) => PS7_i_n_774, + MAXIGP1WSTRB(1) => PS7_i_n_775, + MAXIGP1WSTRB(0) => PS7_i_n_776, + MAXIGP1WVALID => PS7_i_n_102, + MIO(53 downto 0) => buffered_MIO(53 downto 0), + PSCLK => buffered_PS_CLK, + PSPORB => buffered_PS_PORB, + PSSRSTB => buffered_PS_SRSTB, + SAXIACPACLK => '0', + SAXIACPARADDR(31 downto 0) => B"00000000000000000000000000000000", + SAXIACPARBURST(1 downto 0) => B"00", + SAXIACPARCACHE(3 downto 0) => B"0000", + SAXIACPARESETN => PS7_i_n_103, + SAXIACPARID(2 downto 0) => B"000", + SAXIACPARLEN(3 downto 0) => B"0000", + SAXIACPARLOCK(1 downto 0) => B"00", + SAXIACPARPROT(2 downto 0) => B"000", + SAXIACPARQOS(3 downto 0) => B"0000", + SAXIACPARREADY => PS7_i_n_104, + SAXIACPARSIZE(1 downto 0) => B"00", + SAXIACPARUSER(4 downto 0) => B"00000", + SAXIACPARVALID => '0', + SAXIACPAWADDR(31 downto 0) => B"00000000000000000000000000000000", + SAXIACPAWBURST(1 downto 0) => B"00", + SAXIACPAWCACHE(3 downto 0) => B"0000", + SAXIACPAWID(2 downto 0) => B"000", + SAXIACPAWLEN(3 downto 0) => B"0000", + SAXIACPAWLOCK(1 downto 0) => B"00", + SAXIACPAWPROT(2 downto 0) => B"000", + SAXIACPAWQOS(3 downto 0) => B"0000", + SAXIACPAWREADY => PS7_i_n_105, + SAXIACPAWSIZE(1 downto 0) => B"00", + SAXIACPAWUSER(4 downto 0) => B"00000", + SAXIACPAWVALID => '0', + SAXIACPBID(2) => PS7_i_n_351, + SAXIACPBID(1) => PS7_i_n_352, + SAXIACPBID(0) => PS7_i_n_353, + SAXIACPBREADY => '0', + SAXIACPBRESP(1) => PS7_i_n_264, + SAXIACPBRESP(0) => PS7_i_n_265, + SAXIACPBVALID => PS7_i_n_106, + SAXIACPRDATA(63) => PS7_i_n_1001, + SAXIACPRDATA(62) => PS7_i_n_1002, + SAXIACPRDATA(61) => PS7_i_n_1003, + SAXIACPRDATA(60) => PS7_i_n_1004, + SAXIACPRDATA(59) => PS7_i_n_1005, + SAXIACPRDATA(58) => PS7_i_n_1006, + SAXIACPRDATA(57) => PS7_i_n_1007, + SAXIACPRDATA(56) => PS7_i_n_1008, + SAXIACPRDATA(55) => PS7_i_n_1009, + SAXIACPRDATA(54) => PS7_i_n_1010, + SAXIACPRDATA(53) => PS7_i_n_1011, + SAXIACPRDATA(52) => PS7_i_n_1012, + SAXIACPRDATA(51) => PS7_i_n_1013, + SAXIACPRDATA(50) => PS7_i_n_1014, + SAXIACPRDATA(49) => PS7_i_n_1015, + SAXIACPRDATA(48) => PS7_i_n_1016, + SAXIACPRDATA(47) => PS7_i_n_1017, + SAXIACPRDATA(46) => PS7_i_n_1018, + SAXIACPRDATA(45) => PS7_i_n_1019, + SAXIACPRDATA(44) => PS7_i_n_1020, + SAXIACPRDATA(43) => PS7_i_n_1021, + SAXIACPRDATA(42) => PS7_i_n_1022, + SAXIACPRDATA(41) => PS7_i_n_1023, + SAXIACPRDATA(40) => PS7_i_n_1024, + SAXIACPRDATA(39) => PS7_i_n_1025, + SAXIACPRDATA(38) => PS7_i_n_1026, + SAXIACPRDATA(37) => PS7_i_n_1027, + SAXIACPRDATA(36) => PS7_i_n_1028, + SAXIACPRDATA(35) => PS7_i_n_1029, + SAXIACPRDATA(34) => PS7_i_n_1030, + SAXIACPRDATA(33) => PS7_i_n_1031, + SAXIACPRDATA(32) => PS7_i_n_1032, + SAXIACPRDATA(31) => PS7_i_n_1033, + SAXIACPRDATA(30) => PS7_i_n_1034, + SAXIACPRDATA(29) => PS7_i_n_1035, + SAXIACPRDATA(28) => PS7_i_n_1036, + SAXIACPRDATA(27) => PS7_i_n_1037, + SAXIACPRDATA(26) => PS7_i_n_1038, + SAXIACPRDATA(25) => PS7_i_n_1039, + SAXIACPRDATA(24) => PS7_i_n_1040, + SAXIACPRDATA(23) => PS7_i_n_1041, + SAXIACPRDATA(22) => PS7_i_n_1042, + SAXIACPRDATA(21) => PS7_i_n_1043, + SAXIACPRDATA(20) => PS7_i_n_1044, + SAXIACPRDATA(19) => PS7_i_n_1045, + SAXIACPRDATA(18) => PS7_i_n_1046, + SAXIACPRDATA(17) => PS7_i_n_1047, + SAXIACPRDATA(16) => PS7_i_n_1048, + SAXIACPRDATA(15) => PS7_i_n_1049, + SAXIACPRDATA(14) => PS7_i_n_1050, + SAXIACPRDATA(13) => PS7_i_n_1051, + SAXIACPRDATA(12) => PS7_i_n_1052, + SAXIACPRDATA(11) => PS7_i_n_1053, + SAXIACPRDATA(10) => PS7_i_n_1054, + SAXIACPRDATA(9) => PS7_i_n_1055, + SAXIACPRDATA(8) => PS7_i_n_1056, + SAXIACPRDATA(7) => PS7_i_n_1057, + SAXIACPRDATA(6) => PS7_i_n_1058, + SAXIACPRDATA(5) => PS7_i_n_1059, + SAXIACPRDATA(4) => PS7_i_n_1060, + SAXIACPRDATA(3) => PS7_i_n_1061, + SAXIACPRDATA(2) => PS7_i_n_1062, + SAXIACPRDATA(1) => PS7_i_n_1063, + SAXIACPRDATA(0) => PS7_i_n_1064, + SAXIACPRID(2) => PS7_i_n_354, + SAXIACPRID(1) => PS7_i_n_355, + SAXIACPRID(0) => PS7_i_n_356, + SAXIACPRLAST => PS7_i_n_107, + SAXIACPRREADY => '0', + SAXIACPRRESP(1) => PS7_i_n_266, + SAXIACPRRESP(0) => PS7_i_n_267, + SAXIACPRVALID => PS7_i_n_108, + SAXIACPWDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + SAXIACPWID(2 downto 0) => B"000", + SAXIACPWLAST => '0', + SAXIACPWREADY => PS7_i_n_109, + SAXIACPWSTRB(7 downto 0) => B"00000000", + SAXIACPWVALID => '0', + SAXIGP0ACLK => '0', + SAXIGP0ARADDR(31 downto 0) => B"00000000000000000000000000000000", + SAXIGP0ARBURST(1 downto 0) => B"00", + SAXIGP0ARCACHE(3 downto 0) => B"0000", + SAXIGP0ARESETN => PS7_i_n_110, + SAXIGP0ARID(5 downto 0) => B"000000", + SAXIGP0ARLEN(3 downto 0) => B"0000", + SAXIGP0ARLOCK(1 downto 0) => B"00", + SAXIGP0ARPROT(2 downto 0) => B"000", + SAXIGP0ARQOS(3 downto 0) => B"0000", + SAXIGP0ARREADY => PS7_i_n_111, + SAXIGP0ARSIZE(1 downto 0) => B"00", + SAXIGP0ARVALID => '0', + SAXIGP0AWADDR(31 downto 0) => B"00000000000000000000000000000000", + SAXIGP0AWBURST(1 downto 0) => B"00", + SAXIGP0AWCACHE(3 downto 0) => B"0000", + SAXIGP0AWID(5 downto 0) => B"000000", + SAXIGP0AWLEN(3 downto 0) => B"0000", + SAXIGP0AWLOCK(1 downto 0) => B"00", + SAXIGP0AWPROT(2 downto 0) => B"000", + SAXIGP0AWQOS(3 downto 0) => B"0000", + SAXIGP0AWREADY => PS7_i_n_112, + SAXIGP0AWSIZE(1 downto 0) => B"00", + SAXIGP0AWVALID => '0', + SAXIGP0BID(5) => PS7_i_n_777, + SAXIGP0BID(4) => PS7_i_n_778, + SAXIGP0BID(3) => PS7_i_n_779, + SAXIGP0BID(2) => PS7_i_n_780, + SAXIGP0BID(1) => PS7_i_n_781, + SAXIGP0BID(0) => PS7_i_n_782, + SAXIGP0BREADY => '0', + SAXIGP0BRESP(1) => PS7_i_n_268, + SAXIGP0BRESP(0) => PS7_i_n_269, + SAXIGP0BVALID => PS7_i_n_113, + SAXIGP0RDATA(31) => PS7_i_n_625, + SAXIGP0RDATA(30) => PS7_i_n_626, + SAXIGP0RDATA(29) => PS7_i_n_627, + SAXIGP0RDATA(28) => PS7_i_n_628, + SAXIGP0RDATA(27) => PS7_i_n_629, + SAXIGP0RDATA(26) => PS7_i_n_630, + SAXIGP0RDATA(25) => PS7_i_n_631, + SAXIGP0RDATA(24) => PS7_i_n_632, + SAXIGP0RDATA(23) => PS7_i_n_633, + SAXIGP0RDATA(22) => PS7_i_n_634, + SAXIGP0RDATA(21) => PS7_i_n_635, + SAXIGP0RDATA(20) => PS7_i_n_636, + SAXIGP0RDATA(19) => PS7_i_n_637, + SAXIGP0RDATA(18) => PS7_i_n_638, + SAXIGP0RDATA(17) => PS7_i_n_639, + SAXIGP0RDATA(16) => PS7_i_n_640, + SAXIGP0RDATA(15) => PS7_i_n_641, + SAXIGP0RDATA(14) => PS7_i_n_642, + SAXIGP0RDATA(13) => PS7_i_n_643, + SAXIGP0RDATA(12) => PS7_i_n_644, + SAXIGP0RDATA(11) => PS7_i_n_645, + SAXIGP0RDATA(10) => PS7_i_n_646, + SAXIGP0RDATA(9) => PS7_i_n_647, + SAXIGP0RDATA(8) => PS7_i_n_648, + SAXIGP0RDATA(7) => PS7_i_n_649, + SAXIGP0RDATA(6) => PS7_i_n_650, + SAXIGP0RDATA(5) => PS7_i_n_651, + SAXIGP0RDATA(4) => PS7_i_n_652, + SAXIGP0RDATA(3) => PS7_i_n_653, + SAXIGP0RDATA(2) => PS7_i_n_654, + SAXIGP0RDATA(1) => PS7_i_n_655, + SAXIGP0RDATA(0) => PS7_i_n_656, + SAXIGP0RID(5) => PS7_i_n_783, + SAXIGP0RID(4) => PS7_i_n_784, + SAXIGP0RID(3) => PS7_i_n_785, + SAXIGP0RID(2) => PS7_i_n_786, + SAXIGP0RID(1) => PS7_i_n_787, + SAXIGP0RID(0) => PS7_i_n_788, + SAXIGP0RLAST => PS7_i_n_114, + SAXIGP0RREADY => '0', + SAXIGP0RRESP(1) => PS7_i_n_270, + SAXIGP0RRESP(0) => PS7_i_n_271, + SAXIGP0RVALID => PS7_i_n_115, + SAXIGP0WDATA(31 downto 0) => B"00000000000000000000000000000000", + SAXIGP0WID(5 downto 0) => B"000000", + SAXIGP0WLAST => '0', + SAXIGP0WREADY => PS7_i_n_116, + SAXIGP0WSTRB(3 downto 0) => B"0000", + SAXIGP0WVALID => '0', + SAXIGP1ACLK => '0', + SAXIGP1ARADDR(31 downto 0) => B"00000000000000000000000000000000", + SAXIGP1ARBURST(1 downto 0) => B"00", + SAXIGP1ARCACHE(3 downto 0) => B"0000", + SAXIGP1ARESETN => PS7_i_n_117, + SAXIGP1ARID(5 downto 0) => B"000000", + SAXIGP1ARLEN(3 downto 0) => B"0000", + SAXIGP1ARLOCK(1 downto 0) => B"00", + SAXIGP1ARPROT(2 downto 0) => B"000", + SAXIGP1ARQOS(3 downto 0) => B"0000", + SAXIGP1ARREADY => PS7_i_n_118, + SAXIGP1ARSIZE(1 downto 0) => B"00", + SAXIGP1ARVALID => '0', + SAXIGP1AWADDR(31 downto 0) => B"00000000000000000000000000000000", + SAXIGP1AWBURST(1 downto 0) => B"00", + SAXIGP1AWCACHE(3 downto 0) => B"0000", + SAXIGP1AWID(5 downto 0) => B"000000", + SAXIGP1AWLEN(3 downto 0) => B"0000", + SAXIGP1AWLOCK(1 downto 0) => B"00", + SAXIGP1AWPROT(2 downto 0) => B"000", + SAXIGP1AWQOS(3 downto 0) => B"0000", + SAXIGP1AWREADY => PS7_i_n_119, + SAXIGP1AWSIZE(1 downto 0) => B"00", + SAXIGP1AWVALID => '0', + SAXIGP1BID(5) => PS7_i_n_789, + SAXIGP1BID(4) => PS7_i_n_790, + SAXIGP1BID(3) => PS7_i_n_791, + SAXIGP1BID(2) => PS7_i_n_792, + SAXIGP1BID(1) => PS7_i_n_793, + SAXIGP1BID(0) => PS7_i_n_794, + SAXIGP1BREADY => '0', + SAXIGP1BRESP(1) => PS7_i_n_272, + SAXIGP1BRESP(0) => PS7_i_n_273, + SAXIGP1BVALID => PS7_i_n_120, + SAXIGP1RDATA(31) => PS7_i_n_657, + SAXIGP1RDATA(30) => PS7_i_n_658, + SAXIGP1RDATA(29) => PS7_i_n_659, + SAXIGP1RDATA(28) => PS7_i_n_660, + SAXIGP1RDATA(27) => PS7_i_n_661, + SAXIGP1RDATA(26) => PS7_i_n_662, + SAXIGP1RDATA(25) => PS7_i_n_663, + SAXIGP1RDATA(24) => PS7_i_n_664, + SAXIGP1RDATA(23) => PS7_i_n_665, + SAXIGP1RDATA(22) => PS7_i_n_666, + SAXIGP1RDATA(21) => PS7_i_n_667, + SAXIGP1RDATA(20) => PS7_i_n_668, + SAXIGP1RDATA(19) => PS7_i_n_669, + SAXIGP1RDATA(18) => PS7_i_n_670, + SAXIGP1RDATA(17) => PS7_i_n_671, + SAXIGP1RDATA(16) => PS7_i_n_672, + SAXIGP1RDATA(15) => PS7_i_n_673, + SAXIGP1RDATA(14) => PS7_i_n_674, + SAXIGP1RDATA(13) => PS7_i_n_675, + SAXIGP1RDATA(12) => PS7_i_n_676, + SAXIGP1RDATA(11) => PS7_i_n_677, + SAXIGP1RDATA(10) => PS7_i_n_678, + SAXIGP1RDATA(9) => PS7_i_n_679, + SAXIGP1RDATA(8) => PS7_i_n_680, + SAXIGP1RDATA(7) => PS7_i_n_681, + SAXIGP1RDATA(6) => PS7_i_n_682, + SAXIGP1RDATA(5) => PS7_i_n_683, + SAXIGP1RDATA(4) => PS7_i_n_684, + SAXIGP1RDATA(3) => PS7_i_n_685, + SAXIGP1RDATA(2) => PS7_i_n_686, + SAXIGP1RDATA(1) => PS7_i_n_687, + SAXIGP1RDATA(0) => PS7_i_n_688, + SAXIGP1RID(5) => PS7_i_n_795, + SAXIGP1RID(4) => PS7_i_n_796, + SAXIGP1RID(3) => PS7_i_n_797, + SAXIGP1RID(2) => PS7_i_n_798, + SAXIGP1RID(1) => PS7_i_n_799, + SAXIGP1RID(0) => PS7_i_n_800, + SAXIGP1RLAST => PS7_i_n_121, + SAXIGP1RREADY => '0', + SAXIGP1RRESP(1) => PS7_i_n_274, + SAXIGP1RRESP(0) => PS7_i_n_275, + SAXIGP1RVALID => PS7_i_n_122, + SAXIGP1WDATA(31 downto 0) => B"00000000000000000000000000000000", + SAXIGP1WID(5 downto 0) => B"000000", + SAXIGP1WLAST => '0', + SAXIGP1WREADY => PS7_i_n_123, + SAXIGP1WSTRB(3 downto 0) => B"0000", + SAXIGP1WVALID => '0', + SAXIHP0ACLK => '0', + SAXIHP0ARADDR(31 downto 0) => B"00000000000000000000000000000000", + SAXIHP0ARBURST(1 downto 0) => B"00", + SAXIHP0ARCACHE(3 downto 0) => B"0000", + SAXIHP0ARESETN => PS7_i_n_124, + SAXIHP0ARID(5 downto 0) => B"000000", + SAXIHP0ARLEN(3 downto 0) => B"0000", + SAXIHP0ARLOCK(1 downto 0) => B"00", + SAXIHP0ARPROT(2 downto 0) => B"000", + SAXIHP0ARQOS(3 downto 0) => B"0000", + SAXIHP0ARREADY => PS7_i_n_125, + SAXIHP0ARSIZE(1 downto 0) => B"00", + SAXIHP0ARVALID => '0', + SAXIHP0AWADDR(31 downto 0) => B"00000000000000000000000000000000", + SAXIHP0AWBURST(1 downto 0) => B"00", + SAXIHP0AWCACHE(3 downto 0) => B"0000", + SAXIHP0AWID(5 downto 0) => B"000000", + SAXIHP0AWLEN(3 downto 0) => B"0000", + SAXIHP0AWLOCK(1 downto 0) => B"00", + SAXIHP0AWPROT(2 downto 0) => B"000", + SAXIHP0AWQOS(3 downto 0) => B"0000", + SAXIHP0AWREADY => PS7_i_n_126, + SAXIHP0AWSIZE(1 downto 0) => B"00", + SAXIHP0AWVALID => '0', + SAXIHP0BID(5) => PS7_i_n_801, + SAXIHP0BID(4) => PS7_i_n_802, + SAXIHP0BID(3) => PS7_i_n_803, + SAXIHP0BID(2) => PS7_i_n_804, + SAXIHP0BID(1) => PS7_i_n_805, + SAXIHP0BID(0) => PS7_i_n_806, + SAXIHP0BREADY => '0', + SAXIHP0BRESP(1) => PS7_i_n_276, + SAXIHP0BRESP(0) => PS7_i_n_277, + SAXIHP0BVALID => PS7_i_n_127, + SAXIHP0RACOUNT(2) => PS7_i_n_357, + SAXIHP0RACOUNT(1) => PS7_i_n_358, + SAXIHP0RACOUNT(0) => PS7_i_n_359, + SAXIHP0RCOUNT(7) => PS7_i_n_1337, + SAXIHP0RCOUNT(6) => PS7_i_n_1338, + SAXIHP0RCOUNT(5) => PS7_i_n_1339, + SAXIHP0RCOUNT(4) => PS7_i_n_1340, + SAXIHP0RCOUNT(3) => PS7_i_n_1341, + SAXIHP0RCOUNT(2) => PS7_i_n_1342, + SAXIHP0RCOUNT(1) => PS7_i_n_1343, + SAXIHP0RCOUNT(0) => PS7_i_n_1344, + SAXIHP0RDATA(63) => PS7_i_n_1065, + SAXIHP0RDATA(62) => PS7_i_n_1066, + SAXIHP0RDATA(61) => PS7_i_n_1067, + SAXIHP0RDATA(60) => PS7_i_n_1068, + SAXIHP0RDATA(59) => PS7_i_n_1069, + SAXIHP0RDATA(58) => PS7_i_n_1070, + SAXIHP0RDATA(57) => PS7_i_n_1071, + SAXIHP0RDATA(56) => PS7_i_n_1072, + SAXIHP0RDATA(55) => PS7_i_n_1073, + SAXIHP0RDATA(54) => PS7_i_n_1074, + SAXIHP0RDATA(53) => PS7_i_n_1075, + SAXIHP0RDATA(52) => PS7_i_n_1076, + SAXIHP0RDATA(51) => PS7_i_n_1077, + SAXIHP0RDATA(50) => PS7_i_n_1078, + SAXIHP0RDATA(49) => PS7_i_n_1079, + SAXIHP0RDATA(48) => PS7_i_n_1080, + SAXIHP0RDATA(47) => PS7_i_n_1081, + SAXIHP0RDATA(46) => PS7_i_n_1082, + SAXIHP0RDATA(45) => PS7_i_n_1083, + SAXIHP0RDATA(44) => PS7_i_n_1084, + SAXIHP0RDATA(43) => PS7_i_n_1085, + SAXIHP0RDATA(42) => PS7_i_n_1086, + SAXIHP0RDATA(41) => PS7_i_n_1087, + SAXIHP0RDATA(40) => PS7_i_n_1088, + SAXIHP0RDATA(39) => PS7_i_n_1089, + SAXIHP0RDATA(38) => PS7_i_n_1090, + SAXIHP0RDATA(37) => PS7_i_n_1091, + SAXIHP0RDATA(36) => PS7_i_n_1092, + SAXIHP0RDATA(35) => PS7_i_n_1093, + SAXIHP0RDATA(34) => PS7_i_n_1094, + SAXIHP0RDATA(33) => PS7_i_n_1095, + SAXIHP0RDATA(32) => PS7_i_n_1096, + SAXIHP0RDATA(31) => PS7_i_n_1097, + SAXIHP0RDATA(30) => PS7_i_n_1098, + SAXIHP0RDATA(29) => PS7_i_n_1099, + SAXIHP0RDATA(28) => PS7_i_n_1100, + SAXIHP0RDATA(27) => PS7_i_n_1101, + SAXIHP0RDATA(26) => PS7_i_n_1102, + SAXIHP0RDATA(25) => PS7_i_n_1103, + SAXIHP0RDATA(24) => PS7_i_n_1104, + SAXIHP0RDATA(23) => PS7_i_n_1105, + SAXIHP0RDATA(22) => PS7_i_n_1106, + SAXIHP0RDATA(21) => PS7_i_n_1107, + SAXIHP0RDATA(20) => PS7_i_n_1108, + SAXIHP0RDATA(19) => PS7_i_n_1109, + SAXIHP0RDATA(18) => PS7_i_n_1110, + SAXIHP0RDATA(17) => PS7_i_n_1111, + SAXIHP0RDATA(16) => PS7_i_n_1112, + SAXIHP0RDATA(15) => PS7_i_n_1113, + SAXIHP0RDATA(14) => PS7_i_n_1114, + SAXIHP0RDATA(13) => PS7_i_n_1115, + SAXIHP0RDATA(12) => PS7_i_n_1116, + SAXIHP0RDATA(11) => PS7_i_n_1117, + SAXIHP0RDATA(10) => PS7_i_n_1118, + SAXIHP0RDATA(9) => PS7_i_n_1119, + SAXIHP0RDATA(8) => PS7_i_n_1120, + SAXIHP0RDATA(7) => PS7_i_n_1121, + SAXIHP0RDATA(6) => PS7_i_n_1122, + SAXIHP0RDATA(5) => PS7_i_n_1123, + SAXIHP0RDATA(4) => PS7_i_n_1124, + SAXIHP0RDATA(3) => PS7_i_n_1125, + SAXIHP0RDATA(2) => PS7_i_n_1126, + SAXIHP0RDATA(1) => PS7_i_n_1127, + SAXIHP0RDATA(0) => PS7_i_n_1128, + SAXIHP0RDISSUECAP1EN => '0', + SAXIHP0RID(5) => PS7_i_n_807, + SAXIHP0RID(4) => PS7_i_n_808, + SAXIHP0RID(3) => PS7_i_n_809, + SAXIHP0RID(2) => PS7_i_n_810, + SAXIHP0RID(1) => PS7_i_n_811, + SAXIHP0RID(0) => PS7_i_n_812, + SAXIHP0RLAST => PS7_i_n_128, + SAXIHP0RREADY => '0', + SAXIHP0RRESP(1) => PS7_i_n_278, + SAXIHP0RRESP(0) => PS7_i_n_279, + SAXIHP0RVALID => PS7_i_n_129, + SAXIHP0WACOUNT(5) => PS7_i_n_813, + SAXIHP0WACOUNT(4) => PS7_i_n_814, + SAXIHP0WACOUNT(3) => PS7_i_n_815, + SAXIHP0WACOUNT(2) => PS7_i_n_816, + SAXIHP0WACOUNT(1) => PS7_i_n_817, + SAXIHP0WACOUNT(0) => PS7_i_n_818, + SAXIHP0WCOUNT(7) => PS7_i_n_1345, + SAXIHP0WCOUNT(6) => PS7_i_n_1346, + SAXIHP0WCOUNT(5) => PS7_i_n_1347, + SAXIHP0WCOUNT(4) => PS7_i_n_1348, + SAXIHP0WCOUNT(3) => PS7_i_n_1349, + SAXIHP0WCOUNT(2) => PS7_i_n_1350, + SAXIHP0WCOUNT(1) => PS7_i_n_1351, + SAXIHP0WCOUNT(0) => PS7_i_n_1352, + SAXIHP0WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + SAXIHP0WID(5 downto 0) => B"000000", + SAXIHP0WLAST => '0', + SAXIHP0WREADY => PS7_i_n_130, + SAXIHP0WRISSUECAP1EN => '0', + SAXIHP0WSTRB(7 downto 0) => B"00000000", + SAXIHP0WVALID => '0', + SAXIHP1ACLK => '0', + SAXIHP1ARADDR(31 downto 0) => B"00000000000000000000000000000000", + SAXIHP1ARBURST(1 downto 0) => B"00", + SAXIHP1ARCACHE(3 downto 0) => B"0000", + SAXIHP1ARESETN => PS7_i_n_131, + SAXIHP1ARID(5 downto 0) => B"000000", + SAXIHP1ARLEN(3 downto 0) => B"0000", + SAXIHP1ARLOCK(1 downto 0) => B"00", + SAXIHP1ARPROT(2 downto 0) => B"000", + SAXIHP1ARQOS(3 downto 0) => B"0000", + SAXIHP1ARREADY => PS7_i_n_132, + SAXIHP1ARSIZE(1 downto 0) => B"00", + SAXIHP1ARVALID => '0', + SAXIHP1AWADDR(31 downto 0) => B"00000000000000000000000000000000", + SAXIHP1AWBURST(1 downto 0) => B"00", + SAXIHP1AWCACHE(3 downto 0) => B"0000", + SAXIHP1AWID(5 downto 0) => B"000000", + SAXIHP1AWLEN(3 downto 0) => B"0000", + SAXIHP1AWLOCK(1 downto 0) => B"00", + SAXIHP1AWPROT(2 downto 0) => B"000", + SAXIHP1AWQOS(3 downto 0) => B"0000", + SAXIHP1AWREADY => PS7_i_n_133, + SAXIHP1AWSIZE(1 downto 0) => B"00", + SAXIHP1AWVALID => '0', + SAXIHP1BID(5) => PS7_i_n_819, + SAXIHP1BID(4) => PS7_i_n_820, + SAXIHP1BID(3) => PS7_i_n_821, + SAXIHP1BID(2) => PS7_i_n_822, + SAXIHP1BID(1) => PS7_i_n_823, + SAXIHP1BID(0) => PS7_i_n_824, + SAXIHP1BREADY => '0', + SAXIHP1BRESP(1) => PS7_i_n_280, + SAXIHP1BRESP(0) => PS7_i_n_281, + SAXIHP1BVALID => PS7_i_n_134, + SAXIHP1RACOUNT(2) => PS7_i_n_360, + SAXIHP1RACOUNT(1) => PS7_i_n_361, + SAXIHP1RACOUNT(0) => PS7_i_n_362, + SAXIHP1RCOUNT(7) => PS7_i_n_1353, + SAXIHP1RCOUNT(6) => PS7_i_n_1354, + SAXIHP1RCOUNT(5) => PS7_i_n_1355, + SAXIHP1RCOUNT(4) => PS7_i_n_1356, + SAXIHP1RCOUNT(3) => PS7_i_n_1357, + SAXIHP1RCOUNT(2) => PS7_i_n_1358, + SAXIHP1RCOUNT(1) => PS7_i_n_1359, + SAXIHP1RCOUNT(0) => PS7_i_n_1360, + SAXIHP1RDATA(63) => PS7_i_n_1129, + SAXIHP1RDATA(62) => PS7_i_n_1130, + SAXIHP1RDATA(61) => PS7_i_n_1131, + SAXIHP1RDATA(60) => PS7_i_n_1132, + SAXIHP1RDATA(59) => PS7_i_n_1133, + SAXIHP1RDATA(58) => PS7_i_n_1134, + SAXIHP1RDATA(57) => PS7_i_n_1135, + SAXIHP1RDATA(56) => PS7_i_n_1136, + SAXIHP1RDATA(55) => PS7_i_n_1137, + SAXIHP1RDATA(54) => PS7_i_n_1138, + SAXIHP1RDATA(53) => PS7_i_n_1139, + SAXIHP1RDATA(52) => PS7_i_n_1140, + SAXIHP1RDATA(51) => PS7_i_n_1141, + SAXIHP1RDATA(50) => PS7_i_n_1142, + SAXIHP1RDATA(49) => PS7_i_n_1143, + SAXIHP1RDATA(48) => PS7_i_n_1144, + SAXIHP1RDATA(47) => PS7_i_n_1145, + SAXIHP1RDATA(46) => PS7_i_n_1146, + SAXIHP1RDATA(45) => PS7_i_n_1147, + SAXIHP1RDATA(44) => PS7_i_n_1148, + SAXIHP1RDATA(43) => PS7_i_n_1149, + SAXIHP1RDATA(42) => PS7_i_n_1150, + SAXIHP1RDATA(41) => PS7_i_n_1151, + SAXIHP1RDATA(40) => PS7_i_n_1152, + SAXIHP1RDATA(39) => PS7_i_n_1153, + SAXIHP1RDATA(38) => PS7_i_n_1154, + SAXIHP1RDATA(37) => PS7_i_n_1155, + SAXIHP1RDATA(36) => PS7_i_n_1156, + SAXIHP1RDATA(35) => PS7_i_n_1157, + SAXIHP1RDATA(34) => PS7_i_n_1158, + SAXIHP1RDATA(33) => PS7_i_n_1159, + SAXIHP1RDATA(32) => PS7_i_n_1160, + SAXIHP1RDATA(31) => PS7_i_n_1161, + SAXIHP1RDATA(30) => PS7_i_n_1162, + SAXIHP1RDATA(29) => PS7_i_n_1163, + SAXIHP1RDATA(28) => PS7_i_n_1164, + SAXIHP1RDATA(27) => PS7_i_n_1165, + SAXIHP1RDATA(26) => PS7_i_n_1166, + SAXIHP1RDATA(25) => PS7_i_n_1167, + SAXIHP1RDATA(24) => PS7_i_n_1168, + SAXIHP1RDATA(23) => PS7_i_n_1169, + SAXIHP1RDATA(22) => PS7_i_n_1170, + SAXIHP1RDATA(21) => PS7_i_n_1171, + SAXIHP1RDATA(20) => PS7_i_n_1172, + SAXIHP1RDATA(19) => PS7_i_n_1173, + SAXIHP1RDATA(18) => PS7_i_n_1174, + SAXIHP1RDATA(17) => PS7_i_n_1175, + SAXIHP1RDATA(16) => PS7_i_n_1176, + SAXIHP1RDATA(15) => PS7_i_n_1177, + SAXIHP1RDATA(14) => PS7_i_n_1178, + SAXIHP1RDATA(13) => PS7_i_n_1179, + SAXIHP1RDATA(12) => PS7_i_n_1180, + SAXIHP1RDATA(11) => PS7_i_n_1181, + SAXIHP1RDATA(10) => PS7_i_n_1182, + SAXIHP1RDATA(9) => PS7_i_n_1183, + SAXIHP1RDATA(8) => PS7_i_n_1184, + SAXIHP1RDATA(7) => PS7_i_n_1185, + SAXIHP1RDATA(6) => PS7_i_n_1186, + SAXIHP1RDATA(5) => PS7_i_n_1187, + SAXIHP1RDATA(4) => PS7_i_n_1188, + SAXIHP1RDATA(3) => PS7_i_n_1189, + SAXIHP1RDATA(2) => PS7_i_n_1190, + SAXIHP1RDATA(1) => PS7_i_n_1191, + SAXIHP1RDATA(0) => PS7_i_n_1192, + SAXIHP1RDISSUECAP1EN => '0', + SAXIHP1RID(5) => PS7_i_n_825, + SAXIHP1RID(4) => PS7_i_n_826, + SAXIHP1RID(3) => PS7_i_n_827, + SAXIHP1RID(2) => PS7_i_n_828, + SAXIHP1RID(1) => PS7_i_n_829, + SAXIHP1RID(0) => PS7_i_n_830, + SAXIHP1RLAST => PS7_i_n_135, + SAXIHP1RREADY => '0', + SAXIHP1RRESP(1) => PS7_i_n_282, + SAXIHP1RRESP(0) => PS7_i_n_283, + SAXIHP1RVALID => PS7_i_n_136, + SAXIHP1WACOUNT(5) => PS7_i_n_831, + SAXIHP1WACOUNT(4) => PS7_i_n_832, + SAXIHP1WACOUNT(3) => PS7_i_n_833, + SAXIHP1WACOUNT(2) => PS7_i_n_834, + SAXIHP1WACOUNT(1) => PS7_i_n_835, + SAXIHP1WACOUNT(0) => PS7_i_n_836, + SAXIHP1WCOUNT(7) => PS7_i_n_1361, + SAXIHP1WCOUNT(6) => PS7_i_n_1362, + SAXIHP1WCOUNT(5) => PS7_i_n_1363, + SAXIHP1WCOUNT(4) => PS7_i_n_1364, + SAXIHP1WCOUNT(3) => PS7_i_n_1365, + SAXIHP1WCOUNT(2) => PS7_i_n_1366, + SAXIHP1WCOUNT(1) => PS7_i_n_1367, + SAXIHP1WCOUNT(0) => PS7_i_n_1368, + SAXIHP1WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + SAXIHP1WID(5 downto 0) => B"000000", + SAXIHP1WLAST => '0', + SAXIHP1WREADY => PS7_i_n_137, + SAXIHP1WRISSUECAP1EN => '0', + SAXIHP1WSTRB(7 downto 0) => B"00000000", + SAXIHP1WVALID => '0', + SAXIHP2ACLK => '0', + SAXIHP2ARADDR(31 downto 0) => B"00000000000000000000000000000000", + SAXIHP2ARBURST(1 downto 0) => B"00", + SAXIHP2ARCACHE(3 downto 0) => B"0000", + SAXIHP2ARESETN => PS7_i_n_138, + SAXIHP2ARID(5 downto 0) => B"000000", + SAXIHP2ARLEN(3 downto 0) => B"0000", + SAXIHP2ARLOCK(1 downto 0) => B"00", + SAXIHP2ARPROT(2 downto 0) => B"000", + SAXIHP2ARQOS(3 downto 0) => B"0000", + SAXIHP2ARREADY => PS7_i_n_139, + SAXIHP2ARSIZE(1 downto 0) => B"00", + SAXIHP2ARVALID => '0', + SAXIHP2AWADDR(31 downto 0) => B"00000000000000000000000000000000", + SAXIHP2AWBURST(1 downto 0) => B"00", + SAXIHP2AWCACHE(3 downto 0) => B"0000", + SAXIHP2AWID(5 downto 0) => B"000000", + SAXIHP2AWLEN(3 downto 0) => B"0000", + SAXIHP2AWLOCK(1 downto 0) => B"00", + SAXIHP2AWPROT(2 downto 0) => B"000", + SAXIHP2AWQOS(3 downto 0) => B"0000", + SAXIHP2AWREADY => PS7_i_n_140, + SAXIHP2AWSIZE(1 downto 0) => B"00", + SAXIHP2AWVALID => '0', + SAXIHP2BID(5) => PS7_i_n_837, + SAXIHP2BID(4) => PS7_i_n_838, + SAXIHP2BID(3) => PS7_i_n_839, + SAXIHP2BID(2) => PS7_i_n_840, + SAXIHP2BID(1) => PS7_i_n_841, + SAXIHP2BID(0) => PS7_i_n_842, + SAXIHP2BREADY => '0', + SAXIHP2BRESP(1) => PS7_i_n_284, + SAXIHP2BRESP(0) => PS7_i_n_285, + SAXIHP2BVALID => PS7_i_n_141, + SAXIHP2RACOUNT(2) => PS7_i_n_363, + SAXIHP2RACOUNT(1) => PS7_i_n_364, + SAXIHP2RACOUNT(0) => PS7_i_n_365, + SAXIHP2RCOUNT(7) => PS7_i_n_1369, + SAXIHP2RCOUNT(6) => PS7_i_n_1370, + SAXIHP2RCOUNT(5) => PS7_i_n_1371, + SAXIHP2RCOUNT(4) => PS7_i_n_1372, + SAXIHP2RCOUNT(3) => PS7_i_n_1373, + SAXIHP2RCOUNT(2) => PS7_i_n_1374, + SAXIHP2RCOUNT(1) => PS7_i_n_1375, + SAXIHP2RCOUNT(0) => PS7_i_n_1376, + SAXIHP2RDATA(63) => PS7_i_n_1193, + SAXIHP2RDATA(62) => PS7_i_n_1194, + SAXIHP2RDATA(61) => PS7_i_n_1195, + SAXIHP2RDATA(60) => PS7_i_n_1196, + SAXIHP2RDATA(59) => PS7_i_n_1197, + SAXIHP2RDATA(58) => PS7_i_n_1198, + SAXIHP2RDATA(57) => PS7_i_n_1199, + SAXIHP2RDATA(56) => PS7_i_n_1200, + SAXIHP2RDATA(55) => PS7_i_n_1201, + SAXIHP2RDATA(54) => PS7_i_n_1202, + SAXIHP2RDATA(53) => PS7_i_n_1203, + SAXIHP2RDATA(52) => PS7_i_n_1204, + SAXIHP2RDATA(51) => PS7_i_n_1205, + SAXIHP2RDATA(50) => PS7_i_n_1206, + SAXIHP2RDATA(49) => PS7_i_n_1207, + SAXIHP2RDATA(48) => PS7_i_n_1208, + SAXIHP2RDATA(47) => PS7_i_n_1209, + SAXIHP2RDATA(46) => PS7_i_n_1210, + SAXIHP2RDATA(45) => PS7_i_n_1211, + SAXIHP2RDATA(44) => PS7_i_n_1212, + SAXIHP2RDATA(43) => PS7_i_n_1213, + SAXIHP2RDATA(42) => PS7_i_n_1214, + SAXIHP2RDATA(41) => PS7_i_n_1215, + SAXIHP2RDATA(40) => PS7_i_n_1216, + SAXIHP2RDATA(39) => PS7_i_n_1217, + SAXIHP2RDATA(38) => PS7_i_n_1218, + SAXIHP2RDATA(37) => PS7_i_n_1219, + SAXIHP2RDATA(36) => PS7_i_n_1220, + SAXIHP2RDATA(35) => PS7_i_n_1221, + SAXIHP2RDATA(34) => PS7_i_n_1222, + SAXIHP2RDATA(33) => PS7_i_n_1223, + SAXIHP2RDATA(32) => PS7_i_n_1224, + SAXIHP2RDATA(31) => PS7_i_n_1225, + SAXIHP2RDATA(30) => PS7_i_n_1226, + SAXIHP2RDATA(29) => PS7_i_n_1227, + SAXIHP2RDATA(28) => PS7_i_n_1228, + SAXIHP2RDATA(27) => PS7_i_n_1229, + SAXIHP2RDATA(26) => PS7_i_n_1230, + SAXIHP2RDATA(25) => PS7_i_n_1231, + SAXIHP2RDATA(24) => PS7_i_n_1232, + SAXIHP2RDATA(23) => PS7_i_n_1233, + SAXIHP2RDATA(22) => PS7_i_n_1234, + SAXIHP2RDATA(21) => PS7_i_n_1235, + SAXIHP2RDATA(20) => PS7_i_n_1236, + SAXIHP2RDATA(19) => PS7_i_n_1237, + SAXIHP2RDATA(18) => PS7_i_n_1238, + SAXIHP2RDATA(17) => PS7_i_n_1239, + SAXIHP2RDATA(16) => PS7_i_n_1240, + SAXIHP2RDATA(15) => PS7_i_n_1241, + SAXIHP2RDATA(14) => PS7_i_n_1242, + SAXIHP2RDATA(13) => PS7_i_n_1243, + SAXIHP2RDATA(12) => PS7_i_n_1244, + SAXIHP2RDATA(11) => PS7_i_n_1245, + SAXIHP2RDATA(10) => PS7_i_n_1246, + SAXIHP2RDATA(9) => PS7_i_n_1247, + SAXIHP2RDATA(8) => PS7_i_n_1248, + SAXIHP2RDATA(7) => PS7_i_n_1249, + SAXIHP2RDATA(6) => PS7_i_n_1250, + SAXIHP2RDATA(5) => PS7_i_n_1251, + SAXIHP2RDATA(4) => PS7_i_n_1252, + SAXIHP2RDATA(3) => PS7_i_n_1253, + SAXIHP2RDATA(2) => PS7_i_n_1254, + SAXIHP2RDATA(1) => PS7_i_n_1255, + SAXIHP2RDATA(0) => PS7_i_n_1256, + SAXIHP2RDISSUECAP1EN => '0', + SAXIHP2RID(5) => PS7_i_n_843, + SAXIHP2RID(4) => PS7_i_n_844, + SAXIHP2RID(3) => PS7_i_n_845, + SAXIHP2RID(2) => PS7_i_n_846, + SAXIHP2RID(1) => PS7_i_n_847, + SAXIHP2RID(0) => PS7_i_n_848, + SAXIHP2RLAST => PS7_i_n_142, + SAXIHP2RREADY => '0', + SAXIHP2RRESP(1) => PS7_i_n_286, + SAXIHP2RRESP(0) => PS7_i_n_287, + SAXIHP2RVALID => PS7_i_n_143, + SAXIHP2WACOUNT(5) => PS7_i_n_849, + SAXIHP2WACOUNT(4) => PS7_i_n_850, + SAXIHP2WACOUNT(3) => PS7_i_n_851, + SAXIHP2WACOUNT(2) => PS7_i_n_852, + SAXIHP2WACOUNT(1) => PS7_i_n_853, + SAXIHP2WACOUNT(0) => PS7_i_n_854, + SAXIHP2WCOUNT(7) => PS7_i_n_1377, + SAXIHP2WCOUNT(6) => PS7_i_n_1378, + SAXIHP2WCOUNT(5) => PS7_i_n_1379, + SAXIHP2WCOUNT(4) => PS7_i_n_1380, + SAXIHP2WCOUNT(3) => PS7_i_n_1381, + SAXIHP2WCOUNT(2) => PS7_i_n_1382, + SAXIHP2WCOUNT(1) => PS7_i_n_1383, + SAXIHP2WCOUNT(0) => PS7_i_n_1384, + SAXIHP2WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + SAXIHP2WID(5 downto 0) => B"000000", + SAXIHP2WLAST => '0', + SAXIHP2WREADY => PS7_i_n_144, + SAXIHP2WRISSUECAP1EN => '0', + SAXIHP2WSTRB(7 downto 0) => B"00000000", + SAXIHP2WVALID => '0', + SAXIHP3ACLK => '0', + SAXIHP3ARADDR(31 downto 0) => B"00000000000000000000000000000000", + SAXIHP3ARBURST(1 downto 0) => B"00", + SAXIHP3ARCACHE(3 downto 0) => B"0000", + SAXIHP3ARESETN => PS7_i_n_145, + SAXIHP3ARID(5 downto 0) => B"000000", + SAXIHP3ARLEN(3 downto 0) => B"0000", + SAXIHP3ARLOCK(1 downto 0) => B"00", + SAXIHP3ARPROT(2 downto 0) => B"000", + SAXIHP3ARQOS(3 downto 0) => B"0000", + SAXIHP3ARREADY => PS7_i_n_146, + SAXIHP3ARSIZE(1 downto 0) => B"00", + SAXIHP3ARVALID => '0', + SAXIHP3AWADDR(31 downto 0) => B"00000000000000000000000000000000", + SAXIHP3AWBURST(1 downto 0) => B"00", + SAXIHP3AWCACHE(3 downto 0) => B"0000", + SAXIHP3AWID(5 downto 0) => B"000000", + SAXIHP3AWLEN(3 downto 0) => B"0000", + SAXIHP3AWLOCK(1 downto 0) => B"00", + SAXIHP3AWPROT(2 downto 0) => B"000", + SAXIHP3AWQOS(3 downto 0) => B"0000", + SAXIHP3AWREADY => PS7_i_n_147, + SAXIHP3AWSIZE(1 downto 0) => B"00", + SAXIHP3AWVALID => '0', + SAXIHP3BID(5) => PS7_i_n_855, + SAXIHP3BID(4) => PS7_i_n_856, + SAXIHP3BID(3) => PS7_i_n_857, + SAXIHP3BID(2) => PS7_i_n_858, + SAXIHP3BID(1) => PS7_i_n_859, + SAXIHP3BID(0) => PS7_i_n_860, + SAXIHP3BREADY => '0', + SAXIHP3BRESP(1) => PS7_i_n_288, + SAXIHP3BRESP(0) => PS7_i_n_289, + SAXIHP3BVALID => PS7_i_n_148, + SAXIHP3RACOUNT(2) => PS7_i_n_366, + SAXIHP3RACOUNT(1) => PS7_i_n_367, + SAXIHP3RACOUNT(0) => PS7_i_n_368, + SAXIHP3RCOUNT(7) => PS7_i_n_1385, + SAXIHP3RCOUNT(6) => PS7_i_n_1386, + SAXIHP3RCOUNT(5) => PS7_i_n_1387, + SAXIHP3RCOUNT(4) => PS7_i_n_1388, + SAXIHP3RCOUNT(3) => PS7_i_n_1389, + SAXIHP3RCOUNT(2) => PS7_i_n_1390, + SAXIHP3RCOUNT(1) => PS7_i_n_1391, + SAXIHP3RCOUNT(0) => PS7_i_n_1392, + SAXIHP3RDATA(63) => PS7_i_n_1257, + SAXIHP3RDATA(62) => PS7_i_n_1258, + SAXIHP3RDATA(61) => PS7_i_n_1259, + SAXIHP3RDATA(60) => PS7_i_n_1260, + SAXIHP3RDATA(59) => PS7_i_n_1261, + SAXIHP3RDATA(58) => PS7_i_n_1262, + SAXIHP3RDATA(57) => PS7_i_n_1263, + SAXIHP3RDATA(56) => PS7_i_n_1264, + SAXIHP3RDATA(55) => PS7_i_n_1265, + SAXIHP3RDATA(54) => PS7_i_n_1266, + SAXIHP3RDATA(53) => PS7_i_n_1267, + SAXIHP3RDATA(52) => PS7_i_n_1268, + SAXIHP3RDATA(51) => PS7_i_n_1269, + SAXIHP3RDATA(50) => PS7_i_n_1270, + SAXIHP3RDATA(49) => PS7_i_n_1271, + SAXIHP3RDATA(48) => PS7_i_n_1272, + SAXIHP3RDATA(47) => PS7_i_n_1273, + SAXIHP3RDATA(46) => PS7_i_n_1274, + SAXIHP3RDATA(45) => PS7_i_n_1275, + SAXIHP3RDATA(44) => PS7_i_n_1276, + SAXIHP3RDATA(43) => PS7_i_n_1277, + SAXIHP3RDATA(42) => PS7_i_n_1278, + SAXIHP3RDATA(41) => PS7_i_n_1279, + SAXIHP3RDATA(40) => PS7_i_n_1280, + SAXIHP3RDATA(39) => PS7_i_n_1281, + SAXIHP3RDATA(38) => PS7_i_n_1282, + SAXIHP3RDATA(37) => PS7_i_n_1283, + SAXIHP3RDATA(36) => PS7_i_n_1284, + SAXIHP3RDATA(35) => PS7_i_n_1285, + SAXIHP3RDATA(34) => PS7_i_n_1286, + SAXIHP3RDATA(33) => PS7_i_n_1287, + SAXIHP3RDATA(32) => PS7_i_n_1288, + SAXIHP3RDATA(31) => PS7_i_n_1289, + SAXIHP3RDATA(30) => PS7_i_n_1290, + SAXIHP3RDATA(29) => PS7_i_n_1291, + SAXIHP3RDATA(28) => PS7_i_n_1292, + SAXIHP3RDATA(27) => PS7_i_n_1293, + SAXIHP3RDATA(26) => PS7_i_n_1294, + SAXIHP3RDATA(25) => PS7_i_n_1295, + SAXIHP3RDATA(24) => PS7_i_n_1296, + SAXIHP3RDATA(23) => PS7_i_n_1297, + SAXIHP3RDATA(22) => PS7_i_n_1298, + SAXIHP3RDATA(21) => PS7_i_n_1299, + SAXIHP3RDATA(20) => PS7_i_n_1300, + SAXIHP3RDATA(19) => PS7_i_n_1301, + SAXIHP3RDATA(18) => PS7_i_n_1302, + SAXIHP3RDATA(17) => PS7_i_n_1303, + SAXIHP3RDATA(16) => PS7_i_n_1304, + SAXIHP3RDATA(15) => PS7_i_n_1305, + SAXIHP3RDATA(14) => PS7_i_n_1306, + SAXIHP3RDATA(13) => PS7_i_n_1307, + SAXIHP3RDATA(12) => PS7_i_n_1308, + SAXIHP3RDATA(11) => PS7_i_n_1309, + SAXIHP3RDATA(10) => PS7_i_n_1310, + SAXIHP3RDATA(9) => PS7_i_n_1311, + SAXIHP3RDATA(8) => PS7_i_n_1312, + SAXIHP3RDATA(7) => PS7_i_n_1313, + SAXIHP3RDATA(6) => PS7_i_n_1314, + SAXIHP3RDATA(5) => PS7_i_n_1315, + SAXIHP3RDATA(4) => PS7_i_n_1316, + SAXIHP3RDATA(3) => PS7_i_n_1317, + SAXIHP3RDATA(2) => PS7_i_n_1318, + SAXIHP3RDATA(1) => PS7_i_n_1319, + SAXIHP3RDATA(0) => PS7_i_n_1320, + SAXIHP3RDISSUECAP1EN => '0', + SAXIHP3RID(5) => PS7_i_n_861, + SAXIHP3RID(4) => PS7_i_n_862, + SAXIHP3RID(3) => PS7_i_n_863, + SAXIHP3RID(2) => PS7_i_n_864, + SAXIHP3RID(1) => PS7_i_n_865, + SAXIHP3RID(0) => PS7_i_n_866, + SAXIHP3RLAST => PS7_i_n_149, + SAXIHP3RREADY => '0', + SAXIHP3RRESP(1) => PS7_i_n_290, + SAXIHP3RRESP(0) => PS7_i_n_291, + SAXIHP3RVALID => PS7_i_n_150, + SAXIHP3WACOUNT(5) => PS7_i_n_867, + SAXIHP3WACOUNT(4) => PS7_i_n_868, + SAXIHP3WACOUNT(3) => PS7_i_n_869, + SAXIHP3WACOUNT(2) => PS7_i_n_870, + SAXIHP3WACOUNT(1) => PS7_i_n_871, + SAXIHP3WACOUNT(0) => PS7_i_n_872, + SAXIHP3WCOUNT(7) => PS7_i_n_1393, + SAXIHP3WCOUNT(6) => PS7_i_n_1394, + SAXIHP3WCOUNT(5) => PS7_i_n_1395, + SAXIHP3WCOUNT(4) => PS7_i_n_1396, + SAXIHP3WCOUNT(3) => PS7_i_n_1397, + SAXIHP3WCOUNT(2) => PS7_i_n_1398, + SAXIHP3WCOUNT(1) => PS7_i_n_1399, + SAXIHP3WCOUNT(0) => PS7_i_n_1400, + SAXIHP3WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + SAXIHP3WID(5 downto 0) => B"000000", + SAXIHP3WLAST => '0', + SAXIHP3WREADY => PS7_i_n_151, + SAXIHP3WRISSUECAP1EN => '0', + SAXIHP3WSTRB(7 downto 0) => B"00000000", + SAXIHP3WVALID => '0' + ); +PS_CLK_BIBUF: unisim.vcomponents.BIBUF + port map ( + IO => buffered_PS_CLK, + PAD => PS_CLK + ); +PS_PORB_BIBUF: unisim.vcomponents.BIBUF + port map ( + IO => buffered_PS_PORB, + PAD => PS_PORB + ); +PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF + port map ( + IO => buffered_PS_SRSTB, + PAD => PS_SRSTB + ); +\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG + port map ( + I => FCLK_CLK_unbuffered(0), + O => FCLK_CLK0 + ); +\buffer_fclk_clk_1.FCLK_CLK_1_BUFG\: unisim.vcomponents.BUFG + port map ( + I => FCLK_CLK_unbuffered(1), + O => FCLK_CLK1 + ); +\buffer_fclk_clk_2.FCLK_CLK_2_BUFG\: unisim.vcomponents.BUFG + port map ( + I => FCLK_CLK_unbuffered(2), + O => FCLK_CLK2 + ); +\buffer_fclk_clk_3.FCLK_CLK_3_BUFG\: unisim.vcomponents.BUFG + port map ( + I => FCLK_CLK_unbuffered(3), + O => FCLK_CLK3 + ); +\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(0), + PAD => MIO(0) + ); +\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(10), + PAD => MIO(10) + ); +\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(11), + PAD => MIO(11) + ); +\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(12), + PAD => MIO(12) + ); +\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(13), + PAD => MIO(13) + ); +\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(14), + PAD => MIO(14) + ); +\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(15), + PAD => MIO(15) + ); +\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(16), + PAD => MIO(16) + ); +\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(17), + PAD => MIO(17) + ); +\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(18), + PAD => MIO(18) + ); +\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(19), + PAD => MIO(19) + ); +\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(1), + PAD => MIO(1) + ); +\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(20), + PAD => MIO(20) + ); +\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(21), + PAD => MIO(21) + ); +\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(22), + PAD => MIO(22) + ); +\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(23), + PAD => MIO(23) + ); +\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(24), + PAD => MIO(24) + ); +\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(25), + PAD => MIO(25) + ); +\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(26), + PAD => MIO(26) + ); +\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(27), + PAD => MIO(27) + ); +\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(28), + PAD => MIO(28) + ); +\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(29), + PAD => MIO(29) + ); +\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(2), + PAD => MIO(2) + ); +\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(30), + PAD => MIO(30) + ); +\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(31), + PAD => MIO(31) + ); +\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(32), + PAD => MIO(32) + ); +\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(33), + PAD => MIO(33) + ); +\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(34), + PAD => MIO(34) + ); +\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(35), + PAD => MIO(35) + ); +\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(36), + PAD => MIO(36) + ); +\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(37), + PAD => MIO(37) + ); +\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(38), + PAD => MIO(38) + ); +\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(39), + PAD => MIO(39) + ); +\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(3), + PAD => MIO(3) + ); +\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(40), + PAD => MIO(40) + ); +\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(41), + PAD => MIO(41) + ); +\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(42), + PAD => MIO(42) + ); +\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(43), + PAD => MIO(43) + ); +\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(44), + PAD => MIO(44) + ); +\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(45), + PAD => MIO(45) + ); +\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(46), + PAD => MIO(46) + ); +\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(47), + PAD => MIO(47) + ); +\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(48), + PAD => MIO(48) + ); +\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(49), + PAD => MIO(49) + ); +\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(4), + PAD => MIO(4) + ); +\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(50), + PAD => MIO(50) + ); +\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(51), + PAD => MIO(51) + ); +\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(52), + PAD => MIO(52) + ); +\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(53), + PAD => MIO(53) + ); +\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(5), + PAD => MIO(5) + ); +\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(6), + PAD => MIO(6) + ); +\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(7), + PAD => MIO(7) + ); +\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(8), + PAD => MIO(8) + ); +\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(9), + PAD => MIO(9) + ); +\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_BankAddr(0), + PAD => DDR_BankAddr(0) + ); +\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_BankAddr(1), + PAD => DDR_BankAddr(1) + ); +\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_BankAddr(2), + PAD => DDR_BankAddr(2) + ); +\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Addr(0), + PAD => DDR_Addr(0) + ); +\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Addr(10), + PAD => DDR_Addr(10) + ); +\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Addr(11), + PAD => DDR_Addr(11) + ); +\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Addr(12), + PAD => DDR_Addr(12) + ); +\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Addr(13), + PAD => DDR_Addr(13) + ); +\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Addr(14), + PAD => DDR_Addr(14) + ); +\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Addr(1), + PAD => DDR_Addr(1) + ); +\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Addr(2), + PAD => DDR_Addr(2) + ); +\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Addr(3), + PAD => DDR_Addr(3) + ); +\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Addr(4), + PAD => DDR_Addr(4) + ); +\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Addr(5), + PAD => DDR_Addr(5) + ); +\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Addr(6), + PAD => DDR_Addr(6) + ); +\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Addr(7), + PAD => DDR_Addr(7) + ); +\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Addr(8), + PAD => DDR_Addr(8) + ); +\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Addr(9), + PAD => DDR_Addr(9) + ); +\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DM(0), + PAD => DDR_DM(0) + ); +\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DM(1), + PAD => DDR_DM(1) + ); +\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DM(2), + PAD => DDR_DM(2) + ); +\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DM(3), + PAD => DDR_DM(3) + ); +\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(0), + PAD => DDR_DQ(0) + ); +\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(10), + PAD => DDR_DQ(10) + ); +\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(11), + PAD => DDR_DQ(11) + ); +\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(12), + PAD => DDR_DQ(12) + ); +\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(13), + PAD => DDR_DQ(13) + ); +\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(14), + PAD => DDR_DQ(14) + ); +\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(15), + PAD => DDR_DQ(15) + ); +\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(16), + PAD => DDR_DQ(16) + ); +\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(17), + PAD => DDR_DQ(17) + ); +\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(18), + PAD => DDR_DQ(18) + ); +\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(19), + PAD => DDR_DQ(19) + ); +\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(1), + PAD => DDR_DQ(1) + ); +\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(20), + PAD => DDR_DQ(20) + ); +\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(21), + PAD => DDR_DQ(21) + ); +\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(22), + PAD => DDR_DQ(22) + ); +\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(23), + PAD => DDR_DQ(23) + ); +\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(24), + PAD => DDR_DQ(24) + ); +\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(25), + PAD => DDR_DQ(25) + ); +\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(26), + PAD => DDR_DQ(26) + ); +\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(27), + PAD => DDR_DQ(27) + ); +\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(28), + PAD => DDR_DQ(28) + ); +\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(29), + PAD => DDR_DQ(29) + ); +\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(2), + PAD => DDR_DQ(2) + ); +\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(30), + PAD => DDR_DQ(30) + ); +\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(31), + PAD => DDR_DQ(31) + ); +\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(3), + PAD => DDR_DQ(3) + ); +\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(4), + PAD => DDR_DQ(4) + ); +\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(5), + PAD => DDR_DQ(5) + ); +\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(6), + PAD => DDR_DQ(6) + ); +\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(7), + PAD => DDR_DQ(7) + ); +\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(8), + PAD => DDR_DQ(8) + ); +\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(9), + PAD => DDR_DQ(9) + ); +\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQS_n(0), + PAD => DDR_DQS_n(0) + ); +\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQS_n(1), + PAD => DDR_DQS_n(1) + ); +\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQS_n(2), + PAD => DDR_DQS_n(2) + ); +\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQS_n(3), + PAD => DDR_DQS_n(3) + ); +\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQS(0), + PAD => DDR_DQS(0) + ); +\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQS(1), + PAD => DDR_DQS(1) + ); +\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQS(2), + PAD => DDR_DQS(2) + ); +\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQS(3), + PAD => DDR_DQS(3) + ); +i_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_CTL_PIPE[0]\ + ); +i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[0]\(1) + ); +i_10: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[7]\(1) + ); +i_11: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[7]\(0) + ); +i_12: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[6]\(1) + ); +i_13: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[6]\(0) + ); +i_14: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[5]\(1) + ); +i_15: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[5]\(0) + ); +i_16: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[4]\(1) + ); +i_17: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[4]\(0) + ); +i_18: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[3]\(1) + ); +i_19: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[3]\(0) + ); +i_2: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[0]\(0) + ); +i_20: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[2]\(1) + ); +i_21: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[2]\(0) + ); +i_22: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[1]\(1) + ); +i_23: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[1]\(0) + ); +i_3: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_CTL_PIPE[7]\ + ); +i_4: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_CTL_PIPE[6]\ + ); +i_5: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_CTL_PIPE[5]\ + ); +i_6: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_CTL_PIPE[4]\ + ); +i_7: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_CTL_PIPE[3]\ + ); +i_8: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_CTL_PIPE[2]\ + ); +i_9: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_CTL_PIPE[1]\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_processing_system7_0_0 is + port ( + M_AXI_GP0_ARVALID : out STD_LOGIC; + M_AXI_GP0_AWVALID : out STD_LOGIC; + M_AXI_GP0_BREADY : out STD_LOGIC; + M_AXI_GP0_RREADY : out STD_LOGIC; + M_AXI_GP0_WLAST : out STD_LOGIC; + M_AXI_GP0_WVALID : out STD_LOGIC; + M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_ACLK : in STD_LOGIC; + M_AXI_GP0_ARREADY : in STD_LOGIC; + M_AXI_GP0_AWREADY : in STD_LOGIC; + M_AXI_GP0_BVALID : in STD_LOGIC; + M_AXI_GP0_RLAST : in STD_LOGIC; + M_AXI_GP0_RVALID : in STD_LOGIC; + M_AXI_GP0_WREADY : in STD_LOGIC; + M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + FCLK_CLK0 : out STD_LOGIC; + FCLK_CLK1 : out STD_LOGIC; + FCLK_CLK2 : out STD_LOGIC; + FCLK_CLK3 : out STD_LOGIC; + FCLK_RESET0_N : out STD_LOGIC; + MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); + DDR_CAS_n : inout STD_LOGIC; + DDR_CKE : inout STD_LOGIC; + DDR_Clk_n : inout STD_LOGIC; + DDR_Clk : inout STD_LOGIC; + DDR_CS_n : inout STD_LOGIC; + DDR_DRSTB : inout STD_LOGIC; + DDR_ODT : inout STD_LOGIC; + DDR_RAS_n : inout STD_LOGIC; + DDR_WEB : inout STD_LOGIC; + DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); + DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); + DDR_VRN : inout STD_LOGIC; + DDR_VRP : inout STD_LOGIC; + DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); + DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + PS_SRSTB : inout STD_LOGIC; + PS_CLK : inout STD_LOGIC; + PS_PORB : inout STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of NewExtInst_TOP_processing_system7_0_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of NewExtInst_TOP_processing_system7_0_0 : entity is "NewExtInst_TOP_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}"; + attribute DowngradeIPIdentifiedWarnings : string; + attribute DowngradeIPIdentifiedWarnings of NewExtInst_TOP_processing_system7_0_0 : entity is "yes"; + attribute X_CORE_INFO : string; + attribute X_CORE_INFO of NewExtInst_TOP_processing_system7_0_0 : entity is "processing_system7_v5_5_processing_system7,Vivado 2023.2"; +end NewExtInst_TOP_processing_system7_0_0; + +architecture STRUCTURE of NewExtInst_TOP_processing_system7_0_0 is + signal \\ : STD_LOGIC; + signal \\ : STD_LOGIC; + signal \^m_axi_gp0_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^m_axi_gp0_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC; + signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC; + signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC; + signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC; + signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC; + signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC; + signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC; + signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC; + signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC; + signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC; + signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC; + signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC; + signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC; + signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC; + signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC; + signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC; + signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC; + signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC; + signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC; + signal NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC; + signal NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC; + signal NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC; + signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC; + signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC; + signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC; + signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC; + signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC; + signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC; + signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal NLW_inst_M_AXI_GP0_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); + signal NLW_inst_M_AXI_GP0_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 to 2 ); + signal NLW_inst_M_AXI_GP0_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); + signal NLW_inst_M_AXI_GP0_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 to 2 ); + signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute C_DM_WIDTH : integer; + attribute C_DM_WIDTH of inst : label is 4; + attribute C_DQS_WIDTH : integer; + attribute C_DQS_WIDTH of inst : label is 4; + attribute C_DQ_WIDTH : integer; + attribute C_DQ_WIDTH of inst : label is 32; + attribute C_EMIO_GPIO_WIDTH : integer; + attribute C_EMIO_GPIO_WIDTH of inst : label is 64; + attribute C_EN_EMIO_ENET0 : integer; + attribute C_EN_EMIO_ENET0 of inst : label is 0; + attribute C_EN_EMIO_ENET1 : integer; + attribute C_EN_EMIO_ENET1 of inst : label is 0; + attribute C_EN_EMIO_PJTAG : integer; + attribute C_EN_EMIO_PJTAG of inst : label is 0; + attribute C_EN_EMIO_TRACE : integer; + attribute C_EN_EMIO_TRACE of inst : label is 0; + attribute C_FCLK_CLK0_BUF : string; + attribute C_FCLK_CLK0_BUF of inst : label is "TRUE"; + attribute C_FCLK_CLK1_BUF : string; + attribute C_FCLK_CLK1_BUF of inst : label is "TRUE"; + attribute C_FCLK_CLK2_BUF : string; + attribute C_FCLK_CLK2_BUF of inst : label is "TRUE"; + attribute C_FCLK_CLK3_BUF : string; + attribute C_FCLK_CLK3_BUF of inst : label is "TRUE"; + attribute C_GP0_EN_MODIFIABLE_TXN : integer; + attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 1; + attribute C_GP1_EN_MODIFIABLE_TXN : integer; + attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 1; + attribute C_INCLUDE_ACP_TRANS_CHECK : integer; + attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0; + attribute C_INCLUDE_TRACE_BUFFER : integer; + attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0; + attribute C_IRQ_F2P_MODE : string; + attribute C_IRQ_F2P_MODE of inst : label is "DIRECT"; + attribute C_MIO_PRIMITIVE : integer; + attribute C_MIO_PRIMITIVE of inst : label is 54; + attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer; + attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0; + attribute C_M_AXI_GP0_ID_WIDTH : integer; + attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12; + attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer; + attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12; + attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer; + attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0; + attribute C_M_AXI_GP1_ID_WIDTH : integer; + attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12; + attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer; + attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12; + attribute C_NUM_F2P_INTR_INPUTS : integer; + attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1; + attribute C_PACKAGE_NAME : string; + attribute C_PACKAGE_NAME of inst : label is "ffg676"; + attribute C_PS7_SI_REV : string; + attribute C_PS7_SI_REV of inst : label is "PRODUCTION"; + attribute C_S_AXI_ACP_ARUSER_VAL : integer; + attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31; + attribute C_S_AXI_ACP_AWUSER_VAL : integer; + attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31; + attribute C_S_AXI_ACP_ID_WIDTH : integer; + attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3; + attribute C_S_AXI_GP0_ID_WIDTH : integer; + attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6; + attribute C_S_AXI_GP1_ID_WIDTH : integer; + attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6; + attribute C_S_AXI_HP0_DATA_WIDTH : integer; + attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64; + attribute C_S_AXI_HP0_ID_WIDTH : integer; + attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6; + attribute C_S_AXI_HP1_DATA_WIDTH : integer; + attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64; + attribute C_S_AXI_HP1_ID_WIDTH : integer; + attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6; + attribute C_S_AXI_HP2_DATA_WIDTH : integer; + attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64; + attribute C_S_AXI_HP2_ID_WIDTH : integer; + attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6; + attribute C_S_AXI_HP3_DATA_WIDTH : integer; + attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64; + attribute C_S_AXI_HP3_ID_WIDTH : integer; + attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6; + attribute C_TRACE_BUFFER_CLOCK_DELAY : integer; + attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12; + attribute C_TRACE_BUFFER_FIFO_SIZE : integer; + attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128; + attribute C_TRACE_INTERNAL_WIDTH : integer; + attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2; + attribute C_TRACE_PIPELINE_WIDTH : integer; + attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8; + attribute C_USE_AXI_NONSECURE : integer; + attribute C_USE_AXI_NONSECURE of inst : label is 0; + attribute C_USE_DEFAULT_ACP_USER_VAL : integer; + attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0; + attribute C_USE_M_AXI_GP0 : integer; + attribute C_USE_M_AXI_GP0 of inst : label is 1; + attribute C_USE_M_AXI_GP1 : integer; + attribute C_USE_M_AXI_GP1 of inst : label is 0; + attribute C_USE_S_AXI_ACP : integer; + attribute C_USE_S_AXI_ACP of inst : label is 0; + attribute C_USE_S_AXI_GP0 : integer; + attribute C_USE_S_AXI_GP0 of inst : label is 0; + attribute C_USE_S_AXI_GP1 : integer; + attribute C_USE_S_AXI_GP1 of inst : label is 0; + attribute C_USE_S_AXI_HP0 : integer; + attribute C_USE_S_AXI_HP0 of inst : label is 0; + attribute C_USE_S_AXI_HP1 : integer; + attribute C_USE_S_AXI_HP1 of inst : label is 0; + attribute C_USE_S_AXI_HP2 : integer; + attribute C_USE_S_AXI_HP2 of inst : label is 0; + attribute C_USE_S_AXI_HP3 : integer; + attribute C_USE_S_AXI_HP3 of inst : label is 0; + attribute HW_HANDOFF : string; + attribute HW_HANDOFF of inst : label is "NewExtInst_TOP_processing_system7_0_0.hwdef"; + attribute POWER : string; + attribute POWER of inst : label is "/>"; + attribute USE_TRACE_DATA_EDGE_DETECTOR : integer; + attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0; + attribute X_INTERFACE_INFO : string; + attribute X_INTERFACE_INFO of DDR_CAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N"; + attribute X_INTERFACE_INFO of DDR_CKE : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE"; + attribute X_INTERFACE_INFO of DDR_CS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N"; + attribute X_INTERFACE_INFO of DDR_Clk : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P"; + attribute X_INTERFACE_INFO of DDR_Clk_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N"; + attribute X_INTERFACE_INFO of DDR_DRSTB : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N"; + attribute X_INTERFACE_INFO of DDR_ODT : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT"; + attribute X_INTERFACE_INFO of DDR_RAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N"; + attribute X_INTERFACE_INFO of DDR_VRN : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN"; + attribute X_INTERFACE_INFO of DDR_VRP : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP"; + attribute X_INTERFACE_INFO of DDR_WEB : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N"; + attribute X_INTERFACE_INFO of FCLK_CLK0 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK"; + attribute X_INTERFACE_PARAMETER : string; + attribute X_INTERFACE_PARAMETER of FCLK_CLK0 : signal is "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 25000000, PHASE 0.000, CLK_DOMAIN NewExtInst_TOP_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0"; + attribute X_INTERFACE_INFO of FCLK_CLK1 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK1 CLK"; + attribute X_INTERFACE_PARAMETER of FCLK_CLK1 : signal is "XIL_INTERFACENAME FCLK_CLK1, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN NewExtInst_TOP_processing_system7_0_0_FCLK_CLK1, INSERT_VIP 0"; + attribute X_INTERFACE_INFO of FCLK_CLK2 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK2 CLK"; + attribute X_INTERFACE_PARAMETER of FCLK_CLK2 : signal is "XIL_INTERFACENAME FCLK_CLK2, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN NewExtInst_TOP_processing_system7_0_0_FCLK_CLK2, INSERT_VIP 0"; + attribute X_INTERFACE_INFO of FCLK_CLK3 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK3 CLK"; + attribute X_INTERFACE_PARAMETER of FCLK_CLK3 : signal is "XIL_INTERFACENAME FCLK_CLK3, FREQ_HZ 200000000, PHASE 0.000, CLK_DOMAIN NewExtInst_TOP_processing_system7_0_0_FCLK_CLK3, INSERT_VIP 0"; + attribute X_INTERFACE_INFO of FCLK_RESET0_N : signal is "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST"; + attribute X_INTERFACE_PARAMETER of FCLK_RESET0_N : signal is "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + attribute X_INTERFACE_INFO of M_AXI_GP0_ACLK : signal is "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK"; + attribute X_INTERFACE_PARAMETER of M_AXI_GP0_ACLK : signal is "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0"; + attribute X_INTERFACE_INFO of M_AXI_GP0_ARREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY"; + attribute X_INTERFACE_INFO of M_AXI_GP0_ARVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID"; + attribute X_INTERFACE_INFO of M_AXI_GP0_AWREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY"; + attribute X_INTERFACE_INFO of M_AXI_GP0_AWVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID"; + attribute X_INTERFACE_INFO of M_AXI_GP0_BREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY"; + attribute X_INTERFACE_INFO of M_AXI_GP0_BVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID"; + attribute X_INTERFACE_INFO of M_AXI_GP0_RLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST"; + attribute X_INTERFACE_INFO of M_AXI_GP0_RREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY"; + attribute X_INTERFACE_INFO of M_AXI_GP0_RVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID"; + attribute X_INTERFACE_INFO of M_AXI_GP0_WLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST"; + attribute X_INTERFACE_INFO of M_AXI_GP0_WREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY"; + attribute X_INTERFACE_INFO of M_AXI_GP0_WVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID"; + attribute X_INTERFACE_INFO of PS_CLK : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK"; + attribute X_INTERFACE_INFO of PS_PORB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB"; + attribute X_INTERFACE_PARAMETER of PS_PORB : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false"; + attribute X_INTERFACE_INFO of PS_SRSTB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB"; + attribute X_INTERFACE_INFO of DDR_Addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR"; + attribute X_INTERFACE_INFO of DDR_BankAddr : signal is "xilinx.com:interface:ddrx:1.0 DDR BA"; + attribute X_INTERFACE_INFO of DDR_DM : signal is "xilinx.com:interface:ddrx:1.0 DDR DM"; + attribute X_INTERFACE_INFO of DDR_DQ : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ"; + attribute X_INTERFACE_INFO of DDR_DQS : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P"; + attribute X_INTERFACE_PARAMETER of DDR_DQS : signal is "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11"; + attribute X_INTERFACE_INFO of DDR_DQS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N"; + attribute X_INTERFACE_INFO of MIO : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO"; + attribute X_INTERFACE_INFO of M_AXI_GP0_ARADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR"; + attribute X_INTERFACE_INFO of M_AXI_GP0_ARBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST"; + attribute X_INTERFACE_INFO of M_AXI_GP0_ARCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE"; + attribute X_INTERFACE_INFO of M_AXI_GP0_ARID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID"; + attribute X_INTERFACE_INFO of M_AXI_GP0_ARLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN"; + attribute X_INTERFACE_INFO of M_AXI_GP0_ARLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK"; + attribute X_INTERFACE_INFO of M_AXI_GP0_ARPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT"; + attribute X_INTERFACE_INFO of M_AXI_GP0_ARQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS"; + attribute X_INTERFACE_INFO of M_AXI_GP0_ARSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE"; + attribute X_INTERFACE_INFO of M_AXI_GP0_AWADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR"; + attribute X_INTERFACE_INFO of M_AXI_GP0_AWBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST"; + attribute X_INTERFACE_INFO of M_AXI_GP0_AWCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE"; + attribute X_INTERFACE_INFO of M_AXI_GP0_AWID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID"; + attribute X_INTERFACE_INFO of M_AXI_GP0_AWLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN"; + attribute X_INTERFACE_INFO of M_AXI_GP0_AWLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK"; + attribute X_INTERFACE_INFO of M_AXI_GP0_AWPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT"; + attribute X_INTERFACE_INFO of M_AXI_GP0_AWQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS"; + attribute X_INTERFACE_INFO of M_AXI_GP0_AWSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE"; + attribute X_INTERFACE_INFO of M_AXI_GP0_BID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID"; + attribute X_INTERFACE_INFO of M_AXI_GP0_BRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP"; + attribute X_INTERFACE_INFO of M_AXI_GP0_RDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA"; + attribute X_INTERFACE_PARAMETER of M_AXI_GP0_RDATA : signal is "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0"; + attribute X_INTERFACE_INFO of M_AXI_GP0_RID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID"; + attribute X_INTERFACE_INFO of M_AXI_GP0_RRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP"; + attribute X_INTERFACE_INFO of M_AXI_GP0_WDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA"; + attribute X_INTERFACE_INFO of M_AXI_GP0_WID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID"; + attribute X_INTERFACE_INFO of M_AXI_GP0_WSTRB : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB"; +begin + M_AXI_GP0_ARCACHE(3 downto 2) <= \^m_axi_gp0_arcache\(3 downto 2); + M_AXI_GP0_ARCACHE(1) <= \\; + M_AXI_GP0_ARCACHE(0) <= \^m_axi_gp0_arcache\(0); + M_AXI_GP0_ARSIZE(2) <= \\; + M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0); + M_AXI_GP0_AWCACHE(3 downto 2) <= \^m_axi_gp0_awcache\(3 downto 2); + M_AXI_GP0_AWCACHE(1) <= \\; + M_AXI_GP0_AWCACHE(0) <= \^m_axi_gp0_awcache\(0); + M_AXI_GP0_AWSIZE(2) <= \\; + M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0); +GND: unisim.vcomponents.GND + port map ( + G => \\ + ); +VCC: unisim.vcomponents.VCC + port map ( + P => \\ + ); +inst: entity work.NewExtInst_TOP_processing_system7_0_0_processing_system7_v5_5_processing_system7 + port map ( + CAN0_PHY_RX => '0', + CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED, + CAN1_PHY_RX => '0', + CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED, + Core0_nFIQ => '0', + Core0_nIRQ => '0', + Core1_nFIQ => '0', + Core1_nIRQ => '0', + DDR_ARB(3 downto 0) => B"0000", + DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0), + DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0), + DDR_CAS_n => DDR_CAS_n, + DDR_CKE => DDR_CKE, + DDR_CS_n => DDR_CS_n, + DDR_Clk => DDR_Clk, + DDR_Clk_n => DDR_Clk_n, + DDR_DM(3 downto 0) => DDR_DM(3 downto 0), + DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0), + DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0), + DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0), + DDR_DRSTB => DDR_DRSTB, + DDR_ODT => DDR_ODT, + DDR_RAS_n => DDR_RAS_n, + DDR_VRN => DDR_VRN, + DDR_VRP => DDR_VRP, + DDR_WEB => DDR_WEB, + DMA0_ACLK => '0', + DMA0_DAREADY => '0', + DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0), + DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED, + DMA0_DRLAST => '0', + DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED, + DMA0_DRTYPE(1 downto 0) => B"00", + DMA0_DRVALID => '0', + DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED, + DMA1_ACLK => '0', + DMA1_DAREADY => '0', + DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0), + DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED, + DMA1_DRLAST => '0', + DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED, + DMA1_DRTYPE(1 downto 0) => B"00", + DMA1_DRVALID => '0', + DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED, + DMA2_ACLK => '0', + DMA2_DAREADY => '0', + DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0), + DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED, + DMA2_DRLAST => '0', + DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED, + DMA2_DRTYPE(1 downto 0) => B"00", + DMA2_DRVALID => '0', + DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED, + DMA3_ACLK => '0', + DMA3_DAREADY => '0', + DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0), + DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED, + DMA3_DRLAST => '0', + DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED, + DMA3_DRTYPE(1 downto 0) => B"00", + DMA3_DRVALID => '0', + DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED, + ENET0_EXT_INTIN => '0', + ENET0_GMII_COL => '0', + ENET0_GMII_CRS => '0', + ENET0_GMII_RXD(7 downto 0) => B"00000000", + ENET0_GMII_RX_CLK => '0', + ENET0_GMII_RX_DV => '0', + ENET0_GMII_RX_ER => '0', + ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0), + ENET0_GMII_TX_CLK => '0', + ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED, + ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED, + ENET0_MDIO_I => '0', + ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED, + ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED, + ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED, + ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED, + ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED, + ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED, + ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED, + ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED, + ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED, + ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED, + ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED, + ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED, + ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED, + ENET1_EXT_INTIN => '0', + ENET1_GMII_COL => '0', + ENET1_GMII_CRS => '0', + ENET1_GMII_RXD(7 downto 0) => B"00000000", + ENET1_GMII_RX_CLK => '0', + ENET1_GMII_RX_DV => '0', + ENET1_GMII_RX_ER => '0', + ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0), + ENET1_GMII_TX_CLK => '0', + ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED, + ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED, + ENET1_MDIO_I => '0', + ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED, + ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED, + ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED, + ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED, + ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED, + ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED, + ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED, + ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED, + ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED, + ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED, + ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED, + ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED, + ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED, + EVENT_EVENTI => '0', + EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED, + EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0), + EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0), + FCLK_CLK0 => FCLK_CLK0, + FCLK_CLK1 => FCLK_CLK1, + FCLK_CLK2 => FCLK_CLK2, + FCLK_CLK3 => FCLK_CLK3, + FCLK_CLKTRIG0_N => '0', + FCLK_CLKTRIG1_N => '0', + FCLK_CLKTRIG2_N => '0', + FCLK_CLKTRIG3_N => '0', + FCLK_RESET0_N => FCLK_RESET0_N, + FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED, + FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED, + FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED, + FPGA_IDLE_N => '0', + FTMD_TRACEIN_ATID(3 downto 0) => B"0000", + FTMD_TRACEIN_CLK => '0', + FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000", + FTMD_TRACEIN_VALID => '0', + FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000", + FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED, + FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED, + FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED, + FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED, + FTMT_F2P_TRIG_0 => '0', + FTMT_F2P_TRIG_1 => '0', + FTMT_F2P_TRIG_2 => '0', + FTMT_F2P_TRIG_3 => '0', + FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0), + FTMT_P2F_TRIGACK_0 => '0', + FTMT_P2F_TRIGACK_1 => '0', + FTMT_P2F_TRIGACK_2 => '0', + FTMT_P2F_TRIGACK_3 => '0', + FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED, + FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED, + FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED, + FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED, + GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0), + GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0), + I2C0_SCL_I => '0', + I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED, + I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED, + I2C0_SDA_I => '0', + I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED, + I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED, + I2C1_SCL_I => '0', + I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED, + I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED, + I2C1_SDA_I => '0', + I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED, + I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED, + IRQ_F2P(0) => '0', + IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED, + IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED, + IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED, + IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED, + IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED, + IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED, + IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED, + IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED, + IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED, + IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED, + IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED, + IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED, + IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED, + IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED, + IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED, + IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED, + IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED, + IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED, + IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED, + IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED, + IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED, + IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED, + IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED, + IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED, + IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED, + IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED, + IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED, + IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED, + IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED, + MIO(53 downto 0) => MIO(53 downto 0), + M_AXI_GP0_ACLK => M_AXI_GP0_ACLK, + M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0), + M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0), + M_AXI_GP0_ARCACHE(3 downto 2) => \^m_axi_gp0_arcache\(3 downto 2), + M_AXI_GP0_ARCACHE(1) => NLW_inst_M_AXI_GP0_ARCACHE_UNCONNECTED(1), + M_AXI_GP0_ARCACHE(0) => \^m_axi_gp0_arcache\(0), + M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED, + M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0), + M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0), + M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0), + M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0), + M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0), + M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY, + M_AXI_GP0_ARSIZE(2) => NLW_inst_M_AXI_GP0_ARSIZE_UNCONNECTED(2), + M_AXI_GP0_ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0), + M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID, + M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0), + M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0), + M_AXI_GP0_AWCACHE(3 downto 2) => \^m_axi_gp0_awcache\(3 downto 2), + M_AXI_GP0_AWCACHE(1) => NLW_inst_M_AXI_GP0_AWCACHE_UNCONNECTED(1), + M_AXI_GP0_AWCACHE(0) => \^m_axi_gp0_awcache\(0), + M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0), + M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0), + M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0), + M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0), + M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0), + M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY, + M_AXI_GP0_AWSIZE(2) => NLW_inst_M_AXI_GP0_AWSIZE_UNCONNECTED(2), + M_AXI_GP0_AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0), + M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID, + M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0), + M_AXI_GP0_BREADY => M_AXI_GP0_BREADY, + M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0), + M_AXI_GP0_BVALID => M_AXI_GP0_BVALID, + M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0), + M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0), + M_AXI_GP0_RLAST => M_AXI_GP0_RLAST, + M_AXI_GP0_RREADY => M_AXI_GP0_RREADY, + M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0), + M_AXI_GP0_RVALID => M_AXI_GP0_RVALID, + M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0), + M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0), + M_AXI_GP0_WLAST => M_AXI_GP0_WLAST, + M_AXI_GP0_WREADY => M_AXI_GP0_WREADY, + M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0), + M_AXI_GP0_WVALID => M_AXI_GP0_WVALID, + M_AXI_GP1_ACLK => '0', + M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0), + M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0), + M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0), + M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED, + M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0), + M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0), + M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0), + M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0), + M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0), + M_AXI_GP1_ARREADY => '0', + M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0), + M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED, + M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0), + M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0), + M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0), + M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0), + M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0), + M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0), + M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0), + M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0), + M_AXI_GP1_AWREADY => '0', + M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0), + M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED, + M_AXI_GP1_BID(11 downto 0) => B"000000000000", + M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED, + M_AXI_GP1_BRESP(1 downto 0) => B"00", + M_AXI_GP1_BVALID => '0', + M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000", + M_AXI_GP1_RID(11 downto 0) => B"000000000000", + M_AXI_GP1_RLAST => '0', + M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED, + M_AXI_GP1_RRESP(1 downto 0) => B"00", + M_AXI_GP1_RVALID => '0', + M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0), + M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0), + M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED, + M_AXI_GP1_WREADY => '0', + M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0), + M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED, + PJTAG_TCK => '0', + PJTAG_TDI => '0', + PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED, + PJTAG_TMS => '0', + PS_CLK => PS_CLK, + PS_PORB => PS_PORB, + PS_SRSTB => PS_SRSTB, + SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED, + SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0), + SDIO0_CDN => '0', + SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED, + SDIO0_CLK_FB => '0', + SDIO0_CMD_I => '0', + SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED, + SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED, + SDIO0_DATA_I(3 downto 0) => B"0000", + SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0), + SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0), + SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED, + SDIO0_WP => '0', + SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED, + SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0), + SDIO1_CDN => '0', + SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED, + SDIO1_CLK_FB => '0', + SDIO1_CMD_I => '0', + SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED, + SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED, + SDIO1_DATA_I(3 downto 0) => B"0000", + SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0), + SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0), + SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED, + SDIO1_WP => '0', + SPI0_MISO_I => '0', + SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED, + SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED, + SPI0_MOSI_I => '0', + SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED, + SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED, + SPI0_SCLK_I => '0', + SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED, + SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED, + SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED, + SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED, + SPI0_SS_I => '0', + SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED, + SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED, + SPI1_MISO_I => '0', + SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED, + SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED, + SPI1_MOSI_I => '0', + SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED, + SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED, + SPI1_SCLK_I => '0', + SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED, + SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED, + SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED, + SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED, + SPI1_SS_I => '0', + SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED, + SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED, + SRAM_INTIN => '0', + S_AXI_ACP_ACLK => '0', + S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000", + S_AXI_ACP_ARBURST(1 downto 0) => B"00", + S_AXI_ACP_ARCACHE(3 downto 0) => B"0000", + S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED, + S_AXI_ACP_ARID(2 downto 0) => B"000", + S_AXI_ACP_ARLEN(3 downto 0) => B"0000", + S_AXI_ACP_ARLOCK(1 downto 0) => B"00", + S_AXI_ACP_ARPROT(2 downto 0) => B"000", + S_AXI_ACP_ARQOS(3 downto 0) => B"0000", + S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED, + S_AXI_ACP_ARSIZE(2 downto 0) => B"000", + S_AXI_ACP_ARUSER(4 downto 0) => B"00000", + S_AXI_ACP_ARVALID => '0', + S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000", + S_AXI_ACP_AWBURST(1 downto 0) => B"00", + S_AXI_ACP_AWCACHE(3 downto 0) => B"0000", + S_AXI_ACP_AWID(2 downto 0) => B"000", + S_AXI_ACP_AWLEN(3 downto 0) => B"0000", + S_AXI_ACP_AWLOCK(1 downto 0) => B"00", + S_AXI_ACP_AWPROT(2 downto 0) => B"000", + S_AXI_ACP_AWQOS(3 downto 0) => B"0000", + S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED, + S_AXI_ACP_AWSIZE(2 downto 0) => B"000", + S_AXI_ACP_AWUSER(4 downto 0) => B"00000", + S_AXI_ACP_AWVALID => '0', + S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0), + S_AXI_ACP_BREADY => '0', + S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0), + S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED, + S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0), + S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0), + S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED, + S_AXI_ACP_RREADY => '0', + S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0), + S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED, + S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + S_AXI_ACP_WID(2 downto 0) => B"000", + S_AXI_ACP_WLAST => '0', + S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED, + S_AXI_ACP_WSTRB(7 downto 0) => B"00000000", + S_AXI_ACP_WVALID => '0', + S_AXI_GP0_ACLK => '0', + S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000", + S_AXI_GP0_ARBURST(1 downto 0) => B"00", + S_AXI_GP0_ARCACHE(3 downto 0) => B"0000", + S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED, + S_AXI_GP0_ARID(5 downto 0) => B"000000", + S_AXI_GP0_ARLEN(3 downto 0) => B"0000", + S_AXI_GP0_ARLOCK(1 downto 0) => B"00", + S_AXI_GP0_ARPROT(2 downto 0) => B"000", + S_AXI_GP0_ARQOS(3 downto 0) => B"0000", + S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED, + S_AXI_GP0_ARSIZE(2 downto 0) => B"000", + S_AXI_GP0_ARVALID => '0', + S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000", + S_AXI_GP0_AWBURST(1 downto 0) => B"00", + S_AXI_GP0_AWCACHE(3 downto 0) => B"0000", + S_AXI_GP0_AWID(5 downto 0) => B"000000", + S_AXI_GP0_AWLEN(3 downto 0) => B"0000", + S_AXI_GP0_AWLOCK(1 downto 0) => B"00", + S_AXI_GP0_AWPROT(2 downto 0) => B"000", + S_AXI_GP0_AWQOS(3 downto 0) => B"0000", + S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED, + S_AXI_GP0_AWSIZE(2 downto 0) => B"000", + S_AXI_GP0_AWVALID => '0', + S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0), + S_AXI_GP0_BREADY => '0', + S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0), + S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED, + S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0), + S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0), + S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED, + S_AXI_GP0_RREADY => '0', + S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0), + S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED, + S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000", + S_AXI_GP0_WID(5 downto 0) => B"000000", + S_AXI_GP0_WLAST => '0', + S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED, + S_AXI_GP0_WSTRB(3 downto 0) => B"0000", + S_AXI_GP0_WVALID => '0', + S_AXI_GP1_ACLK => '0', + S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000", + S_AXI_GP1_ARBURST(1 downto 0) => B"00", + S_AXI_GP1_ARCACHE(3 downto 0) => B"0000", + S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED, + S_AXI_GP1_ARID(5 downto 0) => B"000000", + S_AXI_GP1_ARLEN(3 downto 0) => B"0000", + S_AXI_GP1_ARLOCK(1 downto 0) => B"00", + S_AXI_GP1_ARPROT(2 downto 0) => B"000", + S_AXI_GP1_ARQOS(3 downto 0) => B"0000", + S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED, + S_AXI_GP1_ARSIZE(2 downto 0) => B"000", + S_AXI_GP1_ARVALID => '0', + S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000", + S_AXI_GP1_AWBURST(1 downto 0) => B"00", + S_AXI_GP1_AWCACHE(3 downto 0) => B"0000", + S_AXI_GP1_AWID(5 downto 0) => B"000000", + S_AXI_GP1_AWLEN(3 downto 0) => B"0000", + S_AXI_GP1_AWLOCK(1 downto 0) => B"00", + S_AXI_GP1_AWPROT(2 downto 0) => B"000", + S_AXI_GP1_AWQOS(3 downto 0) => B"0000", + S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED, + S_AXI_GP1_AWSIZE(2 downto 0) => B"000", + S_AXI_GP1_AWVALID => '0', + S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0), + S_AXI_GP1_BREADY => '0', + S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0), + S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED, + S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0), + S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0), + S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED, + S_AXI_GP1_RREADY => '0', + S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0), + S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED, + S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000", + S_AXI_GP1_WID(5 downto 0) => B"000000", + S_AXI_GP1_WLAST => '0', + S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED, + S_AXI_GP1_WSTRB(3 downto 0) => B"0000", + S_AXI_GP1_WVALID => '0', + S_AXI_HP0_ACLK => '0', + S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000", + S_AXI_HP0_ARBURST(1 downto 0) => B"00", + S_AXI_HP0_ARCACHE(3 downto 0) => B"0000", + S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED, + S_AXI_HP0_ARID(5 downto 0) => B"000000", + S_AXI_HP0_ARLEN(3 downto 0) => B"0000", + S_AXI_HP0_ARLOCK(1 downto 0) => B"00", + S_AXI_HP0_ARPROT(2 downto 0) => B"000", + S_AXI_HP0_ARQOS(3 downto 0) => B"0000", + S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED, + S_AXI_HP0_ARSIZE(2 downto 0) => B"000", + S_AXI_HP0_ARVALID => '0', + S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000", + S_AXI_HP0_AWBURST(1 downto 0) => B"00", + S_AXI_HP0_AWCACHE(3 downto 0) => B"0000", + S_AXI_HP0_AWID(5 downto 0) => B"000000", + S_AXI_HP0_AWLEN(3 downto 0) => B"0000", + S_AXI_HP0_AWLOCK(1 downto 0) => B"00", + S_AXI_HP0_AWPROT(2 downto 0) => B"000", + S_AXI_HP0_AWQOS(3 downto 0) => B"0000", + S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED, + S_AXI_HP0_AWSIZE(2 downto 0) => B"000", + S_AXI_HP0_AWVALID => '0', + S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0), + S_AXI_HP0_BREADY => '0', + S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0), + S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED, + S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0), + S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0), + S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0), + S_AXI_HP0_RDISSUECAP1_EN => '0', + S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0), + S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED, + S_AXI_HP0_RREADY => '0', + S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0), + S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED, + S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0), + S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0), + S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + S_AXI_HP0_WID(5 downto 0) => B"000000", + S_AXI_HP0_WLAST => '0', + S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED, + S_AXI_HP0_WRISSUECAP1_EN => '0', + S_AXI_HP0_WSTRB(7 downto 0) => B"00000000", + S_AXI_HP0_WVALID => '0', + S_AXI_HP1_ACLK => '0', + S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000", + S_AXI_HP1_ARBURST(1 downto 0) => B"00", + S_AXI_HP1_ARCACHE(3 downto 0) => B"0000", + S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED, + S_AXI_HP1_ARID(5 downto 0) => B"000000", + S_AXI_HP1_ARLEN(3 downto 0) => B"0000", + S_AXI_HP1_ARLOCK(1 downto 0) => B"00", + S_AXI_HP1_ARPROT(2 downto 0) => B"000", + S_AXI_HP1_ARQOS(3 downto 0) => B"0000", + S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED, + S_AXI_HP1_ARSIZE(2 downto 0) => B"000", + S_AXI_HP1_ARVALID => '0', + S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000", + S_AXI_HP1_AWBURST(1 downto 0) => B"00", + S_AXI_HP1_AWCACHE(3 downto 0) => B"0000", + S_AXI_HP1_AWID(5 downto 0) => B"000000", + S_AXI_HP1_AWLEN(3 downto 0) => B"0000", + S_AXI_HP1_AWLOCK(1 downto 0) => B"00", + S_AXI_HP1_AWPROT(2 downto 0) => B"000", + S_AXI_HP1_AWQOS(3 downto 0) => B"0000", + S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED, + S_AXI_HP1_AWSIZE(2 downto 0) => B"000", + S_AXI_HP1_AWVALID => '0', + S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0), + S_AXI_HP1_BREADY => '0', + S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0), + S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED, + S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0), + S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0), + S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0), + S_AXI_HP1_RDISSUECAP1_EN => '0', + S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0), + S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED, + S_AXI_HP1_RREADY => '0', + S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0), + S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED, + S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0), + S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0), + S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + S_AXI_HP1_WID(5 downto 0) => B"000000", + S_AXI_HP1_WLAST => '0', + S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED, + S_AXI_HP1_WRISSUECAP1_EN => '0', + S_AXI_HP1_WSTRB(7 downto 0) => B"00000000", + S_AXI_HP1_WVALID => '0', + S_AXI_HP2_ACLK => '0', + S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000", + S_AXI_HP2_ARBURST(1 downto 0) => B"00", + S_AXI_HP2_ARCACHE(3 downto 0) => B"0000", + S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED, + S_AXI_HP2_ARID(5 downto 0) => B"000000", + S_AXI_HP2_ARLEN(3 downto 0) => B"0000", + S_AXI_HP2_ARLOCK(1 downto 0) => B"00", + S_AXI_HP2_ARPROT(2 downto 0) => B"000", + S_AXI_HP2_ARQOS(3 downto 0) => B"0000", + S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED, + S_AXI_HP2_ARSIZE(2 downto 0) => B"000", + S_AXI_HP2_ARVALID => '0', + S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000", + S_AXI_HP2_AWBURST(1 downto 0) => B"00", + S_AXI_HP2_AWCACHE(3 downto 0) => B"0000", + S_AXI_HP2_AWID(5 downto 0) => B"000000", + S_AXI_HP2_AWLEN(3 downto 0) => B"0000", + S_AXI_HP2_AWLOCK(1 downto 0) => B"00", + S_AXI_HP2_AWPROT(2 downto 0) => B"000", + S_AXI_HP2_AWQOS(3 downto 0) => B"0000", + S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED, + S_AXI_HP2_AWSIZE(2 downto 0) => B"000", + S_AXI_HP2_AWVALID => '0', + S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0), + S_AXI_HP2_BREADY => '0', + S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0), + S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED, + S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0), + S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0), + S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0), + S_AXI_HP2_RDISSUECAP1_EN => '0', + S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0), + S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED, + S_AXI_HP2_RREADY => '0', + S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0), + S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED, + S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0), + S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0), + S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + S_AXI_HP2_WID(5 downto 0) => B"000000", + S_AXI_HP2_WLAST => '0', + S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED, + S_AXI_HP2_WRISSUECAP1_EN => '0', + S_AXI_HP2_WSTRB(7 downto 0) => B"00000000", + S_AXI_HP2_WVALID => '0', + S_AXI_HP3_ACLK => '0', + S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000", + S_AXI_HP3_ARBURST(1 downto 0) => B"00", + S_AXI_HP3_ARCACHE(3 downto 0) => B"0000", + S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED, + S_AXI_HP3_ARID(5 downto 0) => B"000000", + S_AXI_HP3_ARLEN(3 downto 0) => B"0000", + S_AXI_HP3_ARLOCK(1 downto 0) => B"00", + S_AXI_HP3_ARPROT(2 downto 0) => B"000", + S_AXI_HP3_ARQOS(3 downto 0) => B"0000", + S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED, + S_AXI_HP3_ARSIZE(2 downto 0) => B"000", + S_AXI_HP3_ARVALID => '0', + S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000", + S_AXI_HP3_AWBURST(1 downto 0) => B"00", + S_AXI_HP3_AWCACHE(3 downto 0) => B"0000", + S_AXI_HP3_AWID(5 downto 0) => B"000000", + S_AXI_HP3_AWLEN(3 downto 0) => B"0000", + S_AXI_HP3_AWLOCK(1 downto 0) => B"00", + S_AXI_HP3_AWPROT(2 downto 0) => B"000", + S_AXI_HP3_AWQOS(3 downto 0) => B"0000", + S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED, + S_AXI_HP3_AWSIZE(2 downto 0) => B"000", + S_AXI_HP3_AWVALID => '0', + S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0), + S_AXI_HP3_BREADY => '0', + S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0), + S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED, + S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0), + S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0), + S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0), + S_AXI_HP3_RDISSUECAP1_EN => '0', + S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0), + S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED, + S_AXI_HP3_RREADY => '0', + S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0), + S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED, + S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0), + S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0), + S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + S_AXI_HP3_WID(5 downto 0) => B"000000", + S_AXI_HP3_WLAST => '0', + S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED, + S_AXI_HP3_WRISSUECAP1_EN => '0', + S_AXI_HP3_WSTRB(7 downto 0) => B"00000000", + S_AXI_HP3_WVALID => '0', + TRACE_CLK => '0', + TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED, + TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED, + TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0), + TTC0_CLK0_IN => '0', + TTC0_CLK1_IN => '0', + TTC0_CLK2_IN => '0', + TTC0_WAVE0_OUT => NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED, + TTC0_WAVE1_OUT => NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED, + TTC0_WAVE2_OUT => NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED, + TTC1_CLK0_IN => '0', + TTC1_CLK1_IN => '0', + TTC1_CLK2_IN => '0', + TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED, + TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED, + TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED, + UART0_CTSN => '0', + UART0_DCDN => '0', + UART0_DSRN => '0', + UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED, + UART0_RIN => '0', + UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED, + UART0_RX => '1', + UART0_TX => NLW_inst_UART0_TX_UNCONNECTED, + UART1_CTSN => '0', + UART1_DCDN => '0', + UART1_DSRN => '0', + UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED, + UART1_RIN => '0', + UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED, + UART1_RX => '1', + UART1_TX => NLW_inst_UART1_TX_UNCONNECTED, + USB0_PORT_INDCTL(1 downto 0) => NLW_inst_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0), + USB0_VBUS_PWRFAULT => '0', + USB0_VBUS_PWRSELECT => NLW_inst_USB0_VBUS_PWRSELECT_UNCONNECTED, + USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0), + USB1_VBUS_PWRFAULT => '0', + USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED, + WDT_CLK_IN => '0', + WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED + ); +end STRUCTURE; diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/sim/NewExtInst_TOP_processing_system7_0_0.v b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/sim/NewExtInst_TOP_processing_system7_0_0.v new file mode 100644 index 0000000..cf55cc1 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/sim/NewExtInst_TOP_processing_system7_0_0.v @@ -0,0 +1,584 @@ + + + +// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0 +// IP Revision: 1 + +`timescale 1ns/1ps + +module NewExtInst_TOP_processing_system7_0_0 ( +M_AXI_GP0_ARVALID, +M_AXI_GP0_AWVALID, +M_AXI_GP0_BREADY, +M_AXI_GP0_RREADY, +M_AXI_GP0_WLAST, +M_AXI_GP0_WVALID, +M_AXI_GP0_ARID, +M_AXI_GP0_AWID, +M_AXI_GP0_WID, +M_AXI_GP0_ARBURST, +M_AXI_GP0_ARLOCK, +M_AXI_GP0_ARSIZE, +M_AXI_GP0_AWBURST, +M_AXI_GP0_AWLOCK, +M_AXI_GP0_AWSIZE, +M_AXI_GP0_ARPROT, +M_AXI_GP0_AWPROT, +M_AXI_GP0_ARADDR, +M_AXI_GP0_AWADDR, +M_AXI_GP0_WDATA, +M_AXI_GP0_ARCACHE, +M_AXI_GP0_ARLEN, +M_AXI_GP0_ARQOS, +M_AXI_GP0_AWCACHE, +M_AXI_GP0_AWLEN, +M_AXI_GP0_AWQOS, +M_AXI_GP0_WSTRB, +M_AXI_GP0_ACLK, +M_AXI_GP0_ARREADY, +M_AXI_GP0_AWREADY, +M_AXI_GP0_BVALID, +M_AXI_GP0_RLAST, +M_AXI_GP0_RVALID, +M_AXI_GP0_WREADY, +M_AXI_GP0_BID, +M_AXI_GP0_RID, +M_AXI_GP0_BRESP, +M_AXI_GP0_RRESP, +M_AXI_GP0_RDATA, +FCLK_CLK0, +FCLK_CLK1, +FCLK_CLK2, +FCLK_CLK3, +FCLK_RESET0_N, +MIO, +DDR_CAS_n, +DDR_CKE, +DDR_Clk_n, +DDR_Clk, +DDR_CS_n, +DDR_DRSTB, +DDR_ODT, +DDR_RAS_n, +DDR_WEB, +DDR_BankAddr, +DDR_Addr, +DDR_VRN, +DDR_VRP, +DDR_DM, +DDR_DQ, +DDR_DQS_n, +DDR_DQS, +PS_SRSTB, +PS_CLK, +PS_PORB +); +output M_AXI_GP0_ARVALID; +output M_AXI_GP0_AWVALID; +output M_AXI_GP0_BREADY; +output M_AXI_GP0_RREADY; +output M_AXI_GP0_WLAST; +output M_AXI_GP0_WVALID; +output [11 : 0] M_AXI_GP0_ARID; +output [11 : 0] M_AXI_GP0_AWID; +output [11 : 0] M_AXI_GP0_WID; +output [1 : 0] M_AXI_GP0_ARBURST; +output [1 : 0] M_AXI_GP0_ARLOCK; +output [2 : 0] M_AXI_GP0_ARSIZE; +output [1 : 0] M_AXI_GP0_AWBURST; +output [1 : 0] M_AXI_GP0_AWLOCK; +output [2 : 0] M_AXI_GP0_AWSIZE; +output [2 : 0] M_AXI_GP0_ARPROT; +output [2 : 0] M_AXI_GP0_AWPROT; +output [31 : 0] M_AXI_GP0_ARADDR; +output [31 : 0] M_AXI_GP0_AWADDR; +output [31 : 0] M_AXI_GP0_WDATA; +output [3 : 0] M_AXI_GP0_ARCACHE; +output [3 : 0] M_AXI_GP0_ARLEN; +output [3 : 0] M_AXI_GP0_ARQOS; +output [3 : 0] M_AXI_GP0_AWCACHE; +output [3 : 0] M_AXI_GP0_AWLEN; +output [3 : 0] M_AXI_GP0_AWQOS; +output [3 : 0] M_AXI_GP0_WSTRB; +input M_AXI_GP0_ACLK; +input M_AXI_GP0_ARREADY; +input M_AXI_GP0_AWREADY; +input M_AXI_GP0_BVALID; +input M_AXI_GP0_RLAST; +input M_AXI_GP0_RVALID; +input M_AXI_GP0_WREADY; +input [11 : 0] M_AXI_GP0_BID; +input [11 : 0] M_AXI_GP0_RID; +input [1 : 0] M_AXI_GP0_BRESP; +input [1 : 0] M_AXI_GP0_RRESP; +input [31 : 0] M_AXI_GP0_RDATA; +output FCLK_CLK0; +output FCLK_CLK1; +output FCLK_CLK2; +output FCLK_CLK3; +output FCLK_RESET0_N; +input [53 : 0] MIO; +input DDR_CAS_n; +input DDR_CKE; +input DDR_Clk_n; +input DDR_Clk; +input DDR_CS_n; +input DDR_DRSTB; +input DDR_ODT; +input DDR_RAS_n; +input DDR_WEB; +input [2 : 0] DDR_BankAddr; +input [14 : 0] DDR_Addr; +input DDR_VRN; +input DDR_VRP; +input [3 : 0] DDR_DM; +input [31 : 0] DDR_DQ; +input [3 : 0] DDR_DQS_n; +input [3 : 0] DDR_DQS; +input PS_SRSTB; +input PS_CLK; +input PS_PORB; + + processing_system7_vip_v1_0_17 #( + .C_USE_M_AXI_GP0(1), + .C_USE_M_AXI_GP1(0), + .C_USE_S_AXI_ACP(0), + .C_USE_S_AXI_GP0(0), + .C_USE_S_AXI_GP1(0), + .C_USE_S_AXI_HP0(0), + .C_USE_S_AXI_HP1(0), + .C_USE_S_AXI_HP2(0), + .C_USE_S_AXI_HP3(0), + .C_S_AXI_HP0_DATA_WIDTH(64), + .C_S_AXI_HP1_DATA_WIDTH(64), + .C_S_AXI_HP2_DATA_WIDTH(64), + .C_S_AXI_HP3_DATA_WIDTH(64), + .C_HIGH_OCM_EN(0), + .C_FCLK_CLK0_FREQ(25.0), + .C_FCLK_CLK1_FREQ(50.0), + .C_FCLK_CLK2_FREQ(100.0), + .C_FCLK_CLK3_FREQ(200.0), + .C_M_AXI_GP0_ENABLE_STATIC_REMAP(0), + .C_M_AXI_GP1_ENABLE_STATIC_REMAP(0), + .C_M_AXI_GP0_THREAD_ID_WIDTH (12), + .C_M_AXI_GP1_THREAD_ID_WIDTH (12) + ) inst ( + .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID), + .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID), + .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY), + .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY), + .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST), + .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID), + .M_AXI_GP0_ARID(M_AXI_GP0_ARID), + .M_AXI_GP0_AWID(M_AXI_GP0_AWID), + .M_AXI_GP0_WID(M_AXI_GP0_WID), + .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST), + .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK), + .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE), + .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST), + .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK), + .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE), + .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT), + .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT), + .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR), + .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR), + .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA), + .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE), + .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN), + .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS), + .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE), + .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN), + .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS), + .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB), + .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK), + .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY), + .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY), + .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID), + .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST), + .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID), + .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY), + .M_AXI_GP0_BID(M_AXI_GP0_BID), + .M_AXI_GP0_RID(M_AXI_GP0_RID), + .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP), + .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP), + .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA), + .M_AXI_GP1_ARVALID(), + .M_AXI_GP1_AWVALID(), + .M_AXI_GP1_BREADY(), + .M_AXI_GP1_RREADY(), + .M_AXI_GP1_WLAST(), + .M_AXI_GP1_WVALID(), + .M_AXI_GP1_ARID(), + .M_AXI_GP1_AWID(), + .M_AXI_GP1_WID(), + .M_AXI_GP1_ARBURST(), + .M_AXI_GP1_ARLOCK(), + .M_AXI_GP1_ARSIZE(), + .M_AXI_GP1_AWBURST(), + .M_AXI_GP1_AWLOCK(), + .M_AXI_GP1_AWSIZE(), + .M_AXI_GP1_ARPROT(), + .M_AXI_GP1_AWPROT(), + .M_AXI_GP1_ARADDR(), + .M_AXI_GP1_AWADDR(), + .M_AXI_GP1_WDATA(), + .M_AXI_GP1_ARCACHE(), + .M_AXI_GP1_ARLEN(), + .M_AXI_GP1_ARQOS(), + .M_AXI_GP1_AWCACHE(), + .M_AXI_GP1_AWLEN(), + .M_AXI_GP1_AWQOS(), + .M_AXI_GP1_WSTRB(), + .M_AXI_GP1_ACLK(1'B0), + .M_AXI_GP1_ARREADY(1'B0), + .M_AXI_GP1_AWREADY(1'B0), + .M_AXI_GP1_BVALID(1'B0), + .M_AXI_GP1_RLAST(1'B0), + .M_AXI_GP1_RVALID(1'B0), + .M_AXI_GP1_WREADY(1'B0), + .M_AXI_GP1_BID(12'B0), + .M_AXI_GP1_RID(12'B0), + .M_AXI_GP1_BRESP(2'B0), + .M_AXI_GP1_RRESP(2'B0), + .M_AXI_GP1_RDATA(32'B0), + .S_AXI_GP0_ARREADY(), + .S_AXI_GP0_AWREADY(), + .S_AXI_GP0_BVALID(), + .S_AXI_GP0_RLAST(), + .S_AXI_GP0_RVALID(), + .S_AXI_GP0_WREADY(), + .S_AXI_GP0_BRESP(), + .S_AXI_GP0_RRESP(), + .S_AXI_GP0_RDATA(), + .S_AXI_GP0_BID(), + .S_AXI_GP0_RID(), + .S_AXI_GP0_ACLK(1'B0), + .S_AXI_GP0_ARVALID(1'B0), + .S_AXI_GP0_AWVALID(1'B0), + .S_AXI_GP0_BREADY(1'B0), + .S_AXI_GP0_RREADY(1'B0), + .S_AXI_GP0_WLAST(1'B0), + .S_AXI_GP0_WVALID(1'B0), + .S_AXI_GP0_ARBURST(2'B0), + .S_AXI_GP0_ARLOCK(2'B0), + .S_AXI_GP0_ARSIZE(3'B0), + .S_AXI_GP0_AWBURST(2'B0), + .S_AXI_GP0_AWLOCK(2'B0), + .S_AXI_GP0_AWSIZE(3'B0), + .S_AXI_GP0_ARPROT(3'B0), + .S_AXI_GP0_AWPROT(3'B0), + .S_AXI_GP0_ARADDR(32'B0), + .S_AXI_GP0_AWADDR(32'B0), + .S_AXI_GP0_WDATA(32'B0), + .S_AXI_GP0_ARCACHE(4'B0), + .S_AXI_GP0_ARLEN(4'B0), + .S_AXI_GP0_ARQOS(4'B0), + .S_AXI_GP0_AWCACHE(4'B0), + .S_AXI_GP0_AWLEN(4'B0), + .S_AXI_GP0_AWQOS(4'B0), + .S_AXI_GP0_WSTRB(4'B0), + .S_AXI_GP0_ARID(6'B0), + .S_AXI_GP0_AWID(6'B0), + .S_AXI_GP0_WID(6'B0), + .S_AXI_GP1_ARREADY(), + .S_AXI_GP1_AWREADY(), + .S_AXI_GP1_BVALID(), + .S_AXI_GP1_RLAST(), + .S_AXI_GP1_RVALID(), + .S_AXI_GP1_WREADY(), + .S_AXI_GP1_BRESP(), + .S_AXI_GP1_RRESP(), + .S_AXI_GP1_RDATA(), + .S_AXI_GP1_BID(), + .S_AXI_GP1_RID(), + .S_AXI_GP1_ACLK(1'B0), + .S_AXI_GP1_ARVALID(1'B0), + .S_AXI_GP1_AWVALID(1'B0), + .S_AXI_GP1_BREADY(1'B0), + .S_AXI_GP1_RREADY(1'B0), + .S_AXI_GP1_WLAST(1'B0), + .S_AXI_GP1_WVALID(1'B0), + .S_AXI_GP1_ARBURST(2'B0), + .S_AXI_GP1_ARLOCK(2'B0), + .S_AXI_GP1_ARSIZE(3'B0), + .S_AXI_GP1_AWBURST(2'B0), + .S_AXI_GP1_AWLOCK(2'B0), + .S_AXI_GP1_AWSIZE(3'B0), + .S_AXI_GP1_ARPROT(3'B0), + .S_AXI_GP1_AWPROT(3'B0), + .S_AXI_GP1_ARADDR(32'B0), + .S_AXI_GP1_AWADDR(32'B0), + .S_AXI_GP1_WDATA(32'B0), + .S_AXI_GP1_ARCACHE(4'B0), + .S_AXI_GP1_ARLEN(4'B0), + .S_AXI_GP1_ARQOS(4'B0), + .S_AXI_GP1_AWCACHE(4'B0), + .S_AXI_GP1_AWLEN(4'B0), + .S_AXI_GP1_AWQOS(4'B0), + .S_AXI_GP1_WSTRB(4'B0), + .S_AXI_GP1_ARID(6'B0), + .S_AXI_GP1_AWID(6'B0), + .S_AXI_GP1_WID(6'B0), + .S_AXI_ACP_ARREADY(), + .S_AXI_ACP_AWREADY(), + .S_AXI_ACP_BVALID(), + .S_AXI_ACP_RLAST(), + .S_AXI_ACP_RVALID(), + .S_AXI_ACP_WREADY(), + .S_AXI_ACP_BRESP(), + .S_AXI_ACP_RRESP(), + .S_AXI_ACP_BID(), + .S_AXI_ACP_RID(), + .S_AXI_ACP_RDATA(), + .S_AXI_ACP_ACLK(1'B0), + .S_AXI_ACP_ARVALID(1'B0), + .S_AXI_ACP_AWVALID(1'B0), + .S_AXI_ACP_BREADY(1'B0), + .S_AXI_ACP_RREADY(1'B0), + .S_AXI_ACP_WLAST(1'B0), + .S_AXI_ACP_WVALID(1'B0), + .S_AXI_ACP_ARID(3'B0), + .S_AXI_ACP_ARPROT(3'B0), + .S_AXI_ACP_AWID(3'B0), + .S_AXI_ACP_AWPROT(3'B0), + .S_AXI_ACP_WID(3'B0), + .S_AXI_ACP_ARADDR(32'B0), + .S_AXI_ACP_AWADDR(32'B0), + .S_AXI_ACP_ARCACHE(4'B0), + .S_AXI_ACP_ARLEN(4'B0), + .S_AXI_ACP_ARQOS(4'B0), + .S_AXI_ACP_AWCACHE(4'B0), + .S_AXI_ACP_AWLEN(4'B0), + .S_AXI_ACP_AWQOS(4'B0), + .S_AXI_ACP_ARBURST(2'B0), + .S_AXI_ACP_ARLOCK(2'B0), + .S_AXI_ACP_ARSIZE(3'B0), + .S_AXI_ACP_AWBURST(2'B0), + .S_AXI_ACP_AWLOCK(2'B0), + .S_AXI_ACP_AWSIZE(3'B0), + .S_AXI_ACP_ARUSER(5'B0), + .S_AXI_ACP_AWUSER(5'B0), + .S_AXI_ACP_WDATA(64'B0), + .S_AXI_ACP_WSTRB(8'B0), + .S_AXI_HP0_ARREADY(), + .S_AXI_HP0_AWREADY(), + .S_AXI_HP0_BVALID(), + .S_AXI_HP0_RLAST(), + .S_AXI_HP0_RVALID(), + .S_AXI_HP0_WREADY(), + .S_AXI_HP0_BRESP(), + .S_AXI_HP0_RRESP(), + .S_AXI_HP0_BID(), + .S_AXI_HP0_RID(), + .S_AXI_HP0_RDATA(), + .S_AXI_HP0_ACLK(1'B0), + .S_AXI_HP0_ARVALID(1'B0), + .S_AXI_HP0_AWVALID(1'B0), + .S_AXI_HP0_BREADY(1'B0), + .S_AXI_HP0_RREADY(1'B0), + .S_AXI_HP0_WLAST(1'B0), + .S_AXI_HP0_WVALID(1'B0), + .S_AXI_HP0_ARBURST(2'B0), + .S_AXI_HP0_ARLOCK(2'B0), + .S_AXI_HP0_ARSIZE(3'B0), + .S_AXI_HP0_AWBURST(2'B0), + .S_AXI_HP0_AWLOCK(2'B0), + .S_AXI_HP0_AWSIZE(3'B0), + .S_AXI_HP0_ARPROT(3'B0), + .S_AXI_HP0_AWPROT(3'B0), + .S_AXI_HP0_ARADDR(32'B0), + .S_AXI_HP0_AWADDR(32'B0), + .S_AXI_HP0_ARCACHE(4'B0), + .S_AXI_HP0_ARLEN(4'B0), + .S_AXI_HP0_ARQOS(4'B0), + .S_AXI_HP0_AWCACHE(4'B0), + .S_AXI_HP0_AWLEN(4'B0), + .S_AXI_HP0_AWQOS(4'B0), + .S_AXI_HP0_ARID(6'B0), + .S_AXI_HP0_AWID(6'B0), + .S_AXI_HP0_WID(6'B0), + .S_AXI_HP0_WDATA(64'B0), + .S_AXI_HP0_WSTRB(8'B0), + .S_AXI_HP1_ARREADY(), + .S_AXI_HP1_AWREADY(), + .S_AXI_HP1_BVALID(), + .S_AXI_HP1_RLAST(), + .S_AXI_HP1_RVALID(), + .S_AXI_HP1_WREADY(), + .S_AXI_HP1_BRESP(), + .S_AXI_HP1_RRESP(), + .S_AXI_HP1_BID(), + .S_AXI_HP1_RID(), + .S_AXI_HP1_RDATA(), + .S_AXI_HP1_ACLK(1'B0), + .S_AXI_HP1_ARVALID(1'B0), + .S_AXI_HP1_AWVALID(1'B0), + .S_AXI_HP1_BREADY(1'B0), + .S_AXI_HP1_RREADY(1'B0), + .S_AXI_HP1_WLAST(1'B0), + .S_AXI_HP1_WVALID(1'B0), + .S_AXI_HP1_ARBURST(2'B0), + .S_AXI_HP1_ARLOCK(2'B0), + .S_AXI_HP1_ARSIZE(3'B0), + .S_AXI_HP1_AWBURST(2'B0), + .S_AXI_HP1_AWLOCK(2'B0), + .S_AXI_HP1_AWSIZE(3'B0), + .S_AXI_HP1_ARPROT(3'B0), + .S_AXI_HP1_AWPROT(3'B0), + .S_AXI_HP1_ARADDR(32'B0), + .S_AXI_HP1_AWADDR(32'B0), + .S_AXI_HP1_ARCACHE(4'B0), + .S_AXI_HP1_ARLEN(4'B0), + .S_AXI_HP1_ARQOS(4'B0), + .S_AXI_HP1_AWCACHE(4'B0), + .S_AXI_HP1_AWLEN(4'B0), + .S_AXI_HP1_AWQOS(4'B0), + .S_AXI_HP1_ARID(6'B0), + .S_AXI_HP1_AWID(6'B0), + .S_AXI_HP1_WID(6'B0), + .S_AXI_HP1_WDATA(64'B0), + .S_AXI_HP1_WSTRB(8'B0), + .S_AXI_HP2_ARREADY(), + .S_AXI_HP2_AWREADY(), + .S_AXI_HP2_BVALID(), + .S_AXI_HP2_RLAST(), + .S_AXI_HP2_RVALID(), + .S_AXI_HP2_WREADY(), + .S_AXI_HP2_BRESP(), + .S_AXI_HP2_RRESP(), + .S_AXI_HP2_BID(), + .S_AXI_HP2_RID(), + .S_AXI_HP2_RDATA(), + .S_AXI_HP2_ACLK(1'B0), + .S_AXI_HP2_ARVALID(1'B0), + .S_AXI_HP2_AWVALID(1'B0), + .S_AXI_HP2_BREADY(1'B0), + .S_AXI_HP2_RREADY(1'B0), + .S_AXI_HP2_WLAST(1'B0), + .S_AXI_HP2_WVALID(1'B0), + .S_AXI_HP2_ARBURST(2'B0), + .S_AXI_HP2_ARLOCK(2'B0), + .S_AXI_HP2_ARSIZE(3'B0), + .S_AXI_HP2_AWBURST(2'B0), + .S_AXI_HP2_AWLOCK(2'B0), + .S_AXI_HP2_AWSIZE(3'B0), + .S_AXI_HP2_ARPROT(3'B0), + .S_AXI_HP2_AWPROT(3'B0), + .S_AXI_HP2_ARADDR(32'B0), + .S_AXI_HP2_AWADDR(32'B0), + .S_AXI_HP2_ARCACHE(4'B0), + .S_AXI_HP2_ARLEN(4'B0), + .S_AXI_HP2_ARQOS(4'B0), + .S_AXI_HP2_AWCACHE(4'B0), + .S_AXI_HP2_AWLEN(4'B0), + .S_AXI_HP2_AWQOS(4'B0), + .S_AXI_HP2_ARID(6'B0), + .S_AXI_HP2_AWID(6'B0), + .S_AXI_HP2_WID(6'B0), + .S_AXI_HP2_WDATA(64'B0), + .S_AXI_HP2_WSTRB(8'B0), + .S_AXI_HP3_ARREADY(), + .S_AXI_HP3_AWREADY(), + .S_AXI_HP3_BVALID(), + .S_AXI_HP3_RLAST(), + .S_AXI_HP3_RVALID(), + .S_AXI_HP3_WREADY(), + .S_AXI_HP3_BRESP(), + .S_AXI_HP3_RRESP(), + .S_AXI_HP3_BID(), + .S_AXI_HP3_RID(), + .S_AXI_HP3_RDATA(), + .S_AXI_HP3_ACLK(1'B0), + .S_AXI_HP3_ARVALID(1'B0), + .S_AXI_HP3_AWVALID(1'B0), + .S_AXI_HP3_BREADY(1'B0), + .S_AXI_HP3_RREADY(1'B0), + .S_AXI_HP3_WLAST(1'B0), + .S_AXI_HP3_WVALID(1'B0), + .S_AXI_HP3_ARBURST(2'B0), + .S_AXI_HP3_ARLOCK(2'B0), + .S_AXI_HP3_ARSIZE(3'B0), + .S_AXI_HP3_AWBURST(2'B0), + .S_AXI_HP3_AWLOCK(2'B0), + .S_AXI_HP3_AWSIZE(3'B0), + .S_AXI_HP3_ARPROT(3'B0), + .S_AXI_HP3_AWPROT(3'B0), + .S_AXI_HP3_ARADDR(32'B0), + .S_AXI_HP3_AWADDR(32'B0), + .S_AXI_HP3_ARCACHE(4'B0), + .S_AXI_HP3_ARLEN(4'B0), + .S_AXI_HP3_ARQOS(4'B0), + .S_AXI_HP3_AWCACHE(4'B0), + .S_AXI_HP3_AWLEN(4'B0), + .S_AXI_HP3_AWQOS(4'B0), + .S_AXI_HP3_ARID(6'B0), + .S_AXI_HP3_AWID(6'B0), + .S_AXI_HP3_WID(6'B0), + .S_AXI_HP3_WDATA(64'B0), + .S_AXI_HP3_WSTRB(8'B0), + .FCLK_CLK0(FCLK_CLK0), + + .FCLK_CLK1(FCLK_CLK1), + + .FCLK_CLK2(FCLK_CLK2), + + .FCLK_CLK3(FCLK_CLK3), + .FCLK_RESET0_N(FCLK_RESET0_N), + .FCLK_RESET1_N(), + .FCLK_RESET2_N(), + .FCLK_RESET3_N(), + .IRQ_F2P(IRQ_F2P), + .PS_SRSTB(PS_SRSTB), + .PS_CLK(PS_CLK), + .PS_PORB(PS_PORB) + ); +endmodule diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_sim_netlist.v b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_sim_netlist.v new file mode 100644 index 0000000..1395635 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_sim_netlist.v @@ -0,0 +1,985 @@ +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +// Date : Fri May 15 15:26:59 2026 +// Host : mkb running 64-bit unknown +// Command : write_verilog -force -mode funcsim +// /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_sim_netlist.v +// Design : NewExtInst_TOP_rst_clk_wiz_0_100M_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z035ffg676-2 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "NewExtInst_TOP_rst_clk_wiz_0_100M_0,proc_sys_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "proc_sys_reset,Vivado 2023.2" *) +(* NotValidForBitStream *) +module NewExtInst_TOP_rst_clk_wiz_0_100M_0 + (slowest_sync_clk, + ext_reset_in, + aux_reset_in, + mb_debug_sys_rst, + dcm_locked, + mb_reset, + bus_struct_reset, + peripheral_reset, + interconnect_aresetn, + peripheral_aresetn); + (* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0" *) input slowest_sync_clk; + (* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input ext_reset_in; + (* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input aux_reset_in; + (* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input mb_debug_sys_rst; + input dcm_locked; + (* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0" *) output mb_reset; + (* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]bus_struct_reset; + (* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_reset; + (* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]interconnect_aresetn; + (* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_aresetn; + + wire aux_reset_in; + wire [0:0]bus_struct_reset; + wire dcm_locked; + wire ext_reset_in; + wire [0:0]interconnect_aresetn; + wire mb_debug_sys_rst; + wire mb_reset; + wire [0:0]peripheral_aresetn; + wire [0:0]peripheral_reset; + wire slowest_sync_clk; + + (* C_AUX_RESET_HIGH = "1'b0" *) + (* C_AUX_RST_WIDTH = "4" *) + (* C_EXT_RESET_HIGH = "1'b1" *) + (* C_EXT_RST_WIDTH = "4" *) + (* C_FAMILY = "zynq" *) + (* C_NUM_BUS_RST = "1" *) + (* C_NUM_INTERCONNECT_ARESETN = "1" *) + (* C_NUM_PERP_ARESETN = "1" *) + (* C_NUM_PERP_RST = "1" *) + NewExtInst_TOP_rst_clk_wiz_0_100M_0_proc_sys_reset U0 + (.aux_reset_in(aux_reset_in), + .bus_struct_reset(bus_struct_reset), + .dcm_locked(dcm_locked), + .ext_reset_in(ext_reset_in), + .interconnect_aresetn(interconnect_aresetn), + .mb_debug_sys_rst(mb_debug_sys_rst), + .mb_reset(mb_reset), + .peripheral_aresetn(peripheral_aresetn), + .peripheral_reset(peripheral_reset), + .slowest_sync_clk(slowest_sync_clk)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module NewExtInst_TOP_rst_clk_wiz_0_100M_0_cdc_sync + (lpf_exr_reg, + scndry_out, + lpf_exr, + p_1_in4_in, + p_2_in3_in, + exr_lpf, + ext_reset_in, + mb_debug_sys_rst, + slowest_sync_clk); + output lpf_exr_reg; + output scndry_out; + input lpf_exr; + input p_1_in4_in; + input p_2_in3_in; + input [0:0]exr_lpf; + input ext_reset_in; + input mb_debug_sys_rst; + input slowest_sync_clk; + + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ; + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ; + wire Q; + wire exr_d1; + wire [0:0]exr_lpf; + wire ext_reset_in; + wire lpf_exr; + wire lpf_exr_reg; + wire mb_debug_sys_rst; + wire p_1_in4_in; + wire p_2_in3_in; + wire scndry_out; + wire slowest_sync_clk; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(slowest_sync_clk), + .CE(1'b1), + .D(exr_d1), + .Q(Q), + .R(1'b0)); + LUT2 #( + .INIT(4'hE)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1 + (.I0(ext_reset_in), + .I1(mb_debug_sys_rst), + .O(exr_d1)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 + (.C(slowest_sync_clk), + .CE(1'b1), + .D(Q), + .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 + (.C(slowest_sync_clk), + .CE(1'b1), + .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ), + .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 + (.C(slowest_sync_clk), + .CE(1'b1), + .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ), + .Q(scndry_out), + .R(1'b0)); + LUT5 #( + .INIT(32'hEAAAAAA8)) + lpf_exr_i_1 + (.I0(lpf_exr), + .I1(p_1_in4_in), + .I2(p_2_in3_in), + .I3(scndry_out), + .I4(exr_lpf), + .O(lpf_exr_reg)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module NewExtInst_TOP_rst_clk_wiz_0_100M_0_cdc_sync_0 + (lpf_asr_reg, + scndry_out, + lpf_asr, + p_1_in, + p_2_in, + asr_lpf, + aux_reset_in, + slowest_sync_clk); + output lpf_asr_reg; + output scndry_out; + input lpf_asr; + input p_1_in; + input p_2_in; + input [0:0]asr_lpf; + input aux_reset_in; + input slowest_sync_clk; + + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ; + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ; + wire Q; + wire asr_d1; + wire [0:0]asr_lpf; + wire aux_reset_in; + wire lpf_asr; + wire lpf_asr_reg; + wire p_1_in; + wire p_2_in; + wire scndry_out; + wire slowest_sync_clk; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(slowest_sync_clk), + .CE(1'b1), + .D(asr_d1), + .Q(Q), + .R(1'b0)); + LUT1 #( + .INIT(2'h1)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0 + (.I0(aux_reset_in), + .O(asr_d1)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 + (.C(slowest_sync_clk), + .CE(1'b1), + .D(Q), + .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 + (.C(slowest_sync_clk), + .CE(1'b1), + .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ), + .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 + (.C(slowest_sync_clk), + .CE(1'b1), + .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ), + .Q(scndry_out), + .R(1'b0)); + LUT5 #( + .INIT(32'hEAAAAAA8)) + lpf_asr_i_1 + (.I0(lpf_asr), + .I1(p_1_in), + .I2(p_2_in), + .I3(scndry_out), + .I4(asr_lpf), + .O(lpf_asr_reg)); +endmodule + +(* ORIG_REF_NAME = "lpf" *) +module NewExtInst_TOP_rst_clk_wiz_0_100M_0_lpf + (lpf_int, + slowest_sync_clk, + dcm_locked, + ext_reset_in, + mb_debug_sys_rst, + aux_reset_in); + output lpf_int; + input slowest_sync_clk; + input dcm_locked; + input ext_reset_in; + input mb_debug_sys_rst; + input aux_reset_in; + + wire \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0 ; + wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ; + wire Q; + wire [0:0]asr_lpf; + wire aux_reset_in; + wire dcm_locked; + wire [0:0]exr_lpf; + wire ext_reset_in; + wire lpf_asr; + wire lpf_exr; + wire lpf_int; + wire lpf_int0__0; + wire mb_debug_sys_rst; + wire p_1_in; + wire p_1_in4_in; + wire p_2_in; + wire p_2_in3_in; + wire p_3_in1_in; + wire p_3_in6_in; + wire slowest_sync_clk; + + NewExtInst_TOP_rst_clk_wiz_0_100M_0_cdc_sync \ACTIVE_HIGH_EXT.ACT_HI_EXT + (.exr_lpf(exr_lpf), + .ext_reset_in(ext_reset_in), + .lpf_exr(lpf_exr), + .lpf_exr_reg(\ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0 ), + .mb_debug_sys_rst(mb_debug_sys_rst), + .p_1_in4_in(p_1_in4_in), + .p_2_in3_in(p_2_in3_in), + .scndry_out(p_3_in6_in), + .slowest_sync_clk(slowest_sync_clk)); + NewExtInst_TOP_rst_clk_wiz_0_100M_0_cdc_sync_0 \ACTIVE_LOW_AUX.ACT_LO_AUX + (.asr_lpf(asr_lpf), + .aux_reset_in(aux_reset_in), + .lpf_asr(lpf_asr), + .lpf_asr_reg(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ), + .p_1_in(p_1_in), + .p_2_in(p_2_in), + .scndry_out(p_3_in1_in), + .slowest_sync_clk(slowest_sync_clk)); + FDRE #( + .INIT(1'b0)) + \AUX_LPF[1].asr_lpf_reg[1] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(p_3_in1_in), + .Q(p_2_in), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AUX_LPF[2].asr_lpf_reg[2] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(p_2_in), + .Q(p_1_in), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AUX_LPF[3].asr_lpf_reg[3] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(p_1_in), + .Q(asr_lpf), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \EXT_LPF[1].exr_lpf_reg[1] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(p_3_in6_in), + .Q(p_2_in3_in), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \EXT_LPF[2].exr_lpf_reg[2] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(p_2_in3_in), + .Q(p_1_in4_in), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \EXT_LPF[3].exr_lpf_reg[3] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(p_1_in4_in), + .Q(exr_lpf), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "SRL16" *) + (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) + (* box_type = "PRIMITIVE" *) + (* srl_name = "U0/\\EXT_LPF/POR_SRL_I " *) + SRL16E #( + .INIT(16'hFFFF)) + POR_SRL_I + (.A0(1'b1), + .A1(1'b1), + .A2(1'b1), + .A3(1'b1), + .CE(1'b1), + .CLK(slowest_sync_clk), + .D(1'b0), + .Q(Q)); + FDRE #( + .INIT(1'b0)) + lpf_asr_reg + (.C(slowest_sync_clk), + .CE(1'b1), + .D(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ), + .Q(lpf_asr), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + lpf_exr_reg + (.C(slowest_sync_clk), + .CE(1'b1), + .D(\ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0 ), + .Q(lpf_exr), + .R(1'b0)); + LUT4 #( + .INIT(16'hFFFD)) + lpf_int0 + (.I0(dcm_locked), + .I1(lpf_exr), + .I2(lpf_asr), + .I3(Q), + .O(lpf_int0__0)); + FDRE #( + .INIT(1'b0)) + lpf_int_reg + (.C(slowest_sync_clk), + .CE(1'b1), + .D(lpf_int0__0), + .Q(lpf_int), + .R(1'b0)); +endmodule + +(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b1" *) +(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "zynq" *) (* C_NUM_BUS_RST = "1" *) +(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *) (* C_NUM_PERP_RST = "1" *) +(* ORIG_REF_NAME = "proc_sys_reset" *) +module NewExtInst_TOP_rst_clk_wiz_0_100M_0_proc_sys_reset + (slowest_sync_clk, + ext_reset_in, + aux_reset_in, + mb_debug_sys_rst, + dcm_locked, + mb_reset, + bus_struct_reset, + peripheral_reset, + interconnect_aresetn, + peripheral_aresetn); + input slowest_sync_clk; + input ext_reset_in; + input aux_reset_in; + input mb_debug_sys_rst; + input dcm_locked; + output mb_reset; + output [0:0]bus_struct_reset; + output [0:0]peripheral_reset; + output [0:0]interconnect_aresetn; + output [0:0]peripheral_aresetn; + + wire Bsr_out; + wire MB_out; + wire Pr_out; + wire SEQ_n_3; + wire SEQ_n_4; + wire aux_reset_in; + wire [0:0]bus_struct_reset; + wire dcm_locked; + wire ext_reset_in; + wire [0:0]interconnect_aresetn; + wire lpf_int; + wire mb_debug_sys_rst; + wire mb_reset; + wire [0:0]peripheral_aresetn; + wire [0:0]peripheral_reset; + wire slowest_sync_clk; + + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N + (.C(slowest_sync_clk), + .CE(1'b1), + .D(SEQ_n_3), + .Q(interconnect_aresetn), + .R(1'b0)); + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N + (.C(slowest_sync_clk), + .CE(1'b1), + .D(SEQ_n_4), + .Q(peripheral_aresetn), + .R(1'b0)); + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b1), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + \BSR_OUT_DFF[0].FDRE_BSR + (.C(slowest_sync_clk), + .CE(1'b1), + .D(Bsr_out), + .Q(bus_struct_reset), + .R(1'b0)); + NewExtInst_TOP_rst_clk_wiz_0_100M_0_lpf EXT_LPF + (.aux_reset_in(aux_reset_in), + .dcm_locked(dcm_locked), + .ext_reset_in(ext_reset_in), + .lpf_int(lpf_int), + .mb_debug_sys_rst(mb_debug_sys_rst), + .slowest_sync_clk(slowest_sync_clk)); + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b1), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + FDRE_inst + (.C(slowest_sync_clk), + .CE(1'b1), + .D(MB_out), + .Q(mb_reset), + .R(1'b0)); + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b1), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + \PR_OUT_DFF[0].FDRE_PER + (.C(slowest_sync_clk), + .CE(1'b1), + .D(Pr_out), + .Q(peripheral_reset), + .R(1'b0)); + NewExtInst_TOP_rst_clk_wiz_0_100M_0_sequence_psr SEQ + (.Bsr_out(Bsr_out), + .MB_out(MB_out), + .Pr_out(Pr_out), + .bsr_reg_0(SEQ_n_3), + .lpf_int(lpf_int), + .pr_reg_0(SEQ_n_4), + .slowest_sync_clk(slowest_sync_clk)); +endmodule + +(* ORIG_REF_NAME = "sequence_psr" *) +module NewExtInst_TOP_rst_clk_wiz_0_100M_0_sequence_psr + (MB_out, + Bsr_out, + Pr_out, + bsr_reg_0, + pr_reg_0, + lpf_int, + slowest_sync_clk); + output MB_out; + output Bsr_out; + output Pr_out; + output bsr_reg_0; + output pr_reg_0; + input lpf_int; + input slowest_sync_clk; + + wire Bsr_out; + wire Core_i_1_n_0; + wire MB_out; + wire Pr_out; + wire \bsr_dec_reg_n_0_[0] ; + wire \bsr_dec_reg_n_0_[2] ; + wire bsr_i_1_n_0; + wire bsr_reg_0; + wire \core_dec[0]_i_1_n_0 ; + wire \core_dec[2]_i_1_n_0 ; + wire \core_dec_reg_n_0_[0] ; + wire \core_dec_reg_n_0_[1] ; + wire from_sys_i_1_n_0; + wire lpf_int; + wire p_0_in; + wire [2:0]p_3_out; + wire [2:0]p_5_out; + wire pr_dec0__0; + wire \pr_dec_reg_n_0_[0] ; + wire \pr_dec_reg_n_0_[2] ; + wire pr_i_1_n_0; + wire pr_reg_0; + wire seq_clr; + wire [5:0]seq_cnt; + wire seq_cnt_en; + wire slowest_sync_clk; + + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT1 #( + .INIT(2'h1)) + \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1 + (.I0(Bsr_out), + .O(bsr_reg_0)); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT1 #( + .INIT(2'h1)) + \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1 + (.I0(Pr_out), + .O(pr_reg_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + Core_i_1 + (.I0(MB_out), + .I1(p_0_in), + .O(Core_i_1_n_0)); + FDSE #( + .INIT(1'b1)) + Core_reg + (.C(slowest_sync_clk), + .CE(1'b1), + .D(Core_i_1_n_0), + .Q(MB_out), + .S(lpf_int)); + NewExtInst_TOP_rst_clk_wiz_0_100M_0_upcnt_n SEQ_COUNTER + (.Q(seq_cnt), + .seq_clr(seq_clr), + .seq_cnt_en(seq_cnt_en), + .slowest_sync_clk(slowest_sync_clk)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT4 #( + .INIT(16'h0090)) + \bsr_dec[0]_i_1 + (.I0(seq_cnt_en), + .I1(seq_cnt[4]), + .I2(seq_cnt[3]), + .I3(seq_cnt[5]), + .O(p_5_out[0])); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h8)) + \bsr_dec[2]_i_1 + (.I0(\core_dec_reg_n_0_[1] ), + .I1(\bsr_dec_reg_n_0_[0] ), + .O(p_5_out[2])); + FDRE #( + .INIT(1'b0)) + \bsr_dec_reg[0] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(p_5_out[0]), + .Q(\bsr_dec_reg_n_0_[0] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \bsr_dec_reg[2] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(p_5_out[2]), + .Q(\bsr_dec_reg_n_0_[2] ), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h2)) + bsr_i_1 + (.I0(Bsr_out), + .I1(\bsr_dec_reg_n_0_[2] ), + .O(bsr_i_1_n_0)); + FDSE #( + .INIT(1'b1)) + bsr_reg + (.C(slowest_sync_clk), + .CE(1'b1), + .D(bsr_i_1_n_0), + .Q(Bsr_out), + .S(lpf_int)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT4 #( + .INIT(16'h9000)) + \core_dec[0]_i_1 + (.I0(seq_cnt_en), + .I1(seq_cnt[4]), + .I2(seq_cnt[3]), + .I3(seq_cnt[5]), + .O(\core_dec[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h8)) + \core_dec[2]_i_1 + (.I0(\core_dec_reg_n_0_[1] ), + .I1(\core_dec_reg_n_0_[0] ), + .O(\core_dec[2]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \core_dec_reg[0] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(\core_dec[0]_i_1_n_0 ), + .Q(\core_dec_reg_n_0_[0] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \core_dec_reg[1] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(pr_dec0__0), + .Q(\core_dec_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \core_dec_reg[2] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(\core_dec[2]_i_1_n_0 ), + .Q(p_0_in), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h8)) + from_sys_i_1 + (.I0(MB_out), + .I1(seq_cnt_en), + .O(from_sys_i_1_n_0)); + FDSE #( + .INIT(1'b0)) + from_sys_reg + (.C(slowest_sync_clk), + .CE(1'b1), + .D(from_sys_i_1_n_0), + .Q(seq_cnt_en), + .S(lpf_int)); + LUT4 #( + .INIT(16'h0018)) + pr_dec0 + (.I0(seq_cnt_en), + .I1(seq_cnt[0]), + .I2(seq_cnt[2]), + .I3(seq_cnt[1]), + .O(pr_dec0__0)); + LUT4 #( + .INIT(16'h0480)) + \pr_dec[0]_i_1 + (.I0(seq_cnt_en), + .I1(seq_cnt[3]), + .I2(seq_cnt[5]), + .I3(seq_cnt[4]), + .O(p_3_out[0])); + LUT2 #( + .INIT(4'h8)) + \pr_dec[2]_i_1 + (.I0(\core_dec_reg_n_0_[1] ), + .I1(\pr_dec_reg_n_0_[0] ), + .O(p_3_out[2])); + FDRE #( + .INIT(1'b0)) + \pr_dec_reg[0] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(p_3_out[0]), + .Q(\pr_dec_reg_n_0_[0] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \pr_dec_reg[2] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(p_3_out[2]), + .Q(\pr_dec_reg_n_0_[2] ), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT2 #( + .INIT(4'h2)) + pr_i_1 + (.I0(Pr_out), + .I1(\pr_dec_reg_n_0_[2] ), + .O(pr_i_1_n_0)); + FDSE #( + .INIT(1'b1)) + pr_reg + (.C(slowest_sync_clk), + .CE(1'b1), + .D(pr_i_1_n_0), + .Q(Pr_out), + .S(lpf_int)); + FDRE #( + .INIT(1'b0)) + seq_clr_reg + (.C(slowest_sync_clk), + .CE(1'b1), + .D(1'b1), + .Q(seq_clr), + .R(lpf_int)); +endmodule + +(* ORIG_REF_NAME = "upcnt_n" *) +module NewExtInst_TOP_rst_clk_wiz_0_100M_0_upcnt_n + (Q, + seq_clr, + seq_cnt_en, + slowest_sync_clk); + output [5:0]Q; + input seq_clr; + input seq_cnt_en; + input slowest_sync_clk; + + wire [5:0]Q; + wire clear; + wire [5:0]q_int0; + wire seq_clr; + wire seq_cnt_en; + wire slowest_sync_clk; + + LUT1 #( + .INIT(2'h1)) + \q_int[0]_i_1 + (.I0(Q[0]), + .O(q_int0[0])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT2 #( + .INIT(4'h6)) + \q_int[1]_i_1 + (.I0(Q[0]), + .I1(Q[1]), + .O(q_int0[1])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT3 #( + .INIT(8'h78)) + \q_int[2]_i_1 + (.I0(Q[0]), + .I1(Q[1]), + .I2(Q[2]), + .O(q_int0[2])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'h7F80)) + \q_int[3]_i_1 + (.I0(Q[1]), + .I1(Q[0]), + .I2(Q[2]), + .I3(Q[3]), + .O(q_int0[3])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \q_int[4]_i_1 + (.I0(Q[2]), + .I1(Q[0]), + .I2(Q[1]), + .I3(Q[3]), + .I4(Q[4]), + .O(q_int0[4])); + LUT1 #( + .INIT(2'h1)) + \q_int[5]_i_1 + (.I0(seq_clr), + .O(clear)); + LUT6 #( + .INIT(64'h7FFFFFFF80000000)) + \q_int[5]_i_2 + (.I0(Q[3]), + .I1(Q[1]), + .I2(Q[0]), + .I3(Q[2]), + .I4(Q[4]), + .I5(Q[5]), + .O(q_int0[5])); + FDRE #( + .INIT(1'b1)) + \q_int_reg[0] + (.C(slowest_sync_clk), + .CE(seq_cnt_en), + .D(q_int0[0]), + .Q(Q[0]), + .R(clear)); + FDRE #( + .INIT(1'b1)) + \q_int_reg[1] + (.C(slowest_sync_clk), + .CE(seq_cnt_en), + .D(q_int0[1]), + .Q(Q[1]), + .R(clear)); + FDRE #( + .INIT(1'b1)) + \q_int_reg[2] + (.C(slowest_sync_clk), + .CE(seq_cnt_en), + .D(q_int0[2]), + .Q(Q[2]), + .R(clear)); + FDRE #( + .INIT(1'b1)) + \q_int_reg[3] + (.C(slowest_sync_clk), + .CE(seq_cnt_en), + .D(q_int0[3]), + .Q(Q[3]), + .R(clear)); + FDRE #( + .INIT(1'b1)) + \q_int_reg[4] + (.C(slowest_sync_clk), + .CE(seq_cnt_en), + .D(q_int0[4]), + .Q(Q[4]), + .R(clear)); + FDRE #( + .INIT(1'b1)) + \q_int_reg[5] + (.C(slowest_sync_clk), + .CE(seq_cnt_en), + .D(q_int0[5]), + .Q(Q[5]), + .R(clear)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_sim_netlist.vhdl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_sim_netlist.vhdl new file mode 100644 index 0000000..e5ce6a8 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_sim_netlist.vhdl @@ -0,0 +1,1135 @@ +-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +-- Date : Fri May 15 15:26:59 2026 +-- Host : mkb running 64-bit unknown +-- Command : write_vhdl -force -mode funcsim +-- /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_sim_netlist.vhdl +-- Design : NewExtInst_TOP_rst_clk_wiz_0_100M_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z035ffg676-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_rst_clk_wiz_0_100M_0_cdc_sync is + port ( + lpf_exr_reg : out STD_LOGIC; + scndry_out : out STD_LOGIC; + lpf_exr : in STD_LOGIC; + p_1_in4_in : in STD_LOGIC; + p_2_in3_in : in STD_LOGIC; + exr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 ); + ext_reset_in : in STD_LOGIC; + mb_debug_sys_rst : in STD_LOGIC; + slowest_sync_clk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of NewExtInst_TOP_rst_clk_wiz_0_100M_0_cdc_sync : entity is "cdc_sync"; +end NewExtInst_TOP_rst_clk_wiz_0_100M_0_cdc_sync; + +architecture STRUCTURE of NewExtInst_TOP_rst_clk_wiz_0_100M_0_cdc_sync is + signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : STD_LOGIC; + signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : STD_LOGIC; + signal Q : STD_LOGIC; + signal exr_d1 : STD_LOGIC; + signal \^scndry_out\ : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute XILINX_TRANSFORM_PINMAP : string; + attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE"; + attribute box_type : string; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; + attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "VCC:CE"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; + attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "VCC:CE"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; + attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "VCC:CE"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; +begin + scndry_out <= \^scndry_out\; +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => exr_d1, + Q => Q, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => ext_reset_in, + I1 => mb_debug_sys_rst, + O => exr_d1 + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => Q, + Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\, + Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\, + Q => \^scndry_out\, + R => '0' + ); +lpf_exr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"EAAAAAA8" + ) + port map ( + I0 => lpf_exr, + I1 => p_1_in4_in, + I2 => p_2_in3_in, + I3 => \^scndry_out\, + I4 => exr_lpf(0), + O => lpf_exr_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_rst_clk_wiz_0_100M_0_cdc_sync_0 is + port ( + lpf_asr_reg : out STD_LOGIC; + scndry_out : out STD_LOGIC; + lpf_asr : in STD_LOGIC; + p_1_in : in STD_LOGIC; + p_2_in : in STD_LOGIC; + asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 ); + aux_reset_in : in STD_LOGIC; + slowest_sync_clk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of NewExtInst_TOP_rst_clk_wiz_0_100M_0_cdc_sync_0 : entity is "cdc_sync"; +end NewExtInst_TOP_rst_clk_wiz_0_100M_0_cdc_sync_0; + +architecture STRUCTURE of NewExtInst_TOP_rst_clk_wiz_0_100M_0_cdc_sync_0 is + signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : STD_LOGIC; + signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : STD_LOGIC; + signal Q : STD_LOGIC; + signal asr_d1 : STD_LOGIC; + signal \^scndry_out\ : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute XILINX_TRANSFORM_PINMAP : string; + attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE"; + attribute box_type : string; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; + attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "VCC:CE"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; + attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "VCC:CE"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; + attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "VCC:CE"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; +begin + scndry_out <= \^scndry_out\; +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => asr_d1, + Q => Q, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => aux_reset_in, + O => asr_d1 + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => Q, + Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\, + Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\, + Q => \^scndry_out\, + R => '0' + ); +lpf_asr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"EAAAAAA8" + ) + port map ( + I0 => lpf_asr, + I1 => p_1_in, + I2 => p_2_in, + I3 => \^scndry_out\, + I4 => asr_lpf(0), + O => lpf_asr_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_rst_clk_wiz_0_100M_0_upcnt_n is + port ( + Q : out STD_LOGIC_VECTOR ( 5 downto 0 ); + seq_clr : in STD_LOGIC; + seq_cnt_en : in STD_LOGIC; + slowest_sync_clk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of NewExtInst_TOP_rst_clk_wiz_0_100M_0_upcnt_n : entity is "upcnt_n"; +end NewExtInst_TOP_rst_clk_wiz_0_100M_0_upcnt_n; + +architecture STRUCTURE of NewExtInst_TOP_rst_clk_wiz_0_100M_0_upcnt_n is + signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal clear : STD_LOGIC; + signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0"; +begin + Q(5 downto 0) <= \^q\(5 downto 0); +\q_int[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^q\(0), + O => q_int0(0) + ); +\q_int[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^q\(0), + I1 => \^q\(1), + O => q_int0(1) + ); +\q_int[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \^q\(0), + I1 => \^q\(1), + I2 => \^q\(2), + O => q_int0(2) + ); +\q_int[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \^q\(1), + I1 => \^q\(0), + I2 => \^q\(2), + I3 => \^q\(3), + O => q_int0(3) + ); +\q_int[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \^q\(2), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => \^q\(3), + I4 => \^q\(4), + O => q_int0(4) + ); +\q_int[5]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => seq_clr, + O => clear + ); +\q_int[5]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFFFFFF80000000" + ) + port map ( + I0 => \^q\(3), + I1 => \^q\(1), + I2 => \^q\(0), + I3 => \^q\(2), + I4 => \^q\(4), + I5 => \^q\(5), + O => q_int0(5) + ); +\q_int_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => slowest_sync_clk, + CE => seq_cnt_en, + D => q_int0(0), + Q => \^q\(0), + R => clear + ); +\q_int_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => slowest_sync_clk, + CE => seq_cnt_en, + D => q_int0(1), + Q => \^q\(1), + R => clear + ); +\q_int_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => slowest_sync_clk, + CE => seq_cnt_en, + D => q_int0(2), + Q => \^q\(2), + R => clear + ); +\q_int_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => slowest_sync_clk, + CE => seq_cnt_en, + D => q_int0(3), + Q => \^q\(3), + R => clear + ); +\q_int_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => slowest_sync_clk, + CE => seq_cnt_en, + D => q_int0(4), + Q => \^q\(4), + R => clear + ); +\q_int_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => slowest_sync_clk, + CE => seq_cnt_en, + D => q_int0(5), + Q => \^q\(5), + R => clear + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_rst_clk_wiz_0_100M_0_lpf is + port ( + lpf_int : out STD_LOGIC; + slowest_sync_clk : in STD_LOGIC; + dcm_locked : in STD_LOGIC; + ext_reset_in : in STD_LOGIC; + mb_debug_sys_rst : in STD_LOGIC; + aux_reset_in : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of NewExtInst_TOP_rst_clk_wiz_0_100M_0_lpf : entity is "lpf"; +end NewExtInst_TOP_rst_clk_wiz_0_100M_0_lpf; + +architecture STRUCTURE of NewExtInst_TOP_rst_clk_wiz_0_100M_0_lpf is + signal \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0\ : STD_LOGIC; + signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC; + signal Q : STD_LOGIC; + signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 ); + signal exr_lpf : STD_LOGIC_VECTOR ( 0 to 0 ); + signal lpf_asr : STD_LOGIC; + signal lpf_exr : STD_LOGIC; + signal \lpf_int0__0\ : STD_LOGIC; + signal p_1_in : STD_LOGIC; + signal p_1_in4_in : STD_LOGIC; + signal p_2_in : STD_LOGIC; + signal p_2_in3_in : STD_LOGIC; + signal p_3_in1_in : STD_LOGIC; + signal p_3_in6_in : STD_LOGIC; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16"; + attribute XILINX_TRANSFORM_PINMAP : string; + attribute XILINX_TRANSFORM_PINMAP of POR_SRL_I : label is "VCC:CE"; + attribute box_type : string; + attribute box_type of POR_SRL_I : label is "PRIMITIVE"; + attribute srl_name : string; + attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I "; +begin +\ACTIVE_HIGH_EXT.ACT_HI_EXT\: entity work.NewExtInst_TOP_rst_clk_wiz_0_100M_0_cdc_sync + port map ( + exr_lpf(0) => exr_lpf(0), + ext_reset_in => ext_reset_in, + lpf_exr => lpf_exr, + lpf_exr_reg => \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0\, + mb_debug_sys_rst => mb_debug_sys_rst, + p_1_in4_in => p_1_in4_in, + p_2_in3_in => p_2_in3_in, + scndry_out => p_3_in6_in, + slowest_sync_clk => slowest_sync_clk + ); +\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.NewExtInst_TOP_rst_clk_wiz_0_100M_0_cdc_sync_0 + port map ( + asr_lpf(0) => asr_lpf(0), + aux_reset_in => aux_reset_in, + lpf_asr => lpf_asr, + lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\, + p_1_in => p_1_in, + p_2_in => p_2_in, + scndry_out => p_3_in1_in, + slowest_sync_clk => slowest_sync_clk + ); +\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => p_3_in1_in, + Q => p_2_in, + R => '0' + ); +\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => p_2_in, + Q => p_1_in, + R => '0' + ); +\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => p_1_in, + Q => asr_lpf(0), + R => '0' + ); +\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => p_3_in6_in, + Q => p_2_in3_in, + R => '0' + ); +\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => p_2_in3_in, + Q => p_1_in4_in, + R => '0' + ); +\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => p_1_in4_in, + Q => exr_lpf(0), + R => '0' + ); +POR_SRL_I: unisim.vcomponents.SRL16E + generic map( + INIT => X"FFFF" + ) + port map ( + A0 => '1', + A1 => '1', + A2 => '1', + A3 => '1', + CE => '1', + CLK => slowest_sync_clk, + D => '0', + Q => Q + ); +lpf_asr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\, + Q => lpf_asr, + R => '0' + ); +lpf_exr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0\, + Q => lpf_exr, + R => '0' + ); +lpf_int0: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFD" + ) + port map ( + I0 => dcm_locked, + I1 => lpf_exr, + I2 => lpf_asr, + I3 => Q, + O => \lpf_int0__0\ + ); +lpf_int_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => \lpf_int0__0\, + Q => lpf_int, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_rst_clk_wiz_0_100M_0_sequence_psr is + port ( + MB_out : out STD_LOGIC; + Bsr_out : out STD_LOGIC; + Pr_out : out STD_LOGIC; + bsr_reg_0 : out STD_LOGIC; + pr_reg_0 : out STD_LOGIC; + lpf_int : in STD_LOGIC; + slowest_sync_clk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of NewExtInst_TOP_rst_clk_wiz_0_100M_0_sequence_psr : entity is "sequence_psr"; +end NewExtInst_TOP_rst_clk_wiz_0_100M_0_sequence_psr; + +architecture STRUCTURE of NewExtInst_TOP_rst_clk_wiz_0_100M_0_sequence_psr is + signal \^bsr_out\ : STD_LOGIC; + signal Core_i_1_n_0 : STD_LOGIC; + signal \^mb_out\ : STD_LOGIC; + signal \^pr_out\ : STD_LOGIC; + signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC; + signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC; + signal bsr_i_1_n_0 : STD_LOGIC; + signal \core_dec[0]_i_1_n_0\ : STD_LOGIC; + signal \core_dec[2]_i_1_n_0\ : STD_LOGIC; + signal \core_dec_reg_n_0_[0]\ : STD_LOGIC; + signal \core_dec_reg_n_0_[1]\ : STD_LOGIC; + signal from_sys_i_1_n_0 : STD_LOGIC; + signal p_0_in : STD_LOGIC; + signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \pr_dec0__0\ : STD_LOGIC; + signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC; + signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC; + signal pr_i_1_n_0 : STD_LOGIC; + signal seq_clr : STD_LOGIC; + signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal seq_cnt_en : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \bsr_dec[0]_i_1\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair5"; +begin + Bsr_out <= \^bsr_out\; + MB_out <= \^mb_out\; + Pr_out <= \^pr_out\; +\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^bsr_out\, + O => bsr_reg_0 + ); +\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^pr_out\, + O => pr_reg_0 + ); +Core_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^mb_out\, + I1 => p_0_in, + O => Core_i_1_n_0 + ); +Core_reg: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => Core_i_1_n_0, + Q => \^mb_out\, + S => lpf_int + ); +SEQ_COUNTER: entity work.NewExtInst_TOP_rst_clk_wiz_0_100M_0_upcnt_n + port map ( + Q(5 downto 0) => seq_cnt(5 downto 0), + seq_clr => seq_clr, + seq_cnt_en => seq_cnt_en, + slowest_sync_clk => slowest_sync_clk + ); +\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0090" + ) + port map ( + I0 => seq_cnt_en, + I1 => seq_cnt(4), + I2 => seq_cnt(3), + I3 => seq_cnt(5), + O => p_5_out(0) + ); +\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \core_dec_reg_n_0_[1]\, + I1 => \bsr_dec_reg_n_0_[0]\, + O => p_5_out(2) + ); +\bsr_dec_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => p_5_out(0), + Q => \bsr_dec_reg_n_0_[0]\, + R => '0' + ); +\bsr_dec_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => p_5_out(2), + Q => \bsr_dec_reg_n_0_[2]\, + R => '0' + ); +bsr_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^bsr_out\, + I1 => \bsr_dec_reg_n_0_[2]\, + O => bsr_i_1_n_0 + ); +bsr_reg: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => bsr_i_1_n_0, + Q => \^bsr_out\, + S => lpf_int + ); +\core_dec[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9000" + ) + port map ( + I0 => seq_cnt_en, + I1 => seq_cnt(4), + I2 => seq_cnt(3), + I3 => seq_cnt(5), + O => \core_dec[0]_i_1_n_0\ + ); +\core_dec[2]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \core_dec_reg_n_0_[1]\, + I1 => \core_dec_reg_n_0_[0]\, + O => \core_dec[2]_i_1_n_0\ + ); +\core_dec_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => \core_dec[0]_i_1_n_0\, + Q => \core_dec_reg_n_0_[0]\, + R => '0' + ); +\core_dec_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => \pr_dec0__0\, + Q => \core_dec_reg_n_0_[1]\, + R => '0' + ); +\core_dec_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => \core_dec[2]_i_1_n_0\, + Q => p_0_in, + R => '0' + ); +from_sys_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^mb_out\, + I1 => seq_cnt_en, + O => from_sys_i_1_n_0 + ); +from_sys_reg: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => from_sys_i_1_n_0, + Q => seq_cnt_en, + S => lpf_int + ); +pr_dec0: unisim.vcomponents.LUT4 + generic map( + INIT => X"0018" + ) + port map ( + I0 => seq_cnt_en, + I1 => seq_cnt(0), + I2 => seq_cnt(2), + I3 => seq_cnt(1), + O => \pr_dec0__0\ + ); +\pr_dec[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0480" + ) + port map ( + I0 => seq_cnt_en, + I1 => seq_cnt(3), + I2 => seq_cnt(5), + I3 => seq_cnt(4), + O => p_3_out(0) + ); +\pr_dec[2]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \core_dec_reg_n_0_[1]\, + I1 => \pr_dec_reg_n_0_[0]\, + O => p_3_out(2) + ); +\pr_dec_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => p_3_out(0), + Q => \pr_dec_reg_n_0_[0]\, + R => '0' + ); +\pr_dec_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => p_3_out(2), + Q => \pr_dec_reg_n_0_[2]\, + R => '0' + ); +pr_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^pr_out\, + I1 => \pr_dec_reg_n_0_[2]\, + O => pr_i_1_n_0 + ); +pr_reg: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => pr_i_1_n_0, + Q => \^pr_out\, + S => lpf_int + ); +seq_clr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => '1', + Q => seq_clr, + R => lpf_int + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_rst_clk_wiz_0_100M_0_proc_sys_reset is + port ( + slowest_sync_clk : in STD_LOGIC; + ext_reset_in : in STD_LOGIC; + aux_reset_in : in STD_LOGIC; + mb_debug_sys_rst : in STD_LOGIC; + dcm_locked : in STD_LOGIC; + mb_reset : out STD_LOGIC; + bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); + peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); + interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); + peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute C_AUX_RESET_HIGH : string; + attribute C_AUX_RESET_HIGH of NewExtInst_TOP_rst_clk_wiz_0_100M_0_proc_sys_reset : entity is "1'b0"; + attribute C_AUX_RST_WIDTH : integer; + attribute C_AUX_RST_WIDTH of NewExtInst_TOP_rst_clk_wiz_0_100M_0_proc_sys_reset : entity is 4; + attribute C_EXT_RESET_HIGH : string; + attribute C_EXT_RESET_HIGH of NewExtInst_TOP_rst_clk_wiz_0_100M_0_proc_sys_reset : entity is "1'b1"; + attribute C_EXT_RST_WIDTH : integer; + attribute C_EXT_RST_WIDTH of NewExtInst_TOP_rst_clk_wiz_0_100M_0_proc_sys_reset : entity is 4; + attribute C_FAMILY : string; + attribute C_FAMILY of NewExtInst_TOP_rst_clk_wiz_0_100M_0_proc_sys_reset : entity is "zynq"; + attribute C_NUM_BUS_RST : integer; + attribute C_NUM_BUS_RST of NewExtInst_TOP_rst_clk_wiz_0_100M_0_proc_sys_reset : entity is 1; + attribute C_NUM_INTERCONNECT_ARESETN : integer; + attribute C_NUM_INTERCONNECT_ARESETN of NewExtInst_TOP_rst_clk_wiz_0_100M_0_proc_sys_reset : entity is 1; + attribute C_NUM_PERP_ARESETN : integer; + attribute C_NUM_PERP_ARESETN of NewExtInst_TOP_rst_clk_wiz_0_100M_0_proc_sys_reset : entity is 1; + attribute C_NUM_PERP_RST : integer; + attribute C_NUM_PERP_RST of NewExtInst_TOP_rst_clk_wiz_0_100M_0_proc_sys_reset : entity is 1; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of NewExtInst_TOP_rst_clk_wiz_0_100M_0_proc_sys_reset : entity is "proc_sys_reset"; +end NewExtInst_TOP_rst_clk_wiz_0_100M_0_proc_sys_reset; + +architecture STRUCTURE of NewExtInst_TOP_rst_clk_wiz_0_100M_0_proc_sys_reset is + signal Bsr_out : STD_LOGIC; + signal MB_out : STD_LOGIC; + signal Pr_out : STD_LOGIC; + signal SEQ_n_3 : STD_LOGIC; + signal SEQ_n_4 : STD_LOGIC; + signal lpf_int : STD_LOGIC; + attribute box_type : string; + attribute box_type of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : label is "PRIMITIVE"; + attribute box_type of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : label is "PRIMITIVE"; + attribute box_type of \BSR_OUT_DFF[0].FDRE_BSR\ : label is "PRIMITIVE"; + attribute box_type of FDRE_inst : label is "PRIMITIVE"; + attribute box_type of \PR_OUT_DFF[0].FDRE_PER\ : label is "PRIMITIVE"; +begin +\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\: unisim.vcomponents.FDRE + generic map( + INIT => '0', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => SEQ_n_3, + Q => interconnect_aresetn(0), + R => '0' + ); +\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\: unisim.vcomponents.FDRE + generic map( + INIT => '0', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => SEQ_n_4, + Q => peripheral_aresetn(0), + R => '0' + ); +\BSR_OUT_DFF[0].FDRE_BSR\: unisim.vcomponents.FDRE + generic map( + INIT => '1', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => Bsr_out, + Q => bus_struct_reset(0), + R => '0' + ); +EXT_LPF: entity work.NewExtInst_TOP_rst_clk_wiz_0_100M_0_lpf + port map ( + aux_reset_in => aux_reset_in, + dcm_locked => dcm_locked, + ext_reset_in => ext_reset_in, + lpf_int => lpf_int, + mb_debug_sys_rst => mb_debug_sys_rst, + slowest_sync_clk => slowest_sync_clk + ); +FDRE_inst: unisim.vcomponents.FDRE + generic map( + INIT => '1', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => MB_out, + Q => mb_reset, + R => '0' + ); +\PR_OUT_DFF[0].FDRE_PER\: unisim.vcomponents.FDRE + generic map( + INIT => '1', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => Pr_out, + Q => peripheral_reset(0), + R => '0' + ); +SEQ: entity work.NewExtInst_TOP_rst_clk_wiz_0_100M_0_sequence_psr + port map ( + Bsr_out => Bsr_out, + MB_out => MB_out, + Pr_out => Pr_out, + bsr_reg_0 => SEQ_n_3, + lpf_int => lpf_int, + pr_reg_0 => SEQ_n_4, + slowest_sync_clk => slowest_sync_clk + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_rst_clk_wiz_0_100M_0 is + port ( + slowest_sync_clk : in STD_LOGIC; + ext_reset_in : in STD_LOGIC; + aux_reset_in : in STD_LOGIC; + mb_debug_sys_rst : in STD_LOGIC; + dcm_locked : in STD_LOGIC; + mb_reset : out STD_LOGIC; + bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); + peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); + interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); + peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of NewExtInst_TOP_rst_clk_wiz_0_100M_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of NewExtInst_TOP_rst_clk_wiz_0_100M_0 : entity is "NewExtInst_TOP_rst_clk_wiz_0_100M_0,proc_sys_reset,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of NewExtInst_TOP_rst_clk_wiz_0_100M_0 : entity is "yes"; + attribute x_core_info : string; + attribute x_core_info of NewExtInst_TOP_rst_clk_wiz_0_100M_0 : entity is "proc_sys_reset,Vivado 2023.2"; +end NewExtInst_TOP_rst_clk_wiz_0_100M_0; + +architecture STRUCTURE of NewExtInst_TOP_rst_clk_wiz_0_100M_0 is + attribute C_AUX_RESET_HIGH : string; + attribute C_AUX_RESET_HIGH of U0 : label is "1'b0"; + attribute C_AUX_RST_WIDTH : integer; + attribute C_AUX_RST_WIDTH of U0 : label is 4; + attribute C_EXT_RESET_HIGH : string; + attribute C_EXT_RESET_HIGH of U0 : label is "1'b1"; + attribute C_EXT_RST_WIDTH : integer; + attribute C_EXT_RST_WIDTH of U0 : label is 4; + attribute C_FAMILY : string; + attribute C_FAMILY of U0 : label is "zynq"; + attribute C_NUM_BUS_RST : integer; + attribute C_NUM_BUS_RST of U0 : label is 1; + attribute C_NUM_INTERCONNECT_ARESETN : integer; + attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1; + attribute C_NUM_PERP_ARESETN : integer; + attribute C_NUM_PERP_ARESETN of U0 : label is 1; + attribute C_NUM_PERP_RST : integer; + attribute C_NUM_PERP_RST of U0 : label is 1; + attribute x_interface_info : string; + attribute x_interface_info of aux_reset_in : signal is "xilinx.com:signal:reset:1.0 aux_reset RST"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of aux_reset_in : signal is "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + attribute x_interface_info of ext_reset_in : signal is "xilinx.com:signal:reset:1.0 ext_reset RST"; + attribute x_interface_parameter of ext_reset_in : signal is "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_HIGH, INSERT_VIP 0"; + attribute x_interface_info of mb_debug_sys_rst : signal is "xilinx.com:signal:reset:1.0 dbg_reset RST"; + attribute x_interface_parameter of mb_debug_sys_rst : signal is "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0"; + attribute x_interface_info of mb_reset : signal is "xilinx.com:signal:reset:1.0 mb_rst RST"; + attribute x_interface_parameter of mb_reset : signal is "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0"; + attribute x_interface_info of slowest_sync_clk : signal is "xilinx.com:signal:clock:1.0 clock CLK"; + attribute x_interface_parameter of slowest_sync_clk : signal is "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0"; + attribute x_interface_info of bus_struct_reset : signal is "xilinx.com:signal:reset:1.0 bus_struct_reset RST"; + attribute x_interface_parameter of bus_struct_reset : signal is "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0"; + attribute x_interface_info of interconnect_aresetn : signal is "xilinx.com:signal:reset:1.0 interconnect_low_rst RST"; + attribute x_interface_parameter of interconnect_aresetn : signal is "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0"; + attribute x_interface_info of peripheral_aresetn : signal is "xilinx.com:signal:reset:1.0 peripheral_low_rst RST"; + attribute x_interface_parameter of peripheral_aresetn : signal is "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0"; + attribute x_interface_info of peripheral_reset : signal is "xilinx.com:signal:reset:1.0 peripheral_high_rst RST"; + attribute x_interface_parameter of peripheral_reset : signal is "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0"; +begin +U0: entity work.NewExtInst_TOP_rst_clk_wiz_0_100M_0_proc_sys_reset + port map ( + aux_reset_in => aux_reset_in, + bus_struct_reset(0) => bus_struct_reset(0), + dcm_locked => dcm_locked, + ext_reset_in => ext_reset_in, + interconnect_aresetn(0) => interconnect_aresetn(0), + mb_debug_sys_rst => mb_debug_sys_rst, + mb_reset => mb_reset, + peripheral_aresetn(0) => peripheral_aresetn(0), + peripheral_reset(0) => peripheral_reset(0), + slowest_sync_clk => slowest_sync_clk + ); +end STRUCTURE; diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/sim/NewExtInst_TOP_rst_clk_wiz_0_100M_0.vhd b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/sim/NewExtInst_TOP_rst_clk_wiz_0_100M_0.vhd new file mode 100644 index 0000000..90f3d9d --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/sim/NewExtInst_TOP_rst_clk_wiz_0_100M_0.vhd @@ -0,0 +1,147 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0 +-- IP Revision: 14 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY proc_sys_reset_v5_0_14; +USE proc_sys_reset_v5_0_14.proc_sys_reset; + +ENTITY NewExtInst_TOP_rst_clk_wiz_0_100M_0 IS + PORT ( + slowest_sync_clk : IN STD_LOGIC; + ext_reset_in : IN STD_LOGIC; + aux_reset_in : IN STD_LOGIC; + mb_debug_sys_rst : IN STD_LOGIC; + dcm_locked : IN STD_LOGIC; + mb_reset : OUT STD_LOGIC; + bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); +END NewExtInst_TOP_rst_clk_wiz_0_100M_0; + +ARCHITECTURE NewExtInst_TOP_rst_clk_wiz_0_100M_0_arch OF NewExtInst_TOP_rst_clk_wiz_0_100M_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF NewExtInst_TOP_rst_clk_wiz_0_100M_0_arch: ARCHITECTURE IS "yes"; + COMPONENT proc_sys_reset IS + GENERIC ( + C_FAMILY : STRING; + C_EXT_RST_WIDTH : INTEGER; + C_AUX_RST_WIDTH : INTEGER; + C_EXT_RESET_HIGH : STD_LOGIC; + C_AUX_RESET_HIGH : STD_LOGIC; + C_NUM_BUS_RST : INTEGER; + C_NUM_PERP_RST : INTEGER; + C_NUM_INTERCONNECT_ARESETN : INTEGER; + C_NUM_PERP_ARESETN : INTEGER + ); + PORT ( + slowest_sync_clk : IN STD_LOGIC; + ext_reset_in : IN STD_LOGIC; + aux_reset_in : IN STD_LOGIC; + mb_debug_sys_rst : IN STD_LOGIC; + dcm_locked : IN STD_LOGIC; + mb_reset : OUT STD_LOGIC; + bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); + END COMPONENT proc_sys_reset; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_HIGH, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK"; +BEGIN + U0 : proc_sys_reset + GENERIC MAP ( + C_FAMILY => "zynq", + C_EXT_RST_WIDTH => 4, + C_AUX_RST_WIDTH => 4, + C_EXT_RESET_HIGH => '1', + C_AUX_RESET_HIGH => '0', + C_NUM_BUS_RST => 1, + C_NUM_PERP_RST => 1, + C_NUM_INTERCONNECT_ARESETN => 1, + C_NUM_PERP_ARESETN => 1 + ) + PORT MAP ( + slowest_sync_clk => slowest_sync_clk, + ext_reset_in => ext_reset_in, + aux_reset_in => aux_reset_in, + mb_debug_sys_rst => mb_debug_sys_rst, + dcm_locked => dcm_locked, + mb_reset => mb_reset, + bus_struct_reset => bus_struct_reset, + peripheral_reset => peripheral_reset, + interconnect_aresetn => interconnect_aresetn, + peripheral_aresetn => peripheral_aresetn + ); +END NewExtInst_TOP_rst_clk_wiz_0_100M_0_arch; diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_sim_netlist.v b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_sim_netlist.v new file mode 100644 index 0000000..3f6c122 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_sim_netlist.v @@ -0,0 +1,3926 @@ +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +// Date : Fri May 15 15:27:02 2026 +// Host : mkb running 64-bit unknown +// Command : write_verilog -force -mode funcsim +// /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_sim_netlist.v +// Design : NewExtInst_TOP_xbar_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z035ffg676-2 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "NewExtInst_TOP_xbar_0,axi_crossbar_v2_1_30_axi_crossbar,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_crossbar_v2_1_30_axi_crossbar,Vivado 2023.2" *) +(* NotValidForBitStream *) +module NewExtInst_TOP_xbar_0 + (aclk, + aresetn, + s_axi_awaddr, + s_axi_awprot, + s_axi_awvalid, + s_axi_awready, + s_axi_wdata, + s_axi_wstrb, + s_axi_wvalid, + s_axi_wready, + s_axi_bresp, + s_axi_bvalid, + s_axi_bready, + s_axi_araddr, + s_axi_arprot, + s_axi_arvalid, + s_axi_arready, + s_axi_rdata, + s_axi_rresp, + s_axi_rvalid, + s_axi_rready, + m_axi_awaddr, + m_axi_awprot, + m_axi_awvalid, + m_axi_awready, + m_axi_wdata, + m_axi_wstrb, + m_axi_wvalid, + m_axi_wready, + m_axi_bresp, + m_axi_bvalid, + m_axi_bready, + m_axi_araddr, + m_axi_arprot, + m_axi_arvalid, + m_axi_arready, + m_axi_rdata, + m_axi_rresp, + m_axi_rvalid, + m_axi_rready); + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *) input aclk; + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *) input aresetn; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *) input [31:0]s_axi_awaddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *) input [2:0]s_axi_awprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *) input [0:0]s_axi_awvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *) output [0:0]s_axi_awready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *) input [31:0]s_axi_wdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *) input [3:0]s_axi_wstrb; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *) input [0:0]s_axi_wvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *) output [0:0]s_axi_wready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *) output [1:0]s_axi_bresp; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *) output [0:0]s_axi_bvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *) input [0:0]s_axi_bready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *) input [31:0]s_axi_araddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *) input [2:0]s_axi_arprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *) input [0:0]s_axi_arvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *) output [0:0]s_axi_arready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *) output [31:0]s_axi_rdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *) output [1:0]s_axi_rresp; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *) output [0:0]s_axi_rvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [0:0]s_axi_rready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64]" *) output [95:0]m_axi_awaddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6]" *) output [8:0]m_axi_awprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2]" *) output [2:0]m_axi_awvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2]" *) input [2:0]m_axi_awready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64]" *) output [95:0]m_axi_wdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8]" *) output [11:0]m_axi_wstrb; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2]" *) output [2:0]m_axi_wvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2]" *) input [2:0]m_axi_wready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4]" *) input [5:0]m_axi_bresp; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2]" *) input [2:0]m_axi_bvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2]" *) output [2:0]m_axi_bready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64]" *) output [95:0]m_axi_araddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6]" *) output [8:0]m_axi_arprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2]" *) output [2:0]m_axi_arvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2]" *) input [2:0]m_axi_arready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64]" *) input [95:0]m_axi_rdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4]" *) input [5:0]m_axi_rresp; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2]" *) input [2:0]m_axi_rvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2]" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output [2:0]m_axi_rready; + + wire aclk; + wire aresetn; + wire [95:0]m_axi_araddr; + wire [8:0]m_axi_arprot; + wire [2:0]m_axi_arready; + wire [2:0]m_axi_arvalid; + wire [95:0]m_axi_awaddr; + wire [8:0]m_axi_awprot; + wire [2:0]m_axi_awready; + wire [2:0]m_axi_awvalid; + wire [2:0]m_axi_bready; + wire [5:0]m_axi_bresp; + wire [2:0]m_axi_bvalid; + wire [95:0]m_axi_rdata; + wire [2:0]m_axi_rready; + wire [5:0]m_axi_rresp; + wire [2:0]m_axi_rvalid; + wire [95:0]m_axi_wdata; + wire [2:0]m_axi_wready; + wire [11:0]m_axi_wstrb; + wire [2:0]m_axi_wvalid; + wire [31:0]s_axi_araddr; + wire [2:0]s_axi_arprot; + wire [0:0]s_axi_arready; + wire [0:0]s_axi_arvalid; + wire [31:0]s_axi_awaddr; + wire [2:0]s_axi_awprot; + wire [0:0]s_axi_awready; + wire [0:0]s_axi_awvalid; + wire [0:0]s_axi_bready; + wire [1:0]s_axi_bresp; + wire [0:0]s_axi_bvalid; + wire [31:0]s_axi_rdata; + wire [0:0]s_axi_rready; + wire [1:0]s_axi_rresp; + wire [0:0]s_axi_rvalid; + wire [31:0]s_axi_wdata; + wire [0:0]s_axi_wready; + wire [3:0]s_axi_wstrb; + wire [0:0]s_axi_wvalid; + wire [5:0]NLW_inst_m_axi_arburst_UNCONNECTED; + wire [11:0]NLW_inst_m_axi_arcache_UNCONNECTED; + wire [2:0]NLW_inst_m_axi_arid_UNCONNECTED; + wire [23:0]NLW_inst_m_axi_arlen_UNCONNECTED; + wire [2:0]NLW_inst_m_axi_arlock_UNCONNECTED; + wire [11:0]NLW_inst_m_axi_arqos_UNCONNECTED; + wire [11:0]NLW_inst_m_axi_arregion_UNCONNECTED; + wire [8:0]NLW_inst_m_axi_arsize_UNCONNECTED; + wire [2:0]NLW_inst_m_axi_aruser_UNCONNECTED; + wire [5:0]NLW_inst_m_axi_awburst_UNCONNECTED; + wire [11:0]NLW_inst_m_axi_awcache_UNCONNECTED; + wire [2:0]NLW_inst_m_axi_awid_UNCONNECTED; + wire [23:0]NLW_inst_m_axi_awlen_UNCONNECTED; + wire [2:0]NLW_inst_m_axi_awlock_UNCONNECTED; + wire [11:0]NLW_inst_m_axi_awqos_UNCONNECTED; + wire [11:0]NLW_inst_m_axi_awregion_UNCONNECTED; + wire [8:0]NLW_inst_m_axi_awsize_UNCONNECTED; + wire [2:0]NLW_inst_m_axi_awuser_UNCONNECTED; + wire [2:0]NLW_inst_m_axi_wid_UNCONNECTED; + wire [2:0]NLW_inst_m_axi_wlast_UNCONNECTED; + wire [2:0]NLW_inst_m_axi_wuser_UNCONNECTED; + wire [0:0]NLW_inst_s_axi_bid_UNCONNECTED; + wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED; + wire [0:0]NLW_inst_s_axi_rid_UNCONNECTED; + wire [0:0]NLW_inst_s_axi_rlast_UNCONNECTED; + wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED; + + (* C_AXI_ADDR_WIDTH = "32" *) + (* C_AXI_ARUSER_WIDTH = "1" *) + (* C_AXI_AWUSER_WIDTH = "1" *) + (* C_AXI_BUSER_WIDTH = "1" *) + (* C_AXI_DATA_WIDTH = "32" *) + (* C_AXI_ID_WIDTH = "1" *) + (* C_AXI_PROTOCOL = "2" *) + (* C_AXI_RUSER_WIDTH = "1" *) + (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *) + (* C_AXI_WUSER_WIDTH = "1" *) + (* C_CONNECTIVITY_MODE = "0" *) + (* C_DEBUG = "1" *) + (* C_FAMILY = "zynq" *) + (* C_M_AXI_ADDR_WIDTH = "96'b000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000" *) + (* C_M_AXI_BASE_ADDR = "192'b000000000000000000000000000000000100001111000010000000000000000000000000000000000000000000000000010000111100000100000000000000000000000000000000000000000000000001000011110000000000000000000000" *) + (* C_M_AXI_READ_CONNECTIVITY = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) + (* C_M_AXI_READ_ISSUING = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) + (* C_M_AXI_SECURE = "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) + (* C_M_AXI_WRITE_CONNECTIVITY = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) + (* C_M_AXI_WRITE_ISSUING = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) + (* C_NUM_ADDR_RANGES = "1" *) + (* C_NUM_MASTER_SLOTS = "3" *) + (* C_NUM_SLAVE_SLOTS = "1" *) + (* C_R_REGISTER = "1" *) + (* C_S_AXI_ARB_PRIORITY = "0" *) + (* C_S_AXI_BASE_ID = "0" *) + (* C_S_AXI_READ_ACCEPTANCE = "1" *) + (* C_S_AXI_SINGLE_THREAD = "1" *) + (* C_S_AXI_THREAD_ID_WIDTH = "0" *) + (* C_S_AXI_WRITE_ACCEPTANCE = "1" *) + (* DowngradeIPIdentifiedWarnings = "yes" *) + (* P_ADDR_DECODE = "1" *) + (* P_AXI3 = "1" *) + (* P_AXI4 = "0" *) + (* P_AXILITE = "2" *) + (* P_AXILITE_SIZE = "3'b010" *) + (* P_FAMILY = "zynq" *) + (* P_INCR = "2'b01" *) + (* P_LEN = "8" *) + (* P_LOCK = "1" *) + (* P_M_AXI_ERR_MODE = "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) + (* P_M_AXI_SUPPORTS_READ = "3'b111" *) + (* P_M_AXI_SUPPORTS_WRITE = "3'b111" *) + (* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *) + (* P_RANGE_CHECK = "1" *) + (* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) + (* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) + (* P_S_AXI_SUPPORTS_READ = "1'b1" *) + (* P_S_AXI_SUPPORTS_WRITE = "1'b1" *) + NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar inst + (.aclk(aclk), + .aresetn(aresetn), + .m_axi_araddr(m_axi_araddr), + .m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[5:0]), + .m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[11:0]), + .m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[2:0]), + .m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[23:0]), + .m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[2:0]), + .m_axi_arprot(m_axi_arprot), + .m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[11:0]), + .m_axi_arready(m_axi_arready), + .m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[11:0]), + .m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[8:0]), + .m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[2:0]), + .m_axi_arvalid(m_axi_arvalid), + .m_axi_awaddr(m_axi_awaddr), + .m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[5:0]), + .m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[11:0]), + .m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[2:0]), + .m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[23:0]), + .m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[2:0]), + .m_axi_awprot(m_axi_awprot), + .m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[11:0]), + .m_axi_awready(m_axi_awready), + .m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[11:0]), + .m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[8:0]), + .m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[2:0]), + .m_axi_awvalid(m_axi_awvalid), + .m_axi_bid({1'b0,1'b0,1'b0}), + .m_axi_bready(m_axi_bready), + .m_axi_bresp(m_axi_bresp), + .m_axi_buser({1'b0,1'b0,1'b0}), + .m_axi_bvalid(m_axi_bvalid), + .m_axi_rdata(m_axi_rdata), + .m_axi_rid({1'b0,1'b0,1'b0}), + .m_axi_rlast({1'b1,1'b1,1'b1}), + .m_axi_rready(m_axi_rready), + .m_axi_rresp(m_axi_rresp), + .m_axi_ruser({1'b0,1'b0,1'b0}), + .m_axi_rvalid(m_axi_rvalid), + .m_axi_wdata(m_axi_wdata), + .m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[2:0]), + .m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED[2:0]), + .m_axi_wready(m_axi_wready), + .m_axi_wstrb(m_axi_wstrb), + .m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[2:0]), + .m_axi_wvalid(m_axi_wvalid), + .s_axi_araddr(s_axi_araddr), + .s_axi_arburst({1'b0,1'b0}), + .s_axi_arcache({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arid(1'b0), + .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_arlock(1'b0), + .s_axi_arprot(s_axi_arprot), + .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arready(s_axi_arready), + .s_axi_arsize({1'b0,1'b0,1'b0}), + .s_axi_aruser(1'b0), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awburst({1'b0,1'b0}), + .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awid(1'b0), + .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_awlock(1'b0), + .s_axi_awprot(s_axi_awprot), + .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awready(s_axi_awready), + .s_axi_awsize({1'b0,1'b0,1'b0}), + .s_axi_awuser(1'b0), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_bid(NLW_inst_s_axi_bid_UNCONNECTED[0]), + .s_axi_bready(s_axi_bready), + .s_axi_bresp(s_axi_bresp), + .s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_rdata(s_axi_rdata), + .s_axi_rid(NLW_inst_s_axi_rid_UNCONNECTED[0]), + .s_axi_rlast(NLW_inst_s_axi_rlast_UNCONNECTED[0]), + .s_axi_rready(s_axi_rready), + .s_axi_rresp(s_axi_rresp), + .s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_wdata(s_axi_wdata), + .s_axi_wid(1'b0), + .s_axi_wlast(1'b1), + .s_axi_wready(s_axi_wready), + .s_axi_wstrb(s_axi_wstrb), + .s_axi_wuser(1'b0), + .s_axi_wvalid(s_axi_wvalid)); +endmodule + +(* ORIG_REF_NAME = "axi_crossbar_v2_1_30_addr_arbiter_sasd" *) +module NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_addr_arbiter_sasd + (m_valid_i, + SR, + aa_grant_rnw, + D, + Q, + \gen_no_arbiter.m_amesg_i_reg[19]_0 , + \gen_no_arbiter.m_amesg_i_reg[19]_1 , + m_ready_d0, + \m_ready_d_reg[2] , + s_axi_bvalid, + m_axi_bready, + s_axi_wready, + m_axi_wvalid, + s_axi_wvalid_0_sp_1, + m_axi_awvalid, + \gen_no_arbiter.grant_rnw_reg_0 , + \aresetn_d_reg[0] , + \aresetn_d_reg[1] , + E, + m_axi_arvalid, + \m_ready_d_reg[1] , + s_axi_awready, + s_axi_arready, + s_axi_rvalid, + \m_atarget_hot_reg[3] , + \m_ready_d_reg[2]_0 , + aclk, + aresetn_d, + \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 , + s_axi_arvalid, + s_axi_awvalid, + m_ready_d, + \m_ready_d_reg[2]_1 , + s_axi_bvalid_0_sp_1, + s_axi_bready, + \gen_axilite.s_axi_bvalid_i_reg , + s_axi_wready_0_sp_1, + s_axi_wvalid, + m_valid_i_reg, + aa_rready, + m_valid_i_reg_0, + m_ready_d_0, + s_axi_rready, + sr_rvalid, + \gen_no_arbiter.m_valid_i_reg_0 , + \gen_no_arbiter.m_valid_i_reg_1 , + s_axi_arprot, + s_axi_awprot, + s_axi_araddr, + s_axi_awaddr, + mi_wready, + mi_bvalid); + output m_valid_i; + output [0:0]SR; + output aa_grant_rnw; + output [3:0]D; + output [34:0]Q; + output \gen_no_arbiter.m_amesg_i_reg[19]_0 ; + output \gen_no_arbiter.m_amesg_i_reg[19]_1 ; + output [0:0]m_ready_d0; + output \m_ready_d_reg[2] ; + output [0:0]s_axi_bvalid; + output [2:0]m_axi_bready; + output [0:0]s_axi_wready; + output [2:0]m_axi_wvalid; + output s_axi_wvalid_0_sp_1; + output [2:0]m_axi_awvalid; + output \gen_no_arbiter.grant_rnw_reg_0 ; + output \aresetn_d_reg[0] ; + output \aresetn_d_reg[1] ; + output [0:0]E; + output [2:0]m_axi_arvalid; + output \m_ready_d_reg[1] ; + output [0:0]s_axi_awready; + output [0:0]s_axi_arready; + output [0:0]s_axi_rvalid; + output \m_atarget_hot_reg[3] ; + output \m_ready_d_reg[2]_0 ; + input aclk; + input aresetn_d; + input \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 ; + input [0:0]s_axi_arvalid; + input [0:0]s_axi_awvalid; + input [2:0]m_ready_d; + input \m_ready_d_reg[2]_1 ; + input s_axi_bvalid_0_sp_1; + input [0:0]s_axi_bready; + input [3:0]\gen_axilite.s_axi_bvalid_i_reg ; + input s_axi_wready_0_sp_1; + input [0:0]s_axi_wvalid; + input [1:0]m_valid_i_reg; + input aa_rready; + input m_valid_i_reg_0; + input [1:0]m_ready_d_0; + input [0:0]s_axi_rready; + input sr_rvalid; + input \gen_no_arbiter.m_valid_i_reg_0 ; + input \gen_no_arbiter.m_valid_i_reg_1 ; + input [2:0]s_axi_arprot; + input [2:0]s_axi_awprot; + input [31:0]s_axi_araddr; + input [31:0]s_axi_awaddr; + input [0:0]mi_wready; + input [0:0]mi_bvalid; + + wire [3:0]D; + wire [0:0]E; + wire [34:0]Q; + wire [0:0]SR; + wire aa_grant_rnw; + wire aa_rready; + wire aclk; + wire aresetn_d; + wire \aresetn_d_reg[0] ; + wire \aresetn_d_reg[1] ; + wire \gen_axilite.s_axi_bvalid_i_i_2_n_0 ; + wire \gen_axilite.s_axi_bvalid_i_i_3_n_0 ; + wire [3:0]\gen_axilite.s_axi_bvalid_i_reg ; + wire \gen_no_arbiter.grant_rnw_i_1_n_0 ; + wire \gen_no_arbiter.grant_rnw_reg_0 ; + wire \gen_no_arbiter.m_amesg_i_reg[19]_0 ; + wire \gen_no_arbiter.m_amesg_i_reg[19]_1 ; + wire \gen_no_arbiter.m_grant_hot_i[0]_inv_i_1_n_0 ; + wire \gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_n_0 ; + wire \gen_no_arbiter.m_grant_hot_i[0]_inv_i_4_n_0 ; + wire \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 ; + wire \gen_no_arbiter.m_valid_i_i_1_n_0 ; + wire \gen_no_arbiter.m_valid_i_reg_0 ; + wire \gen_no_arbiter.m_valid_i_reg_1 ; + wire \gen_no_arbiter.s_ready_i[0]_i_1_n_0 ; + wire \m_atarget_hot[3]_i_2_n_0 ; + wire \m_atarget_hot[3]_i_3_n_0 ; + wire \m_atarget_hot[3]_i_4_n_0 ; + wire \m_atarget_hot_reg[3] ; + wire [2:0]m_axi_arvalid; + wire [2:0]m_axi_awvalid; + wire [2:0]m_axi_bready; + wire [2:0]m_axi_wvalid; + wire [2:0]m_ready_d; + wire [0:0]m_ready_d0; + wire [1:0]m_ready_d_0; + wire \m_ready_d_reg[1] ; + wire \m_ready_d_reg[2] ; + wire \m_ready_d_reg[2]_0 ; + wire \m_ready_d_reg[2]_1 ; + wire m_valid_i; + wire m_valid_i_i_2_n_0; + wire m_valid_i_i_3_n_0; + wire [1:0]m_valid_i_reg; + wire m_valid_i_reg_0; + wire [0:0]mi_bvalid; + wire [0:0]mi_wready; + wire p_0_in1_in; + wire [48:1]s_amesg; + wire \s_arvalid_reg[0]_i_1_n_0 ; + wire \s_arvalid_reg_reg_n_0_[0] ; + wire s_awvalid_reg; + wire \s_awvalid_reg[0]_i_1_n_0 ; + wire [31:0]s_axi_araddr; + wire [2:0]s_axi_arprot; + wire [0:0]s_axi_arready; + wire [0:0]s_axi_arvalid; + wire [31:0]s_axi_awaddr; + wire [2:0]s_axi_awprot; + wire [0:0]s_axi_awready; + wire [0:0]s_axi_awvalid; + wire [0:0]s_axi_bready; + wire [0:0]s_axi_bvalid; + wire s_axi_bvalid_0_sn_1; + wire [0:0]s_axi_rready; + wire [0:0]s_axi_rvalid; + wire [0:0]s_axi_wready; + wire s_axi_wready_0_sn_1; + wire [0:0]s_axi_wvalid; + wire s_axi_wvalid_0_sn_1; + wire s_ready_i; + wire sr_rvalid; + + assign s_axi_bvalid_0_sn_1 = s_axi_bvalid_0_sp_1; + assign s_axi_wready_0_sn_1 = s_axi_wready_0_sp_1; + assign s_axi_wvalid_0_sp_1 = s_axi_wvalid_0_sn_1; + LUT6 #( + .INIT(64'hFFFFFDFF00000200)) + \gen_axilite.s_axi_awready_i_i_1 + (.I0(s_axi_wvalid_0_sn_1), + .I1(m_ready_d[2]), + .I2(\gen_no_arbiter.grant_rnw_reg_0 ), + .I3(\gen_axilite.s_axi_bvalid_i_reg [3]), + .I4(mi_bvalid), + .I5(mi_wready), + .O(\m_ready_d_reg[2]_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT2 #( + .INIT(4'hB)) + \gen_axilite.s_axi_awready_i_i_2 + (.I0(aa_grant_rnw), + .I1(m_valid_i), + .O(\gen_no_arbiter.grant_rnw_reg_0 )); + LUT6 #( + .INIT(64'hAAFFAAFF0C000000)) + \gen_axilite.s_axi_bvalid_i_i_1 + (.I0(\gen_axilite.s_axi_bvalid_i_i_2_n_0 ), + .I1(s_axi_wvalid_0_sn_1), + .I2(\gen_axilite.s_axi_bvalid_i_i_3_n_0 ), + .I3(\gen_axilite.s_axi_bvalid_i_reg [3]), + .I4(mi_wready), + .I5(mi_bvalid), + .O(\m_atarget_hot_reg[3] )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT4 #( + .INIT(16'hFBFF)) + \gen_axilite.s_axi_bvalid_i_i_2 + (.I0(aa_grant_rnw), + .I1(m_valid_i), + .I2(m_ready_d[0]), + .I3(s_axi_bready), + .O(\gen_axilite.s_axi_bvalid_i_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT3 #( + .INIT(8'hFB)) + \gen_axilite.s_axi_bvalid_i_i_3 + (.I0(m_ready_d[2]), + .I1(m_valid_i), + .I2(aa_grant_rnw), + .O(\gen_axilite.s_axi_bvalid_i_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT3 #( + .INIT(8'h40)) + \gen_axilite.s_axi_rvalid_i_i_2 + (.I0(m_ready_d_0[1]), + .I1(m_valid_i), + .I2(aa_grant_rnw), + .O(\m_ready_d_reg[1] )); + LUT6 #( + .INIT(64'hFFFF53FF00005000)) + \gen_no_arbiter.grant_rnw_i_1 + (.I0(s_awvalid_reg), + .I1(s_axi_awvalid), + .I2(s_axi_arvalid), + .I3(p_0_in1_in), + .I4(m_valid_i), + .I5(aa_grant_rnw), + .O(\gen_no_arbiter.grant_rnw_i_1_n_0 )); + FDRE \gen_no_arbiter.grant_rnw_reg + (.C(aclk), + .CE(1'b1), + .D(\gen_no_arbiter.grant_rnw_i_1_n_0 ), + .Q(aa_grant_rnw), + .R(SR)); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[10]_i_1 + (.I0(s_axi_araddr[9]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[9]), + .O(s_amesg[10])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[11]_i_1 + (.I0(s_axi_araddr[10]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[10]), + .O(s_amesg[11])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[12]_i_1 + (.I0(s_axi_araddr[11]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[11]), + .O(s_amesg[12])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[13]_i_1 + (.I0(s_axi_araddr[12]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[12]), + .O(s_amesg[13])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[14]_i_1 + (.I0(s_axi_araddr[13]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[13]), + .O(s_amesg[14])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[15]_i_1 + (.I0(s_axi_araddr[14]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[14]), + .O(s_amesg[15])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[16]_i_1 + (.I0(s_axi_araddr[15]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[15]), + .O(s_amesg[16])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[17]_i_1 + (.I0(s_axi_araddr[16]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[16]), + .O(s_amesg[17])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[18]_i_1 + (.I0(s_axi_araddr[17]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[17]), + .O(s_amesg[18])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[19]_i_1 + (.I0(s_axi_araddr[18]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[18]), + .O(s_amesg[19])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[1]_i_1 + (.I0(s_axi_araddr[0]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[0]), + .O(s_amesg[1])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[20]_i_1 + (.I0(s_axi_araddr[19]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[19]), + .O(s_amesg[20])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[21]_i_1 + (.I0(s_axi_araddr[20]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[20]), + .O(s_amesg[21])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[22]_i_1 + (.I0(s_axi_araddr[21]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[21]), + .O(s_amesg[22])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[23]_i_1 + (.I0(s_axi_araddr[22]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[22]), + .O(s_amesg[23])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[24]_i_1 + (.I0(s_axi_araddr[23]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[23]), + .O(s_amesg[24])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[25]_i_1 + (.I0(s_axi_araddr[24]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[24]), + .O(s_amesg[25])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[26]_i_1 + (.I0(s_axi_araddr[25]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[25]), + .O(s_amesg[26])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[27]_i_1 + (.I0(s_axi_araddr[26]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[26]), + .O(s_amesg[27])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[28]_i_1 + (.I0(s_axi_araddr[27]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[27]), + .O(s_amesg[28])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[29]_i_1 + (.I0(s_axi_araddr[28]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[28]), + .O(s_amesg[29])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[2]_i_1 + (.I0(s_axi_araddr[1]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[1]), + .O(s_amesg[2])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[30]_i_1 + (.I0(s_axi_araddr[29]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[29]), + .O(s_amesg[30])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[31]_i_1 + (.I0(s_axi_araddr[30]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[30]), + .O(s_amesg[31])); + LUT1 #( + .INIT(2'h1)) + \gen_no_arbiter.m_amesg_i[32]_i_1 + (.I0(aresetn_d), + .O(SR)); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[32]_i_2 + (.I0(s_axi_araddr[31]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[31]), + .O(s_amesg[32])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[3]_i_1 + (.I0(s_axi_araddr[2]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[2]), + .O(s_amesg[3])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[46]_i_1 + (.I0(s_axi_arprot[0]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awprot[0]), + .O(s_amesg[46])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[47]_i_1 + (.I0(s_axi_arprot[1]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awprot[1]), + .O(s_amesg[47])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[48]_i_1 + (.I0(s_axi_arprot[2]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awprot[2]), + .O(s_amesg[48])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[4]_i_1 + (.I0(s_axi_araddr[3]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[3]), + .O(s_amesg[4])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[5]_i_1 + (.I0(s_axi_araddr[4]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[4]), + .O(s_amesg[5])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[6]_i_1 + (.I0(s_axi_araddr[5]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[5]), + .O(s_amesg[6])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[7]_i_1 + (.I0(s_axi_araddr[6]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[6]), + .O(s_amesg[7])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[8]_i_1 + (.I0(s_axi_araddr[7]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[7]), + .O(s_amesg[8])); + LUT4 #( + .INIT(16'hFB08)) + \gen_no_arbiter.m_amesg_i[9]_i_1 + (.I0(s_axi_araddr[8]), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[8]), + .O(s_amesg[9])); + FDRE \gen_no_arbiter.m_amesg_i_reg[10] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[10]), + .Q(Q[9]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[11] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[11]), + .Q(Q[10]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[12] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[12]), + .Q(Q[11]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[13] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[13]), + .Q(Q[12]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[14] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[14]), + .Q(Q[13]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[15] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[15]), + .Q(Q[14]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[16] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[16]), + .Q(Q[15]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[17] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[17]), + .Q(Q[16]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[18] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[18]), + .Q(Q[17]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[19] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[19]), + .Q(Q[18]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[1] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[1]), + .Q(Q[0]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[20] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[20]), + .Q(Q[19]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[21] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[21]), + .Q(Q[20]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[22] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[22]), + .Q(Q[21]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[23] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[23]), + .Q(Q[22]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[24] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[24]), + .Q(Q[23]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[25] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[25]), + .Q(Q[24]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[26] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[26]), + .Q(Q[25]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[27] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[27]), + .Q(Q[26]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[28] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[28]), + .Q(Q[27]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[29] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[29]), + .Q(Q[28]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[2] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[2]), + .Q(Q[1]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[30] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[30]), + .Q(Q[29]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[31] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[31]), + .Q(Q[30]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[32] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[32]), + .Q(Q[31]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[3] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[3]), + .Q(Q[2]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[46] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[46]), + .Q(Q[32]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[47] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[47]), + .Q(Q[33]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[48] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[48]), + .Q(Q[34]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[4] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[4]), + .Q(Q[3]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[5] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[5]), + .Q(Q[4]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[6] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[6]), + .Q(Q[5]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[7] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[7]), + .Q(Q[6]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[8] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[8]), + .Q(Q[7]), + .R(SR)); + FDRE \gen_no_arbiter.m_amesg_i_reg[9] + (.C(aclk), + .CE(p_0_in1_in), + .D(s_amesg[9]), + .Q(Q[8]), + .R(SR)); + LUT6 #( + .INIT(64'hFFFFFFFF80808C80)) + \gen_no_arbiter.m_grant_hot_i[0]_inv_i_1 + (.I0(\gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_n_0 ), + .I1(m_valid_i), + .I2(aa_grant_rnw), + .I3(m_ready_d0), + .I4(\gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 ), + .I5(\gen_no_arbiter.m_grant_hot_i[0]_inv_i_4_n_0 ), + .O(\gen_no_arbiter.m_grant_hot_i[0]_inv_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT5 #( + .INIT(32'h0000F0F8)) + \gen_no_arbiter.m_grant_hot_i[0]_inv_i_2 + (.I0(aa_grant_rnw), + .I1(m_valid_i), + .I2(m_ready_d_0[1]), + .I3(\gen_no_arbiter.m_valid_i_reg_0 ), + .I4(\gen_no_arbiter.m_valid_i_reg_1 ), + .O(\gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT5 #( + .INIT(32'hD5D5D5F5)) + \gen_no_arbiter.m_grant_hot_i[0]_inv_i_4 + (.I0(aresetn_d), + .I1(m_valid_i), + .I2(p_0_in1_in), + .I3(s_axi_arvalid), + .I4(s_axi_awvalid), + .O(\gen_no_arbiter.m_grant_hot_i[0]_inv_i_4_n_0 )); + (* inverted = "yes" *) + FDRE #( + .INIT(1'b1)) + \gen_no_arbiter.m_grant_hot_i_reg[0]_inv + (.C(aclk), + .CE(1'b1), + .D(\gen_no_arbiter.m_grant_hot_i[0]_inv_i_1_n_0 ), + .Q(p_0_in1_in), + .R(1'b0)); + LUT6 #( + .INIT(64'h35F535F5350535F5)) + \gen_no_arbiter.m_valid_i_i_1 + (.I0(p_0_in1_in), + .I1(\gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_n_0 ), + .I2(m_valid_i), + .I3(aa_grant_rnw), + .I4(m_ready_d0), + .I5(\gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 ), + .O(\gen_no_arbiter.m_valid_i_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \gen_no_arbiter.m_valid_i_reg + (.C(aclk), + .CE(1'b1), + .D(\gen_no_arbiter.m_valid_i_i_1_n_0 ), + .Q(m_valid_i), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h10)) + \gen_no_arbiter.s_ready_i[0]_i_1 + (.I0(m_valid_i), + .I1(p_0_in1_in), + .I2(aresetn_d), + .O(\gen_no_arbiter.s_ready_i[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \gen_no_arbiter.s_ready_i_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\gen_no_arbiter.s_ready_i[0]_i_1_n_0 ), + .Q(s_ready_i), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT4 #( + .INIT(16'hFFFD)) + \m_atarget_enc[0]_i_1 + (.I0(\m_atarget_hot[3]_i_2_n_0 ), + .I1(Q[18]), + .I2(Q[19]), + .I3(Q[16]), + .O(\gen_no_arbiter.m_amesg_i_reg[19]_1 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT4 #( + .INIT(16'hFFFD)) + \m_atarget_enc[1]_i_1 + (.I0(\m_atarget_hot[3]_i_2_n_0 ), + .I1(Q[18]), + .I2(Q[19]), + .I3(Q[17]), + .O(\gen_no_arbiter.m_amesg_i_reg[19]_0 )); + LUT6 #( + .INIT(64'h0000000000000004)) + \m_atarget_hot[0]_i_1 + (.I0(Q[16]), + .I1(\m_atarget_hot[3]_i_2_n_0 ), + .I2(Q[18]), + .I3(Q[19]), + .I4(Q[17]), + .I5(p_0_in1_in), + .O(D[0])); + LUT6 #( + .INIT(64'h0000000000000008)) + \m_atarget_hot[1]_i_1 + (.I0(Q[16]), + .I1(\m_atarget_hot[3]_i_2_n_0 ), + .I2(Q[18]), + .I3(Q[19]), + .I4(Q[17]), + .I5(p_0_in1_in), + .O(D[1])); + LUT6 #( + .INIT(64'h0000000000100000)) + \m_atarget_hot[2]_i_1 + (.I0(Q[19]), + .I1(Q[18]), + .I2(Q[17]), + .I3(Q[16]), + .I4(\m_atarget_hot[3]_i_2_n_0 ), + .I5(p_0_in1_in), + .O(D[2])); + LUT6 #( + .INIT(64'h5555555155515551)) + \m_atarget_hot[3]_i_1 + (.I0(p_0_in1_in), + .I1(\m_atarget_hot[3]_i_2_n_0 ), + .I2(Q[18]), + .I3(Q[19]), + .I4(Q[17]), + .I5(Q[16]), + .O(D[3])); + LUT6 #( + .INIT(64'h0000000000008000)) + \m_atarget_hot[3]_i_2 + (.I0(Q[23]), + .I1(Q[24]), + .I2(Q[22]), + .I3(Q[25]), + .I4(\m_atarget_hot[3]_i_3_n_0 ), + .I5(\m_atarget_hot[3]_i_4_n_0 ), + .O(\m_atarget_hot[3]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFFEF)) + \m_atarget_hot[3]_i_3 + (.I0(Q[31]), + .I1(Q[28]), + .I2(Q[30]), + .I3(Q[27]), + .O(\m_atarget_hot[3]_i_3_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \m_atarget_hot[3]_i_4 + (.I0(Q[29]), + .I1(Q[26]), + .I2(Q[21]), + .I3(Q[20]), + .O(\m_atarget_hot[3]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT4 #( + .INIT(16'h0080)) + \m_axi_arvalid[0]_INST_0 + (.I0(\gen_axilite.s_axi_bvalid_i_reg [0]), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(m_ready_d_0[1]), + .O(m_axi_arvalid[0])); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT4 #( + .INIT(16'h0080)) + \m_axi_arvalid[1]_INST_0 + (.I0(\gen_axilite.s_axi_bvalid_i_reg [1]), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(m_ready_d_0[1]), + .O(m_axi_arvalid[1])); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT4 #( + .INIT(16'h0080)) + \m_axi_arvalid[2]_INST_0 + (.I0(\gen_axilite.s_axi_bvalid_i_reg [2]), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(m_ready_d_0[1]), + .O(m_axi_arvalid[2])); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT4 #( + .INIT(16'h0020)) + \m_axi_awvalid[0]_INST_0 + (.I0(\gen_axilite.s_axi_bvalid_i_reg [0]), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(m_ready_d[2]), + .O(m_axi_awvalid[0])); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT4 #( + .INIT(16'h0020)) + \m_axi_awvalid[1]_INST_0 + (.I0(\gen_axilite.s_axi_bvalid_i_reg [1]), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(m_ready_d[2]), + .O(m_axi_awvalid[1])); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT4 #( + .INIT(16'h0020)) + \m_axi_awvalid[2]_INST_0 + (.I0(\gen_axilite.s_axi_bvalid_i_reg [2]), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(m_ready_d[2]), + .O(m_axi_awvalid[2])); + LUT5 #( + .INIT(32'h00000800)) + \m_axi_bready[0]_INST_0 + (.I0(\gen_axilite.s_axi_bvalid_i_reg [0]), + .I1(s_axi_bready), + .I2(m_ready_d[0]), + .I3(m_valid_i), + .I4(aa_grant_rnw), + .O(m_axi_bready[0])); + LUT5 #( + .INIT(32'h00000800)) + \m_axi_bready[1]_INST_0 + (.I0(\gen_axilite.s_axi_bvalid_i_reg [1]), + .I1(s_axi_bready), + .I2(m_ready_d[0]), + .I3(m_valid_i), + .I4(aa_grant_rnw), + .O(m_axi_bready[1])); + LUT5 #( + .INIT(32'h00000800)) + \m_axi_bready[2]_INST_0 + (.I0(\gen_axilite.s_axi_bvalid_i_reg [2]), + .I1(s_axi_bready), + .I2(m_ready_d[0]), + .I3(m_valid_i), + .I4(aa_grant_rnw), + .O(m_axi_bready[2])); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT5 #( + .INIT(32'h00200000)) + \m_axi_wvalid[0]_INST_0 + (.I0(\gen_axilite.s_axi_bvalid_i_reg [0]), + .I1(m_ready_d[1]), + .I2(m_valid_i), + .I3(aa_grant_rnw), + .I4(s_axi_wvalid), + .O(m_axi_wvalid[0])); + LUT5 #( + .INIT(32'h00200000)) + \m_axi_wvalid[1]_INST_0 + (.I0(\gen_axilite.s_axi_bvalid_i_reg [1]), + .I1(m_ready_d[1]), + .I2(m_valid_i), + .I3(aa_grant_rnw), + .I4(s_axi_wvalid), + .O(m_axi_wvalid[1])); + LUT5 #( + .INIT(32'h00200000)) + \m_axi_wvalid[2]_INST_0 + (.I0(\gen_axilite.s_axi_bvalid_i_reg [2]), + .I1(m_ready_d[1]), + .I2(m_valid_i), + .I3(aa_grant_rnw), + .I4(s_axi_wvalid), + .O(m_axi_wvalid[2])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h0080FFFF)) + \m_payload_i[34]_i_1 + (.I0(s_axi_rready), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(m_ready_d_0[0]), + .I4(sr_rvalid), + .O(E)); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT4 #( + .INIT(16'h4555)) + \m_ready_d[2]_i_2 + (.I0(m_ready_d[2]), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(\m_ready_d_reg[2]_1 ), + .O(\m_ready_d_reg[2] )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT4 #( + .INIT(16'h0020)) + \m_ready_d[2]_i_3 + (.I0(s_axi_wvalid), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(m_ready_d[1]), + .O(s_axi_wvalid_0_sn_1)); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'hF0F4F0F0)) + \m_ready_d[2]_i_4 + (.I0(aa_grant_rnw), + .I1(m_valid_i), + .I2(m_ready_d[0]), + .I3(s_axi_bvalid_0_sn_1), + .I4(s_axi_bready), + .O(m_ready_d0)); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT3 #( + .INIT(8'h8A)) + m_valid_i_i_1 + (.I0(m_valid_i_reg[1]), + .I1(m_valid_i_i_2_n_0), + .I2(m_valid_i_i_3_n_0), + .O(\aresetn_d_reg[1] )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h8AAAAAAA)) + m_valid_i_i_2 + (.I0(sr_rvalid), + .I1(m_ready_d_0[0]), + .I2(m_valid_i), + .I3(aa_grant_rnw), + .I4(s_axi_rready), + .O(m_valid_i_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'hA8AAAAAA)) + m_valid_i_i_3 + (.I0(aa_rready), + .I1(m_valid_i_reg_0), + .I2(m_ready_d_0[0]), + .I3(m_valid_i), + .I4(aa_grant_rnw), + .O(m_valid_i_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT4 #( + .INIT(16'h0040)) + \s_arvalid_reg[0]_i_1 + (.I0(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(aresetn_d), + .I3(s_ready_i), + .O(\s_arvalid_reg[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \s_arvalid_reg_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\s_arvalid_reg[0]_i_1_n_0 ), + .Q(\s_arvalid_reg_reg_n_0_[0] ), + .R(1'b0)); + LUT6 #( + .INIT(64'h0000000000D00000)) + \s_awvalid_reg[0]_i_1 + (.I0(s_axi_arvalid), + .I1(s_awvalid_reg), + .I2(s_axi_awvalid), + .I3(\s_arvalid_reg_reg_n_0_[0] ), + .I4(aresetn_d), + .I5(s_ready_i), + .O(\s_awvalid_reg[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \s_awvalid_reg_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\s_awvalid_reg[0]_i_1_n_0 ), + .Q(s_awvalid_reg), + .R(1'b0)); + LUT2 #( + .INIT(4'h8)) + \s_axi_arready[0]_INST_0 + (.I0(aa_grant_rnw), + .I1(s_ready_i), + .O(s_axi_arready)); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_awready[0]_INST_0 + (.I0(s_ready_i), + .I1(aa_grant_rnw), + .O(s_axi_awready)); + LUT5 #( + .INIT(32'h00000100)) + \s_axi_bvalid[0]_INST_0 + (.I0(p_0_in1_in), + .I1(s_axi_bvalid_0_sn_1), + .I2(m_ready_d[0]), + .I3(m_valid_i), + .I4(aa_grant_rnw), + .O(s_axi_bvalid)); + LUT2 #( + .INIT(4'h4)) + \s_axi_rvalid[0]_INST_0 + (.I0(p_0_in1_in), + .I1(sr_rvalid), + .O(s_axi_rvalid)); + LUT5 #( + .INIT(32'h00000004)) + \s_axi_wready[0]_INST_0 + (.I0(m_ready_d[1]), + .I1(m_valid_i), + .I2(aa_grant_rnw), + .I3(p_0_in1_in), + .I4(s_axi_wready_0_sn_1), + .O(s_axi_wready)); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT3 #( + .INIT(8'h8A)) + s_ready_i_i_1 + (.I0(m_valid_i_reg[0]), + .I1(m_valid_i_i_3_n_0), + .I2(m_valid_i_i_2_n_0), + .O(\aresetn_d_reg[0] )); +endmodule + +(* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) +(* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "32" *) (* C_AXI_ID_WIDTH = "1" *) +(* C_AXI_PROTOCOL = "2" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *) +(* C_AXI_WUSER_WIDTH = "1" *) (* C_CONNECTIVITY_MODE = "0" *) (* C_DEBUG = "1" *) +(* C_FAMILY = "zynq" *) (* C_M_AXI_ADDR_WIDTH = "96'b000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000" *) (* C_M_AXI_BASE_ADDR = "192'b000000000000000000000000000000000100001111000010000000000000000000000000000000000000000000000000010000111100000100000000000000000000000000000000000000000000000001000011110000000000000000000000" *) +(* C_M_AXI_READ_CONNECTIVITY = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_READ_ISSUING = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_SECURE = "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) +(* C_M_AXI_WRITE_CONNECTIVITY = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_WRITE_ISSUING = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_NUM_ADDR_RANGES = "1" *) +(* C_NUM_MASTER_SLOTS = "3" *) (* C_NUM_SLAVE_SLOTS = "1" *) (* C_R_REGISTER = "1" *) +(* C_S_AXI_ARB_PRIORITY = "0" *) (* C_S_AXI_BASE_ID = "0" *) (* C_S_AXI_READ_ACCEPTANCE = "1" *) +(* C_S_AXI_SINGLE_THREAD = "1" *) (* C_S_AXI_THREAD_ID_WIDTH = "0" *) (* C_S_AXI_WRITE_ACCEPTANCE = "1" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "axi_crossbar_v2_1_30_axi_crossbar" *) (* P_ADDR_DECODE = "1" *) +(* P_AXI3 = "1" *) (* P_AXI4 = "0" *) (* P_AXILITE = "2" *) +(* P_AXILITE_SIZE = "3'b010" *) (* P_FAMILY = "zynq" *) (* P_INCR = "2'b01" *) +(* P_LEN = "8" *) (* P_LOCK = "1" *) (* P_M_AXI_ERR_MODE = "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) +(* P_M_AXI_SUPPORTS_READ = "3'b111" *) (* P_M_AXI_SUPPORTS_WRITE = "3'b111" *) (* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *) +(* P_RANGE_CHECK = "1" *) (* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) +(* P_S_AXI_SUPPORTS_READ = "1'b1" *) (* P_S_AXI_SUPPORTS_WRITE = "1'b1" *) +module NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar + (aclk, + aresetn, + s_axi_awid, + s_axi_awaddr, + s_axi_awlen, + s_axi_awsize, + s_axi_awburst, + s_axi_awlock, + s_axi_awcache, + s_axi_awprot, + s_axi_awqos, + s_axi_awuser, + s_axi_awvalid, + s_axi_awready, + s_axi_wid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wlast, + s_axi_wuser, + s_axi_wvalid, + s_axi_wready, + s_axi_bid, + s_axi_bresp, + s_axi_buser, + s_axi_bvalid, + s_axi_bready, + s_axi_arid, + s_axi_araddr, + s_axi_arlen, + s_axi_arsize, + s_axi_arburst, + s_axi_arlock, + s_axi_arcache, + s_axi_arprot, + s_axi_arqos, + s_axi_aruser, + s_axi_arvalid, + s_axi_arready, + s_axi_rid, + s_axi_rdata, + s_axi_rresp, + s_axi_rlast, + s_axi_ruser, + s_axi_rvalid, + s_axi_rready, + m_axi_awid, + m_axi_awaddr, + m_axi_awlen, + m_axi_awsize, + m_axi_awburst, + m_axi_awlock, + m_axi_awcache, + m_axi_awprot, + m_axi_awregion, + m_axi_awqos, + m_axi_awuser, + m_axi_awvalid, + m_axi_awready, + m_axi_wid, + m_axi_wdata, + m_axi_wstrb, + m_axi_wlast, + m_axi_wuser, + m_axi_wvalid, + m_axi_wready, + m_axi_bid, + m_axi_bresp, + m_axi_buser, + m_axi_bvalid, + m_axi_bready, + m_axi_arid, + m_axi_araddr, + m_axi_arlen, + m_axi_arsize, + m_axi_arburst, + m_axi_arlock, + m_axi_arcache, + m_axi_arprot, + m_axi_arregion, + m_axi_arqos, + m_axi_aruser, + m_axi_arvalid, + m_axi_arready, + m_axi_rid, + m_axi_rdata, + m_axi_rresp, + m_axi_rlast, + m_axi_ruser, + m_axi_rvalid, + m_axi_rready); + input aclk; + input aresetn; + input [0:0]s_axi_awid; + input [31:0]s_axi_awaddr; + input [7:0]s_axi_awlen; + input [2:0]s_axi_awsize; + input [1:0]s_axi_awburst; + input [0:0]s_axi_awlock; + input [3:0]s_axi_awcache; + input [2:0]s_axi_awprot; + input [3:0]s_axi_awqos; + input [0:0]s_axi_awuser; + input [0:0]s_axi_awvalid; + output [0:0]s_axi_awready; + input [0:0]s_axi_wid; + input [31:0]s_axi_wdata; + input [3:0]s_axi_wstrb; + input [0:0]s_axi_wlast; + input [0:0]s_axi_wuser; + input [0:0]s_axi_wvalid; + output [0:0]s_axi_wready; + output [0:0]s_axi_bid; + output [1:0]s_axi_bresp; + output [0:0]s_axi_buser; + output [0:0]s_axi_bvalid; + input [0:0]s_axi_bready; + input [0:0]s_axi_arid; + input [31:0]s_axi_araddr; + input [7:0]s_axi_arlen; + input [2:0]s_axi_arsize; + input [1:0]s_axi_arburst; + input [0:0]s_axi_arlock; + input [3:0]s_axi_arcache; + input [2:0]s_axi_arprot; + input [3:0]s_axi_arqos; + input [0:0]s_axi_aruser; + input [0:0]s_axi_arvalid; + output [0:0]s_axi_arready; + output [0:0]s_axi_rid; + output [31:0]s_axi_rdata; + output [1:0]s_axi_rresp; + output [0:0]s_axi_rlast; + output [0:0]s_axi_ruser; + output [0:0]s_axi_rvalid; + input [0:0]s_axi_rready; + output [2:0]m_axi_awid; + output [95:0]m_axi_awaddr; + output [23:0]m_axi_awlen; + output [8:0]m_axi_awsize; + output [5:0]m_axi_awburst; + output [2:0]m_axi_awlock; + output [11:0]m_axi_awcache; + output [8:0]m_axi_awprot; + output [11:0]m_axi_awregion; + output [11:0]m_axi_awqos; + output [2:0]m_axi_awuser; + output [2:0]m_axi_awvalid; + input [2:0]m_axi_awready; + output [2:0]m_axi_wid; + output [95:0]m_axi_wdata; + output [11:0]m_axi_wstrb; + output [2:0]m_axi_wlast; + output [2:0]m_axi_wuser; + output [2:0]m_axi_wvalid; + input [2:0]m_axi_wready; + input [2:0]m_axi_bid; + input [5:0]m_axi_bresp; + input [2:0]m_axi_buser; + input [2:0]m_axi_bvalid; + output [2:0]m_axi_bready; + output [2:0]m_axi_arid; + output [95:0]m_axi_araddr; + output [23:0]m_axi_arlen; + output [8:0]m_axi_arsize; + output [5:0]m_axi_arburst; + output [2:0]m_axi_arlock; + output [11:0]m_axi_arcache; + output [8:0]m_axi_arprot; + output [11:0]m_axi_arregion; + output [11:0]m_axi_arqos; + output [2:0]m_axi_aruser; + output [2:0]m_axi_arvalid; + input [2:0]m_axi_arready; + input [2:0]m_axi_rid; + input [95:0]m_axi_rdata; + input [5:0]m_axi_rresp; + input [2:0]m_axi_rlast; + input [2:0]m_axi_ruser; + input [2:0]m_axi_rvalid; + output [2:0]m_axi_rready; + + wire \ ; + wire aclk; + wire aresetn; + wire [15:0]\^m_axi_araddr ; + wire [2:0]\^m_axi_arprot ; + wire [2:0]m_axi_arready; + wire [2:0]m_axi_arvalid; + wire [95:80]\^m_axi_awaddr ; + wire [2:0]m_axi_awready; + wire [2:0]m_axi_awvalid; + wire [2:0]m_axi_bready; + wire [5:0]m_axi_bresp; + wire [2:0]m_axi_bvalid; + wire [95:0]m_axi_rdata; + wire [2:0]m_axi_rready; + wire [5:0]m_axi_rresp; + wire [2:0]m_axi_rvalid; + wire [2:0]m_axi_wready; + wire [2:0]m_axi_wvalid; + wire [31:0]s_axi_araddr; + wire [2:0]s_axi_arprot; + wire [0:0]s_axi_arready; + wire [0:0]s_axi_arvalid; + wire [31:0]s_axi_awaddr; + wire [2:0]s_axi_awprot; + wire [0:0]s_axi_awready; + wire [0:0]s_axi_awvalid; + wire [0:0]s_axi_bready; + wire [1:0]s_axi_bresp; + wire [0:0]s_axi_bvalid; + wire [31:0]s_axi_rdata; + wire [0:0]s_axi_rready; + wire [1:0]s_axi_rresp; + wire [0:0]s_axi_rvalid; + wire [31:0]s_axi_wdata; + wire [0:0]s_axi_wready; + wire [3:0]s_axi_wstrb; + wire [0:0]s_axi_wvalid; + + assign m_axi_araddr[95:80] = \^m_axi_awaddr [95:80]; + assign m_axi_araddr[79:64] = \^m_axi_araddr [15:0]; + assign m_axi_araddr[63:48] = \^m_axi_awaddr [95:80]; + assign m_axi_araddr[47:32] = \^m_axi_araddr [15:0]; + assign m_axi_araddr[31:16] = \^m_axi_awaddr [95:80]; + assign m_axi_araddr[15:0] = \^m_axi_araddr [15:0]; + assign m_axi_arburst[5] = \ ; + assign m_axi_arburst[4] = \ ; + assign m_axi_arburst[3] = \ ; + assign m_axi_arburst[2] = \ ; + assign m_axi_arburst[1] = \ ; + assign m_axi_arburst[0] = \ ; + assign m_axi_arcache[11] = \ ; + assign m_axi_arcache[10] = \ ; + assign m_axi_arcache[9] = \ ; + assign m_axi_arcache[8] = \ ; + assign m_axi_arcache[7] = \ ; + assign m_axi_arcache[6] = \ ; + assign m_axi_arcache[5] = \ ; + assign m_axi_arcache[4] = \ ; + assign m_axi_arcache[3] = \ ; + assign m_axi_arcache[2] = \ ; + assign m_axi_arcache[1] = \ ; + assign m_axi_arcache[0] = \ ; + assign m_axi_arid[2] = \ ; + assign m_axi_arid[1] = \ ; + assign m_axi_arid[0] = \ ; + assign m_axi_arlen[23] = \ ; + assign m_axi_arlen[22] = \ ; + assign m_axi_arlen[21] = \ ; + assign m_axi_arlen[20] = \ ; + assign m_axi_arlen[19] = \ ; + assign m_axi_arlen[18] = \ ; + assign m_axi_arlen[17] = \ ; + assign m_axi_arlen[16] = \ ; + assign m_axi_arlen[15] = \ ; + assign m_axi_arlen[14] = \ ; + assign m_axi_arlen[13] = \ ; + assign m_axi_arlen[12] = \ ; + assign m_axi_arlen[11] = \ ; + assign m_axi_arlen[10] = \ ; + assign m_axi_arlen[9] = \ ; + assign m_axi_arlen[8] = \ ; + assign m_axi_arlen[7] = \ ; + assign m_axi_arlen[6] = \ ; + assign m_axi_arlen[5] = \ ; + assign m_axi_arlen[4] = \ ; + assign m_axi_arlen[3] = \ ; + assign m_axi_arlen[2] = \ ; + assign m_axi_arlen[1] = \ ; + assign m_axi_arlen[0] = \ ; + assign m_axi_arlock[2] = \ ; + assign m_axi_arlock[1] = \ ; + assign m_axi_arlock[0] = \ ; + assign m_axi_arprot[8:6] = \^m_axi_arprot [2:0]; + assign m_axi_arprot[5:3] = \^m_axi_arprot [2:0]; + assign m_axi_arprot[2:0] = \^m_axi_arprot [2:0]; + assign m_axi_arqos[11] = \ ; + assign m_axi_arqos[10] = \ ; + assign m_axi_arqos[9] = \ ; + assign m_axi_arqos[8] = \ ; + assign m_axi_arqos[7] = \ ; + assign m_axi_arqos[6] = \ ; + assign m_axi_arqos[5] = \ ; + assign m_axi_arqos[4] = \ ; + assign m_axi_arqos[3] = \ ; + assign m_axi_arqos[2] = \ ; + assign m_axi_arqos[1] = \ ; + assign m_axi_arqos[0] = \ ; + assign m_axi_arregion[11] = \ ; + assign m_axi_arregion[10] = \ ; + assign m_axi_arregion[9] = \ ; + assign m_axi_arregion[8] = \ ; + assign m_axi_arregion[7] = \ ; + assign m_axi_arregion[6] = \ ; + assign m_axi_arregion[5] = \ ; + assign m_axi_arregion[4] = \ ; + assign m_axi_arregion[3] = \ ; + assign m_axi_arregion[2] = \ ; + assign m_axi_arregion[1] = \ ; + assign m_axi_arregion[0] = \ ; + assign m_axi_arsize[8] = \ ; + assign m_axi_arsize[7] = \ ; + assign m_axi_arsize[6] = \ ; + assign m_axi_arsize[5] = \ ; + assign m_axi_arsize[4] = \ ; + assign m_axi_arsize[3] = \ ; + assign m_axi_arsize[2] = \ ; + assign m_axi_arsize[1] = \ ; + assign m_axi_arsize[0] = \ ; + assign m_axi_aruser[2] = \ ; + assign m_axi_aruser[1] = \ ; + assign m_axi_aruser[0] = \ ; + assign m_axi_awaddr[95:80] = \^m_axi_awaddr [95:80]; + assign m_axi_awaddr[79:64] = \^m_axi_araddr [15:0]; + assign m_axi_awaddr[63:48] = \^m_axi_awaddr [95:80]; + assign m_axi_awaddr[47:32] = \^m_axi_araddr [15:0]; + assign m_axi_awaddr[31:16] = \^m_axi_awaddr [95:80]; + assign m_axi_awaddr[15:0] = \^m_axi_araddr [15:0]; + assign m_axi_awburst[5] = \ ; + assign m_axi_awburst[4] = \ ; + assign m_axi_awburst[3] = \ ; + assign m_axi_awburst[2] = \ ; + assign m_axi_awburst[1] = \ ; + assign m_axi_awburst[0] = \ ; + assign m_axi_awcache[11] = \ ; + assign m_axi_awcache[10] = \ ; + assign m_axi_awcache[9] = \ ; + assign m_axi_awcache[8] = \ ; + assign m_axi_awcache[7] = \ ; + assign m_axi_awcache[6] = \ ; + assign m_axi_awcache[5] = \ ; + assign m_axi_awcache[4] = \ ; + assign m_axi_awcache[3] = \ ; + assign m_axi_awcache[2] = \ ; + assign m_axi_awcache[1] = \ ; + assign m_axi_awcache[0] = \ ; + assign m_axi_awid[2] = \ ; + assign m_axi_awid[1] = \ ; + assign m_axi_awid[0] = \ ; + assign m_axi_awlen[23] = \ ; + assign m_axi_awlen[22] = \ ; + assign m_axi_awlen[21] = \ ; + assign m_axi_awlen[20] = \ ; + assign m_axi_awlen[19] = \ ; + assign m_axi_awlen[18] = \ ; + assign m_axi_awlen[17] = \ ; + assign m_axi_awlen[16] = \ ; + assign m_axi_awlen[15] = \ ; + assign m_axi_awlen[14] = \ ; + assign m_axi_awlen[13] = \ ; + assign m_axi_awlen[12] = \ ; + assign m_axi_awlen[11] = \ ; + assign m_axi_awlen[10] = \ ; + assign m_axi_awlen[9] = \ ; + assign m_axi_awlen[8] = \ ; + assign m_axi_awlen[7] = \ ; + assign m_axi_awlen[6] = \ ; + assign m_axi_awlen[5] = \ ; + assign m_axi_awlen[4] = \ ; + assign m_axi_awlen[3] = \ ; + assign m_axi_awlen[2] = \ ; + assign m_axi_awlen[1] = \ ; + assign m_axi_awlen[0] = \ ; + assign m_axi_awlock[2] = \ ; + assign m_axi_awlock[1] = \ ; + assign m_axi_awlock[0] = \ ; + assign m_axi_awprot[8:6] = \^m_axi_arprot [2:0]; + assign m_axi_awprot[5:3] = \^m_axi_arprot [2:0]; + assign m_axi_awprot[2:0] = \^m_axi_arprot [2:0]; + assign m_axi_awqos[11] = \ ; + assign m_axi_awqos[10] = \ ; + assign m_axi_awqos[9] = \ ; + assign m_axi_awqos[8] = \ ; + assign m_axi_awqos[7] = \ ; + assign m_axi_awqos[6] = \ ; + assign m_axi_awqos[5] = \ ; + assign m_axi_awqos[4] = \ ; + assign m_axi_awqos[3] = \ ; + assign m_axi_awqos[2] = \ ; + assign m_axi_awqos[1] = \ ; + assign m_axi_awqos[0] = \ ; + assign m_axi_awregion[11] = \ ; + assign m_axi_awregion[10] = \ ; + assign m_axi_awregion[9] = \ ; + assign m_axi_awregion[8] = \ ; + assign m_axi_awregion[7] = \ ; + assign m_axi_awregion[6] = \ ; + assign m_axi_awregion[5] = \ ; + assign m_axi_awregion[4] = \ ; + assign m_axi_awregion[3] = \ ; + assign m_axi_awregion[2] = \ ; + assign m_axi_awregion[1] = \ ; + assign m_axi_awregion[0] = \ ; + assign m_axi_awsize[8] = \ ; + assign m_axi_awsize[7] = \ ; + assign m_axi_awsize[6] = \ ; + assign m_axi_awsize[5] = \ ; + assign m_axi_awsize[4] = \ ; + assign m_axi_awsize[3] = \ ; + assign m_axi_awsize[2] = \ ; + assign m_axi_awsize[1] = \ ; + assign m_axi_awsize[0] = \ ; + assign m_axi_awuser[2] = \ ; + assign m_axi_awuser[1] = \ ; + assign m_axi_awuser[0] = \ ; + assign m_axi_wdata[95:64] = s_axi_wdata; + assign m_axi_wdata[63:32] = s_axi_wdata; + assign m_axi_wdata[31:0] = s_axi_wdata; + assign m_axi_wid[2] = \ ; + assign m_axi_wid[1] = \ ; + assign m_axi_wid[0] = \ ; + assign m_axi_wlast[2] = \ ; + assign m_axi_wlast[1] = \ ; + assign m_axi_wlast[0] = \ ; + assign m_axi_wstrb[11:8] = s_axi_wstrb; + assign m_axi_wstrb[7:4] = s_axi_wstrb; + assign m_axi_wstrb[3:0] = s_axi_wstrb; + assign m_axi_wuser[2] = \ ; + assign m_axi_wuser[1] = \ ; + assign m_axi_wuser[0] = \ ; + assign s_axi_bid[0] = \ ; + assign s_axi_buser[0] = \ ; + assign s_axi_rid[0] = \ ; + assign s_axi_rlast[0] = \ ; + assign s_axi_ruser[0] = \ ; + GND GND + (.G(\ )); + NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_crossbar_sasd \gen_sasd.crossbar_sasd_0 + (.Q({\^m_axi_arprot ,\^m_axi_awaddr ,\^m_axi_araddr }), + .aclk(aclk), + .aresetn(aresetn), + .m_axi_arready(m_axi_arready), + .m_axi_arvalid(m_axi_arvalid), + .m_axi_awready(m_axi_awready), + .m_axi_awvalid(m_axi_awvalid), + .m_axi_bready(m_axi_bready), + .m_axi_bresp(m_axi_bresp), + .m_axi_bvalid(m_axi_bvalid), + .m_axi_rdata(m_axi_rdata), + .m_axi_rready(m_axi_rready), + .m_axi_rresp(m_axi_rresp), + .m_axi_rvalid(m_axi_rvalid), + .m_axi_wready(m_axi_wready), + .m_axi_wvalid(m_axi_wvalid), + .\m_payload_i_reg[34] ({s_axi_rdata,s_axi_rresp}), + .s_axi_araddr(s_axi_araddr), + .s_axi_arprot(s_axi_arprot), + .s_axi_arready(s_axi_arready), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awprot(s_axi_awprot), + .s_axi_awready(s_axi_awready), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_bready(s_axi_bready), + .s_axi_bresp(s_axi_bresp), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_rready(s_axi_rready), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_wready(s_axi_wready), + .s_axi_wvalid(s_axi_wvalid)); +endmodule + +(* ORIG_REF_NAME = "axi_crossbar_v2_1_30_crossbar_sasd" *) +module NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_crossbar_sasd + (Q, + \m_payload_i_reg[34] , + s_axi_bvalid, + m_axi_bready, + s_axi_wready, + m_axi_wvalid, + m_axi_awvalid, + m_axi_arvalid, + s_axi_bresp, + s_axi_awready, + s_axi_arready, + s_axi_rvalid, + m_axi_rready, + aresetn, + aclk, + s_axi_arvalid, + s_axi_awvalid, + s_axi_wvalid, + s_axi_bready, + s_axi_rready, + m_axi_rresp, + m_axi_rdata, + m_axi_rvalid, + m_axi_wready, + m_axi_awready, + m_axi_bvalid, + m_axi_arready, + m_axi_bresp, + s_axi_arprot, + s_axi_awprot, + s_axi_araddr, + s_axi_awaddr); + output [34:0]Q; + output [33:0]\m_payload_i_reg[34] ; + output [0:0]s_axi_bvalid; + output [2:0]m_axi_bready; + output [0:0]s_axi_wready; + output [2:0]m_axi_wvalid; + output [2:0]m_axi_awvalid; + output [2:0]m_axi_arvalid; + output [1:0]s_axi_bresp; + output [0:0]s_axi_awready; + output [0:0]s_axi_arready; + output [0:0]s_axi_rvalid; + output [2:0]m_axi_rready; + input aresetn; + input aclk; + input [0:0]s_axi_arvalid; + input [0:0]s_axi_awvalid; + input [0:0]s_axi_wvalid; + input [0:0]s_axi_bready; + input [0:0]s_axi_rready; + input [5:0]m_axi_rresp; + input [95:0]m_axi_rdata; + input [2:0]m_axi_rvalid; + input [2:0]m_axi_wready; + input [2:0]m_axi_awready; + input [2:0]m_axi_bvalid; + input [2:0]m_axi_arready; + input [5:0]m_axi_bresp; + input [2:0]s_axi_arprot; + input [2:0]s_axi_awprot; + input [31:0]s_axi_araddr; + input [31:0]s_axi_awaddr; + + wire [34:0]Q; + wire aa_grant_rnw; + wire aa_rready; + wire aclk; + wire addr_arbiter_inst_n_4; + wire addr_arbiter_inst_n_42; + wire addr_arbiter_inst_n_43; + wire addr_arbiter_inst_n_45; + wire addr_arbiter_inst_n_54; + wire addr_arbiter_inst_n_58; + wire addr_arbiter_inst_n_59; + wire addr_arbiter_inst_n_60; + wire addr_arbiter_inst_n_65; + wire addr_arbiter_inst_n_69; + wire addr_arbiter_inst_n_70; + wire aresetn; + wire aresetn_d; + wire \gen_decerr.decerr_slave_inst_n_2 ; + wire \gen_decerr.decerr_slave_inst_n_3 ; + wire \gen_decerr.decerr_slave_inst_n_4 ; + wire \gen_decerr.decerr_slave_inst_n_5 ; + wire \gen_decerr.decerr_slave_inst_n_6 ; + wire [1:0]m_atarget_enc; + wire [3:0]m_atarget_hot; + wire [3:0]m_atarget_hot0; + wire [2:0]m_axi_arready; + wire [2:0]m_axi_arvalid; + wire [2:0]m_axi_awready; + wire [2:0]m_axi_awvalid; + wire [2:0]m_axi_bready; + wire [5:0]m_axi_bresp; + wire [2:0]m_axi_bvalid; + wire [95:0]m_axi_rdata; + wire [2:0]m_axi_rready; + wire [5:0]m_axi_rresp; + wire [2:0]m_axi_rvalid; + wire [2:0]m_axi_wready; + wire [2:0]m_axi_wvalid; + wire [33:0]\m_payload_i_reg[34] ; + wire [1:0]m_ready_d; + wire [0:0]m_ready_d0; + wire [2:0]m_ready_d_0; + wire m_valid_i; + wire [3:3]mi_bvalid; + wire [3:3]mi_wready; + wire p_1_in; + wire reg_slice_r_n_2; + wire reg_slice_r_n_6; + wire reg_slice_r_n_7; + wire reset; + wire [31:0]s_axi_araddr; + wire [2:0]s_axi_arprot; + wire [0:0]s_axi_arready; + wire [0:0]s_axi_arvalid; + wire [31:0]s_axi_awaddr; + wire [2:0]s_axi_awprot; + wire [0:0]s_axi_awready; + wire [0:0]s_axi_awvalid; + wire [0:0]s_axi_bready; + wire [1:0]s_axi_bresp; + wire [0:0]s_axi_bvalid; + wire [0:0]s_axi_rready; + wire [0:0]s_axi_rvalid; + wire [0:0]s_axi_wready; + wire [0:0]s_axi_wvalid; + wire splitter_aw_n_0; + wire sr_rvalid; + + NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_addr_arbiter_sasd addr_arbiter_inst + (.D({m_atarget_hot0[3],addr_arbiter_inst_n_4,m_atarget_hot0[1:0]}), + .E(p_1_in), + .Q(Q), + .SR(reset), + .aa_grant_rnw(aa_grant_rnw), + .aa_rready(aa_rready), + .aclk(aclk), + .aresetn_d(aresetn_d), + .\aresetn_d_reg[0] (addr_arbiter_inst_n_59), + .\aresetn_d_reg[1] (addr_arbiter_inst_n_60), + .\gen_axilite.s_axi_bvalid_i_reg (m_atarget_hot), + .\gen_no_arbiter.grant_rnw_reg_0 (addr_arbiter_inst_n_58), + .\gen_no_arbiter.m_amesg_i_reg[19]_0 (addr_arbiter_inst_n_42), + .\gen_no_arbiter.m_amesg_i_reg[19]_1 (addr_arbiter_inst_n_43), + .\gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 (splitter_aw_n_0), + .\gen_no_arbiter.m_valid_i_reg_0 (\gen_decerr.decerr_slave_inst_n_6 ), + .\gen_no_arbiter.m_valid_i_reg_1 (reg_slice_r_n_2), + .\m_atarget_hot_reg[3] (addr_arbiter_inst_n_69), + .m_axi_arvalid(m_axi_arvalid), + .m_axi_awvalid(m_axi_awvalid), + .m_axi_bready(m_axi_bready), + .m_axi_wvalid(m_axi_wvalid), + .m_ready_d(m_ready_d_0), + .m_ready_d0(m_ready_d0), + .m_ready_d_0(m_ready_d), + .\m_ready_d_reg[1] (addr_arbiter_inst_n_65), + .\m_ready_d_reg[2] (addr_arbiter_inst_n_45), + .\m_ready_d_reg[2]_0 (addr_arbiter_inst_n_70), + .\m_ready_d_reg[2]_1 (\gen_decerr.decerr_slave_inst_n_4 ), + .m_valid_i(m_valid_i), + .m_valid_i_reg({reg_slice_r_n_6,reg_slice_r_n_7}), + .m_valid_i_reg_0(\gen_decerr.decerr_slave_inst_n_2 ), + .mi_bvalid(mi_bvalid), + .mi_wready(mi_wready), + .s_axi_araddr(s_axi_araddr), + .s_axi_arprot(s_axi_arprot), + .s_axi_arready(s_axi_arready), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awprot(s_axi_awprot), + .s_axi_awready(s_axi_awready), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_bready(s_axi_bready), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_bvalid_0_sp_1(\gen_decerr.decerr_slave_inst_n_5 ), + .s_axi_rready(s_axi_rready), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_wready(s_axi_wready), + .s_axi_wready_0_sp_1(\gen_decerr.decerr_slave_inst_n_3 ), + .s_axi_wvalid(s_axi_wvalid), + .s_axi_wvalid_0_sp_1(addr_arbiter_inst_n_54), + .sr_rvalid(sr_rvalid)); + FDRE #( + .INIT(1'b0)) + aresetn_d_reg + (.C(aclk), + .CE(1'b1), + .D(aresetn), + .Q(aresetn_d), + .R(1'b0)); + NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_decerr_slave \gen_decerr.decerr_slave_inst + (.Q(m_atarget_hot[3]), + .SR(reset), + .aa_rready(aa_rready), + .aclk(aclk), + .aresetn_d(aresetn_d), + .\gen_axilite.s_axi_awready_i_reg_0 (\gen_decerr.decerr_slave_inst_n_3 ), + .\gen_axilite.s_axi_awready_i_reg_1 (addr_arbiter_inst_n_70), + .\gen_axilite.s_axi_bvalid_i_reg_0 (addr_arbiter_inst_n_69), + .\gen_axilite.s_axi_rvalid_i_reg_0 (addr_arbiter_inst_n_65), + .m_axi_arready(m_axi_arready), + .m_axi_arready_2_sp_1(\gen_decerr.decerr_slave_inst_n_6 ), + .m_axi_awready(m_axi_awready), + .m_axi_awready_2_sp_1(\gen_decerr.decerr_slave_inst_n_4 ), + .m_axi_bvalid(m_axi_bvalid), + .m_axi_bvalid_2_sp_1(\gen_decerr.decerr_slave_inst_n_5 ), + .m_axi_rvalid(m_axi_rvalid), + .m_axi_rvalid_1_sp_1(\gen_decerr.decerr_slave_inst_n_2 ), + .m_axi_wready(m_axi_wready), + .\m_ready_d_reg[2] (m_atarget_enc), + .mi_bvalid(mi_bvalid), + .mi_wready(mi_wready)); + FDRE #( + .INIT(1'b0)) + \m_atarget_enc_reg[0] + (.C(aclk), + .CE(1'b1), + .D(addr_arbiter_inst_n_43), + .Q(m_atarget_enc[0]), + .R(reset)); + FDRE #( + .INIT(1'b0)) + \m_atarget_enc_reg[1] + (.C(aclk), + .CE(1'b1), + .D(addr_arbiter_inst_n_42), + .Q(m_atarget_enc[1]), + .R(reset)); + FDRE #( + .INIT(1'b0)) + \m_atarget_hot_reg[0] + (.C(aclk), + .CE(1'b1), + .D(m_atarget_hot0[0]), + .Q(m_atarget_hot[0]), + .R(reset)); + FDRE #( + .INIT(1'b0)) + \m_atarget_hot_reg[1] + (.C(aclk), + .CE(1'b1), + .D(m_atarget_hot0[1]), + .Q(m_atarget_hot[1]), + .R(reset)); + FDRE #( + .INIT(1'b0)) + \m_atarget_hot_reg[2] + (.C(aclk), + .CE(1'b1), + .D(addr_arbiter_inst_n_4), + .Q(m_atarget_hot[2]), + .R(reset)); + FDRE #( + .INIT(1'b0)) + \m_atarget_hot_reg[3] + (.C(aclk), + .CE(1'b1), + .D(m_atarget_hot0[3]), + .Q(m_atarget_hot[3]), + .R(reset)); + NewExtInst_TOP_xbar_0_axi_register_slice_v2_1_29_axic_register_slice reg_slice_r + (.E(p_1_in), + .Q(m_atarget_enc), + .SR(reset), + .aa_grant_rnw(aa_grant_rnw), + .aa_rready(aa_rready), + .aclk(aclk), + .\aresetn_d_reg[1]_0 ({reg_slice_r_n_6,reg_slice_r_n_7}), + .m_axi_rdata(m_axi_rdata), + .m_axi_rready(m_axi_rready), + .\m_axi_rready[2] (m_atarget_hot[2:0]), + .m_axi_rresp(m_axi_rresp), + .\m_payload_i_reg[34]_0 (\m_payload_i_reg[34] ), + .m_ready_d(m_ready_d[0]), + .m_valid_i(m_valid_i), + .m_valid_i_reg_0(reg_slice_r_n_2), + .m_valid_i_reg_1(addr_arbiter_inst_n_60), + .s_axi_rready(s_axi_rready), + .s_ready_i_reg_0(addr_arbiter_inst_n_59), + .sr_rvalid(sr_rvalid)); + LUT5 #( + .INIT(32'hFCEEFC22)) + \s_axi_bresp[0]_INST_0 + (.I0(m_axi_bresp[0]), + .I1(m_atarget_enc[0]), + .I2(m_axi_bresp[4]), + .I3(m_atarget_enc[1]), + .I4(m_axi_bresp[2]), + .O(s_axi_bresp[0])); + LUT5 #( + .INIT(32'hFCEEFC22)) + \s_axi_bresp[1]_INST_0 + (.I0(m_axi_bresp[1]), + .I1(m_atarget_enc[0]), + .I2(m_axi_bresp[5]), + .I3(m_atarget_enc[1]), + .I4(m_axi_bresp[3]), + .O(s_axi_bresp[1])); + NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_splitter__parameterized0 splitter_ar + (.aa_grant_rnw(aa_grant_rnw), + .aclk(aclk), + .aresetn_d(aresetn_d), + .m_ready_d(m_ready_d), + .\m_ready_d_reg[1]_0 (\gen_decerr.decerr_slave_inst_n_6 ), + .\m_ready_d_reg[1]_1 (reg_slice_r_n_2), + .m_valid_i(m_valid_i)); + NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_splitter splitter_aw + (.aclk(aclk), + .aresetn_d(aresetn_d), + .\gen_no_arbiter.m_grant_hot_i_reg[0]_inv (\gen_decerr.decerr_slave_inst_n_4 ), + .\gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 (addr_arbiter_inst_n_58), + .m_ready_d(m_ready_d_0), + .m_ready_d0(m_ready_d0), + .\m_ready_d_reg[1]_0 (splitter_aw_n_0), + .\m_ready_d_reg[2]_0 (\gen_decerr.decerr_slave_inst_n_3 ), + .\m_ready_d_reg[2]_1 (addr_arbiter_inst_n_45), + .\m_ready_d_reg[2]_2 (addr_arbiter_inst_n_54), + .s_axi_wvalid(s_axi_wvalid)); +endmodule + +(* ORIG_REF_NAME = "axi_crossbar_v2_1_30_decerr_slave" *) +module NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_decerr_slave + (mi_bvalid, + mi_wready, + m_axi_rvalid_1_sp_1, + \gen_axilite.s_axi_awready_i_reg_0 , + m_axi_awready_2_sp_1, + m_axi_bvalid_2_sp_1, + m_axi_arready_2_sp_1, + SR, + \gen_axilite.s_axi_bvalid_i_reg_0 , + aclk, + \gen_axilite.s_axi_awready_i_reg_1 , + Q, + \gen_axilite.s_axi_rvalid_i_reg_0 , + aresetn_d, + m_axi_rvalid, + \m_ready_d_reg[2] , + m_axi_wready, + m_axi_awready, + m_axi_bvalid, + m_axi_arready, + aa_rready); + output [0:0]mi_bvalid; + output [0:0]mi_wready; + output m_axi_rvalid_1_sp_1; + output \gen_axilite.s_axi_awready_i_reg_0 ; + output m_axi_awready_2_sp_1; + output m_axi_bvalid_2_sp_1; + output m_axi_arready_2_sp_1; + input [0:0]SR; + input \gen_axilite.s_axi_bvalid_i_reg_0 ; + input aclk; + input \gen_axilite.s_axi_awready_i_reg_1 ; + input [0:0]Q; + input \gen_axilite.s_axi_rvalid_i_reg_0 ; + input aresetn_d; + input [2:0]m_axi_rvalid; + input [1:0]\m_ready_d_reg[2] ; + input [2:0]m_axi_wready; + input [2:0]m_axi_awready; + input [2:0]m_axi_bvalid; + input [2:0]m_axi_arready; + input aa_rready; + + wire [0:0]Q; + wire [0:0]SR; + wire aa_rready; + wire aclk; + wire aresetn_d; + wire \gen_axilite.s_axi_arready_i_i_1_n_0 ; + wire \gen_axilite.s_axi_awready_i_reg_0 ; + wire \gen_axilite.s_axi_awready_i_reg_1 ; + wire \gen_axilite.s_axi_bvalid_i_reg_0 ; + wire \gen_axilite.s_axi_rvalid_i_i_1_n_0 ; + wire \gen_axilite.s_axi_rvalid_i_reg_0 ; + wire [2:0]m_axi_arready; + wire m_axi_arready_2_sn_1; + wire [2:0]m_axi_awready; + wire m_axi_awready_2_sn_1; + wire [2:0]m_axi_bvalid; + wire m_axi_bvalid_2_sn_1; + wire [2:0]m_axi_rvalid; + wire m_axi_rvalid_1_sn_1; + wire [2:0]m_axi_wready; + wire [1:0]\m_ready_d_reg[2] ; + wire [3:3]mi_arready; + wire [0:0]mi_bvalid; + wire [3:3]mi_rvalid; + wire [0:0]mi_wready; + + assign m_axi_arready_2_sp_1 = m_axi_arready_2_sn_1; + assign m_axi_awready_2_sp_1 = m_axi_awready_2_sn_1; + assign m_axi_bvalid_2_sp_1 = m_axi_bvalid_2_sn_1; + assign m_axi_rvalid_1_sp_1 = m_axi_rvalid_1_sn_1; + LUT5 #( + .INIT(32'hF07F0000)) + \gen_axilite.s_axi_arready_i_i_1 + (.I0(Q), + .I1(\gen_axilite.s_axi_rvalid_i_reg_0 ), + .I2(mi_arready), + .I3(mi_rvalid), + .I4(aresetn_d), + .O(\gen_axilite.s_axi_arready_i_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \gen_axilite.s_axi_arready_i_reg + (.C(aclk), + .CE(1'b1), + .D(\gen_axilite.s_axi_arready_i_i_1_n_0 ), + .Q(mi_arready), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gen_axilite.s_axi_awready_i_reg + (.C(aclk), + .CE(1'b1), + .D(\gen_axilite.s_axi_awready_i_reg_1 ), + .Q(mi_wready), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \gen_axilite.s_axi_bvalid_i_reg + (.C(aclk), + .CE(1'b1), + .D(\gen_axilite.s_axi_bvalid_i_reg_0 ), + .Q(mi_bvalid), + .R(SR)); + LUT5 #( + .INIT(32'h0FFF8800)) + \gen_axilite.s_axi_rvalid_i_i_1 + (.I0(mi_arready), + .I1(\gen_axilite.s_axi_rvalid_i_reg_0 ), + .I2(aa_rready), + .I3(Q), + .I4(mi_rvalid), + .O(\gen_axilite.s_axi_rvalid_i_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \gen_axilite.s_axi_rvalid_i_reg + (.C(aclk), + .CE(1'b1), + .D(\gen_axilite.s_axi_rvalid_i_i_1_n_0 ), + .Q(mi_rvalid), + .R(SR)); + LUT6 #( + .INIT(64'h33550F0033550FFF)) + \m_ready_d[1]_i_2 + (.I0(m_axi_arready[2]), + .I1(mi_arready), + .I2(m_axi_arready[1]), + .I3(\m_ready_d_reg[2] [0]), + .I4(\m_ready_d_reg[2] [1]), + .I5(m_axi_arready[0]), + .O(m_axi_arready_2_sn_1)); + LUT6 #( + .INIT(64'hCCAAFFF0CCAA00F0)) + \m_ready_d[2]_i_5 + (.I0(m_axi_awready[2]), + .I1(mi_wready), + .I2(m_axi_awready[0]), + .I3(\m_ready_d_reg[2] [0]), + .I4(\m_ready_d_reg[2] [1]), + .I5(m_axi_awready[1]), + .O(m_axi_awready_2_sn_1)); + LUT6 #( + .INIT(64'h00550F33FF550F33)) + m_valid_i_i_4 + (.I0(m_axi_rvalid[1]), + .I1(m_axi_rvalid[0]), + .I2(m_axi_rvalid[2]), + .I3(\m_ready_d_reg[2] [1]), + .I4(\m_ready_d_reg[2] [0]), + .I5(mi_rvalid), + .O(m_axi_rvalid_1_sn_1)); + LUT6 #( + .INIT(64'h0055330FFF55330F)) + \s_axi_bvalid[0]_INST_0_i_1 + (.I0(m_axi_bvalid[2]), + .I1(m_axi_bvalid[1]), + .I2(m_axi_bvalid[0]), + .I3(\m_ready_d_reg[2] [0]), + .I4(\m_ready_d_reg[2] [1]), + .I5(mi_bvalid), + .O(m_axi_bvalid_2_sn_1)); + LUT6 #( + .INIT(64'h55000F3355FF0F33)) + \s_axi_wready[0]_INST_0_i_1 + (.I0(mi_wready), + .I1(m_axi_wready[0]), + .I2(m_axi_wready[2]), + .I3(\m_ready_d_reg[2] [1]), + .I4(\m_ready_d_reg[2] [0]), + .I5(m_axi_wready[1]), + .O(\gen_axilite.s_axi_awready_i_reg_0 )); +endmodule + +(* ORIG_REF_NAME = "axi_crossbar_v2_1_30_splitter" *) +module NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_splitter + (\m_ready_d_reg[1]_0 , + m_ready_d, + s_axi_wvalid, + \m_ready_d_reg[2]_0 , + \gen_no_arbiter.m_grant_hot_i_reg[0]_inv , + \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 , + \m_ready_d_reg[2]_1 , + \m_ready_d_reg[2]_2 , + m_ready_d0, + aresetn_d, + aclk); + output \m_ready_d_reg[1]_0 ; + output [2:0]m_ready_d; + input [0:0]s_axi_wvalid; + input \m_ready_d_reg[2]_0 ; + input \gen_no_arbiter.m_grant_hot_i_reg[0]_inv ; + input \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 ; + input \m_ready_d_reg[2]_1 ; + input \m_ready_d_reg[2]_2 ; + input [0:0]m_ready_d0; + input aresetn_d; + input aclk; + + wire aclk; + wire aresetn_d; + wire \gen_no_arbiter.m_grant_hot_i_reg[0]_inv ; + wire \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 ; + wire [2:0]m_ready_d; + wire [0:0]m_ready_d0; + wire \m_ready_d[0]_i_1_n_0 ; + wire \m_ready_d[1]_i_1_n_0 ; + wire \m_ready_d[2]_i_1_n_0 ; + wire \m_ready_d_reg[1]_0 ; + wire \m_ready_d_reg[2]_0 ; + wire \m_ready_d_reg[2]_1 ; + wire \m_ready_d_reg[2]_2 ; + wire [0:0]s_axi_wvalid; + + LUT6 #( + .INIT(64'h55555151FFFF51FF)) + \gen_no_arbiter.m_grant_hot_i[0]_inv_i_3 + (.I0(m_ready_d[1]), + .I1(s_axi_wvalid), + .I2(\m_ready_d_reg[2]_0 ), + .I3(\gen_no_arbiter.m_grant_hot_i_reg[0]_inv ), + .I4(\gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 ), + .I5(m_ready_d[2]), + .O(\m_ready_d_reg[1]_0 )); + LUT6 #( + .INIT(64'hBABB000000000000)) + \m_ready_d[0]_i_1 + (.I0(\m_ready_d_reg[2]_1 ), + .I1(m_ready_d[1]), + .I2(\m_ready_d_reg[2]_0 ), + .I3(\m_ready_d_reg[2]_2 ), + .I4(m_ready_d0), + .I5(aresetn_d), + .O(\m_ready_d[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h8A88CFCC00000000)) + \m_ready_d[1]_i_1 + (.I0(\m_ready_d_reg[2]_1 ), + .I1(m_ready_d[1]), + .I2(\m_ready_d_reg[2]_0 ), + .I3(\m_ready_d_reg[2]_2 ), + .I4(m_ready_d0), + .I5(aresetn_d), + .O(\m_ready_d[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'h1011555500000000)) + \m_ready_d[2]_i_1 + (.I0(\m_ready_d_reg[2]_1 ), + .I1(m_ready_d[1]), + .I2(\m_ready_d_reg[2]_0 ), + .I3(\m_ready_d_reg[2]_2 ), + .I4(m_ready_d0), + .I5(aresetn_d), + .O(\m_ready_d[2]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \m_ready_d_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\m_ready_d[0]_i_1_n_0 ), + .Q(m_ready_d[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \m_ready_d_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\m_ready_d[1]_i_1_n_0 ), + .Q(m_ready_d[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \m_ready_d_reg[2] + (.C(aclk), + .CE(1'b1), + .D(\m_ready_d[2]_i_1_n_0 ), + .Q(m_ready_d[2]), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "axi_crossbar_v2_1_30_splitter" *) +module NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_splitter__parameterized0 + (m_ready_d, + aresetn_d, + aa_grant_rnw, + m_valid_i, + \m_ready_d_reg[1]_0 , + \m_ready_d_reg[1]_1 , + aclk); + output [1:0]m_ready_d; + input aresetn_d; + input aa_grant_rnw; + input m_valid_i; + input \m_ready_d_reg[1]_0 ; + input \m_ready_d_reg[1]_1 ; + input aclk; + + wire aa_grant_rnw; + wire aclk; + wire aresetn_d; + wire [1:0]m_ready_d; + wire \m_ready_d[0]_i_1_n_0 ; + wire \m_ready_d[1]_i_1_n_0 ; + wire \m_ready_d_reg[1]_0 ; + wire \m_ready_d_reg[1]_1 ; + wire m_valid_i; + + LUT6 #( + .INIT(64'h0000000000AA002A)) + \m_ready_d[0]_i_1 + (.I0(aresetn_d), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(m_ready_d[1]), + .I4(\m_ready_d_reg[1]_0 ), + .I5(\m_ready_d_reg[1]_1 ), + .O(\m_ready_d[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAA00AA8000000000)) + \m_ready_d[1]_i_1 + (.I0(aresetn_d), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(m_ready_d[1]), + .I4(\m_ready_d_reg[1]_0 ), + .I5(\m_ready_d_reg[1]_1 ), + .O(\m_ready_d[1]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \m_ready_d_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\m_ready_d[0]_i_1_n_0 ), + .Q(m_ready_d[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \m_ready_d_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\m_ready_d[1]_i_1_n_0 ), + .Q(m_ready_d[1]), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "axi_register_slice_v2_1_29_axic_register_slice" *) +module NewExtInst_TOP_xbar_0_axi_register_slice_v2_1_29_axic_register_slice + (sr_rvalid, + aa_rready, + m_valid_i_reg_0, + m_axi_rready, + \aresetn_d_reg[1]_0 , + \m_payload_i_reg[34]_0 , + m_valid_i_reg_1, + aclk, + s_ready_i_reg_0, + s_axi_rready, + aa_grant_rnw, + m_valid_i, + m_ready_d, + m_axi_rresp, + Q, + m_axi_rdata, + \m_axi_rready[2] , + SR, + E); + output sr_rvalid; + output aa_rready; + output m_valid_i_reg_0; + output [2:0]m_axi_rready; + output [1:0]\aresetn_d_reg[1]_0 ; + output [33:0]\m_payload_i_reg[34]_0 ; + input m_valid_i_reg_1; + input aclk; + input s_ready_i_reg_0; + input [0:0]s_axi_rready; + input aa_grant_rnw; + input m_valid_i; + input [0:0]m_ready_d; + input [5:0]m_axi_rresp; + input [1:0]Q; + input [95:0]m_axi_rdata; + input [2:0]\m_axi_rready[2] ; + input [0:0]SR; + input [0:0]E; + + wire [0:0]E; + wire [1:0]Q; + wire [0:0]SR; + wire aa_grant_rnw; + wire aa_rready; + wire aclk; + wire [1:0]\aresetn_d_reg[1]_0 ; + wire [95:0]m_axi_rdata; + wire [2:0]m_axi_rready; + wire [2:0]\m_axi_rready[2] ; + wire [5:0]m_axi_rresp; + wire \m_payload_i[12]_i_2_n_0 ; + wire \m_payload_i[13]_i_2_n_0 ; + wire \m_payload_i[14]_i_2_n_0 ; + wire \m_payload_i[15]_i_2_n_0 ; + wire \m_payload_i[17]_i_2_n_0 ; + wire \m_payload_i[18]_i_2_n_0 ; + wire \m_payload_i[1]_i_2_n_0 ; + wire \m_payload_i[25]_i_2_n_0 ; + wire \m_payload_i[26]_i_2_n_0 ; + wire \m_payload_i[28]_i_2_n_0 ; + wire \m_payload_i[29]_i_2_n_0 ; + wire \m_payload_i[2]_i_2_n_0 ; + wire \m_payload_i[30]_i_2_n_0 ; + wire \m_payload_i[31]_i_2_n_0 ; + wire \m_payload_i[33]_i_2_n_0 ; + wire \m_payload_i[34]_i_3_n_0 ; + wire \m_payload_i[5]_i_2_n_0 ; + wire \m_payload_i[6]_i_2_n_0 ; + wire \m_payload_i[7]_i_2_n_0 ; + wire [33:0]\m_payload_i_reg[34]_0 ; + wire \m_payload_i_reg_n_0_[0] ; + wire [0:0]m_ready_d; + wire m_valid_i; + wire m_valid_i_reg_0; + wire m_valid_i_reg_1; + wire [0:0]s_axi_rready; + wire s_ready_i_reg_0; + wire [34:0]skid_buffer; + wire \skid_buffer[10]_i_1_n_0 ; + wire \skid_buffer[11]_i_1_n_0 ; + wire \skid_buffer[16]_i_1_n_0 ; + wire \skid_buffer[19]_i_1_n_0 ; + wire \skid_buffer[20]_i_1_n_0 ; + wire \skid_buffer[21]_i_1_n_0 ; + wire \skid_buffer[22]_i_1_n_0 ; + wire \skid_buffer[23]_i_1_n_0 ; + wire \skid_buffer[24]_i_1_n_0 ; + wire \skid_buffer[27]_i_1_n_0 ; + wire \skid_buffer[32]_i_1_n_0 ; + wire \skid_buffer[3]_i_1_n_0 ; + wire \skid_buffer[4]_i_1_n_0 ; + wire \skid_buffer[8]_i_1_n_0 ; + wire \skid_buffer[9]_i_1_n_0 ; + wire \skid_buffer_reg_n_0_[0] ; + wire \skid_buffer_reg_n_0_[10] ; + wire \skid_buffer_reg_n_0_[11] ; + wire \skid_buffer_reg_n_0_[12] ; + wire \skid_buffer_reg_n_0_[13] ; + wire \skid_buffer_reg_n_0_[14] ; + wire \skid_buffer_reg_n_0_[15] ; + wire \skid_buffer_reg_n_0_[16] ; + wire \skid_buffer_reg_n_0_[17] ; + wire \skid_buffer_reg_n_0_[18] ; + wire \skid_buffer_reg_n_0_[19] ; + wire \skid_buffer_reg_n_0_[1] ; + wire \skid_buffer_reg_n_0_[20] ; + wire \skid_buffer_reg_n_0_[21] ; + wire \skid_buffer_reg_n_0_[22] ; + wire \skid_buffer_reg_n_0_[23] ; + wire \skid_buffer_reg_n_0_[24] ; + wire \skid_buffer_reg_n_0_[25] ; + wire \skid_buffer_reg_n_0_[26] ; + wire \skid_buffer_reg_n_0_[27] ; + wire \skid_buffer_reg_n_0_[28] ; + wire \skid_buffer_reg_n_0_[29] ; + wire \skid_buffer_reg_n_0_[2] ; + wire \skid_buffer_reg_n_0_[30] ; + wire \skid_buffer_reg_n_0_[31] ; + wire \skid_buffer_reg_n_0_[32] ; + wire \skid_buffer_reg_n_0_[33] ; + wire \skid_buffer_reg_n_0_[34] ; + wire \skid_buffer_reg_n_0_[3] ; + wire \skid_buffer_reg_n_0_[4] ; + wire \skid_buffer_reg_n_0_[5] ; + wire \skid_buffer_reg_n_0_[6] ; + wire \skid_buffer_reg_n_0_[7] ; + wire \skid_buffer_reg_n_0_[8] ; + wire \skid_buffer_reg_n_0_[9] ; + wire sr_rvalid; + + FDRE #( + .INIT(1'b0)) + \aresetn_d_reg[0] + (.C(aclk), + .CE(1'b1), + .D(1'b1), + .Q(\aresetn_d_reg[1]_0 [0]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \aresetn_d_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\aresetn_d_reg[1]_0 [0]), + .Q(\aresetn_d_reg[1]_0 [1]), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_rready[0]_INST_0 + (.I0(aa_rready), + .I1(\m_axi_rready[2] [0]), + .O(m_axi_rready[0])); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_rready[1]_INST_0 + (.I0(aa_rready), + .I1(\m_axi_rready[2] [1]), + .O(m_axi_rready[1])); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_rready[2]_INST_0 + (.I0(aa_rready), + .I1(\m_axi_rready[2] [2]), + .O(m_axi_rready[2])); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[10]_i_1 + (.I0(\skid_buffer[10]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[10] ), + .O(skid_buffer[10])); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[11]_i_1 + (.I0(\skid_buffer[11]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[11] ), + .O(skid_buffer[11])); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT3 #( + .INIT(8'h0E)) + \m_payload_i[12]_i_1 + (.I0(\skid_buffer_reg_n_0_[12] ), + .I1(aa_rready), + .I2(\m_payload_i[12]_i_2_n_0 ), + .O(skid_buffer[12])); + LUT6 #( + .INIT(64'h00330F5500000000)) + \m_payload_i[12]_i_2 + (.I0(m_axi_rdata[9]), + .I1(m_axi_rdata[73]), + .I2(m_axi_rdata[41]), + .I3(Q[0]), + .I4(Q[1]), + .I5(aa_rready), + .O(\m_payload_i[12]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT3 #( + .INIT(8'h0E)) + \m_payload_i[13]_i_1 + (.I0(\skid_buffer_reg_n_0_[13] ), + .I1(aa_rready), + .I2(\m_payload_i[13]_i_2_n_0 ), + .O(skid_buffer[13])); + LUT6 #( + .INIT(64'h00330F5500000000)) + \m_payload_i[13]_i_2 + (.I0(m_axi_rdata[10]), + .I1(m_axi_rdata[74]), + .I2(m_axi_rdata[42]), + .I3(Q[0]), + .I4(Q[1]), + .I5(aa_rready), + .O(\m_payload_i[13]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT3 #( + .INIT(8'h0E)) + \m_payload_i[14]_i_1 + (.I0(\skid_buffer_reg_n_0_[14] ), + .I1(aa_rready), + .I2(\m_payload_i[14]_i_2_n_0 ), + .O(skid_buffer[14])); + LUT6 #( + .INIT(64'h00330F5500000000)) + \m_payload_i[14]_i_2 + (.I0(m_axi_rdata[11]), + .I1(m_axi_rdata[75]), + .I2(m_axi_rdata[43]), + .I3(Q[0]), + .I4(Q[1]), + .I5(aa_rready), + .O(\m_payload_i[14]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT3 #( + .INIT(8'h0E)) + \m_payload_i[15]_i_1 + (.I0(\skid_buffer_reg_n_0_[15] ), + .I1(aa_rready), + .I2(\m_payload_i[15]_i_2_n_0 ), + .O(skid_buffer[15])); + LUT6 #( + .INIT(64'h00330F5500000000)) + \m_payload_i[15]_i_2 + (.I0(m_axi_rdata[12]), + .I1(m_axi_rdata[76]), + .I2(m_axi_rdata[44]), + .I3(Q[0]), + .I4(Q[1]), + .I5(aa_rready), + .O(\m_payload_i[15]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[16]_i_1 + (.I0(\skid_buffer[16]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[16] ), + .O(skid_buffer[16])); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT3 #( + .INIT(8'h0E)) + \m_payload_i[17]_i_1 + (.I0(\skid_buffer_reg_n_0_[17] ), + .I1(aa_rready), + .I2(\m_payload_i[17]_i_2_n_0 ), + .O(skid_buffer[17])); + LUT6 #( + .INIT(64'h00330F5500000000)) + \m_payload_i[17]_i_2 + (.I0(m_axi_rdata[14]), + .I1(m_axi_rdata[78]), + .I2(m_axi_rdata[46]), + .I3(Q[0]), + .I4(Q[1]), + .I5(aa_rready), + .O(\m_payload_i[17]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT3 #( + .INIT(8'h0E)) + \m_payload_i[18]_i_1 + (.I0(\skid_buffer_reg_n_0_[18] ), + .I1(aa_rready), + .I2(\m_payload_i[18]_i_2_n_0 ), + .O(skid_buffer[18])); + LUT6 #( + .INIT(64'h00330F5500000000)) + \m_payload_i[18]_i_2 + (.I0(m_axi_rdata[15]), + .I1(m_axi_rdata[79]), + .I2(m_axi_rdata[47]), + .I3(Q[0]), + .I4(Q[1]), + .I5(aa_rready), + .O(\m_payload_i[18]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[19]_i_1 + (.I0(\skid_buffer[19]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[19] ), + .O(skid_buffer[19])); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT3 #( + .INIT(8'h0E)) + \m_payload_i[1]_i_1 + (.I0(\skid_buffer_reg_n_0_[1] ), + .I1(aa_rready), + .I2(\m_payload_i[1]_i_2_n_0 ), + .O(skid_buffer[1])); + LUT6 #( + .INIT(64'h00330F5500000000)) + \m_payload_i[1]_i_2 + (.I0(m_axi_rresp[0]), + .I1(m_axi_rresp[4]), + .I2(m_axi_rresp[2]), + .I3(Q[0]), + .I4(Q[1]), + .I5(aa_rready), + .O(\m_payload_i[1]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[20]_i_1 + (.I0(\skid_buffer[20]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[20] ), + .O(skid_buffer[20])); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[21]_i_1 + (.I0(\skid_buffer[21]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[21] ), + .O(skid_buffer[21])); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[22]_i_1 + (.I0(\skid_buffer[22]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[22] ), + .O(skid_buffer[22])); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[23]_i_1 + (.I0(\skid_buffer[23]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[23] ), + .O(skid_buffer[23])); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[24]_i_1 + (.I0(\skid_buffer[24]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[24] ), + .O(skid_buffer[24])); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT3 #( + .INIT(8'h0E)) + \m_payload_i[25]_i_1 + (.I0(\skid_buffer_reg_n_0_[25] ), + .I1(aa_rready), + .I2(\m_payload_i[25]_i_2_n_0 ), + .O(skid_buffer[25])); + LUT6 #( + .INIT(64'h00330F5500000000)) + \m_payload_i[25]_i_2 + (.I0(m_axi_rdata[22]), + .I1(m_axi_rdata[86]), + .I2(m_axi_rdata[54]), + .I3(Q[0]), + .I4(Q[1]), + .I5(aa_rready), + .O(\m_payload_i[25]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT3 #( + .INIT(8'h0E)) + \m_payload_i[26]_i_1 + (.I0(\skid_buffer_reg_n_0_[26] ), + .I1(aa_rready), + .I2(\m_payload_i[26]_i_2_n_0 ), + .O(skid_buffer[26])); + LUT6 #( + .INIT(64'h00330F5500000000)) + \m_payload_i[26]_i_2 + (.I0(m_axi_rdata[23]), + .I1(m_axi_rdata[87]), + .I2(m_axi_rdata[55]), + .I3(Q[0]), + .I4(Q[1]), + .I5(aa_rready), + .O(\m_payload_i[26]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[27]_i_1 + (.I0(\skid_buffer[27]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[27] ), + .O(skid_buffer[27])); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT3 #( + .INIT(8'h0E)) + \m_payload_i[28]_i_1 + (.I0(\skid_buffer_reg_n_0_[28] ), + .I1(aa_rready), + .I2(\m_payload_i[28]_i_2_n_0 ), + .O(skid_buffer[28])); + LUT6 #( + .INIT(64'h00330F5500000000)) + \m_payload_i[28]_i_2 + (.I0(m_axi_rdata[25]), + .I1(m_axi_rdata[89]), + .I2(m_axi_rdata[57]), + .I3(Q[0]), + .I4(Q[1]), + .I5(aa_rready), + .O(\m_payload_i[28]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT3 #( + .INIT(8'h0E)) + \m_payload_i[29]_i_1 + (.I0(\skid_buffer_reg_n_0_[29] ), + .I1(aa_rready), + .I2(\m_payload_i[29]_i_2_n_0 ), + .O(skid_buffer[29])); + LUT6 #( + .INIT(64'h00330F5500000000)) + \m_payload_i[29]_i_2 + (.I0(m_axi_rdata[26]), + .I1(m_axi_rdata[90]), + .I2(m_axi_rdata[58]), + .I3(Q[0]), + .I4(Q[1]), + .I5(aa_rready), + .O(\m_payload_i[29]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT3 #( + .INIT(8'h0E)) + \m_payload_i[2]_i_1 + (.I0(\skid_buffer_reg_n_0_[2] ), + .I1(aa_rready), + .I2(\m_payload_i[2]_i_2_n_0 ), + .O(skid_buffer[2])); + LUT6 #( + .INIT(64'h00330F5500000000)) + \m_payload_i[2]_i_2 + (.I0(m_axi_rresp[1]), + .I1(m_axi_rresp[5]), + .I2(m_axi_rresp[3]), + .I3(Q[0]), + .I4(Q[1]), + .I5(aa_rready), + .O(\m_payload_i[2]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT3 #( + .INIT(8'h0E)) + \m_payload_i[30]_i_1 + (.I0(\skid_buffer_reg_n_0_[30] ), + .I1(aa_rready), + .I2(\m_payload_i[30]_i_2_n_0 ), + .O(skid_buffer[30])); + LUT6 #( + .INIT(64'h00330F5500000000)) + \m_payload_i[30]_i_2 + (.I0(m_axi_rdata[27]), + .I1(m_axi_rdata[91]), + .I2(m_axi_rdata[59]), + .I3(Q[0]), + .I4(Q[1]), + .I5(aa_rready), + .O(\m_payload_i[30]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT3 #( + .INIT(8'h0E)) + \m_payload_i[31]_i_1 + (.I0(\skid_buffer_reg_n_0_[31] ), + .I1(aa_rready), + .I2(\m_payload_i[31]_i_2_n_0 ), + .O(skid_buffer[31])); + LUT6 #( + .INIT(64'h00330F5500000000)) + \m_payload_i[31]_i_2 + (.I0(m_axi_rdata[28]), + .I1(m_axi_rdata[92]), + .I2(m_axi_rdata[60]), + .I3(Q[0]), + .I4(Q[1]), + .I5(aa_rready), + .O(\m_payload_i[31]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[32]_i_1 + (.I0(\skid_buffer[32]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[32] ), + .O(skid_buffer[32])); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT3 #( + .INIT(8'h0E)) + \m_payload_i[33]_i_1 + (.I0(\skid_buffer_reg_n_0_[33] ), + .I1(aa_rready), + .I2(\m_payload_i[33]_i_2_n_0 ), + .O(skid_buffer[33])); + LUT6 #( + .INIT(64'h00330F5500000000)) + \m_payload_i[33]_i_2 + (.I0(m_axi_rdata[30]), + .I1(m_axi_rdata[94]), + .I2(m_axi_rdata[62]), + .I3(Q[0]), + .I4(Q[1]), + .I5(aa_rready), + .O(\m_payload_i[33]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT3 #( + .INIT(8'h0E)) + \m_payload_i[34]_i_2 + (.I0(\skid_buffer_reg_n_0_[34] ), + .I1(aa_rready), + .I2(\m_payload_i[34]_i_3_n_0 ), + .O(skid_buffer[34])); + LUT6 #( + .INIT(64'h003000500030F050)) + \m_payload_i[34]_i_3 + (.I0(m_axi_rdata[31]), + .I1(m_axi_rdata[95]), + .I2(aa_rready), + .I3(Q[0]), + .I4(Q[1]), + .I5(m_axi_rdata[63]), + .O(\m_payload_i[34]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[3]_i_1 + (.I0(\skid_buffer[3]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[3] ), + .O(skid_buffer[3])); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[4]_i_1 + (.I0(\skid_buffer[4]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[4] ), + .O(skid_buffer[4])); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT3 #( + .INIT(8'h0E)) + \m_payload_i[5]_i_1 + (.I0(\skid_buffer_reg_n_0_[5] ), + .I1(aa_rready), + .I2(\m_payload_i[5]_i_2_n_0 ), + .O(skid_buffer[5])); + LUT6 #( + .INIT(64'h00330F5500000000)) + \m_payload_i[5]_i_2 + (.I0(m_axi_rdata[2]), + .I1(m_axi_rdata[66]), + .I2(m_axi_rdata[34]), + .I3(Q[0]), + .I4(Q[1]), + .I5(aa_rready), + .O(\m_payload_i[5]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT3 #( + .INIT(8'h0E)) + \m_payload_i[6]_i_1 + (.I0(\skid_buffer_reg_n_0_[6] ), + .I1(aa_rready), + .I2(\m_payload_i[6]_i_2_n_0 ), + .O(skid_buffer[6])); + LUT6 #( + .INIT(64'h00330F5500000000)) + \m_payload_i[6]_i_2 + (.I0(m_axi_rdata[3]), + .I1(m_axi_rdata[67]), + .I2(m_axi_rdata[35]), + .I3(Q[0]), + .I4(Q[1]), + .I5(aa_rready), + .O(\m_payload_i[6]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT3 #( + .INIT(8'h0E)) + \m_payload_i[7]_i_1 + (.I0(\skid_buffer_reg_n_0_[7] ), + .I1(aa_rready), + .I2(\m_payload_i[7]_i_2_n_0 ), + .O(skid_buffer[7])); + LUT6 #( + .INIT(64'h00330F5500000000)) + \m_payload_i[7]_i_2 + (.I0(m_axi_rdata[4]), + .I1(m_axi_rdata[68]), + .I2(m_axi_rdata[36]), + .I3(Q[0]), + .I4(Q[1]), + .I5(aa_rready), + .O(\m_payload_i[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[8]_i_1 + (.I0(\skid_buffer[8]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[8] ), + .O(skid_buffer[8])); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[9]_i_1 + (.I0(\skid_buffer[9]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[9] ), + .O(skid_buffer[9])); + FDRE \m_payload_i_reg[0] + (.C(aclk), + .CE(E), + .D(skid_buffer[0]), + .Q(\m_payload_i_reg_n_0_[0] ), + .R(1'b0)); + FDRE \m_payload_i_reg[10] + (.C(aclk), + .CE(E), + .D(skid_buffer[10]), + .Q(\m_payload_i_reg[34]_0 [9]), + .R(1'b0)); + FDRE \m_payload_i_reg[11] + (.C(aclk), + .CE(E), + .D(skid_buffer[11]), + .Q(\m_payload_i_reg[34]_0 [10]), + .R(1'b0)); + FDRE \m_payload_i_reg[12] + (.C(aclk), + .CE(E), + .D(skid_buffer[12]), + .Q(\m_payload_i_reg[34]_0 [11]), + .R(1'b0)); + FDRE \m_payload_i_reg[13] + (.C(aclk), + .CE(E), + .D(skid_buffer[13]), + .Q(\m_payload_i_reg[34]_0 [12]), + .R(1'b0)); + FDRE \m_payload_i_reg[14] + (.C(aclk), + .CE(E), + .D(skid_buffer[14]), + .Q(\m_payload_i_reg[34]_0 [13]), + .R(1'b0)); + FDRE \m_payload_i_reg[15] + (.C(aclk), + .CE(E), + .D(skid_buffer[15]), + .Q(\m_payload_i_reg[34]_0 [14]), + .R(1'b0)); + FDRE \m_payload_i_reg[16] + (.C(aclk), + .CE(E), + .D(skid_buffer[16]), + .Q(\m_payload_i_reg[34]_0 [15]), + .R(1'b0)); + FDRE \m_payload_i_reg[17] + (.C(aclk), + .CE(E), + .D(skid_buffer[17]), + .Q(\m_payload_i_reg[34]_0 [16]), + .R(1'b0)); + FDRE \m_payload_i_reg[18] + (.C(aclk), + .CE(E), + .D(skid_buffer[18]), + .Q(\m_payload_i_reg[34]_0 [17]), + .R(1'b0)); + FDRE \m_payload_i_reg[19] + (.C(aclk), + .CE(E), + .D(skid_buffer[19]), + .Q(\m_payload_i_reg[34]_0 [18]), + .R(1'b0)); + FDRE \m_payload_i_reg[1] + (.C(aclk), + .CE(E), + .D(skid_buffer[1]), + .Q(\m_payload_i_reg[34]_0 [0]), + .R(1'b0)); + FDRE \m_payload_i_reg[20] + (.C(aclk), + .CE(E), + .D(skid_buffer[20]), + .Q(\m_payload_i_reg[34]_0 [19]), + .R(1'b0)); + FDRE \m_payload_i_reg[21] + (.C(aclk), + .CE(E), + .D(skid_buffer[21]), + .Q(\m_payload_i_reg[34]_0 [20]), + .R(1'b0)); + FDRE \m_payload_i_reg[22] + (.C(aclk), + .CE(E), + .D(skid_buffer[22]), + .Q(\m_payload_i_reg[34]_0 [21]), + .R(1'b0)); + FDRE \m_payload_i_reg[23] + (.C(aclk), + .CE(E), + .D(skid_buffer[23]), + .Q(\m_payload_i_reg[34]_0 [22]), + .R(1'b0)); + FDRE \m_payload_i_reg[24] + (.C(aclk), + .CE(E), + .D(skid_buffer[24]), + .Q(\m_payload_i_reg[34]_0 [23]), + .R(1'b0)); + FDRE \m_payload_i_reg[25] + (.C(aclk), + .CE(E), + .D(skid_buffer[25]), + .Q(\m_payload_i_reg[34]_0 [24]), + .R(1'b0)); + FDRE \m_payload_i_reg[26] + (.C(aclk), + .CE(E), + .D(skid_buffer[26]), + .Q(\m_payload_i_reg[34]_0 [25]), + .R(1'b0)); + FDRE \m_payload_i_reg[27] + (.C(aclk), + .CE(E), + .D(skid_buffer[27]), + .Q(\m_payload_i_reg[34]_0 [26]), + .R(1'b0)); + FDRE \m_payload_i_reg[28] + (.C(aclk), + .CE(E), + .D(skid_buffer[28]), + .Q(\m_payload_i_reg[34]_0 [27]), + .R(1'b0)); + FDRE \m_payload_i_reg[29] + (.C(aclk), + .CE(E), + .D(skid_buffer[29]), + .Q(\m_payload_i_reg[34]_0 [28]), + .R(1'b0)); + FDRE \m_payload_i_reg[2] + (.C(aclk), + .CE(E), + .D(skid_buffer[2]), + .Q(\m_payload_i_reg[34]_0 [1]), + .R(1'b0)); + FDRE \m_payload_i_reg[30] + (.C(aclk), + .CE(E), + .D(skid_buffer[30]), + .Q(\m_payload_i_reg[34]_0 [29]), + .R(1'b0)); + FDRE \m_payload_i_reg[31] + (.C(aclk), + .CE(E), + .D(skid_buffer[31]), + .Q(\m_payload_i_reg[34]_0 [30]), + .R(1'b0)); + FDRE \m_payload_i_reg[32] + (.C(aclk), + .CE(E), + .D(skid_buffer[32]), + .Q(\m_payload_i_reg[34]_0 [31]), + .R(1'b0)); + FDRE \m_payload_i_reg[33] + (.C(aclk), + .CE(E), + .D(skid_buffer[33]), + .Q(\m_payload_i_reg[34]_0 [32]), + .R(1'b0)); + FDRE \m_payload_i_reg[34] + (.C(aclk), + .CE(E), + .D(skid_buffer[34]), + .Q(\m_payload_i_reg[34]_0 [33]), + .R(1'b0)); + FDRE \m_payload_i_reg[3] + (.C(aclk), + .CE(E), + .D(skid_buffer[3]), + .Q(\m_payload_i_reg[34]_0 [2]), + .R(1'b0)); + FDRE \m_payload_i_reg[4] + (.C(aclk), + .CE(E), + .D(skid_buffer[4]), + .Q(\m_payload_i_reg[34]_0 [3]), + .R(1'b0)); + FDRE \m_payload_i_reg[5] + (.C(aclk), + .CE(E), + .D(skid_buffer[5]), + .Q(\m_payload_i_reg[34]_0 [4]), + .R(1'b0)); + FDRE \m_payload_i_reg[6] + (.C(aclk), + .CE(E), + .D(skid_buffer[6]), + .Q(\m_payload_i_reg[34]_0 [5]), + .R(1'b0)); + FDRE \m_payload_i_reg[7] + (.C(aclk), + .CE(E), + .D(skid_buffer[7]), + .Q(\m_payload_i_reg[34]_0 [6]), + .R(1'b0)); + FDRE \m_payload_i_reg[8] + (.C(aclk), + .CE(E), + .D(skid_buffer[8]), + .Q(\m_payload_i_reg[34]_0 [7]), + .R(1'b0)); + FDRE \m_payload_i_reg[9] + (.C(aclk), + .CE(E), + .D(skid_buffer[9]), + .Q(\m_payload_i_reg[34]_0 [8]), + .R(1'b0)); + LUT6 #( + .INIT(64'h000000007FFFFFFF)) + \m_ready_d[1]_i_3 + (.I0(sr_rvalid), + .I1(\m_payload_i_reg_n_0_[0] ), + .I2(s_axi_rready), + .I3(aa_grant_rnw), + .I4(m_valid_i), + .I5(m_ready_d), + .O(m_valid_i_reg_0)); + FDRE #( + .INIT(1'b0)) + m_valid_i_reg + (.C(aclk), + .CE(1'b1), + .D(m_valid_i_reg_1), + .Q(sr_rvalid), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + s_ready_i_reg + (.C(aclk), + .CE(1'b1), + .D(s_ready_i_reg_0), + .Q(aa_rready), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT2 #( + .INIT(4'hE)) + \skid_buffer[0]_i_1 + (.I0(aa_rready), + .I1(\skid_buffer_reg_n_0_[0] ), + .O(skid_buffer[0])); + LUT5 #( + .INIT(32'h0CAF0CA0)) + \skid_buffer[10]_i_1 + (.I0(m_axi_rdata[71]), + .I1(m_axi_rdata[39]), + .I2(Q[1]), + .I3(Q[0]), + .I4(m_axi_rdata[7]), + .O(\skid_buffer[10]_i_1_n_0 )); + LUT5 #( + .INIT(32'h0CAF0CA0)) + \skid_buffer[11]_i_1 + (.I0(m_axi_rdata[72]), + .I1(m_axi_rdata[40]), + .I2(Q[1]), + .I3(Q[0]), + .I4(m_axi_rdata[8]), + .O(\skid_buffer[11]_i_1_n_0 )); + LUT5 #( + .INIT(32'h0FCA00CA)) + \skid_buffer[16]_i_1 + (.I0(m_axi_rdata[13]), + .I1(m_axi_rdata[77]), + .I2(Q[1]), + .I3(Q[0]), + .I4(m_axi_rdata[45]), + .O(\skid_buffer[16]_i_1_n_0 )); + LUT5 #( + .INIT(32'h0CAF0CA0)) + \skid_buffer[19]_i_1 + (.I0(m_axi_rdata[80]), + .I1(m_axi_rdata[48]), + .I2(Q[1]), + .I3(Q[0]), + .I4(m_axi_rdata[16]), + .O(\skid_buffer[19]_i_1_n_0 )); + LUT5 #( + .INIT(32'h0CAF0CA0)) + \skid_buffer[20]_i_1 + (.I0(m_axi_rdata[81]), + .I1(m_axi_rdata[49]), + .I2(Q[1]), + .I3(Q[0]), + .I4(m_axi_rdata[17]), + .O(\skid_buffer[20]_i_1_n_0 )); + LUT5 #( + .INIT(32'h0CAF0CA0)) + \skid_buffer[21]_i_1 + (.I0(m_axi_rdata[82]), + .I1(m_axi_rdata[50]), + .I2(Q[1]), + .I3(Q[0]), + .I4(m_axi_rdata[18]), + .O(\skid_buffer[21]_i_1_n_0 )); + LUT5 #( + .INIT(32'h0CAF0CA0)) + \skid_buffer[22]_i_1 + (.I0(m_axi_rdata[83]), + .I1(m_axi_rdata[51]), + .I2(Q[1]), + .I3(Q[0]), + .I4(m_axi_rdata[19]), + .O(\skid_buffer[22]_i_1_n_0 )); + LUT5 #( + .INIT(32'h0FCA00CA)) + \skid_buffer[23]_i_1 + (.I0(m_axi_rdata[20]), + .I1(m_axi_rdata[84]), + .I2(Q[1]), + .I3(Q[0]), + .I4(m_axi_rdata[52]), + .O(\skid_buffer[23]_i_1_n_0 )); + LUT5 #( + .INIT(32'h0FCA00CA)) + \skid_buffer[24]_i_1 + (.I0(m_axi_rdata[21]), + .I1(m_axi_rdata[53]), + .I2(Q[0]), + .I3(Q[1]), + .I4(m_axi_rdata[85]), + .O(\skid_buffer[24]_i_1_n_0 )); + LUT5 #( + .INIT(32'h0CAF0CA0)) + \skid_buffer[27]_i_1 + (.I0(m_axi_rdata[88]), + .I1(m_axi_rdata[56]), + .I2(Q[1]), + .I3(Q[0]), + .I4(m_axi_rdata[24]), + .O(\skid_buffer[27]_i_1_n_0 )); + LUT5 #( + .INIT(32'h0FCA00CA)) + \skid_buffer[32]_i_1 + (.I0(m_axi_rdata[29]), + .I1(m_axi_rdata[93]), + .I2(Q[1]), + .I3(Q[0]), + .I4(m_axi_rdata[61]), + .O(\skid_buffer[32]_i_1_n_0 )); + LUT5 #( + .INIT(32'h0CAF0CA0)) + \skid_buffer[3]_i_1 + (.I0(m_axi_rdata[64]), + .I1(m_axi_rdata[32]), + .I2(Q[1]), + .I3(Q[0]), + .I4(m_axi_rdata[0]), + .O(\skid_buffer[3]_i_1_n_0 )); + LUT5 #( + .INIT(32'h0FCA00CA)) + \skid_buffer[4]_i_1 + (.I0(m_axi_rdata[1]), + .I1(m_axi_rdata[65]), + .I2(Q[1]), + .I3(Q[0]), + .I4(m_axi_rdata[33]), + .O(\skid_buffer[4]_i_1_n_0 )); + LUT5 #( + .INIT(32'h0CAF0CA0)) + \skid_buffer[8]_i_1 + (.I0(m_axi_rdata[69]), + .I1(m_axi_rdata[37]), + .I2(Q[1]), + .I3(Q[0]), + .I4(m_axi_rdata[5]), + .O(\skid_buffer[8]_i_1_n_0 )); + LUT5 #( + .INIT(32'h0CAF0CA0)) + \skid_buffer[9]_i_1 + (.I0(m_axi_rdata[70]), + .I1(m_axi_rdata[38]), + .I2(Q[1]), + .I3(Q[0]), + .I4(m_axi_rdata[6]), + .O(\skid_buffer[9]_i_1_n_0 )); + FDRE \skid_buffer_reg[0] + (.C(aclk), + .CE(1'b1), + .D(skid_buffer[0]), + .Q(\skid_buffer_reg_n_0_[0] ), + .R(1'b0)); + FDRE \skid_buffer_reg[10] + (.C(aclk), + .CE(aa_rready), + .D(\skid_buffer[10]_i_1_n_0 ), + .Q(\skid_buffer_reg_n_0_[10] ), + .R(1'b0)); + FDRE \skid_buffer_reg[11] + (.C(aclk), + .CE(aa_rready), + .D(\skid_buffer[11]_i_1_n_0 ), + .Q(\skid_buffer_reg_n_0_[11] ), + .R(1'b0)); + FDRE \skid_buffer_reg[12] + (.C(aclk), + .CE(1'b1), + .D(skid_buffer[12]), + .Q(\skid_buffer_reg_n_0_[12] ), + .R(1'b0)); + FDRE \skid_buffer_reg[13] + (.C(aclk), + .CE(1'b1), + .D(skid_buffer[13]), + .Q(\skid_buffer_reg_n_0_[13] ), + .R(1'b0)); + FDRE \skid_buffer_reg[14] + (.C(aclk), + .CE(1'b1), + .D(skid_buffer[14]), + .Q(\skid_buffer_reg_n_0_[14] ), + .R(1'b0)); + FDRE \skid_buffer_reg[15] + (.C(aclk), + .CE(1'b1), + .D(skid_buffer[15]), + .Q(\skid_buffer_reg_n_0_[15] ), + .R(1'b0)); + FDRE \skid_buffer_reg[16] + (.C(aclk), + .CE(aa_rready), + .D(\skid_buffer[16]_i_1_n_0 ), + .Q(\skid_buffer_reg_n_0_[16] ), + .R(1'b0)); + FDRE \skid_buffer_reg[17] + (.C(aclk), + .CE(1'b1), + .D(skid_buffer[17]), + .Q(\skid_buffer_reg_n_0_[17] ), + .R(1'b0)); + FDRE \skid_buffer_reg[18] + (.C(aclk), + .CE(1'b1), + .D(skid_buffer[18]), + .Q(\skid_buffer_reg_n_0_[18] ), + .R(1'b0)); + FDRE \skid_buffer_reg[19] + (.C(aclk), + .CE(aa_rready), + .D(\skid_buffer[19]_i_1_n_0 ), + .Q(\skid_buffer_reg_n_0_[19] ), + .R(1'b0)); + FDRE \skid_buffer_reg[1] + (.C(aclk), + .CE(1'b1), + .D(skid_buffer[1]), + .Q(\skid_buffer_reg_n_0_[1] ), + .R(1'b0)); + FDRE \skid_buffer_reg[20] + (.C(aclk), + .CE(aa_rready), + .D(\skid_buffer[20]_i_1_n_0 ), + .Q(\skid_buffer_reg_n_0_[20] ), + .R(1'b0)); + FDRE \skid_buffer_reg[21] + (.C(aclk), + .CE(aa_rready), + .D(\skid_buffer[21]_i_1_n_0 ), + .Q(\skid_buffer_reg_n_0_[21] ), + .R(1'b0)); + FDRE \skid_buffer_reg[22] + (.C(aclk), + .CE(aa_rready), + .D(\skid_buffer[22]_i_1_n_0 ), + .Q(\skid_buffer_reg_n_0_[22] ), + .R(1'b0)); + FDRE \skid_buffer_reg[23] + (.C(aclk), + .CE(aa_rready), + .D(\skid_buffer[23]_i_1_n_0 ), + .Q(\skid_buffer_reg_n_0_[23] ), + .R(1'b0)); + FDRE \skid_buffer_reg[24] + (.C(aclk), + .CE(aa_rready), + .D(\skid_buffer[24]_i_1_n_0 ), + .Q(\skid_buffer_reg_n_0_[24] ), + .R(1'b0)); + FDRE \skid_buffer_reg[25] + (.C(aclk), + .CE(1'b1), + .D(skid_buffer[25]), + .Q(\skid_buffer_reg_n_0_[25] ), + .R(1'b0)); + FDRE \skid_buffer_reg[26] + (.C(aclk), + .CE(1'b1), + .D(skid_buffer[26]), + .Q(\skid_buffer_reg_n_0_[26] ), + .R(1'b0)); + FDRE \skid_buffer_reg[27] + (.C(aclk), + .CE(aa_rready), + .D(\skid_buffer[27]_i_1_n_0 ), + .Q(\skid_buffer_reg_n_0_[27] ), + .R(1'b0)); + FDRE \skid_buffer_reg[28] + (.C(aclk), + .CE(1'b1), + .D(skid_buffer[28]), + .Q(\skid_buffer_reg_n_0_[28] ), + .R(1'b0)); + FDRE \skid_buffer_reg[29] + (.C(aclk), + .CE(1'b1), + .D(skid_buffer[29]), + .Q(\skid_buffer_reg_n_0_[29] ), + .R(1'b0)); + FDRE \skid_buffer_reg[2] + (.C(aclk), + .CE(1'b1), + .D(skid_buffer[2]), + .Q(\skid_buffer_reg_n_0_[2] ), + .R(1'b0)); + FDRE \skid_buffer_reg[30] + (.C(aclk), + .CE(1'b1), + .D(skid_buffer[30]), + .Q(\skid_buffer_reg_n_0_[30] ), + .R(1'b0)); + FDRE \skid_buffer_reg[31] + (.C(aclk), + .CE(1'b1), + .D(skid_buffer[31]), + .Q(\skid_buffer_reg_n_0_[31] ), + .R(1'b0)); + FDRE \skid_buffer_reg[32] + (.C(aclk), + .CE(aa_rready), + .D(\skid_buffer[32]_i_1_n_0 ), + .Q(\skid_buffer_reg_n_0_[32] ), + .R(1'b0)); + FDRE \skid_buffer_reg[33] + (.C(aclk), + .CE(1'b1), + .D(skid_buffer[33]), + .Q(\skid_buffer_reg_n_0_[33] ), + .R(1'b0)); + FDRE \skid_buffer_reg[34] + (.C(aclk), + .CE(1'b1), + .D(skid_buffer[34]), + .Q(\skid_buffer_reg_n_0_[34] ), + .R(1'b0)); + FDRE \skid_buffer_reg[3] + (.C(aclk), + .CE(aa_rready), + .D(\skid_buffer[3]_i_1_n_0 ), + .Q(\skid_buffer_reg_n_0_[3] ), + .R(1'b0)); + FDRE \skid_buffer_reg[4] + (.C(aclk), + .CE(aa_rready), + .D(\skid_buffer[4]_i_1_n_0 ), + .Q(\skid_buffer_reg_n_0_[4] ), + .R(1'b0)); + FDRE \skid_buffer_reg[5] + (.C(aclk), + .CE(1'b1), + .D(skid_buffer[5]), + .Q(\skid_buffer_reg_n_0_[5] ), + .R(1'b0)); + FDRE \skid_buffer_reg[6] + (.C(aclk), + .CE(1'b1), + .D(skid_buffer[6]), + .Q(\skid_buffer_reg_n_0_[6] ), + .R(1'b0)); + FDRE \skid_buffer_reg[7] + (.C(aclk), + .CE(1'b1), + .D(skid_buffer[7]), + .Q(\skid_buffer_reg_n_0_[7] ), + .R(1'b0)); + FDRE \skid_buffer_reg[8] + (.C(aclk), + .CE(aa_rready), + .D(\skid_buffer[8]_i_1_n_0 ), + .Q(\skid_buffer_reg_n_0_[8] ), + .R(1'b0)); + FDRE \skid_buffer_reg[9] + (.C(aclk), + .CE(aa_rready), + .D(\skid_buffer[9]_i_1_n_0 ), + .Q(\skid_buffer_reg_n_0_[9] ), + .R(1'b0)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_sim_netlist.vhdl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_sim_netlist.vhdl new file mode 100644 index 0000000..7faff97 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_sim_netlist.vhdl @@ -0,0 +1,4465 @@ +-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +-- Date : Fri May 15 15:27:02 2026 +-- Host : mkb running 64-bit unknown +-- Command : write_vhdl -force -mode funcsim +-- /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_sim_netlist.vhdl +-- Design : NewExtInst_TOP_xbar_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z035ffg676-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_addr_arbiter_sasd is + port ( + m_valid_i : out STD_LOGIC; + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + aa_grant_rnw : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 3 downto 0 ); + Q : out STD_LOGIC_VECTOR ( 34 downto 0 ); + \gen_no_arbiter.m_amesg_i_reg[19]_0\ : out STD_LOGIC; + \gen_no_arbiter.m_amesg_i_reg[19]_1\ : out STD_LOGIC; + m_ready_d0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + \m_ready_d_reg[2]\ : out STD_LOGIC; + s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_bready : out STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_wvalid : out STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_wvalid_0_sp_1 : out STD_LOGIC; + m_axi_awvalid : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \gen_no_arbiter.grant_rnw_reg_0\ : out STD_LOGIC; + \aresetn_d_reg[0]\ : out STD_LOGIC; + \aresetn_d_reg[1]\ : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_arvalid : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \m_ready_d_reg[1]\ : out STD_LOGIC; + s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + \m_atarget_hot_reg[3]\ : out STD_LOGIC; + \m_ready_d_reg[2]_0\ : out STD_LOGIC; + aclk : in STD_LOGIC; + aresetn_d : in STD_LOGIC; + \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0\ : in STD_LOGIC; + s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_ready_d : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \m_ready_d_reg[2]_1\ : in STD_LOGIC; + s_axi_bvalid_0_sp_1 : in STD_LOGIC; + s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_axilite.s_axi_bvalid_i_reg\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wready_0_sp_1 : in STD_LOGIC; + s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_valid_i_reg : in STD_LOGIC_VECTOR ( 1 downto 0 ); + aa_rready : in STD_LOGIC; + m_valid_i_reg_0 : in STD_LOGIC; + m_ready_d_0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); + sr_rvalid : in STD_LOGIC; + \gen_no_arbiter.m_valid_i_reg_0\ : in STD_LOGIC; + \gen_no_arbiter.m_valid_i_reg_1\ : in STD_LOGIC; + s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + mi_wready : in STD_LOGIC_VECTOR ( 0 to 0 ); + mi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_addr_arbiter_sasd : entity is "axi_crossbar_v2_1_30_addr_arbiter_sasd"; +end NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_addr_arbiter_sasd; + +architecture STRUCTURE of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_addr_arbiter_sasd is + signal \^q\ : STD_LOGIC_VECTOR ( 34 downto 0 ); + signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^aa_grant_rnw\ : STD_LOGIC; + signal \gen_axilite.s_axi_bvalid_i_i_2_n_0\ : STD_LOGIC; + signal \gen_axilite.s_axi_bvalid_i_i_3_n_0\ : STD_LOGIC; + signal \gen_no_arbiter.grant_rnw_i_1_n_0\ : STD_LOGIC; + signal \^gen_no_arbiter.grant_rnw_reg_0\ : STD_LOGIC; + signal \gen_no_arbiter.m_grant_hot_i[0]_inv_i_1_n_0\ : STD_LOGIC; + signal \gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_n_0\ : STD_LOGIC; + signal \gen_no_arbiter.m_grant_hot_i[0]_inv_i_4_n_0\ : STD_LOGIC; + signal \gen_no_arbiter.m_valid_i_i_1_n_0\ : STD_LOGIC; + signal \gen_no_arbiter.s_ready_i[0]_i_1_n_0\ : STD_LOGIC; + signal \m_atarget_hot[3]_i_2_n_0\ : STD_LOGIC; + signal \m_atarget_hot[3]_i_3_n_0\ : STD_LOGIC; + signal \m_atarget_hot[3]_i_4_n_0\ : STD_LOGIC; + signal \^m_ready_d0\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^m_valid_i\ : STD_LOGIC; + signal m_valid_i_i_2_n_0 : STD_LOGIC; + signal m_valid_i_i_3_n_0 : STD_LOGIC; + signal p_0_in1_in : STD_LOGIC; + signal s_amesg : STD_LOGIC_VECTOR ( 48 downto 1 ); + signal \s_arvalid_reg[0]_i_1_n_0\ : STD_LOGIC; + signal \s_arvalid_reg_reg_n_0_[0]\ : STD_LOGIC; + signal s_awvalid_reg : STD_LOGIC; + signal \s_awvalid_reg[0]_i_1_n_0\ : STD_LOGIC; + signal s_axi_bvalid_0_sn_1 : STD_LOGIC; + signal s_axi_wready_0_sn_1 : STD_LOGIC; + signal s_axi_wvalid_0_sn_1 : STD_LOGIC; + signal s_ready_i : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \gen_axilite.s_axi_awready_i_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \gen_axilite.s_axi_bvalid_i_i_2\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \gen_axilite.s_axi_bvalid_i_i_3\ : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of \gen_axilite.s_axi_rvalid_i_i_2\ : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \gen_no_arbiter.m_grant_hot_i[0]_inv_i_2\ : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \gen_no_arbiter.m_grant_hot_i[0]_inv_i_4\ : label is "soft_lutpair4"; + attribute inverted : string; + attribute inverted of \gen_no_arbiter.m_grant_hot_i_reg[0]_inv\ : label is "yes"; + attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \m_atarget_enc[0]_i_1\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \m_atarget_enc[1]_i_1\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \m_axi_arvalid[0]_INST_0\ : label is "soft_lutpair9"; + attribute SOFT_HLUTNM of \m_axi_arvalid[1]_INST_0\ : label is "soft_lutpair10"; + attribute SOFT_HLUTNM of \m_axi_arvalid[2]_INST_0\ : label is "soft_lutpair11"; + attribute SOFT_HLUTNM of \m_axi_awvalid[0]_INST_0\ : label is "soft_lutpair9"; + attribute SOFT_HLUTNM of \m_axi_awvalid[1]_INST_0\ : label is "soft_lutpair10"; + attribute SOFT_HLUTNM of \m_axi_awvalid[2]_INST_0\ : label is "soft_lutpair11"; + attribute SOFT_HLUTNM of \m_axi_wvalid[0]_INST_0\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \m_ready_d[2]_i_2\ : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of \m_ready_d[2]_i_3\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \m_ready_d[2]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of m_valid_i_i_1 : label is "soft_lutpair12"; + attribute SOFT_HLUTNM of m_valid_i_i_2 : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of m_valid_i_i_3 : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \s_arvalid_reg[0]_i_1\ : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of \s_axi_awready[0]_INST_0\ : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of s_ready_i_i_1 : label is "soft_lutpair12"; +begin + Q(34 downto 0) <= \^q\(34 downto 0); + SR(0) <= \^sr\(0); + aa_grant_rnw <= \^aa_grant_rnw\; + \gen_no_arbiter.grant_rnw_reg_0\ <= \^gen_no_arbiter.grant_rnw_reg_0\; + m_ready_d0(0) <= \^m_ready_d0\(0); + m_valid_i <= \^m_valid_i\; + s_axi_bvalid_0_sn_1 <= s_axi_bvalid_0_sp_1; + s_axi_wready_0_sn_1 <= s_axi_wready_0_sp_1; + s_axi_wvalid_0_sp_1 <= s_axi_wvalid_0_sn_1; +\gen_axilite.s_axi_awready_i_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFDFF00000200" + ) + port map ( + I0 => s_axi_wvalid_0_sn_1, + I1 => m_ready_d(2), + I2 => \^gen_no_arbiter.grant_rnw_reg_0\, + I3 => \gen_axilite.s_axi_bvalid_i_reg\(3), + I4 => mi_bvalid(0), + I5 => mi_wready(0), + O => \m_ready_d_reg[2]_0\ + ); +\gen_axilite.s_axi_awready_i_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^aa_grant_rnw\, + I1 => \^m_valid_i\, + O => \^gen_no_arbiter.grant_rnw_reg_0\ + ); +\gen_axilite.s_axi_bvalid_i_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAFFAAFF0C000000" + ) + port map ( + I0 => \gen_axilite.s_axi_bvalid_i_i_2_n_0\, + I1 => s_axi_wvalid_0_sn_1, + I2 => \gen_axilite.s_axi_bvalid_i_i_3_n_0\, + I3 => \gen_axilite.s_axi_bvalid_i_reg\(3), + I4 => mi_wready(0), + I5 => mi_bvalid(0), + O => \m_atarget_hot_reg[3]\ + ); +\gen_axilite.s_axi_bvalid_i_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FBFF" + ) + port map ( + I0 => \^aa_grant_rnw\, + I1 => \^m_valid_i\, + I2 => m_ready_d(0), + I3 => s_axi_bready(0), + O => \gen_axilite.s_axi_bvalid_i_i_2_n_0\ + ); +\gen_axilite.s_axi_bvalid_i_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FB" + ) + port map ( + I0 => m_ready_d(2), + I1 => \^m_valid_i\, + I2 => \^aa_grant_rnw\, + O => \gen_axilite.s_axi_bvalid_i_i_3_n_0\ + ); +\gen_axilite.s_axi_rvalid_i_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => m_ready_d_0(1), + I1 => \^m_valid_i\, + I2 => \^aa_grant_rnw\, + O => \m_ready_d_reg[1]\ + ); +\gen_no_arbiter.grant_rnw_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF53FF00005000" + ) + port map ( + I0 => s_awvalid_reg, + I1 => s_axi_awvalid(0), + I2 => s_axi_arvalid(0), + I3 => p_0_in1_in, + I4 => \^m_valid_i\, + I5 => \^aa_grant_rnw\, + O => \gen_no_arbiter.grant_rnw_i_1_n_0\ + ); +\gen_no_arbiter.grant_rnw_reg\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \gen_no_arbiter.grant_rnw_i_1_n_0\, + Q => \^aa_grant_rnw\, + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i[10]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(9), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(9), + O => s_amesg(10) + ); +\gen_no_arbiter.m_amesg_i[11]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(10), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(10), + O => s_amesg(11) + ); +\gen_no_arbiter.m_amesg_i[12]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(11), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(11), + O => s_amesg(12) + ); +\gen_no_arbiter.m_amesg_i[13]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(12), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(12), + O => s_amesg(13) + ); +\gen_no_arbiter.m_amesg_i[14]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(13), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(13), + O => s_amesg(14) + ); +\gen_no_arbiter.m_amesg_i[15]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(14), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(14), + O => s_amesg(15) + ); +\gen_no_arbiter.m_amesg_i[16]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(15), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(15), + O => s_amesg(16) + ); +\gen_no_arbiter.m_amesg_i[17]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(16), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(16), + O => s_amesg(17) + ); +\gen_no_arbiter.m_amesg_i[18]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(17), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(17), + O => s_amesg(18) + ); +\gen_no_arbiter.m_amesg_i[19]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(18), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(18), + O => s_amesg(19) + ); +\gen_no_arbiter.m_amesg_i[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(0), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(0), + O => s_amesg(1) + ); +\gen_no_arbiter.m_amesg_i[20]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(19), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(19), + O => s_amesg(20) + ); +\gen_no_arbiter.m_amesg_i[21]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(20), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(20), + O => s_amesg(21) + ); +\gen_no_arbiter.m_amesg_i[22]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(21), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(21), + O => s_amesg(22) + ); +\gen_no_arbiter.m_amesg_i[23]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(22), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(22), + O => s_amesg(23) + ); +\gen_no_arbiter.m_amesg_i[24]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(23), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(23), + O => s_amesg(24) + ); +\gen_no_arbiter.m_amesg_i[25]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(24), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(24), + O => s_amesg(25) + ); +\gen_no_arbiter.m_amesg_i[26]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(25), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(25), + O => s_amesg(26) + ); +\gen_no_arbiter.m_amesg_i[27]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(26), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(26), + O => s_amesg(27) + ); +\gen_no_arbiter.m_amesg_i[28]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(27), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(27), + O => s_amesg(28) + ); +\gen_no_arbiter.m_amesg_i[29]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(28), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(28), + O => s_amesg(29) + ); +\gen_no_arbiter.m_amesg_i[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(1), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(1), + O => s_amesg(2) + ); +\gen_no_arbiter.m_amesg_i[30]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(29), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(29), + O => s_amesg(30) + ); +\gen_no_arbiter.m_amesg_i[31]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(30), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(30), + O => s_amesg(31) + ); +\gen_no_arbiter.m_amesg_i[32]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => aresetn_d, + O => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i[32]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(31), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(31), + O => s_amesg(32) + ); +\gen_no_arbiter.m_amesg_i[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(2), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(2), + O => s_amesg(3) + ); +\gen_no_arbiter.m_amesg_i[46]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_arprot(0), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awprot(0), + O => s_amesg(46) + ); +\gen_no_arbiter.m_amesg_i[47]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_arprot(1), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awprot(1), + O => s_amesg(47) + ); +\gen_no_arbiter.m_amesg_i[48]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_arprot(2), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awprot(2), + O => s_amesg(48) + ); +\gen_no_arbiter.m_amesg_i[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(3), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(3), + O => s_amesg(4) + ); +\gen_no_arbiter.m_amesg_i[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(4), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(4), + O => s_amesg(5) + ); +\gen_no_arbiter.m_amesg_i[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(5), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(5), + O => s_amesg(6) + ); +\gen_no_arbiter.m_amesg_i[7]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(6), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(6), + O => s_amesg(7) + ); +\gen_no_arbiter.m_amesg_i[8]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(7), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(7), + O => s_amesg(8) + ); +\gen_no_arbiter.m_amesg_i[9]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_araddr(8), + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(8), + O => s_amesg(9) + ); +\gen_no_arbiter.m_amesg_i_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(10), + Q => \^q\(9), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(11), + Q => \^q\(10), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(12), + Q => \^q\(11), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(13), + Q => \^q\(12), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(14), + Q => \^q\(13), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(15), + Q => \^q\(14), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(16), + Q => \^q\(15), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(17), + Q => \^q\(16), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(18), + Q => \^q\(17), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(19), + Q => \^q\(18), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(1), + Q => \^q\(0), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(20), + Q => \^q\(19), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(21), + Q => \^q\(20), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(22), + Q => \^q\(21), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(23), + Q => \^q\(22), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(24), + Q => \^q\(23), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(25), + Q => \^q\(24), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[26]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(26), + Q => \^q\(25), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[27]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(27), + Q => \^q\(26), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[28]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(28), + Q => \^q\(27), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[29]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(29), + Q => \^q\(28), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(2), + Q => \^q\(1), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(30), + Q => \^q\(29), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(31), + Q => \^q\(30), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[32]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(32), + Q => \^q\(31), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(3), + Q => \^q\(2), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[46]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(46), + Q => \^q\(32), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[47]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(47), + Q => \^q\(33), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[48]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(48), + Q => \^q\(34), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(4), + Q => \^q\(3), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(5), + Q => \^q\(4), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(6), + Q => \^q\(5), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(7), + Q => \^q\(6), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(8), + Q => \^q\(7), + R => \^sr\(0) + ); +\gen_no_arbiter.m_amesg_i_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in1_in, + D => s_amesg(9), + Q => \^q\(8), + R => \^sr\(0) + ); +\gen_no_arbiter.m_grant_hot_i[0]_inv_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF80808C80" + ) + port map ( + I0 => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_n_0\, + I1 => \^m_valid_i\, + I2 => \^aa_grant_rnw\, + I3 => \^m_ready_d0\(0), + I4 => \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0\, + I5 => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_4_n_0\, + O => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_1_n_0\ + ); +\gen_no_arbiter.m_grant_hot_i[0]_inv_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000F0F8" + ) + port map ( + I0 => \^aa_grant_rnw\, + I1 => \^m_valid_i\, + I2 => m_ready_d_0(1), + I3 => \gen_no_arbiter.m_valid_i_reg_0\, + I4 => \gen_no_arbiter.m_valid_i_reg_1\, + O => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_n_0\ + ); +\gen_no_arbiter.m_grant_hot_i[0]_inv_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D5D5D5F5" + ) + port map ( + I0 => aresetn_d, + I1 => \^m_valid_i\, + I2 => p_0_in1_in, + I3 => s_axi_arvalid(0), + I4 => s_axi_awvalid(0), + O => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_4_n_0\ + ); +\gen_no_arbiter.m_grant_hot_i_reg[0]_inv\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => aclk, + CE => '1', + D => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_1_n_0\, + Q => p_0_in1_in, + R => '0' + ); +\gen_no_arbiter.m_valid_i_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"35F535F5350535F5" + ) + port map ( + I0 => p_0_in1_in, + I1 => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_n_0\, + I2 => \^m_valid_i\, + I3 => \^aa_grant_rnw\, + I4 => \^m_ready_d0\(0), + I5 => \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0\, + O => \gen_no_arbiter.m_valid_i_i_1_n_0\ + ); +\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \gen_no_arbiter.m_valid_i_i_1_n_0\, + Q => \^m_valid_i\, + R => \^sr\(0) + ); +\gen_no_arbiter.s_ready_i[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"10" + ) + port map ( + I0 => \^m_valid_i\, + I1 => p_0_in1_in, + I2 => aresetn_d, + O => \gen_no_arbiter.s_ready_i[0]_i_1_n_0\ + ); +\gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \gen_no_arbiter.s_ready_i[0]_i_1_n_0\, + Q => s_ready_i, + R => '0' + ); +\m_atarget_enc[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFD" + ) + port map ( + I0 => \m_atarget_hot[3]_i_2_n_0\, + I1 => \^q\(18), + I2 => \^q\(19), + I3 => \^q\(16), + O => \gen_no_arbiter.m_amesg_i_reg[19]_1\ + ); +\m_atarget_enc[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFD" + ) + port map ( + I0 => \m_atarget_hot[3]_i_2_n_0\, + I1 => \^q\(18), + I2 => \^q\(19), + I3 => \^q\(17), + O => \gen_no_arbiter.m_amesg_i_reg[19]_0\ + ); +\m_atarget_hot[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000004" + ) + port map ( + I0 => \^q\(16), + I1 => \m_atarget_hot[3]_i_2_n_0\, + I2 => \^q\(18), + I3 => \^q\(19), + I4 => \^q\(17), + I5 => p_0_in1_in, + O => D(0) + ); +\m_atarget_hot[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000008" + ) + port map ( + I0 => \^q\(16), + I1 => \m_atarget_hot[3]_i_2_n_0\, + I2 => \^q\(18), + I3 => \^q\(19), + I4 => \^q\(17), + I5 => p_0_in1_in, + O => D(1) + ); +\m_atarget_hot[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000100000" + ) + port map ( + I0 => \^q\(19), + I1 => \^q\(18), + I2 => \^q\(17), + I3 => \^q\(16), + I4 => \m_atarget_hot[3]_i_2_n_0\, + I5 => p_0_in1_in, + O => D(2) + ); +\m_atarget_hot[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5555555155515551" + ) + port map ( + I0 => p_0_in1_in, + I1 => \m_atarget_hot[3]_i_2_n_0\, + I2 => \^q\(18), + I3 => \^q\(19), + I4 => \^q\(17), + I5 => \^q\(16), + O => D(3) + ); +\m_atarget_hot[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000008000" + ) + port map ( + I0 => \^q\(23), + I1 => \^q\(24), + I2 => \^q\(22), + I3 => \^q\(25), + I4 => \m_atarget_hot[3]_i_3_n_0\, + I5 => \m_atarget_hot[3]_i_4_n_0\, + O => \m_atarget_hot[3]_i_2_n_0\ + ); +\m_atarget_hot[3]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFEF" + ) + port map ( + I0 => \^q\(31), + I1 => \^q\(28), + I2 => \^q\(30), + I3 => \^q\(27), + O => \m_atarget_hot[3]_i_3_n_0\ + ); +\m_atarget_hot[3]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \^q\(29), + I1 => \^q\(26), + I2 => \^q\(21), + I3 => \^q\(20), + O => \m_atarget_hot[3]_i_4_n_0\ + ); +\m_axi_arvalid[0]_INST_0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0080" + ) + port map ( + I0 => \gen_axilite.s_axi_bvalid_i_reg\(0), + I1 => \^aa_grant_rnw\, + I2 => \^m_valid_i\, + I3 => m_ready_d_0(1), + O => m_axi_arvalid(0) + ); +\m_axi_arvalid[1]_INST_0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0080" + ) + port map ( + I0 => \gen_axilite.s_axi_bvalid_i_reg\(1), + I1 => \^aa_grant_rnw\, + I2 => \^m_valid_i\, + I3 => m_ready_d_0(1), + O => m_axi_arvalid(1) + ); +\m_axi_arvalid[2]_INST_0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0080" + ) + port map ( + I0 => \gen_axilite.s_axi_bvalid_i_reg\(2), + I1 => \^aa_grant_rnw\, + I2 => \^m_valid_i\, + I3 => m_ready_d_0(1), + O => m_axi_arvalid(2) + ); +\m_axi_awvalid[0]_INST_0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0020" + ) + port map ( + I0 => \gen_axilite.s_axi_bvalid_i_reg\(0), + I1 => \^aa_grant_rnw\, + I2 => \^m_valid_i\, + I3 => m_ready_d(2), + O => m_axi_awvalid(0) + ); +\m_axi_awvalid[1]_INST_0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0020" + ) + port map ( + I0 => \gen_axilite.s_axi_bvalid_i_reg\(1), + I1 => \^aa_grant_rnw\, + I2 => \^m_valid_i\, + I3 => m_ready_d(2), + O => m_axi_awvalid(1) + ); +\m_axi_awvalid[2]_INST_0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0020" + ) + port map ( + I0 => \gen_axilite.s_axi_bvalid_i_reg\(2), + I1 => \^aa_grant_rnw\, + I2 => \^m_valid_i\, + I3 => m_ready_d(2), + O => m_axi_awvalid(2) + ); +\m_axi_bready[0]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000800" + ) + port map ( + I0 => \gen_axilite.s_axi_bvalid_i_reg\(0), + I1 => s_axi_bready(0), + I2 => m_ready_d(0), + I3 => \^m_valid_i\, + I4 => \^aa_grant_rnw\, + O => m_axi_bready(0) + ); +\m_axi_bready[1]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000800" + ) + port map ( + I0 => \gen_axilite.s_axi_bvalid_i_reg\(1), + I1 => s_axi_bready(0), + I2 => m_ready_d(0), + I3 => \^m_valid_i\, + I4 => \^aa_grant_rnw\, + O => m_axi_bready(1) + ); +\m_axi_bready[2]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000800" + ) + port map ( + I0 => \gen_axilite.s_axi_bvalid_i_reg\(2), + I1 => s_axi_bready(0), + I2 => m_ready_d(0), + I3 => \^m_valid_i\, + I4 => \^aa_grant_rnw\, + O => m_axi_bready(2) + ); +\m_axi_wvalid[0]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00200000" + ) + port map ( + I0 => \gen_axilite.s_axi_bvalid_i_reg\(0), + I1 => m_ready_d(1), + I2 => \^m_valid_i\, + I3 => \^aa_grant_rnw\, + I4 => s_axi_wvalid(0), + O => m_axi_wvalid(0) + ); +\m_axi_wvalid[1]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00200000" + ) + port map ( + I0 => \gen_axilite.s_axi_bvalid_i_reg\(1), + I1 => m_ready_d(1), + I2 => \^m_valid_i\, + I3 => \^aa_grant_rnw\, + I4 => s_axi_wvalid(0), + O => m_axi_wvalid(1) + ); +\m_axi_wvalid[2]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00200000" + ) + port map ( + I0 => \gen_axilite.s_axi_bvalid_i_reg\(2), + I1 => m_ready_d(1), + I2 => \^m_valid_i\, + I3 => \^aa_grant_rnw\, + I4 => s_axi_wvalid(0), + O => m_axi_wvalid(2) + ); +\m_payload_i[34]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0080FFFF" + ) + port map ( + I0 => s_axi_rready(0), + I1 => \^aa_grant_rnw\, + I2 => \^m_valid_i\, + I3 => m_ready_d_0(0), + I4 => sr_rvalid, + O => E(0) + ); +\m_ready_d[2]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4555" + ) + port map ( + I0 => m_ready_d(2), + I1 => \^aa_grant_rnw\, + I2 => \^m_valid_i\, + I3 => \m_ready_d_reg[2]_1\, + O => \m_ready_d_reg[2]\ + ); +\m_ready_d[2]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0020" + ) + port map ( + I0 => s_axi_wvalid(0), + I1 => \^aa_grant_rnw\, + I2 => \^m_valid_i\, + I3 => m_ready_d(1), + O => s_axi_wvalid_0_sn_1 + ); +\m_ready_d[2]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F0F4F0F0" + ) + port map ( + I0 => \^aa_grant_rnw\, + I1 => \^m_valid_i\, + I2 => m_ready_d(0), + I3 => s_axi_bvalid_0_sn_1, + I4 => s_axi_bready(0), + O => \^m_ready_d0\(0) + ); +m_valid_i_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"8A" + ) + port map ( + I0 => m_valid_i_reg(1), + I1 => m_valid_i_i_2_n_0, + I2 => m_valid_i_i_3_n_0, + O => \aresetn_d_reg[1]\ + ); +m_valid_i_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"8AAAAAAA" + ) + port map ( + I0 => sr_rvalid, + I1 => m_ready_d_0(0), + I2 => \^m_valid_i\, + I3 => \^aa_grant_rnw\, + I4 => s_axi_rready(0), + O => m_valid_i_i_2_n_0 + ); +m_valid_i_i_3: unisim.vcomponents.LUT5 + generic map( + INIT => X"A8AAAAAA" + ) + port map ( + I0 => aa_rready, + I1 => m_valid_i_reg_0, + I2 => m_ready_d_0(0), + I3 => \^m_valid_i\, + I4 => \^aa_grant_rnw\, + O => m_valid_i_i_3_n_0 + ); +\s_arvalid_reg[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0040" + ) + port map ( + I0 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => aresetn_d, + I3 => s_ready_i, + O => \s_arvalid_reg[0]_i_1_n_0\ + ); +\s_arvalid_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \s_arvalid_reg[0]_i_1_n_0\, + Q => \s_arvalid_reg_reg_n_0_[0]\, + R => '0' + ); +\s_awvalid_reg[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000D00000" + ) + port map ( + I0 => s_axi_arvalid(0), + I1 => s_awvalid_reg, + I2 => s_axi_awvalid(0), + I3 => \s_arvalid_reg_reg_n_0_[0]\, + I4 => aresetn_d, + I5 => s_ready_i, + O => \s_awvalid_reg[0]_i_1_n_0\ + ); +\s_awvalid_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \s_awvalid_reg[0]_i_1_n_0\, + Q => s_awvalid_reg, + R => '0' + ); +\s_axi_arready[0]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_grant_rnw\, + I1 => s_ready_i, + O => s_axi_arready(0) + ); +\s_axi_awready[0]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => s_ready_i, + I1 => \^aa_grant_rnw\, + O => s_axi_awready(0) + ); +\s_axi_bvalid[0]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000100" + ) + port map ( + I0 => p_0_in1_in, + I1 => s_axi_bvalid_0_sn_1, + I2 => m_ready_d(0), + I3 => \^m_valid_i\, + I4 => \^aa_grant_rnw\, + O => s_axi_bvalid(0) + ); +\s_axi_rvalid[0]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"4" + ) + port map ( + I0 => p_0_in1_in, + I1 => sr_rvalid, + O => s_axi_rvalid(0) + ); +\s_axi_wready[0]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000004" + ) + port map ( + I0 => m_ready_d(1), + I1 => \^m_valid_i\, + I2 => \^aa_grant_rnw\, + I3 => p_0_in1_in, + I4 => s_axi_wready_0_sn_1, + O => s_axi_wready(0) + ); +s_ready_i_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"8A" + ) + port map ( + I0 => m_valid_i_reg(0), + I1 => m_valid_i_i_3_n_0, + I2 => m_valid_i_i_2_n_0, + O => \aresetn_d_reg[0]\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_decerr_slave is + port ( + mi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + mi_wready : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rvalid_1_sp_1 : out STD_LOGIC; + \gen_axilite.s_axi_awready_i_reg_0\ : out STD_LOGIC; + m_axi_awready_2_sp_1 : out STD_LOGIC; + m_axi_bvalid_2_sp_1 : out STD_LOGIC; + m_axi_arready_2_sp_1 : out STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_axilite.s_axi_bvalid_i_reg_0\ : in STD_LOGIC; + aclk : in STD_LOGIC; + \gen_axilite.s_axi_awready_i_reg_1\ : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_axilite.s_axi_rvalid_i_reg_0\ : in STD_LOGIC; + aresetn_d : in STD_LOGIC; + m_axi_rvalid : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \m_ready_d_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_wready : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awready : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_bvalid : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arready : in STD_LOGIC_VECTOR ( 2 downto 0 ); + aa_rready : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_decerr_slave : entity is "axi_crossbar_v2_1_30_decerr_slave"; +end NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_decerr_slave; + +architecture STRUCTURE of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_decerr_slave is + signal \gen_axilite.s_axi_arready_i_i_1_n_0\ : STD_LOGIC; + signal \gen_axilite.s_axi_rvalid_i_i_1_n_0\ : STD_LOGIC; + signal m_axi_arready_2_sn_1 : STD_LOGIC; + signal m_axi_awready_2_sn_1 : STD_LOGIC; + signal m_axi_bvalid_2_sn_1 : STD_LOGIC; + signal m_axi_rvalid_1_sn_1 : STD_LOGIC; + signal mi_arready : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \^mi_bvalid\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal mi_rvalid : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \^mi_wready\ : STD_LOGIC_VECTOR ( 0 to 0 ); +begin + m_axi_arready_2_sp_1 <= m_axi_arready_2_sn_1; + m_axi_awready_2_sp_1 <= m_axi_awready_2_sn_1; + m_axi_bvalid_2_sp_1 <= m_axi_bvalid_2_sn_1; + m_axi_rvalid_1_sp_1 <= m_axi_rvalid_1_sn_1; + mi_bvalid(0) <= \^mi_bvalid\(0); + mi_wready(0) <= \^mi_wready\(0); +\gen_axilite.s_axi_arready_i_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F07F0000" + ) + port map ( + I0 => Q(0), + I1 => \gen_axilite.s_axi_rvalid_i_reg_0\, + I2 => mi_arready(3), + I3 => mi_rvalid(3), + I4 => aresetn_d, + O => \gen_axilite.s_axi_arready_i_i_1_n_0\ + ); +\gen_axilite.s_axi_arready_i_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \gen_axilite.s_axi_arready_i_i_1_n_0\, + Q => mi_arready(3), + R => '0' + ); +\gen_axilite.s_axi_awready_i_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \gen_axilite.s_axi_awready_i_reg_1\, + Q => \^mi_wready\(0), + R => SR(0) + ); +\gen_axilite.s_axi_bvalid_i_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \gen_axilite.s_axi_bvalid_i_reg_0\, + Q => \^mi_bvalid\(0), + R => SR(0) + ); +\gen_axilite.s_axi_rvalid_i_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0FFF8800" + ) + port map ( + I0 => mi_arready(3), + I1 => \gen_axilite.s_axi_rvalid_i_reg_0\, + I2 => aa_rready, + I3 => Q(0), + I4 => mi_rvalid(3), + O => \gen_axilite.s_axi_rvalid_i_i_1_n_0\ + ); +\gen_axilite.s_axi_rvalid_i_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \gen_axilite.s_axi_rvalid_i_i_1_n_0\, + Q => mi_rvalid(3), + R => SR(0) + ); +\m_ready_d[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"33550F0033550FFF" + ) + port map ( + I0 => m_axi_arready(2), + I1 => mi_arready(3), + I2 => m_axi_arready(1), + I3 => \m_ready_d_reg[2]\(0), + I4 => \m_ready_d_reg[2]\(1), + I5 => m_axi_arready(0), + O => m_axi_arready_2_sn_1 + ); +\m_ready_d[2]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CCAAFFF0CCAA00F0" + ) + port map ( + I0 => m_axi_awready(2), + I1 => \^mi_wready\(0), + I2 => m_axi_awready(0), + I3 => \m_ready_d_reg[2]\(0), + I4 => \m_ready_d_reg[2]\(1), + I5 => m_axi_awready(1), + O => m_axi_awready_2_sn_1 + ); +m_valid_i_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"00550F33FF550F33" + ) + port map ( + I0 => m_axi_rvalid(1), + I1 => m_axi_rvalid(0), + I2 => m_axi_rvalid(2), + I3 => \m_ready_d_reg[2]\(1), + I4 => \m_ready_d_reg[2]\(0), + I5 => mi_rvalid(3), + O => m_axi_rvalid_1_sn_1 + ); +\s_axi_bvalid[0]_INST_0_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0055330FFF55330F" + ) + port map ( + I0 => m_axi_bvalid(2), + I1 => m_axi_bvalid(1), + I2 => m_axi_bvalid(0), + I3 => \m_ready_d_reg[2]\(0), + I4 => \m_ready_d_reg[2]\(1), + I5 => \^mi_bvalid\(0), + O => m_axi_bvalid_2_sn_1 + ); +\s_axi_wready[0]_INST_0_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"55000F3355FF0F33" + ) + port map ( + I0 => \^mi_wready\(0), + I1 => m_axi_wready(0), + I2 => m_axi_wready(2), + I3 => \m_ready_d_reg[2]\(1), + I4 => \m_ready_d_reg[2]\(0), + I5 => m_axi_wready(1), + O => \gen_axilite.s_axi_awready_i_reg_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_splitter is + port ( + \m_ready_d_reg[1]_0\ : out STD_LOGIC; + m_ready_d : out STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + \m_ready_d_reg[2]_0\ : in STD_LOGIC; + \gen_no_arbiter.m_grant_hot_i_reg[0]_inv\ : in STD_LOGIC; + \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0\ : in STD_LOGIC; + \m_ready_d_reg[2]_1\ : in STD_LOGIC; + \m_ready_d_reg[2]_2\ : in STD_LOGIC; + m_ready_d0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + aresetn_d : in STD_LOGIC; + aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_splitter : entity is "axi_crossbar_v2_1_30_splitter"; +end NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_splitter; + +architecture STRUCTURE of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_splitter is + signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC; + signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC; + signal \m_ready_d[2]_i_1_n_0\ : STD_LOGIC; +begin + m_ready_d(2 downto 0) <= \^m_ready_d\(2 downto 0); +\gen_no_arbiter.m_grant_hot_i[0]_inv_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"55555151FFFF51FF" + ) + port map ( + I0 => \^m_ready_d\(1), + I1 => s_axi_wvalid(0), + I2 => \m_ready_d_reg[2]_0\, + I3 => \gen_no_arbiter.m_grant_hot_i_reg[0]_inv\, + I4 => \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0\, + I5 => \^m_ready_d\(2), + O => \m_ready_d_reg[1]_0\ + ); +\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BABB000000000000" + ) + port map ( + I0 => \m_ready_d_reg[2]_1\, + I1 => \^m_ready_d\(1), + I2 => \m_ready_d_reg[2]_0\, + I3 => \m_ready_d_reg[2]_2\, + I4 => m_ready_d0(0), + I5 => aresetn_d, + O => \m_ready_d[0]_i_1_n_0\ + ); +\m_ready_d[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8A88CFCC00000000" + ) + port map ( + I0 => \m_ready_d_reg[2]_1\, + I1 => \^m_ready_d\(1), + I2 => \m_ready_d_reg[2]_0\, + I3 => \m_ready_d_reg[2]_2\, + I4 => m_ready_d0(0), + I5 => aresetn_d, + O => \m_ready_d[1]_i_1_n_0\ + ); +\m_ready_d[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1011555500000000" + ) + port map ( + I0 => \m_ready_d_reg[2]_1\, + I1 => \^m_ready_d\(1), + I2 => \m_ready_d_reg[2]_0\, + I3 => \m_ready_d_reg[2]_2\, + I4 => m_ready_d0(0), + I5 => aresetn_d, + O => \m_ready_d[2]_i_1_n_0\ + ); +\m_ready_d_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \m_ready_d[0]_i_1_n_0\, + Q => \^m_ready_d\(0), + R => '0' + ); +\m_ready_d_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \m_ready_d[1]_i_1_n_0\, + Q => \^m_ready_d\(1), + R => '0' + ); +\m_ready_d_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \m_ready_d[2]_i_1_n_0\, + Q => \^m_ready_d\(2), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_splitter__parameterized0\ is + port ( + m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 ); + aresetn_d : in STD_LOGIC; + aa_grant_rnw : in STD_LOGIC; + m_valid_i : in STD_LOGIC; + \m_ready_d_reg[1]_0\ : in STD_LOGIC; + \m_ready_d_reg[1]_1\ : in STD_LOGIC; + aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_splitter__parameterized0\ : entity is "axi_crossbar_v2_1_30_splitter"; +end \NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_splitter__parameterized0\; + +architecture STRUCTURE of \NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_splitter__parameterized0\ is + signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC; + signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC; +begin + m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0); +\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000AA002A" + ) + port map ( + I0 => aresetn_d, + I1 => aa_grant_rnw, + I2 => m_valid_i, + I3 => \^m_ready_d\(1), + I4 => \m_ready_d_reg[1]_0\, + I5 => \m_ready_d_reg[1]_1\, + O => \m_ready_d[0]_i_1_n_0\ + ); +\m_ready_d[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AA00AA8000000000" + ) + port map ( + I0 => aresetn_d, + I1 => aa_grant_rnw, + I2 => m_valid_i, + I3 => \^m_ready_d\(1), + I4 => \m_ready_d_reg[1]_0\, + I5 => \m_ready_d_reg[1]_1\, + O => \m_ready_d[1]_i_1_n_0\ + ); +\m_ready_d_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \m_ready_d[0]_i_1_n_0\, + Q => \^m_ready_d\(0), + R => '0' + ); +\m_ready_d_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \m_ready_d[1]_i_1_n_0\, + Q => \^m_ready_d\(1), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_xbar_0_axi_register_slice_v2_1_29_axic_register_slice is + port ( + sr_rvalid : out STD_LOGIC; + aa_rready : out STD_LOGIC; + m_valid_i_reg_0 : out STD_LOGIC; + m_axi_rready : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \aresetn_d_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \m_payload_i_reg[34]_0\ : out STD_LOGIC_VECTOR ( 33 downto 0 ); + m_valid_i_reg_1 : in STD_LOGIC; + aclk : in STD_LOGIC; + s_ready_i_reg_0 : in STD_LOGIC; + s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); + aa_grant_rnw : in STD_LOGIC; + m_valid_i : in STD_LOGIC; + m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 5 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_rdata : in STD_LOGIC_VECTOR ( 95 downto 0 ); + \m_axi_rready[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of NewExtInst_TOP_xbar_0_axi_register_slice_v2_1_29_axic_register_slice : entity is "axi_register_slice_v2_1_29_axic_register_slice"; +end NewExtInst_TOP_xbar_0_axi_register_slice_v2_1_29_axic_register_slice; + +architecture STRUCTURE of NewExtInst_TOP_xbar_0_axi_register_slice_v2_1_29_axic_register_slice is + signal \^aa_rready\ : STD_LOGIC; + signal \^aresetn_d_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \m_payload_i[12]_i_2_n_0\ : STD_LOGIC; + signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC; + signal \m_payload_i[14]_i_2_n_0\ : STD_LOGIC; + signal \m_payload_i[15]_i_2_n_0\ : STD_LOGIC; + signal \m_payload_i[17]_i_2_n_0\ : STD_LOGIC; + signal \m_payload_i[18]_i_2_n_0\ : STD_LOGIC; + signal \m_payload_i[1]_i_2_n_0\ : STD_LOGIC; + signal \m_payload_i[25]_i_2_n_0\ : STD_LOGIC; + signal \m_payload_i[26]_i_2_n_0\ : STD_LOGIC; + signal \m_payload_i[28]_i_2_n_0\ : STD_LOGIC; + signal \m_payload_i[29]_i_2_n_0\ : STD_LOGIC; + signal \m_payload_i[2]_i_2_n_0\ : STD_LOGIC; + signal \m_payload_i[30]_i_2_n_0\ : STD_LOGIC; + signal \m_payload_i[31]_i_2_n_0\ : STD_LOGIC; + signal \m_payload_i[33]_i_2_n_0\ : STD_LOGIC; + signal \m_payload_i[34]_i_3_n_0\ : STD_LOGIC; + signal \m_payload_i[5]_i_2_n_0\ : STD_LOGIC; + signal \m_payload_i[6]_i_2_n_0\ : STD_LOGIC; + signal \m_payload_i[7]_i_2_n_0\ : STD_LOGIC; + signal \m_payload_i_reg_n_0_[0]\ : STD_LOGIC; + signal skid_buffer : STD_LOGIC_VECTOR ( 34 downto 0 ); + signal \skid_buffer[10]_i_1_n_0\ : STD_LOGIC; + signal \skid_buffer[11]_i_1_n_0\ : STD_LOGIC; + signal \skid_buffer[16]_i_1_n_0\ : STD_LOGIC; + signal \skid_buffer[19]_i_1_n_0\ : STD_LOGIC; + signal \skid_buffer[20]_i_1_n_0\ : STD_LOGIC; + signal \skid_buffer[21]_i_1_n_0\ : STD_LOGIC; + signal \skid_buffer[22]_i_1_n_0\ : STD_LOGIC; + signal \skid_buffer[23]_i_1_n_0\ : STD_LOGIC; + signal \skid_buffer[24]_i_1_n_0\ : STD_LOGIC; + signal \skid_buffer[27]_i_1_n_0\ : STD_LOGIC; + signal \skid_buffer[32]_i_1_n_0\ : STD_LOGIC; + signal \skid_buffer[3]_i_1_n_0\ : STD_LOGIC; + signal \skid_buffer[4]_i_1_n_0\ : STD_LOGIC; + signal \skid_buffer[8]_i_1_n_0\ : STD_LOGIC; + signal \skid_buffer[9]_i_1_n_0\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; + signal \^sr_rvalid\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \m_axi_rready[0]_INST_0\ : label is "soft_lutpair31"; + attribute SOFT_HLUTNM of \m_axi_rready[1]_INST_0\ : label is "soft_lutpair31"; + attribute SOFT_HLUTNM of \m_axi_rready[2]_INST_0\ : label is "soft_lutpair30"; + attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair17"; + attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \m_payload_i[13]_i_1\ : label is "soft_lutpair19"; + attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair19"; + attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair20"; + attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair20"; + attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair21"; + attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair21"; + attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair22"; + attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair13"; + attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair22"; + attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair24"; + attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair24"; + attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair26"; + attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair26"; + attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair27"; + attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair13"; + attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair27"; + attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair28"; + attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair28"; + attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair29"; + attribute SOFT_HLUTNM of \m_payload_i[34]_i_2\ : label is "soft_lutpair29"; + attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair14"; + attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair14"; + attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair15"; + attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair15"; + attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair16"; + attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair16"; + attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair17"; + attribute SOFT_HLUTNM of \skid_buffer[0]_i_1\ : label is "soft_lutpair30"; +begin + aa_rready <= \^aa_rready\; + \aresetn_d_reg[1]_0\(1 downto 0) <= \^aresetn_d_reg[1]_0\(1 downto 0); + sr_rvalid <= \^sr_rvalid\; +\aresetn_d_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => '1', + Q => \^aresetn_d_reg[1]_0\(0), + R => SR(0) + ); +\aresetn_d_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \^aresetn_d_reg[1]_0\(0), + Q => \^aresetn_d_reg[1]_0\(1), + R => SR(0) + ); +\m_axi_rready[0]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_rready\, + I1 => \m_axi_rready[2]\(0), + O => m_axi_rready(0) + ); +\m_axi_rready[1]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_rready\, + I1 => \m_axi_rready[2]\(1), + O => m_axi_rready(1) + ); +\m_axi_rready[2]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_rready\, + I1 => \m_axi_rready[2]\(2), + O => m_axi_rready(2) + ); +\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer[10]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[10]\, + O => skid_buffer(10) + ); +\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer[11]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[11]\, + O => skid_buffer(11) + ); +\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => \skid_buffer_reg_n_0_[12]\, + I1 => \^aa_rready\, + I2 => \m_payload_i[12]_i_2_n_0\, + O => skid_buffer(12) + ); +\m_payload_i[12]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00330F5500000000" + ) + port map ( + I0 => m_axi_rdata(9), + I1 => m_axi_rdata(73), + I2 => m_axi_rdata(41), + I3 => Q(0), + I4 => Q(1), + I5 => \^aa_rready\, + O => \m_payload_i[12]_i_2_n_0\ + ); +\m_payload_i[13]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => \skid_buffer_reg_n_0_[13]\, + I1 => \^aa_rready\, + I2 => \m_payload_i[13]_i_2_n_0\, + O => skid_buffer(13) + ); +\m_payload_i[13]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00330F5500000000" + ) + port map ( + I0 => m_axi_rdata(10), + I1 => m_axi_rdata(74), + I2 => m_axi_rdata(42), + I3 => Q(0), + I4 => Q(1), + I5 => \^aa_rready\, + O => \m_payload_i[13]_i_2_n_0\ + ); +\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => \skid_buffer_reg_n_0_[14]\, + I1 => \^aa_rready\, + I2 => \m_payload_i[14]_i_2_n_0\, + O => skid_buffer(14) + ); +\m_payload_i[14]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00330F5500000000" + ) + port map ( + I0 => m_axi_rdata(11), + I1 => m_axi_rdata(75), + I2 => m_axi_rdata(43), + I3 => Q(0), + I4 => Q(1), + I5 => \^aa_rready\, + O => \m_payload_i[14]_i_2_n_0\ + ); +\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => \skid_buffer_reg_n_0_[15]\, + I1 => \^aa_rready\, + I2 => \m_payload_i[15]_i_2_n_0\, + O => skid_buffer(15) + ); +\m_payload_i[15]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00330F5500000000" + ) + port map ( + I0 => m_axi_rdata(12), + I1 => m_axi_rdata(76), + I2 => m_axi_rdata(44), + I3 => Q(0), + I4 => Q(1), + I5 => \^aa_rready\, + O => \m_payload_i[15]_i_2_n_0\ + ); +\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer[16]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[16]\, + O => skid_buffer(16) + ); +\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => \skid_buffer_reg_n_0_[17]\, + I1 => \^aa_rready\, + I2 => \m_payload_i[17]_i_2_n_0\, + O => skid_buffer(17) + ); +\m_payload_i[17]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00330F5500000000" + ) + port map ( + I0 => m_axi_rdata(14), + I1 => m_axi_rdata(78), + I2 => m_axi_rdata(46), + I3 => Q(0), + I4 => Q(1), + I5 => \^aa_rready\, + O => \m_payload_i[17]_i_2_n_0\ + ); +\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => \skid_buffer_reg_n_0_[18]\, + I1 => \^aa_rready\, + I2 => \m_payload_i[18]_i_2_n_0\, + O => skid_buffer(18) + ); +\m_payload_i[18]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00330F5500000000" + ) + port map ( + I0 => m_axi_rdata(15), + I1 => m_axi_rdata(79), + I2 => m_axi_rdata(47), + I3 => Q(0), + I4 => Q(1), + I5 => \^aa_rready\, + O => \m_payload_i[18]_i_2_n_0\ + ); +\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer[19]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[19]\, + O => skid_buffer(19) + ); +\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => \skid_buffer_reg_n_0_[1]\, + I1 => \^aa_rready\, + I2 => \m_payload_i[1]_i_2_n_0\, + O => skid_buffer(1) + ); +\m_payload_i[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00330F5500000000" + ) + port map ( + I0 => m_axi_rresp(0), + I1 => m_axi_rresp(4), + I2 => m_axi_rresp(2), + I3 => Q(0), + I4 => Q(1), + I5 => \^aa_rready\, + O => \m_payload_i[1]_i_2_n_0\ + ); +\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer[20]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[20]\, + O => skid_buffer(20) + ); +\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer[21]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[21]\, + O => skid_buffer(21) + ); +\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer[22]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[22]\, + O => skid_buffer(22) + ); +\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer[23]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[23]\, + O => skid_buffer(23) + ); +\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer[24]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[24]\, + O => skid_buffer(24) + ); +\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => \skid_buffer_reg_n_0_[25]\, + I1 => \^aa_rready\, + I2 => \m_payload_i[25]_i_2_n_0\, + O => skid_buffer(25) + ); +\m_payload_i[25]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00330F5500000000" + ) + port map ( + I0 => m_axi_rdata(22), + I1 => m_axi_rdata(86), + I2 => m_axi_rdata(54), + I3 => Q(0), + I4 => Q(1), + I5 => \^aa_rready\, + O => \m_payload_i[25]_i_2_n_0\ + ); +\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => \skid_buffer_reg_n_0_[26]\, + I1 => \^aa_rready\, + I2 => \m_payload_i[26]_i_2_n_0\, + O => skid_buffer(26) + ); +\m_payload_i[26]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00330F5500000000" + ) + port map ( + I0 => m_axi_rdata(23), + I1 => m_axi_rdata(87), + I2 => m_axi_rdata(55), + I3 => Q(0), + I4 => Q(1), + I5 => \^aa_rready\, + O => \m_payload_i[26]_i_2_n_0\ + ); +\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer[27]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[27]\, + O => skid_buffer(27) + ); +\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => \skid_buffer_reg_n_0_[28]\, + I1 => \^aa_rready\, + I2 => \m_payload_i[28]_i_2_n_0\, + O => skid_buffer(28) + ); +\m_payload_i[28]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00330F5500000000" + ) + port map ( + I0 => m_axi_rdata(25), + I1 => m_axi_rdata(89), + I2 => m_axi_rdata(57), + I3 => Q(0), + I4 => Q(1), + I5 => \^aa_rready\, + O => \m_payload_i[28]_i_2_n_0\ + ); +\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => \skid_buffer_reg_n_0_[29]\, + I1 => \^aa_rready\, + I2 => \m_payload_i[29]_i_2_n_0\, + O => skid_buffer(29) + ); +\m_payload_i[29]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00330F5500000000" + ) + port map ( + I0 => m_axi_rdata(26), + I1 => m_axi_rdata(90), + I2 => m_axi_rdata(58), + I3 => Q(0), + I4 => Q(1), + I5 => \^aa_rready\, + O => \m_payload_i[29]_i_2_n_0\ + ); +\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => \skid_buffer_reg_n_0_[2]\, + I1 => \^aa_rready\, + I2 => \m_payload_i[2]_i_2_n_0\, + O => skid_buffer(2) + ); +\m_payload_i[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00330F5500000000" + ) + port map ( + I0 => m_axi_rresp(1), + I1 => m_axi_rresp(5), + I2 => m_axi_rresp(3), + I3 => Q(0), + I4 => Q(1), + I5 => \^aa_rready\, + O => \m_payload_i[2]_i_2_n_0\ + ); +\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => \skid_buffer_reg_n_0_[30]\, + I1 => \^aa_rready\, + I2 => \m_payload_i[30]_i_2_n_0\, + O => skid_buffer(30) + ); +\m_payload_i[30]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00330F5500000000" + ) + port map ( + I0 => m_axi_rdata(27), + I1 => m_axi_rdata(91), + I2 => m_axi_rdata(59), + I3 => Q(0), + I4 => Q(1), + I5 => \^aa_rready\, + O => \m_payload_i[30]_i_2_n_0\ + ); +\m_payload_i[31]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => \skid_buffer_reg_n_0_[31]\, + I1 => \^aa_rready\, + I2 => \m_payload_i[31]_i_2_n_0\, + O => skid_buffer(31) + ); +\m_payload_i[31]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00330F5500000000" + ) + port map ( + I0 => m_axi_rdata(28), + I1 => m_axi_rdata(92), + I2 => m_axi_rdata(60), + I3 => Q(0), + I4 => Q(1), + I5 => \^aa_rready\, + O => \m_payload_i[31]_i_2_n_0\ + ); +\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer[32]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[32]\, + O => skid_buffer(32) + ); +\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => \skid_buffer_reg_n_0_[33]\, + I1 => \^aa_rready\, + I2 => \m_payload_i[33]_i_2_n_0\, + O => skid_buffer(33) + ); +\m_payload_i[33]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00330F5500000000" + ) + port map ( + I0 => m_axi_rdata(30), + I1 => m_axi_rdata(94), + I2 => m_axi_rdata(62), + I3 => Q(0), + I4 => Q(1), + I5 => \^aa_rready\, + O => \m_payload_i[33]_i_2_n_0\ + ); +\m_payload_i[34]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => \skid_buffer_reg_n_0_[34]\, + I1 => \^aa_rready\, + I2 => \m_payload_i[34]_i_3_n_0\, + O => skid_buffer(34) + ); +\m_payload_i[34]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"003000500030F050" + ) + port map ( + I0 => m_axi_rdata(31), + I1 => m_axi_rdata(95), + I2 => \^aa_rready\, + I3 => Q(0), + I4 => Q(1), + I5 => m_axi_rdata(63), + O => \m_payload_i[34]_i_3_n_0\ + ); +\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer[3]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[3]\, + O => skid_buffer(3) + ); +\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer[4]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[4]\, + O => skid_buffer(4) + ); +\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => \skid_buffer_reg_n_0_[5]\, + I1 => \^aa_rready\, + I2 => \m_payload_i[5]_i_2_n_0\, + O => skid_buffer(5) + ); +\m_payload_i[5]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00330F5500000000" + ) + port map ( + I0 => m_axi_rdata(2), + I1 => m_axi_rdata(66), + I2 => m_axi_rdata(34), + I3 => Q(0), + I4 => Q(1), + I5 => \^aa_rready\, + O => \m_payload_i[5]_i_2_n_0\ + ); +\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => \skid_buffer_reg_n_0_[6]\, + I1 => \^aa_rready\, + I2 => \m_payload_i[6]_i_2_n_0\, + O => skid_buffer(6) + ); +\m_payload_i[6]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00330F5500000000" + ) + port map ( + I0 => m_axi_rdata(3), + I1 => m_axi_rdata(67), + I2 => m_axi_rdata(35), + I3 => Q(0), + I4 => Q(1), + I5 => \^aa_rready\, + O => \m_payload_i[6]_i_2_n_0\ + ); +\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => \skid_buffer_reg_n_0_[7]\, + I1 => \^aa_rready\, + I2 => \m_payload_i[7]_i_2_n_0\, + O => skid_buffer(7) + ); +\m_payload_i[7]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00330F5500000000" + ) + port map ( + I0 => m_axi_rdata(4), + I1 => m_axi_rdata(68), + I2 => m_axi_rdata(36), + I3 => Q(0), + I4 => Q(1), + I5 => \^aa_rready\, + O => \m_payload_i[7]_i_2_n_0\ + ); +\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer[8]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[8]\, + O => skid_buffer(8) + ); +\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \skid_buffer[9]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[9]\, + O => skid_buffer(9) + ); +\m_payload_i_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(0), + Q => \m_payload_i_reg_n_0_[0]\, + R => '0' + ); +\m_payload_i_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(10), + Q => \m_payload_i_reg[34]_0\(9), + R => '0' + ); +\m_payload_i_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(11), + Q => \m_payload_i_reg[34]_0\(10), + R => '0' + ); +\m_payload_i_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(12), + Q => \m_payload_i_reg[34]_0\(11), + R => '0' + ); +\m_payload_i_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(13), + Q => \m_payload_i_reg[34]_0\(12), + R => '0' + ); +\m_payload_i_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(14), + Q => \m_payload_i_reg[34]_0\(13), + R => '0' + ); +\m_payload_i_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(15), + Q => \m_payload_i_reg[34]_0\(14), + R => '0' + ); +\m_payload_i_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(16), + Q => \m_payload_i_reg[34]_0\(15), + R => '0' + ); +\m_payload_i_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(17), + Q => \m_payload_i_reg[34]_0\(16), + R => '0' + ); +\m_payload_i_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(18), + Q => \m_payload_i_reg[34]_0\(17), + R => '0' + ); +\m_payload_i_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(19), + Q => \m_payload_i_reg[34]_0\(18), + R => '0' + ); +\m_payload_i_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(1), + Q => \m_payload_i_reg[34]_0\(0), + R => '0' + ); +\m_payload_i_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(20), + Q => \m_payload_i_reg[34]_0\(19), + R => '0' + ); +\m_payload_i_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(21), + Q => \m_payload_i_reg[34]_0\(20), + R => '0' + ); +\m_payload_i_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(22), + Q => \m_payload_i_reg[34]_0\(21), + R => '0' + ); +\m_payload_i_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(23), + Q => \m_payload_i_reg[34]_0\(22), + R => '0' + ); +\m_payload_i_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(24), + Q => \m_payload_i_reg[34]_0\(23), + R => '0' + ); +\m_payload_i_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(25), + Q => \m_payload_i_reg[34]_0\(24), + R => '0' + ); +\m_payload_i_reg[26]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(26), + Q => \m_payload_i_reg[34]_0\(25), + R => '0' + ); +\m_payload_i_reg[27]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(27), + Q => \m_payload_i_reg[34]_0\(26), + R => '0' + ); +\m_payload_i_reg[28]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(28), + Q => \m_payload_i_reg[34]_0\(27), + R => '0' + ); +\m_payload_i_reg[29]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(29), + Q => \m_payload_i_reg[34]_0\(28), + R => '0' + ); +\m_payload_i_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(2), + Q => \m_payload_i_reg[34]_0\(1), + R => '0' + ); +\m_payload_i_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(30), + Q => \m_payload_i_reg[34]_0\(29), + R => '0' + ); +\m_payload_i_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(31), + Q => \m_payload_i_reg[34]_0\(30), + R => '0' + ); +\m_payload_i_reg[32]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(32), + Q => \m_payload_i_reg[34]_0\(31), + R => '0' + ); +\m_payload_i_reg[33]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(33), + Q => \m_payload_i_reg[34]_0\(32), + R => '0' + ); +\m_payload_i_reg[34]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(34), + Q => \m_payload_i_reg[34]_0\(33), + R => '0' + ); +\m_payload_i_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(3), + Q => \m_payload_i_reg[34]_0\(2), + R => '0' + ); +\m_payload_i_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(4), + Q => \m_payload_i_reg[34]_0\(3), + R => '0' + ); +\m_payload_i_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(5), + Q => \m_payload_i_reg[34]_0\(4), + R => '0' + ); +\m_payload_i_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(6), + Q => \m_payload_i_reg[34]_0\(5), + R => '0' + ); +\m_payload_i_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(7), + Q => \m_payload_i_reg[34]_0\(6), + R => '0' + ); +\m_payload_i_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(8), + Q => \m_payload_i_reg[34]_0\(7), + R => '0' + ); +\m_payload_i_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(9), + Q => \m_payload_i_reg[34]_0\(8), + R => '0' + ); +\m_ready_d[1]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000007FFFFFFF" + ) + port map ( + I0 => \^sr_rvalid\, + I1 => \m_payload_i_reg_n_0_[0]\, + I2 => s_axi_rready(0), + I3 => aa_grant_rnw, + I4 => m_valid_i, + I5 => m_ready_d(0), + O => m_valid_i_reg_0 + ); +m_valid_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => m_valid_i_reg_1, + Q => \^sr_rvalid\, + R => '0' + ); +s_ready_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_ready_i_reg_0, + Q => \^aa_rready\, + R => '0' + ); +\skid_buffer[0]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^aa_rready\, + I1 => \skid_buffer_reg_n_0_[0]\, + O => skid_buffer(0) + ); +\skid_buffer[10]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0CAF0CA0" + ) + port map ( + I0 => m_axi_rdata(71), + I1 => m_axi_rdata(39), + I2 => Q(1), + I3 => Q(0), + I4 => m_axi_rdata(7), + O => \skid_buffer[10]_i_1_n_0\ + ); +\skid_buffer[11]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0CAF0CA0" + ) + port map ( + I0 => m_axi_rdata(72), + I1 => m_axi_rdata(40), + I2 => Q(1), + I3 => Q(0), + I4 => m_axi_rdata(8), + O => \skid_buffer[11]_i_1_n_0\ + ); +\skid_buffer[16]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0FCA00CA" + ) + port map ( + I0 => m_axi_rdata(13), + I1 => m_axi_rdata(77), + I2 => Q(1), + I3 => Q(0), + I4 => m_axi_rdata(45), + O => \skid_buffer[16]_i_1_n_0\ + ); +\skid_buffer[19]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0CAF0CA0" + ) + port map ( + I0 => m_axi_rdata(80), + I1 => m_axi_rdata(48), + I2 => Q(1), + I3 => Q(0), + I4 => m_axi_rdata(16), + O => \skid_buffer[19]_i_1_n_0\ + ); +\skid_buffer[20]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0CAF0CA0" + ) + port map ( + I0 => m_axi_rdata(81), + I1 => m_axi_rdata(49), + I2 => Q(1), + I3 => Q(0), + I4 => m_axi_rdata(17), + O => \skid_buffer[20]_i_1_n_0\ + ); +\skid_buffer[21]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0CAF0CA0" + ) + port map ( + I0 => m_axi_rdata(82), + I1 => m_axi_rdata(50), + I2 => Q(1), + I3 => Q(0), + I4 => m_axi_rdata(18), + O => \skid_buffer[21]_i_1_n_0\ + ); +\skid_buffer[22]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0CAF0CA0" + ) + port map ( + I0 => m_axi_rdata(83), + I1 => m_axi_rdata(51), + I2 => Q(1), + I3 => Q(0), + I4 => m_axi_rdata(19), + O => \skid_buffer[22]_i_1_n_0\ + ); +\skid_buffer[23]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0FCA00CA" + ) + port map ( + I0 => m_axi_rdata(20), + I1 => m_axi_rdata(84), + I2 => Q(1), + I3 => Q(0), + I4 => m_axi_rdata(52), + O => \skid_buffer[23]_i_1_n_0\ + ); +\skid_buffer[24]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0FCA00CA" + ) + port map ( + I0 => m_axi_rdata(21), + I1 => m_axi_rdata(53), + I2 => Q(0), + I3 => Q(1), + I4 => m_axi_rdata(85), + O => \skid_buffer[24]_i_1_n_0\ + ); +\skid_buffer[27]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0CAF0CA0" + ) + port map ( + I0 => m_axi_rdata(88), + I1 => m_axi_rdata(56), + I2 => Q(1), + I3 => Q(0), + I4 => m_axi_rdata(24), + O => \skid_buffer[27]_i_1_n_0\ + ); +\skid_buffer[32]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0FCA00CA" + ) + port map ( + I0 => m_axi_rdata(29), + I1 => m_axi_rdata(93), + I2 => Q(1), + I3 => Q(0), + I4 => m_axi_rdata(61), + O => \skid_buffer[32]_i_1_n_0\ + ); +\skid_buffer[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0CAF0CA0" + ) + port map ( + I0 => m_axi_rdata(64), + I1 => m_axi_rdata(32), + I2 => Q(1), + I3 => Q(0), + I4 => m_axi_rdata(0), + O => \skid_buffer[3]_i_1_n_0\ + ); +\skid_buffer[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0FCA00CA" + ) + port map ( + I0 => m_axi_rdata(1), + I1 => m_axi_rdata(65), + I2 => Q(1), + I3 => Q(0), + I4 => m_axi_rdata(33), + O => \skid_buffer[4]_i_1_n_0\ + ); +\skid_buffer[8]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0CAF0CA0" + ) + port map ( + I0 => m_axi_rdata(69), + I1 => m_axi_rdata(37), + I2 => Q(1), + I3 => Q(0), + I4 => m_axi_rdata(5), + O => \skid_buffer[8]_i_1_n_0\ + ); +\skid_buffer[9]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0CAF0CA0" + ) + port map ( + I0 => m_axi_rdata(70), + I1 => m_axi_rdata(38), + I2 => Q(1), + I3 => Q(0), + I4 => m_axi_rdata(6), + O => \skid_buffer[9]_i_1_n_0\ + ); +\skid_buffer_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => skid_buffer(0), + Q => \skid_buffer_reg_n_0_[0]\, + R => '0' + ); +\skid_buffer_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^aa_rready\, + D => \skid_buffer[10]_i_1_n_0\, + Q => \skid_buffer_reg_n_0_[10]\, + R => '0' + ); +\skid_buffer_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^aa_rready\, + D => \skid_buffer[11]_i_1_n_0\, + Q => \skid_buffer_reg_n_0_[11]\, + R => '0' + ); +\skid_buffer_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => skid_buffer(12), + Q => \skid_buffer_reg_n_0_[12]\, + R => '0' + ); +\skid_buffer_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => skid_buffer(13), + Q => \skid_buffer_reg_n_0_[13]\, + R => '0' + ); +\skid_buffer_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => skid_buffer(14), + Q => \skid_buffer_reg_n_0_[14]\, + R => '0' + ); +\skid_buffer_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => skid_buffer(15), + Q => \skid_buffer_reg_n_0_[15]\, + R => '0' + ); +\skid_buffer_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^aa_rready\, + D => \skid_buffer[16]_i_1_n_0\, + Q => \skid_buffer_reg_n_0_[16]\, + R => '0' + ); +\skid_buffer_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => skid_buffer(17), + Q => \skid_buffer_reg_n_0_[17]\, + R => '0' + ); +\skid_buffer_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => skid_buffer(18), + Q => \skid_buffer_reg_n_0_[18]\, + R => '0' + ); +\skid_buffer_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^aa_rready\, + D => \skid_buffer[19]_i_1_n_0\, + Q => \skid_buffer_reg_n_0_[19]\, + R => '0' + ); +\skid_buffer_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => skid_buffer(1), + Q => \skid_buffer_reg_n_0_[1]\, + R => '0' + ); +\skid_buffer_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^aa_rready\, + D => \skid_buffer[20]_i_1_n_0\, + Q => \skid_buffer_reg_n_0_[20]\, + R => '0' + ); +\skid_buffer_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^aa_rready\, + D => \skid_buffer[21]_i_1_n_0\, + Q => \skid_buffer_reg_n_0_[21]\, + R => '0' + ); +\skid_buffer_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^aa_rready\, + D => \skid_buffer[22]_i_1_n_0\, + Q => \skid_buffer_reg_n_0_[22]\, + R => '0' + ); +\skid_buffer_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^aa_rready\, + D => \skid_buffer[23]_i_1_n_0\, + Q => \skid_buffer_reg_n_0_[23]\, + R => '0' + ); +\skid_buffer_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^aa_rready\, + D => \skid_buffer[24]_i_1_n_0\, + Q => \skid_buffer_reg_n_0_[24]\, + R => '0' + ); +\skid_buffer_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => skid_buffer(25), + Q => \skid_buffer_reg_n_0_[25]\, + R => '0' + ); +\skid_buffer_reg[26]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => skid_buffer(26), + Q => \skid_buffer_reg_n_0_[26]\, + R => '0' + ); +\skid_buffer_reg[27]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^aa_rready\, + D => \skid_buffer[27]_i_1_n_0\, + Q => \skid_buffer_reg_n_0_[27]\, + R => '0' + ); +\skid_buffer_reg[28]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => skid_buffer(28), + Q => \skid_buffer_reg_n_0_[28]\, + R => '0' + ); +\skid_buffer_reg[29]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => skid_buffer(29), + Q => \skid_buffer_reg_n_0_[29]\, + R => '0' + ); +\skid_buffer_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => skid_buffer(2), + Q => \skid_buffer_reg_n_0_[2]\, + R => '0' + ); +\skid_buffer_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => skid_buffer(30), + Q => \skid_buffer_reg_n_0_[30]\, + R => '0' + ); +\skid_buffer_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => skid_buffer(31), + Q => \skid_buffer_reg_n_0_[31]\, + R => '0' + ); +\skid_buffer_reg[32]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^aa_rready\, + D => \skid_buffer[32]_i_1_n_0\, + Q => \skid_buffer_reg_n_0_[32]\, + R => '0' + ); +\skid_buffer_reg[33]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => skid_buffer(33), + Q => \skid_buffer_reg_n_0_[33]\, + R => '0' + ); +\skid_buffer_reg[34]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => skid_buffer(34), + Q => \skid_buffer_reg_n_0_[34]\, + R => '0' + ); +\skid_buffer_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^aa_rready\, + D => \skid_buffer[3]_i_1_n_0\, + Q => \skid_buffer_reg_n_0_[3]\, + R => '0' + ); +\skid_buffer_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^aa_rready\, + D => \skid_buffer[4]_i_1_n_0\, + Q => \skid_buffer_reg_n_0_[4]\, + R => '0' + ); +\skid_buffer_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => skid_buffer(5), + Q => \skid_buffer_reg_n_0_[5]\, + R => '0' + ); +\skid_buffer_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => skid_buffer(6), + Q => \skid_buffer_reg_n_0_[6]\, + R => '0' + ); +\skid_buffer_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => skid_buffer(7), + Q => \skid_buffer_reg_n_0_[7]\, + R => '0' + ); +\skid_buffer_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^aa_rready\, + D => \skid_buffer[8]_i_1_n_0\, + Q => \skid_buffer_reg_n_0_[8]\, + R => '0' + ); +\skid_buffer_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^aa_rready\, + D => \skid_buffer[9]_i_1_n_0\, + Q => \skid_buffer_reg_n_0_[9]\, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_crossbar_sasd is + port ( + Q : out STD_LOGIC_VECTOR ( 34 downto 0 ); + \m_payload_i_reg[34]\ : out STD_LOGIC_VECTOR ( 33 downto 0 ); + s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_bready : out STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_wvalid : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awvalid : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arvalid : out STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rready : out STD_LOGIC_VECTOR ( 2 downto 0 ); + aresetn : in STD_LOGIC; + aclk : in STD_LOGIC; + s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 5 downto 0 ); + m_axi_rdata : in STD_LOGIC_VECTOR ( 95 downto 0 ); + m_axi_rvalid : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_wready : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awready : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_bvalid : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arready : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_bresp : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_crossbar_sasd : entity is "axi_crossbar_v2_1_30_crossbar_sasd"; +end NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_crossbar_sasd; + +architecture STRUCTURE of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_crossbar_sasd is + signal aa_grant_rnw : STD_LOGIC; + signal aa_rready : STD_LOGIC; + signal addr_arbiter_inst_n_4 : STD_LOGIC; + signal addr_arbiter_inst_n_42 : STD_LOGIC; + signal addr_arbiter_inst_n_43 : STD_LOGIC; + signal addr_arbiter_inst_n_45 : STD_LOGIC; + signal addr_arbiter_inst_n_54 : STD_LOGIC; + signal addr_arbiter_inst_n_58 : STD_LOGIC; + signal addr_arbiter_inst_n_59 : STD_LOGIC; + signal addr_arbiter_inst_n_60 : STD_LOGIC; + signal addr_arbiter_inst_n_65 : STD_LOGIC; + signal addr_arbiter_inst_n_69 : STD_LOGIC; + signal addr_arbiter_inst_n_70 : STD_LOGIC; + signal aresetn_d : STD_LOGIC; + signal \gen_decerr.decerr_slave_inst_n_2\ : STD_LOGIC; + signal \gen_decerr.decerr_slave_inst_n_3\ : STD_LOGIC; + signal \gen_decerr.decerr_slave_inst_n_4\ : STD_LOGIC; + signal \gen_decerr.decerr_slave_inst_n_5\ : STD_LOGIC; + signal \gen_decerr.decerr_slave_inst_n_6\ : STD_LOGIC; + signal m_atarget_enc : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m_atarget_hot : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal m_atarget_hot0 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal m_ready_d : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m_ready_d0 : STD_LOGIC_VECTOR ( 0 to 0 ); + signal m_ready_d_0 : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal m_valid_i : STD_LOGIC; + signal mi_bvalid : STD_LOGIC_VECTOR ( 3 to 3 ); + signal mi_wready : STD_LOGIC_VECTOR ( 3 to 3 ); + signal p_1_in : STD_LOGIC; + signal reg_slice_r_n_2 : STD_LOGIC; + signal reg_slice_r_n_6 : STD_LOGIC; + signal reg_slice_r_n_7 : STD_LOGIC; + signal reset : STD_LOGIC; + signal splitter_aw_n_0 : STD_LOGIC; + signal sr_rvalid : STD_LOGIC; +begin +addr_arbiter_inst: entity work.NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_addr_arbiter_sasd + port map ( + D(3) => m_atarget_hot0(3), + D(2) => addr_arbiter_inst_n_4, + D(1 downto 0) => m_atarget_hot0(1 downto 0), + E(0) => p_1_in, + Q(34 downto 0) => Q(34 downto 0), + SR(0) => reset, + aa_grant_rnw => aa_grant_rnw, + aa_rready => aa_rready, + aclk => aclk, + aresetn_d => aresetn_d, + \aresetn_d_reg[0]\ => addr_arbiter_inst_n_59, + \aresetn_d_reg[1]\ => addr_arbiter_inst_n_60, + \gen_axilite.s_axi_bvalid_i_reg\(3 downto 0) => m_atarget_hot(3 downto 0), + \gen_no_arbiter.grant_rnw_reg_0\ => addr_arbiter_inst_n_58, + \gen_no_arbiter.m_amesg_i_reg[19]_0\ => addr_arbiter_inst_n_42, + \gen_no_arbiter.m_amesg_i_reg[19]_1\ => addr_arbiter_inst_n_43, + \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0\ => splitter_aw_n_0, + \gen_no_arbiter.m_valid_i_reg_0\ => \gen_decerr.decerr_slave_inst_n_6\, + \gen_no_arbiter.m_valid_i_reg_1\ => reg_slice_r_n_2, + \m_atarget_hot_reg[3]\ => addr_arbiter_inst_n_69, + m_axi_arvalid(2 downto 0) => m_axi_arvalid(2 downto 0), + m_axi_awvalid(2 downto 0) => m_axi_awvalid(2 downto 0), + m_axi_bready(2 downto 0) => m_axi_bready(2 downto 0), + m_axi_wvalid(2 downto 0) => m_axi_wvalid(2 downto 0), + m_ready_d(2 downto 0) => m_ready_d_0(2 downto 0), + m_ready_d0(0) => m_ready_d0(0), + m_ready_d_0(1 downto 0) => m_ready_d(1 downto 0), + \m_ready_d_reg[1]\ => addr_arbiter_inst_n_65, + \m_ready_d_reg[2]\ => addr_arbiter_inst_n_45, + \m_ready_d_reg[2]_0\ => addr_arbiter_inst_n_70, + \m_ready_d_reg[2]_1\ => \gen_decerr.decerr_slave_inst_n_4\, + m_valid_i => m_valid_i, + m_valid_i_reg(1) => reg_slice_r_n_6, + m_valid_i_reg(0) => reg_slice_r_n_7, + m_valid_i_reg_0 => \gen_decerr.decerr_slave_inst_n_2\, + mi_bvalid(0) => mi_bvalid(3), + mi_wready(0) => mi_wready(3), + s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), + s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), + s_axi_arready(0) => s_axi_arready(0), + s_axi_arvalid(0) => s_axi_arvalid(0), + s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), + s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), + s_axi_awready(0) => s_axi_awready(0), + s_axi_awvalid(0) => s_axi_awvalid(0), + s_axi_bready(0) => s_axi_bready(0), + s_axi_bvalid(0) => s_axi_bvalid(0), + s_axi_bvalid_0_sp_1 => \gen_decerr.decerr_slave_inst_n_5\, + s_axi_rready(0) => s_axi_rready(0), + s_axi_rvalid(0) => s_axi_rvalid(0), + s_axi_wready(0) => s_axi_wready(0), + s_axi_wready_0_sp_1 => \gen_decerr.decerr_slave_inst_n_3\, + s_axi_wvalid(0) => s_axi_wvalid(0), + s_axi_wvalid_0_sp_1 => addr_arbiter_inst_n_54, + sr_rvalid => sr_rvalid + ); +aresetn_d_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => aresetn, + Q => aresetn_d, + R => '0' + ); +\gen_decerr.decerr_slave_inst\: entity work.NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_decerr_slave + port map ( + Q(0) => m_atarget_hot(3), + SR(0) => reset, + aa_rready => aa_rready, + aclk => aclk, + aresetn_d => aresetn_d, + \gen_axilite.s_axi_awready_i_reg_0\ => \gen_decerr.decerr_slave_inst_n_3\, + \gen_axilite.s_axi_awready_i_reg_1\ => addr_arbiter_inst_n_70, + \gen_axilite.s_axi_bvalid_i_reg_0\ => addr_arbiter_inst_n_69, + \gen_axilite.s_axi_rvalid_i_reg_0\ => addr_arbiter_inst_n_65, + m_axi_arready(2 downto 0) => m_axi_arready(2 downto 0), + m_axi_arready_2_sp_1 => \gen_decerr.decerr_slave_inst_n_6\, + m_axi_awready(2 downto 0) => m_axi_awready(2 downto 0), + m_axi_awready_2_sp_1 => \gen_decerr.decerr_slave_inst_n_4\, + m_axi_bvalid(2 downto 0) => m_axi_bvalid(2 downto 0), + m_axi_bvalid_2_sp_1 => \gen_decerr.decerr_slave_inst_n_5\, + m_axi_rvalid(2 downto 0) => m_axi_rvalid(2 downto 0), + m_axi_rvalid_1_sp_1 => \gen_decerr.decerr_slave_inst_n_2\, + m_axi_wready(2 downto 0) => m_axi_wready(2 downto 0), + \m_ready_d_reg[2]\(1 downto 0) => m_atarget_enc(1 downto 0), + mi_bvalid(0) => mi_bvalid(3), + mi_wready(0) => mi_wready(3) + ); +\m_atarget_enc_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => addr_arbiter_inst_n_43, + Q => m_atarget_enc(0), + R => reset + ); +\m_atarget_enc_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => addr_arbiter_inst_n_42, + Q => m_atarget_enc(1), + R => reset + ); +\m_atarget_hot_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => m_atarget_hot0(0), + Q => m_atarget_hot(0), + R => reset + ); +\m_atarget_hot_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => m_atarget_hot0(1), + Q => m_atarget_hot(1), + R => reset + ); +\m_atarget_hot_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => addr_arbiter_inst_n_4, + Q => m_atarget_hot(2), + R => reset + ); +\m_atarget_hot_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => m_atarget_hot0(3), + Q => m_atarget_hot(3), + R => reset + ); +reg_slice_r: entity work.NewExtInst_TOP_xbar_0_axi_register_slice_v2_1_29_axic_register_slice + port map ( + E(0) => p_1_in, + Q(1 downto 0) => m_atarget_enc(1 downto 0), + SR(0) => reset, + aa_grant_rnw => aa_grant_rnw, + aa_rready => aa_rready, + aclk => aclk, + \aresetn_d_reg[1]_0\(1) => reg_slice_r_n_6, + \aresetn_d_reg[1]_0\(0) => reg_slice_r_n_7, + m_axi_rdata(95 downto 0) => m_axi_rdata(95 downto 0), + m_axi_rready(2 downto 0) => m_axi_rready(2 downto 0), + \m_axi_rready[2]\(2 downto 0) => m_atarget_hot(2 downto 0), + m_axi_rresp(5 downto 0) => m_axi_rresp(5 downto 0), + \m_payload_i_reg[34]_0\(33 downto 0) => \m_payload_i_reg[34]\(33 downto 0), + m_ready_d(0) => m_ready_d(0), + m_valid_i => m_valid_i, + m_valid_i_reg_0 => reg_slice_r_n_2, + m_valid_i_reg_1 => addr_arbiter_inst_n_60, + s_axi_rready(0) => s_axi_rready(0), + s_ready_i_reg_0 => addr_arbiter_inst_n_59, + sr_rvalid => sr_rvalid + ); +\s_axi_bresp[0]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FCEEFC22" + ) + port map ( + I0 => m_axi_bresp(0), + I1 => m_atarget_enc(0), + I2 => m_axi_bresp(4), + I3 => m_atarget_enc(1), + I4 => m_axi_bresp(2), + O => s_axi_bresp(0) + ); +\s_axi_bresp[1]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FCEEFC22" + ) + port map ( + I0 => m_axi_bresp(1), + I1 => m_atarget_enc(0), + I2 => m_axi_bresp(5), + I3 => m_atarget_enc(1), + I4 => m_axi_bresp(3), + O => s_axi_bresp(1) + ); +splitter_ar: entity work.\NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_splitter__parameterized0\ + port map ( + aa_grant_rnw => aa_grant_rnw, + aclk => aclk, + aresetn_d => aresetn_d, + m_ready_d(1 downto 0) => m_ready_d(1 downto 0), + \m_ready_d_reg[1]_0\ => \gen_decerr.decerr_slave_inst_n_6\, + \m_ready_d_reg[1]_1\ => reg_slice_r_n_2, + m_valid_i => m_valid_i + ); +splitter_aw: entity work.NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_splitter + port map ( + aclk => aclk, + aresetn_d => aresetn_d, + \gen_no_arbiter.m_grant_hot_i_reg[0]_inv\ => \gen_decerr.decerr_slave_inst_n_4\, + \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0\ => addr_arbiter_inst_n_58, + m_ready_d(2 downto 0) => m_ready_d_0(2 downto 0), + m_ready_d0(0) => m_ready_d0(0), + \m_ready_d_reg[1]_0\ => splitter_aw_n_0, + \m_ready_d_reg[2]_0\ => \gen_decerr.decerr_slave_inst_n_3\, + \m_ready_d_reg[2]_1\ => addr_arbiter_inst_n_45, + \m_ready_d_reg[2]_2\ => addr_arbiter_inst_n_54, + s_axi_wvalid(0) => s_axi_wvalid(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar is + port ( + aclk : in STD_LOGIC; + aresetn : in STD_LOGIC; + s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awid : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awaddr : out STD_LOGIC_VECTOR ( 95 downto 0 ); + m_axi_awlen : out STD_LOGIC_VECTOR ( 23 downto 0 ); + m_axi_awsize : out STD_LOGIC_VECTOR ( 8 downto 0 ); + m_axi_awburst : out STD_LOGIC_VECTOR ( 5 downto 0 ); + m_axi_awlock : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awcache : out STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_awprot : out STD_LOGIC_VECTOR ( 8 downto 0 ); + m_axi_awregion : out STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_awqos : out STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_awuser : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awvalid : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awready : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_wid : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_wdata : out STD_LOGIC_VECTOR ( 95 downto 0 ); + m_axi_wstrb : out STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_wlast : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_wuser : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_wvalid : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_wready : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_bid : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_bresp : in STD_LOGIC_VECTOR ( 5 downto 0 ); + m_axi_buser : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_bvalid : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_bready : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arid : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_araddr : out STD_LOGIC_VECTOR ( 95 downto 0 ); + m_axi_arlen : out STD_LOGIC_VECTOR ( 23 downto 0 ); + m_axi_arsize : out STD_LOGIC_VECTOR ( 8 downto 0 ); + m_axi_arburst : out STD_LOGIC_VECTOR ( 5 downto 0 ); + m_axi_arlock : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arcache : out STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_arprot : out STD_LOGIC_VECTOR ( 8 downto 0 ); + m_axi_arregion : out STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_arqos : out STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_aruser : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arvalid : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arready : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_rid : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_rdata : in STD_LOGIC_VECTOR ( 95 downto 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 5 downto 0 ); + m_axi_rlast : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_ruser : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_rvalid : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_rready : out STD_LOGIC_VECTOR ( 2 downto 0 ) + ); + attribute C_AXI_ADDR_WIDTH : integer; + attribute C_AXI_ADDR_WIDTH of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is 32; + attribute C_AXI_ARUSER_WIDTH : integer; + attribute C_AXI_ARUSER_WIDTH of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is 1; + attribute C_AXI_AWUSER_WIDTH : integer; + attribute C_AXI_AWUSER_WIDTH of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is 1; + attribute C_AXI_BUSER_WIDTH : integer; + attribute C_AXI_BUSER_WIDTH of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is 1; + attribute C_AXI_DATA_WIDTH : integer; + attribute C_AXI_DATA_WIDTH of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is 32; + attribute C_AXI_ID_WIDTH : integer; + attribute C_AXI_ID_WIDTH of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is 1; + attribute C_AXI_PROTOCOL : integer; + attribute C_AXI_PROTOCOL of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is 2; + attribute C_AXI_RUSER_WIDTH : integer; + attribute C_AXI_RUSER_WIDTH of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is 1; + attribute C_AXI_SUPPORTS_USER_SIGNALS : integer; + attribute C_AXI_SUPPORTS_USER_SIGNALS of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is 0; + attribute C_AXI_WUSER_WIDTH : integer; + attribute C_AXI_WUSER_WIDTH of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is 1; + attribute C_CONNECTIVITY_MODE : integer; + attribute C_CONNECTIVITY_MODE of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is 0; + attribute C_DEBUG : integer; + attribute C_DEBUG of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is 1; + attribute C_FAMILY : string; + attribute C_FAMILY of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is "zynq"; + attribute C_M_AXI_ADDR_WIDTH : string; + attribute C_M_AXI_ADDR_WIDTH of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is "96'b000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000"; + attribute C_M_AXI_BASE_ADDR : string; + attribute C_M_AXI_BASE_ADDR of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is "192'b000000000000000000000000000000000100001111000010000000000000000000000000000000000000000000000000010000111100000100000000000000000000000000000000000000000000000001000011110000000000000000000000"; + attribute C_M_AXI_READ_CONNECTIVITY : string; + attribute C_M_AXI_READ_CONNECTIVITY of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"; + attribute C_M_AXI_READ_ISSUING : string; + attribute C_M_AXI_READ_ISSUING of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"; + attribute C_M_AXI_SECURE : string; + attribute C_M_AXI_SECURE of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute C_M_AXI_WRITE_CONNECTIVITY : string; + attribute C_M_AXI_WRITE_CONNECTIVITY of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"; + attribute C_M_AXI_WRITE_ISSUING : string; + attribute C_M_AXI_WRITE_ISSUING of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"; + attribute C_NUM_ADDR_RANGES : integer; + attribute C_NUM_ADDR_RANGES of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is 1; + attribute C_NUM_MASTER_SLOTS : integer; + attribute C_NUM_MASTER_SLOTS of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is 3; + attribute C_NUM_SLAVE_SLOTS : integer; + attribute C_NUM_SLAVE_SLOTS of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is 1; + attribute C_R_REGISTER : integer; + attribute C_R_REGISTER of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is 1; + attribute C_S_AXI_ARB_PRIORITY : integer; + attribute C_S_AXI_ARB_PRIORITY of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is 0; + attribute C_S_AXI_BASE_ID : integer; + attribute C_S_AXI_BASE_ID of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is 0; + attribute C_S_AXI_READ_ACCEPTANCE : integer; + attribute C_S_AXI_READ_ACCEPTANCE of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is 1; + attribute C_S_AXI_SINGLE_THREAD : integer; + attribute C_S_AXI_SINGLE_THREAD of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is 1; + attribute C_S_AXI_THREAD_ID_WIDTH : integer; + attribute C_S_AXI_THREAD_ID_WIDTH of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is 0; + attribute C_S_AXI_WRITE_ACCEPTANCE : integer; + attribute C_S_AXI_WRITE_ACCEPTANCE of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is 1; + attribute DowngradeIPIdentifiedWarnings : string; + attribute DowngradeIPIdentifiedWarnings of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is "yes"; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is "axi_crossbar_v2_1_30_axi_crossbar"; + attribute P_ADDR_DECODE : integer; + attribute P_ADDR_DECODE of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is 1; + attribute P_AXI3 : integer; + attribute P_AXI3 of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is 1; + attribute P_AXI4 : integer; + attribute P_AXI4 of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is 0; + attribute P_AXILITE : integer; + attribute P_AXILITE of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is 2; + attribute P_AXILITE_SIZE : string; + attribute P_AXILITE_SIZE of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is "3'b010"; + attribute P_FAMILY : string; + attribute P_FAMILY of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is "zynq"; + attribute P_INCR : string; + attribute P_INCR of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is "2'b01"; + attribute P_LEN : integer; + attribute P_LEN of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is 8; + attribute P_LOCK : integer; + attribute P_LOCK of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is 1; + attribute P_M_AXI_ERR_MODE : string; + attribute P_M_AXI_ERR_MODE of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute P_M_AXI_SUPPORTS_READ : string; + attribute P_M_AXI_SUPPORTS_READ of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is "3'b111"; + attribute P_M_AXI_SUPPORTS_WRITE : string; + attribute P_M_AXI_SUPPORTS_WRITE of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is "3'b111"; + attribute P_ONES : string; + attribute P_ONES of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is "65'b11111111111111111111111111111111111111111111111111111111111111111"; + attribute P_RANGE_CHECK : integer; + attribute P_RANGE_CHECK of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is 1; + attribute P_S_AXI_BASE_ID : string; + attribute P_S_AXI_BASE_ID of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000"; + attribute P_S_AXI_HIGH_ID : string; + attribute P_S_AXI_HIGH_ID of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000"; + attribute P_S_AXI_SUPPORTS_READ : string; + attribute P_S_AXI_SUPPORTS_READ of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is "1'b1"; + attribute P_S_AXI_SUPPORTS_WRITE : string; + attribute P_S_AXI_SUPPORTS_WRITE of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar : entity is "1'b1"; +end NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar; + +architecture STRUCTURE of NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar is + signal \\ : STD_LOGIC; + signal \^m_axi_araddr\ : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \^m_axi_arprot\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \^m_axi_awaddr\ : STD_LOGIC_VECTOR ( 95 downto 80 ); + signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 ); +begin + \^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0); + \^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0); + m_axi_araddr(95 downto 80) <= \^m_axi_awaddr\(95 downto 80); + m_axi_araddr(79 downto 64) <= \^m_axi_araddr\(15 downto 0); + m_axi_araddr(63 downto 48) <= \^m_axi_awaddr\(95 downto 80); + m_axi_araddr(47 downto 32) <= \^m_axi_araddr\(15 downto 0); + m_axi_araddr(31 downto 16) <= \^m_axi_awaddr\(95 downto 80); + m_axi_araddr(15 downto 0) <= \^m_axi_araddr\(15 downto 0); + m_axi_arburst(5) <= \\; + m_axi_arburst(4) <= \\; + m_axi_arburst(3) <= \\; + m_axi_arburst(2) <= \\; + m_axi_arburst(1) <= \\; + m_axi_arburst(0) <= \\; + m_axi_arcache(11) <= \\; + m_axi_arcache(10) <= \\; + m_axi_arcache(9) <= \\; + m_axi_arcache(8) <= \\; + m_axi_arcache(7) <= \\; + m_axi_arcache(6) <= \\; + m_axi_arcache(5) <= \\; + m_axi_arcache(4) <= \\; + m_axi_arcache(3) <= \\; + m_axi_arcache(2) <= \\; + m_axi_arcache(1) <= \\; + m_axi_arcache(0) <= \\; + m_axi_arid(2) <= \\; + m_axi_arid(1) <= \\; + m_axi_arid(0) <= \\; + m_axi_arlen(23) <= \\; + m_axi_arlen(22) <= \\; + m_axi_arlen(21) <= \\; + m_axi_arlen(20) <= \\; + m_axi_arlen(19) <= \\; + m_axi_arlen(18) <= \\; + m_axi_arlen(17) <= \\; + m_axi_arlen(16) <= \\; + m_axi_arlen(15) <= \\; + m_axi_arlen(14) <= \\; + m_axi_arlen(13) <= \\; + m_axi_arlen(12) <= \\; + m_axi_arlen(11) <= \\; + m_axi_arlen(10) <= \\; + m_axi_arlen(9) <= \\; + m_axi_arlen(8) <= \\; + m_axi_arlen(7) <= \\; + m_axi_arlen(6) <= \\; + m_axi_arlen(5) <= \\; + m_axi_arlen(4) <= \\; + m_axi_arlen(3) <= \\; + m_axi_arlen(2) <= \\; + m_axi_arlen(1) <= \\; + m_axi_arlen(0) <= \\; + m_axi_arlock(2) <= \\; + m_axi_arlock(1) <= \\; + m_axi_arlock(0) <= \\; + m_axi_arprot(8 downto 6) <= \^m_axi_arprot\(2 downto 0); + m_axi_arprot(5 downto 3) <= \^m_axi_arprot\(2 downto 0); + m_axi_arprot(2 downto 0) <= \^m_axi_arprot\(2 downto 0); + m_axi_arqos(11) <= \\; + m_axi_arqos(10) <= \\; + m_axi_arqos(9) <= \\; + m_axi_arqos(8) <= \\; + m_axi_arqos(7) <= \\; + m_axi_arqos(6) <= \\; + m_axi_arqos(5) <= \\; + m_axi_arqos(4) <= \\; + m_axi_arqos(3) <= \\; + m_axi_arqos(2) <= \\; + m_axi_arqos(1) <= \\; + m_axi_arqos(0) <= \\; + m_axi_arregion(11) <= \\; + m_axi_arregion(10) <= \\; + m_axi_arregion(9) <= \\; + m_axi_arregion(8) <= \\; + m_axi_arregion(7) <= \\; + m_axi_arregion(6) <= \\; + m_axi_arregion(5) <= \\; + m_axi_arregion(4) <= \\; + m_axi_arregion(3) <= \\; + m_axi_arregion(2) <= \\; + m_axi_arregion(1) <= \\; + m_axi_arregion(0) <= \\; + m_axi_arsize(8) <= \\; + m_axi_arsize(7) <= \\; + m_axi_arsize(6) <= \\; + m_axi_arsize(5) <= \\; + m_axi_arsize(4) <= \\; + m_axi_arsize(3) <= \\; + m_axi_arsize(2) <= \\; + m_axi_arsize(1) <= \\; + m_axi_arsize(0) <= \\; + m_axi_aruser(2) <= \\; + m_axi_aruser(1) <= \\; + m_axi_aruser(0) <= \\; + m_axi_awaddr(95 downto 80) <= \^m_axi_awaddr\(95 downto 80); + m_axi_awaddr(79 downto 64) <= \^m_axi_araddr\(15 downto 0); + m_axi_awaddr(63 downto 48) <= \^m_axi_awaddr\(95 downto 80); + m_axi_awaddr(47 downto 32) <= \^m_axi_araddr\(15 downto 0); + m_axi_awaddr(31 downto 16) <= \^m_axi_awaddr\(95 downto 80); + m_axi_awaddr(15 downto 0) <= \^m_axi_araddr\(15 downto 0); + m_axi_awburst(5) <= \\; + m_axi_awburst(4) <= \\; + m_axi_awburst(3) <= \\; + m_axi_awburst(2) <= \\; + m_axi_awburst(1) <= \\; + m_axi_awburst(0) <= \\; + m_axi_awcache(11) <= \\; + m_axi_awcache(10) <= \\; + m_axi_awcache(9) <= \\; + m_axi_awcache(8) <= \\; + m_axi_awcache(7) <= \\; + m_axi_awcache(6) <= \\; + m_axi_awcache(5) <= \\; + m_axi_awcache(4) <= \\; + m_axi_awcache(3) <= \\; + m_axi_awcache(2) <= \\; + m_axi_awcache(1) <= \\; + m_axi_awcache(0) <= \\; + m_axi_awid(2) <= \\; + m_axi_awid(1) <= \\; + m_axi_awid(0) <= \\; + m_axi_awlen(23) <= \\; + m_axi_awlen(22) <= \\; + m_axi_awlen(21) <= \\; + m_axi_awlen(20) <= \\; + m_axi_awlen(19) <= \\; + m_axi_awlen(18) <= \\; + m_axi_awlen(17) <= \\; + m_axi_awlen(16) <= \\; + m_axi_awlen(15) <= \\; + m_axi_awlen(14) <= \\; + m_axi_awlen(13) <= \\; + m_axi_awlen(12) <= \\; + m_axi_awlen(11) <= \\; + m_axi_awlen(10) <= \\; + m_axi_awlen(9) <= \\; + m_axi_awlen(8) <= \\; + m_axi_awlen(7) <= \\; + m_axi_awlen(6) <= \\; + m_axi_awlen(5) <= \\; + m_axi_awlen(4) <= \\; + m_axi_awlen(3) <= \\; + m_axi_awlen(2) <= \\; + m_axi_awlen(1) <= \\; + m_axi_awlen(0) <= \\; + m_axi_awlock(2) <= \\; + m_axi_awlock(1) <= \\; + m_axi_awlock(0) <= \\; + m_axi_awprot(8 downto 6) <= \^m_axi_arprot\(2 downto 0); + m_axi_awprot(5 downto 3) <= \^m_axi_arprot\(2 downto 0); + m_axi_awprot(2 downto 0) <= \^m_axi_arprot\(2 downto 0); + m_axi_awqos(11) <= \\; + m_axi_awqos(10) <= \\; + m_axi_awqos(9) <= \\; + m_axi_awqos(8) <= \\; + m_axi_awqos(7) <= \\; + m_axi_awqos(6) <= \\; + m_axi_awqos(5) <= \\; + m_axi_awqos(4) <= \\; + m_axi_awqos(3) <= \\; + m_axi_awqos(2) <= \\; + m_axi_awqos(1) <= \\; + m_axi_awqos(0) <= \\; + m_axi_awregion(11) <= \\; + m_axi_awregion(10) <= \\; + m_axi_awregion(9) <= \\; + m_axi_awregion(8) <= \\; + m_axi_awregion(7) <= \\; + m_axi_awregion(6) <= \\; + m_axi_awregion(5) <= \\; + m_axi_awregion(4) <= \\; + m_axi_awregion(3) <= \\; + m_axi_awregion(2) <= \\; + m_axi_awregion(1) <= \\; + m_axi_awregion(0) <= \\; + m_axi_awsize(8) <= \\; + m_axi_awsize(7) <= \\; + m_axi_awsize(6) <= \\; + m_axi_awsize(5) <= \\; + m_axi_awsize(4) <= \\; + m_axi_awsize(3) <= \\; + m_axi_awsize(2) <= \\; + m_axi_awsize(1) <= \\; + m_axi_awsize(0) <= \\; + m_axi_awuser(2) <= \\; + m_axi_awuser(1) <= \\; + m_axi_awuser(0) <= \\; + m_axi_wdata(95 downto 64) <= \^s_axi_wdata\(31 downto 0); + m_axi_wdata(63 downto 32) <= \^s_axi_wdata\(31 downto 0); + m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0); + m_axi_wid(2) <= \\; + m_axi_wid(1) <= \\; + m_axi_wid(0) <= \\; + m_axi_wlast(2) <= \\; + m_axi_wlast(1) <= \\; + m_axi_wlast(0) <= \\; + m_axi_wstrb(11 downto 8) <= \^s_axi_wstrb\(3 downto 0); + m_axi_wstrb(7 downto 4) <= \^s_axi_wstrb\(3 downto 0); + m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0); + m_axi_wuser(2) <= \\; + m_axi_wuser(1) <= \\; + m_axi_wuser(0) <= \\; + s_axi_bid(0) <= \\; + s_axi_buser(0) <= \\; + s_axi_rid(0) <= \\; + s_axi_rlast(0) <= \\; + s_axi_ruser(0) <= \\; +GND: unisim.vcomponents.GND + port map ( + G => \\ + ); +\gen_sasd.crossbar_sasd_0\: entity work.NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_crossbar_sasd + port map ( + Q(34 downto 32) => \^m_axi_arprot\(2 downto 0), + Q(31 downto 16) => \^m_axi_awaddr\(95 downto 80), + Q(15 downto 0) => \^m_axi_araddr\(15 downto 0), + aclk => aclk, + aresetn => aresetn, + m_axi_arready(2 downto 0) => m_axi_arready(2 downto 0), + m_axi_arvalid(2 downto 0) => m_axi_arvalid(2 downto 0), + m_axi_awready(2 downto 0) => m_axi_awready(2 downto 0), + m_axi_awvalid(2 downto 0) => m_axi_awvalid(2 downto 0), + m_axi_bready(2 downto 0) => m_axi_bready(2 downto 0), + m_axi_bresp(5 downto 0) => m_axi_bresp(5 downto 0), + m_axi_bvalid(2 downto 0) => m_axi_bvalid(2 downto 0), + m_axi_rdata(95 downto 0) => m_axi_rdata(95 downto 0), + m_axi_rready(2 downto 0) => m_axi_rready(2 downto 0), + m_axi_rresp(5 downto 0) => m_axi_rresp(5 downto 0), + m_axi_rvalid(2 downto 0) => m_axi_rvalid(2 downto 0), + m_axi_wready(2 downto 0) => m_axi_wready(2 downto 0), + m_axi_wvalid(2 downto 0) => m_axi_wvalid(2 downto 0), + \m_payload_i_reg[34]\(33 downto 2) => s_axi_rdata(31 downto 0), + \m_payload_i_reg[34]\(1 downto 0) => s_axi_rresp(1 downto 0), + s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), + s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), + s_axi_arready(0) => s_axi_arready(0), + s_axi_arvalid(0) => s_axi_arvalid(0), + s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), + s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), + s_axi_awready(0) => s_axi_awready(0), + s_axi_awvalid(0) => s_axi_awvalid(0), + s_axi_bready(0) => s_axi_bready(0), + s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0), + s_axi_bvalid(0) => s_axi_bvalid(0), + s_axi_rready(0) => s_axi_rready(0), + s_axi_rvalid(0) => s_axi_rvalid(0), + s_axi_wready(0) => s_axi_wready(0), + s_axi_wvalid(0) => s_axi_wvalid(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity NewExtInst_TOP_xbar_0 is + port ( + aclk : in STD_LOGIC; + aresetn : in STD_LOGIC; + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awaddr : out STD_LOGIC_VECTOR ( 95 downto 0 ); + m_axi_awprot : out STD_LOGIC_VECTOR ( 8 downto 0 ); + m_axi_awvalid : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awready : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_wdata : out STD_LOGIC_VECTOR ( 95 downto 0 ); + m_axi_wstrb : out STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_wvalid : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_wready : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_bresp : in STD_LOGIC_VECTOR ( 5 downto 0 ); + m_axi_bvalid : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_bready : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_araddr : out STD_LOGIC_VECTOR ( 95 downto 0 ); + m_axi_arprot : out STD_LOGIC_VECTOR ( 8 downto 0 ); + m_axi_arvalid : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arready : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_rdata : in STD_LOGIC_VECTOR ( 95 downto 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 5 downto 0 ); + m_axi_rvalid : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_rready : out STD_LOGIC_VECTOR ( 2 downto 0 ) + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of NewExtInst_TOP_xbar_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of NewExtInst_TOP_xbar_0 : entity is "NewExtInst_TOP_xbar_0,axi_crossbar_v2_1_30_axi_crossbar,{}"; + attribute DowngradeIPIdentifiedWarnings : string; + attribute DowngradeIPIdentifiedWarnings of NewExtInst_TOP_xbar_0 : entity is "yes"; + attribute X_CORE_INFO : string; + attribute X_CORE_INFO of NewExtInst_TOP_xbar_0 : entity is "axi_crossbar_v2_1_30_axi_crossbar,Vivado 2023.2"; +end NewExtInst_TOP_xbar_0; + +architecture STRUCTURE of NewExtInst_TOP_xbar_0 is + signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 ); + signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 ); + signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_s_axi_rlast_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + attribute C_AXI_ADDR_WIDTH : integer; + attribute C_AXI_ADDR_WIDTH of inst : label is 32; + attribute C_AXI_ARUSER_WIDTH : integer; + attribute C_AXI_ARUSER_WIDTH of inst : label is 1; + attribute C_AXI_AWUSER_WIDTH : integer; + attribute C_AXI_AWUSER_WIDTH of inst : label is 1; + attribute C_AXI_BUSER_WIDTH : integer; + attribute C_AXI_BUSER_WIDTH of inst : label is 1; + attribute C_AXI_DATA_WIDTH : integer; + attribute C_AXI_DATA_WIDTH of inst : label is 32; + attribute C_AXI_ID_WIDTH : integer; + attribute C_AXI_ID_WIDTH of inst : label is 1; + attribute C_AXI_PROTOCOL : integer; + attribute C_AXI_PROTOCOL of inst : label is 2; + attribute C_AXI_RUSER_WIDTH : integer; + attribute C_AXI_RUSER_WIDTH of inst : label is 1; + attribute C_AXI_SUPPORTS_USER_SIGNALS : integer; + attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0; + attribute C_AXI_WUSER_WIDTH : integer; + attribute C_AXI_WUSER_WIDTH of inst : label is 1; + attribute C_CONNECTIVITY_MODE : integer; + attribute C_CONNECTIVITY_MODE of inst : label is 0; + attribute C_DEBUG : integer; + attribute C_DEBUG of inst : label is 1; + attribute C_FAMILY : string; + attribute C_FAMILY of inst : label is "zynq"; + attribute C_M_AXI_ADDR_WIDTH : string; + attribute C_M_AXI_ADDR_WIDTH of inst : label is "96'b000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000"; + attribute C_M_AXI_BASE_ADDR : string; + attribute C_M_AXI_BASE_ADDR of inst : label is "192'b000000000000000000000000000000000100001111000010000000000000000000000000000000000000000000000000010000111100000100000000000000000000000000000000000000000000000001000011110000000000000000000000"; + attribute C_M_AXI_READ_CONNECTIVITY : string; + attribute C_M_AXI_READ_CONNECTIVITY of inst : label is "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"; + attribute C_M_AXI_READ_ISSUING : string; + attribute C_M_AXI_READ_ISSUING of inst : label is "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"; + attribute C_M_AXI_SECURE : string; + attribute C_M_AXI_SECURE of inst : label is "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute C_M_AXI_WRITE_CONNECTIVITY : string; + attribute C_M_AXI_WRITE_CONNECTIVITY of inst : label is "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"; + attribute C_M_AXI_WRITE_ISSUING : string; + attribute C_M_AXI_WRITE_ISSUING of inst : label is "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"; + attribute C_NUM_ADDR_RANGES : integer; + attribute C_NUM_ADDR_RANGES of inst : label is 1; + attribute C_NUM_MASTER_SLOTS : integer; + attribute C_NUM_MASTER_SLOTS of inst : label is 3; + attribute C_NUM_SLAVE_SLOTS : integer; + attribute C_NUM_SLAVE_SLOTS of inst : label is 1; + attribute C_R_REGISTER : integer; + attribute C_R_REGISTER of inst : label is 1; + attribute C_S_AXI_ARB_PRIORITY : integer; + attribute C_S_AXI_ARB_PRIORITY of inst : label is 0; + attribute C_S_AXI_BASE_ID : integer; + attribute C_S_AXI_BASE_ID of inst : label is 0; + attribute C_S_AXI_READ_ACCEPTANCE : integer; + attribute C_S_AXI_READ_ACCEPTANCE of inst : label is 1; + attribute C_S_AXI_SINGLE_THREAD : integer; + attribute C_S_AXI_SINGLE_THREAD of inst : label is 1; + attribute C_S_AXI_THREAD_ID_WIDTH : integer; + attribute C_S_AXI_THREAD_ID_WIDTH of inst : label is 0; + attribute C_S_AXI_WRITE_ACCEPTANCE : integer; + attribute C_S_AXI_WRITE_ACCEPTANCE of inst : label is 1; + attribute DowngradeIPIdentifiedWarnings of inst : label is "yes"; + attribute P_ADDR_DECODE : integer; + attribute P_ADDR_DECODE of inst : label is 1; + attribute P_AXI3 : integer; + attribute P_AXI3 of inst : label is 1; + attribute P_AXI4 : integer; + attribute P_AXI4 of inst : label is 0; + attribute P_AXILITE : integer; + attribute P_AXILITE of inst : label is 2; + attribute P_AXILITE_SIZE : string; + attribute P_AXILITE_SIZE of inst : label is "3'b010"; + attribute P_FAMILY : string; + attribute P_FAMILY of inst : label is "zynq"; + attribute P_INCR : string; + attribute P_INCR of inst : label is "2'b01"; + attribute P_LEN : integer; + attribute P_LEN of inst : label is 8; + attribute P_LOCK : integer; + attribute P_LOCK of inst : label is 1; + attribute P_M_AXI_ERR_MODE : string; + attribute P_M_AXI_ERR_MODE of inst : label is "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute P_M_AXI_SUPPORTS_READ : string; + attribute P_M_AXI_SUPPORTS_READ of inst : label is "3'b111"; + attribute P_M_AXI_SUPPORTS_WRITE : string; + attribute P_M_AXI_SUPPORTS_WRITE of inst : label is "3'b111"; + attribute P_ONES : string; + attribute P_ONES of inst : label is "65'b11111111111111111111111111111111111111111111111111111111111111111"; + attribute P_RANGE_CHECK : integer; + attribute P_RANGE_CHECK of inst : label is 1; + attribute P_S_AXI_BASE_ID : string; + attribute P_S_AXI_BASE_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000"; + attribute P_S_AXI_HIGH_ID : string; + attribute P_S_AXI_HIGH_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000"; + attribute P_S_AXI_SUPPORTS_READ : string; + attribute P_S_AXI_SUPPORTS_READ of inst : label is "1'b1"; + attribute P_S_AXI_SUPPORTS_WRITE : string; + attribute P_S_AXI_SUPPORTS_WRITE of inst : label is "1'b1"; + attribute X_INTERFACE_INFO : string; + attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLKIF CLK"; + attribute X_INTERFACE_PARAMETER : string; + attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLKIF, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0"; + attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RSTIF RST"; + attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT"; + attribute X_INTERFACE_INFO of m_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64]"; + attribute X_INTERFACE_INFO of m_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6]"; + attribute X_INTERFACE_INFO of m_axi_arready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2]"; + attribute X_INTERFACE_INFO of m_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2]"; + attribute X_INTERFACE_INFO of m_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64]"; + attribute X_INTERFACE_INFO of m_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6]"; + attribute X_INTERFACE_INFO of m_axi_awready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2]"; + attribute X_INTERFACE_INFO of m_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2]"; + attribute X_INTERFACE_INFO of m_axi_bready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2]"; + attribute X_INTERFACE_INFO of m_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4]"; + attribute X_INTERFACE_INFO of m_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2]"; + attribute X_INTERFACE_INFO of m_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64]"; + attribute X_INTERFACE_INFO of m_axi_rready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2]"; + attribute X_INTERFACE_PARAMETER of m_axi_rready : signal is "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0"; + attribute X_INTERFACE_INFO of m_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4]"; + attribute X_INTERFACE_INFO of m_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2]"; + attribute X_INTERFACE_INFO of m_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64]"; + attribute X_INTERFACE_INFO of m_axi_wready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2]"; + attribute X_INTERFACE_INFO of m_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8]"; + attribute X_INTERFACE_INFO of m_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2]"; + attribute X_INTERFACE_INFO of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR"; + attribute X_INTERFACE_INFO of s_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT"; + attribute X_INTERFACE_INFO of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY"; + attribute X_INTERFACE_INFO of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID"; + attribute X_INTERFACE_INFO of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR"; + attribute X_INTERFACE_INFO of s_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT"; + attribute X_INTERFACE_INFO of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY"; + attribute X_INTERFACE_INFO of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID"; + attribute X_INTERFACE_INFO of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BREADY"; + attribute X_INTERFACE_INFO of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BRESP"; + attribute X_INTERFACE_INFO of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BVALID"; + attribute X_INTERFACE_INFO of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RDATA"; + attribute X_INTERFACE_INFO of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RREADY"; + attribute X_INTERFACE_PARAMETER of s_axi_rready : signal is "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0"; + attribute X_INTERFACE_INFO of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RRESP"; + attribute X_INTERFACE_INFO of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RVALID"; + attribute X_INTERFACE_INFO of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WDATA"; + attribute X_INTERFACE_INFO of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WREADY"; + attribute X_INTERFACE_INFO of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB"; + attribute X_INTERFACE_INFO of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WVALID"; +begin +inst: entity work.NewExtInst_TOP_xbar_0_axi_crossbar_v2_1_30_axi_crossbar + port map ( + aclk => aclk, + aresetn => aresetn, + m_axi_araddr(95 downto 0) => m_axi_araddr(95 downto 0), + m_axi_arburst(5 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(5 downto 0), + m_axi_arcache(11 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(11 downto 0), + m_axi_arid(2 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(2 downto 0), + m_axi_arlen(23 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(23 downto 0), + m_axi_arlock(2 downto 0) => NLW_inst_m_axi_arlock_UNCONNECTED(2 downto 0), + m_axi_arprot(8 downto 0) => m_axi_arprot(8 downto 0), + m_axi_arqos(11 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(11 downto 0), + m_axi_arready(2 downto 0) => m_axi_arready(2 downto 0), + m_axi_arregion(11 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(11 downto 0), + m_axi_arsize(8 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(8 downto 0), + m_axi_aruser(2 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(2 downto 0), + m_axi_arvalid(2 downto 0) => m_axi_arvalid(2 downto 0), + m_axi_awaddr(95 downto 0) => m_axi_awaddr(95 downto 0), + m_axi_awburst(5 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(5 downto 0), + m_axi_awcache(11 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(11 downto 0), + m_axi_awid(2 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(2 downto 0), + m_axi_awlen(23 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(23 downto 0), + m_axi_awlock(2 downto 0) => NLW_inst_m_axi_awlock_UNCONNECTED(2 downto 0), + m_axi_awprot(8 downto 0) => m_axi_awprot(8 downto 0), + m_axi_awqos(11 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(11 downto 0), + m_axi_awready(2 downto 0) => m_axi_awready(2 downto 0), + m_axi_awregion(11 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(11 downto 0), + m_axi_awsize(8 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(8 downto 0), + m_axi_awuser(2 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(2 downto 0), + m_axi_awvalid(2 downto 0) => m_axi_awvalid(2 downto 0), + m_axi_bid(2 downto 0) => B"000", + m_axi_bready(2 downto 0) => m_axi_bready(2 downto 0), + m_axi_bresp(5 downto 0) => m_axi_bresp(5 downto 0), + m_axi_buser(2 downto 0) => B"000", + m_axi_bvalid(2 downto 0) => m_axi_bvalid(2 downto 0), + m_axi_rdata(95 downto 0) => m_axi_rdata(95 downto 0), + m_axi_rid(2 downto 0) => B"000", + m_axi_rlast(2 downto 0) => B"111", + m_axi_rready(2 downto 0) => m_axi_rready(2 downto 0), + m_axi_rresp(5 downto 0) => m_axi_rresp(5 downto 0), + m_axi_ruser(2 downto 0) => B"000", + m_axi_rvalid(2 downto 0) => m_axi_rvalid(2 downto 0), + m_axi_wdata(95 downto 0) => m_axi_wdata(95 downto 0), + m_axi_wid(2 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(2 downto 0), + m_axi_wlast(2 downto 0) => NLW_inst_m_axi_wlast_UNCONNECTED(2 downto 0), + m_axi_wready(2 downto 0) => m_axi_wready(2 downto 0), + m_axi_wstrb(11 downto 0) => m_axi_wstrb(11 downto 0), + m_axi_wuser(2 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(2 downto 0), + m_axi_wvalid(2 downto 0) => m_axi_wvalid(2 downto 0), + s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), + s_axi_arburst(1 downto 0) => B"00", + s_axi_arcache(3 downto 0) => B"0000", + s_axi_arid(0) => '0', + s_axi_arlen(7 downto 0) => B"00000000", + s_axi_arlock(0) => '0', + s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), + s_axi_arqos(3 downto 0) => B"0000", + s_axi_arready(0) => s_axi_arready(0), + s_axi_arsize(2 downto 0) => B"000", + s_axi_aruser(0) => '0', + s_axi_arvalid(0) => s_axi_arvalid(0), + s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), + s_axi_awburst(1 downto 0) => B"00", + s_axi_awcache(3 downto 0) => B"0000", + s_axi_awid(0) => '0', + s_axi_awlen(7 downto 0) => B"00000000", + s_axi_awlock(0) => '0', + s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), + s_axi_awqos(3 downto 0) => B"0000", + s_axi_awready(0) => s_axi_awready(0), + s_axi_awsize(2 downto 0) => B"000", + s_axi_awuser(0) => '0', + s_axi_awvalid(0) => s_axi_awvalid(0), + s_axi_bid(0) => NLW_inst_s_axi_bid_UNCONNECTED(0), + s_axi_bready(0) => s_axi_bready(0), + s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0), + s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0), + s_axi_bvalid(0) => s_axi_bvalid(0), + s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), + s_axi_rid(0) => NLW_inst_s_axi_rid_UNCONNECTED(0), + s_axi_rlast(0) => NLW_inst_s_axi_rlast_UNCONNECTED(0), + s_axi_rready(0) => s_axi_rready(0), + s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0), + s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0), + s_axi_rvalid(0) => s_axi_rvalid(0), + s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), + s_axi_wid(0) => '0', + s_axi_wlast(0) => '1', + s_axi_wready(0) => s_axi_wready(0), + s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0), + s_axi_wuser(0) => '0', + s_axi_wvalid(0) => s_axi_wvalid(0) + ); +end STRUCTURE; diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/sim/NewExtInst_TOP_xbar_0.v b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/sim/NewExtInst_TOP_xbar_0.v new file mode 100644 index 0000000..f11495c --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/sim/NewExtInst_TOP_xbar_0.v @@ -0,0 +1,310 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:axi_crossbar:2.1 +// IP Revision: 30 + +`timescale 1ns/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module NewExtInst_TOP_xbar_0 ( + aclk, + aresetn, + s_axi_awaddr, + s_axi_awprot, + s_axi_awvalid, + s_axi_awready, + s_axi_wdata, + s_axi_wstrb, + s_axi_wvalid, + s_axi_wready, + s_axi_bresp, + s_axi_bvalid, + s_axi_bready, + s_axi_araddr, + s_axi_arprot, + s_axi_arvalid, + s_axi_arready, + s_axi_rdata, + s_axi_rresp, + s_axi_rvalid, + s_axi_rready, + m_axi_awaddr, + m_axi_awprot, + m_axi_awvalid, + m_axi_awready, + m_axi_wdata, + m_axi_wstrb, + m_axi_wvalid, + m_axi_wready, + m_axi_bresp, + m_axi_bvalid, + m_axi_bready, + m_axi_araddr, + m_axi_arprot, + m_axi_arvalid, + m_axi_arready, + m_axi_rdata, + m_axi_rresp, + m_axi_rvalid, + m_axi_rready +); + +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) +input wire aclk; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) +input wire aresetn; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *) +input wire [31 : 0] s_axi_awaddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *) +input wire [2 : 0] s_axi_awprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *) +input wire [0 : 0] s_axi_awvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *) +output wire [0 : 0] s_axi_awready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *) +input wire [31 : 0] s_axi_wdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *) +input wire [3 : 0] s_axi_wstrb; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *) +input wire [0 : 0] s_axi_wvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *) +output wire [0 : 0] s_axi_wready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *) +output wire [1 : 0] s_axi_bresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *) +output wire [0 : 0] s_axi_bvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *) +input wire [0 : 0] s_axi_bready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *) +input wire [31 : 0] s_axi_araddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *) +input wire [2 : 0] s_axi_arprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *) +input wire [0 : 0] s_axi_arvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *) +output wire [0 : 0] s_axi_arready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *) +output wire [31 : 0] s_axi_rdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *) +output wire [1 : 0] s_axi_rresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *) +output wire [0 : 0] s_axi_rvalid; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 4, NUM_WRITE_THREADS\ + 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) +input wire [0 : 0] s_axi_rready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64]" *) +output wire [95 : 0] m_axi_awaddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6]" *) +output wire [8 : 0] m_axi_awprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2]" *) +output wire [2 : 0] m_axi_awvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2]" *) +input wire [2 : 0] m_axi_awready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64]" *) +output wire [95 : 0] m_axi_wdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8]" *) +output wire [11 : 0] m_axi_wstrb; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2]" *) +output wire [2 : 0] m_axi_wvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2]" *) +input wire [2 : 0] m_axi_wready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4]" *) +input wire [5 : 0] m_axi_bresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2]" *) +input wire [2 : 0] m_axi_bvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2]" *) +output wire [2 : 0] m_axi_bready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64]" *) +output wire [95 : 0] m_axi_araddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6]" *) +output wire [8 : 0] m_axi_arprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2]" *) +output wire [2 : 0] m_axi_arvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2]" *) +input wire [2 : 0] m_axi_arready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64]" *) +input wire [95 : 0] m_axi_rdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4]" *) +input wire [5 : 0] m_axi_rresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2]" *) +input wire [2 : 0] m_axi_rvalid; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS\ + 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_D\ +OMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING \ +2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2]" *) +output wire [2 : 0] m_axi_rready; + + axi_crossbar_v2_1_30_axi_crossbar #( + .C_FAMILY("zynq"), + .C_NUM_SLAVE_SLOTS(1), + .C_NUM_MASTER_SLOTS(3), + .C_AXI_ID_WIDTH(1), + .C_AXI_ADDR_WIDTH(32), + .C_AXI_DATA_WIDTH(32), + .C_AXI_PROTOCOL(2), + .C_NUM_ADDR_RANGES(1), + .C_M_AXI_BASE_ADDR(192'H0000000043c200000000000043c100000000000043c00000), + .C_M_AXI_ADDR_WIDTH(96'H000000100000001000000010), + .C_S_AXI_BASE_ID(32'H00000000), + .C_S_AXI_THREAD_ID_WIDTH(32'H00000000), + .C_AXI_SUPPORTS_USER_SIGNALS(0), + .C_AXI_AWUSER_WIDTH(1), + .C_AXI_ARUSER_WIDTH(1), + .C_AXI_WUSER_WIDTH(1), + .C_AXI_RUSER_WIDTH(1), + .C_AXI_BUSER_WIDTH(1), + .C_M_AXI_WRITE_CONNECTIVITY(96'H000000010000000100000001), + .C_M_AXI_READ_CONNECTIVITY(96'H000000010000000100000001), + .C_R_REGISTER(1), + .C_S_AXI_SINGLE_THREAD(32'H00000001), + .C_S_AXI_WRITE_ACCEPTANCE(32'H00000001), + .C_S_AXI_READ_ACCEPTANCE(32'H00000001), + .C_M_AXI_WRITE_ISSUING(96'H000000010000000100000001), + .C_M_AXI_READ_ISSUING(96'H000000010000000100000001), + .C_S_AXI_ARB_PRIORITY(32'H00000000), + .C_M_AXI_SECURE(96'H000000000000000000000000), + .C_CONNECTIVITY_MODE(0) + ) inst ( + .aclk(aclk), + .aresetn(aresetn), + .s_axi_awid(1'H0), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awlen(8'H00), + .s_axi_awsize(3'H0), + .s_axi_awburst(2'H0), + .s_axi_awlock(1'H0), + .s_axi_awcache(4'H0), + .s_axi_awprot(s_axi_awprot), + .s_axi_awqos(4'H0), + .s_axi_awuser(1'H0), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_awready(s_axi_awready), + .s_axi_wid(1'H0), + .s_axi_wdata(s_axi_wdata), + .s_axi_wstrb(s_axi_wstrb), + .s_axi_wlast(1'H1), + .s_axi_wuser(1'H0), + .s_axi_wvalid(s_axi_wvalid), + .s_axi_wready(s_axi_wready), + .s_axi_bid(), + .s_axi_bresp(s_axi_bresp), + .s_axi_buser(), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_bready(s_axi_bready), + .s_axi_arid(1'H0), + .s_axi_araddr(s_axi_araddr), + .s_axi_arlen(8'H00), + .s_axi_arsize(3'H0), + .s_axi_arburst(2'H0), + .s_axi_arlock(1'H0), + .s_axi_arcache(4'H0), + .s_axi_arprot(s_axi_arprot), + .s_axi_arqos(4'H0), + .s_axi_aruser(1'H0), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_arready(s_axi_arready), + .s_axi_rid(), + .s_axi_rdata(s_axi_rdata), + .s_axi_rresp(s_axi_rresp), + .s_axi_rlast(), + .s_axi_ruser(), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_rready(s_axi_rready), + .m_axi_awid(), + .m_axi_awaddr(m_axi_awaddr), + .m_axi_awlen(), + .m_axi_awsize(), + .m_axi_awburst(), + .m_axi_awlock(), + .m_axi_awcache(), + .m_axi_awprot(m_axi_awprot), + .m_axi_awregion(), + .m_axi_awqos(), + .m_axi_awuser(), + .m_axi_awvalid(m_axi_awvalid), + .m_axi_awready(m_axi_awready), + .m_axi_wid(), + .m_axi_wdata(m_axi_wdata), + .m_axi_wstrb(m_axi_wstrb), + .m_axi_wlast(), + .m_axi_wuser(), + .m_axi_wvalid(m_axi_wvalid), + .m_axi_wready(m_axi_wready), + .m_axi_bid(3'H0), + .m_axi_bresp(m_axi_bresp), + .m_axi_buser(3'H0), + .m_axi_bvalid(m_axi_bvalid), + .m_axi_bready(m_axi_bready), + .m_axi_arid(), + .m_axi_araddr(m_axi_araddr), + .m_axi_arlen(), + .m_axi_arsize(), + .m_axi_arburst(), + .m_axi_arlock(), + .m_axi_arcache(), + .m_axi_arprot(m_axi_arprot), + .m_axi_arregion(), + .m_axi_arqos(), + .m_axi_aruser(), + .m_axi_arvalid(m_axi_arvalid), + .m_axi_arready(m_axi_arready), + .m_axi_rid(3'H0), + .m_axi_rdata(m_axi_rdata), + .m_axi_rresp(m_axi_rresp), + .m_axi_rlast(3'H7), + .m_axi_ruser(3'H0), + .m_axi_rvalid(m_axi_rvalid), + .m_axi_rready(m_axi_rready) + ); +endmodule diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v new file mode 100755 index 0000000..e54befa --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v @@ -0,0 +1,128 @@ + +`timescale 1 ns / 1 ps + + module SPI_Con_v1_0 # + ( + // Users to add parameters here + + // User parameters ends + // Do not modify the parameters beyond this line + + + // Parameters of Axi Slave Bus Interface S00_AXI + parameter integer C_S00_AXI_DATA_WIDTH = 32, + parameter integer C_S00_AXI_ADDR_WIDTH = 7 + ) + ( + // Users to add ports here + input wire i_miso, + output wire o_sclk, + output wire o_cs, + output wire o_mosi, + + + // User ports ends + // Do not modify the ports beyond this line + + + // Ports of Axi Slave Bus Interface S00_AXI + input wire s00_axi_aclk, + input wire s00_axi_aresetn, + input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr, + input wire [2 : 0] s00_axi_awprot, + input wire s00_axi_awvalid, + output wire s00_axi_awready, + input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata, + input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb, + input wire s00_axi_wvalid, + output wire s00_axi_wready, + output wire [1 : 0] s00_axi_bresp, + output wire s00_axi_bvalid, + input wire s00_axi_bready, + input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr, + input wire [2 : 0] s00_axi_arprot, + input wire s00_axi_arvalid, + output wire s00_axi_arready, + output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata, + output wire [1 : 0] s00_axi_rresp, + output wire s00_axi_rvalid, + input wire s00_axi_rready + ); +// Public Reg + reg [6:0]spi_addr ; + reg [23:0]spi_data; + reg w_req; + reg r_req; + reg spi_done; + + +// Instantiation of Axi Bus Interface S00_AXI +// This inst will handle actul AXI commiuncation and register read/write + SPI_Con_v1_0_S00_AXI # ( + .C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH), + .C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH) + ) SPI_Con_v1_0_S00_AXI_inst ( + .S_AXI_ACLK(s00_axi_aclk), + .S_AXI_ARESETN(s00_axi_aresetn), + .S_AXI_AWADDR(s00_axi_awaddr), + .S_AXI_AWPROT(s00_axi_awprot), + .S_AXI_AWVALID(s00_axi_awvalid), + .S_AXI_AWREADY(s00_axi_awready), + .S_AXI_WDATA(s00_axi_wdata), + .S_AXI_WSTRB(s00_axi_wstrb), + .S_AXI_WVALID(s00_axi_wvalid), + .S_AXI_WREADY(s00_axi_wready), + .S_AXI_BRESP(s00_axi_bresp), + .S_AXI_BVALID(s00_axi_bvalid), + .S_AXI_BREADY(s00_axi_bready), + .S_AXI_ARADDR(s00_axi_araddr), + .S_AXI_ARPROT(s00_axi_arprot), + .S_AXI_ARVALID(s00_axi_arvalid), + .S_AXI_ARREADY(s00_axi_arready), + .S_AXI_RDATA(s00_axi_rdata), + .S_AXI_RRESP(s00_axi_rresp), + .S_AXI_RVALID(s00_axi_rvalid), + .S_AXI_RREADY(s00_axi_rready), + .i_spi_data(spi_data), + .i_spi_done(spi_done), + .o_wreq(w_req), + .o_spi_addr(spi_addr), + .o_rreq(r_req) + ); + + // Add user logic here + //SPI Reg + reg mosi_reg; + reg miso_reg; + reg sclk_reg; + reg cs_reg; + + //Flag reg + reg busy_flag; + + + always @(posedge s00_axi_aclk) begin + if (s00_axi_aresetn == 1'b0) begin + mosi_reg <= 1'b0; + miso_reg <= 1'b0; + sclk_reg <= 1'b0; + cs_reg <= 1'b1; + spi_done <= 1'b1; + end + else begin + if ((w_req == 1'b1) | (r_req == 1'b1)) begin + spi_done <= 1'b0; + + end + else begin + + end + end + end + + assign o_cs = cs_reg; + assign o_sclk = sclk_reg; + assign o_mosi = mosi_reg; + // User logic ends + + endmodule diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v new file mode 100755 index 0000000..9aab778 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v @@ -0,0 +1,716 @@ + +`timescale 1 ns / 1 ps + + module SPI_Con_v1_0_S00_AXI # + ( + // Users to add parameters here + + // User parameters ends + // Do not modify the parameters beyond this line + + // Width of S_AXI data bus + parameter integer C_S_AXI_DATA_WIDTH = 32, + // Width of S_AXI address bus + parameter integer C_S_AXI_ADDR_WIDTH = 7 + ) + ( + // Users to add ports here + input wire i_spi_data, + input wire i_spi_done, + output wire o_wreq, + output wire o_spi_addr, + output wire o_rreq, + // User ports ends + // Do not modify the ports beyond this line + + // Global Clock Signal + input wire S_AXI_ACLK, + // Global Reset Signal. This Signal is Active LOW + input wire S_AXI_ARESETN, + // Write address (issued by master, acceped by Slave) + input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR, + // Write channel Protection type. This signal indicates the + // privilege and security level of the transaction, and whether + // the transaction is a data access or an instruction access. + input wire [2 : 0] S_AXI_AWPROT, + // Write address valid. This signal indicates that the master signaling + // valid write address and control information. + input wire S_AXI_AWVALID, + // Write address ready. This signal indicates that the slave is ready + // to accept an address and associated control signals. + output wire S_AXI_AWREADY, + // Write data (issued by master, acceped by Slave) + input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA, + // Write strobes. This signal indicates which byte lanes hold + // valid data. There is one write strobe bit for each eight + // bits of the write data bus. + input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB, + // Write valid. This signal indicates that valid write + // data and strobes are available. + input wire S_AXI_WVALID, + // Write ready. This signal indicates that the slave + // can accept the write data. + output wire S_AXI_WREADY, + // Write response. This signal indicates the status + // of the write transaction. + output wire [1 : 0] S_AXI_BRESP, + // Write response valid. This signal indicates that the channel + // is signaling a valid write response. + output wire S_AXI_BVALID, + // Response ready. This signal indicates that the master + // can accept a write response. + input wire S_AXI_BREADY, + // Read address (issued by master, acceped by Slave) + input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR, + // Protection type. This signal indicates the privilege + // and security level of the transaction, and whether the + // transaction is a data access or an instruction access. + input wire [2 : 0] S_AXI_ARPROT, + // Read address valid. This signal indicates that the channel + // is signaling valid read address and control information. + input wire S_AXI_ARVALID, + // Read address ready. This signal indicates that the slave is + // ready to accept an address and associated control signals. + output wire S_AXI_ARREADY, + // Read data (issued by slave) + output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA, + // Read response. This signal indicates the status of the + // read transfer. + output wire [1 : 0] S_AXI_RRESP, + // Read valid. This signal indicates that the channel is + // signaling the required read data. + output wire S_AXI_RVALID, + // Read ready. This signal indicates that the master can + // accept the read data and response information. + input wire S_AXI_RREADY + ); + + // AXI4LITE signals + reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr; + reg axi_awready; + reg axi_wready; + reg [1 : 0] axi_bresp; + reg axi_bvalid; + reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr; + reg axi_arready; + reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata; + reg [1 : 0] axi_rresp; + reg axi_rvalid; + + // Example-specific design signals + // local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + // ADDR_LSB is used for addressing 32/64 bit registers/memories + // ADDR_LSB = 2 for 32 bits (n downto 2) + // ADDR_LSB = 3 for 64 bits (n downto 3) + localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1; + localparam integer OPT_MEM_ADDR_BITS = 4; + //---------------------------------------------- + //-- Signals for user logic register space example + //------------------------------------------------ + //-- Number of Slave Registers 32 + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg8; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg9; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg10; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg11; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg12; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg13; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg14; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg15; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg16; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg17; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg18; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg19; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg20; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg21; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg22; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg23; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg24; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg25; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg26; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg27; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg28; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg29; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg30; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg31; + wire slv_reg_rden; + wire slv_reg_wren; + reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out; + integer byte_index; + reg aw_en; + + // I/O Connections assignments + + assign S_AXI_AWREADY = axi_awready; + assign S_AXI_WREADY = axi_wready; + assign S_AXI_BRESP = axi_bresp; + assign S_AXI_BVALID = axi_bvalid; + assign S_AXI_ARREADY = axi_arready; + assign S_AXI_RDATA = axi_rdata; + assign S_AXI_RRESP = axi_rresp; + assign S_AXI_RVALID = axi_rvalid; + // Implement axi_awready generation + // axi_awready is asserted for one S_AXI_ACLK clock cycle when both + // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + // de-asserted when reset is low. + + always @( posedge S_AXI_ACLK ) + begin + if ( S_AXI_ARESETN == 1'b0 ) + begin + axi_awready <= 1'b0; + aw_en <= 1'b1; + end + else + begin + if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en) + begin + // slave is ready to accept write address when + // there is a valid write address and write data + // on the write address and data bus. This design + // expects no outstanding transactions. + axi_awready <= 1'b1; + aw_en <= 1'b0; + end + else if (S_AXI_BREADY && axi_bvalid) + begin + aw_en <= 1'b1; + axi_awready <= 1'b0; + end + else + begin + axi_awready <= 1'b0; + end + end + end + + // Implement axi_awaddr latching + // This process is used to latch the address when both + // S_AXI_AWVALID and S_AXI_WVALID are valid. + + always @( posedge S_AXI_ACLK ) + begin + if ( S_AXI_ARESETN == 1'b0 ) + begin + axi_awaddr <= 0; + end + else + begin + if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en) + begin + // Write Address latching + axi_awaddr <= S_AXI_AWADDR; + end + end + end + + // Implement axi_wready generation + // axi_wready is asserted for one S_AXI_ACLK clock cycle when both + // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + // de-asserted when reset is low. + + always @( posedge S_AXI_ACLK ) + begin + if ( S_AXI_ARESETN == 1'b0 ) + begin + axi_wready <= 1'b0; + end + else + begin + if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en ) + begin + // slave is ready to accept write data when + // there is a valid write address and write data + // on the write address and data bus. This design + // expects no outstanding transactions. + axi_wready <= 1'b1; + end + else + begin + axi_wready <= 1'b0; + end + end + end + + // Implement memory mapped register select and write logic generation + // The write data is accepted and written to memory mapped registers when + // axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + // select byte enables of slave registers while writing. + // These registers are cleared when reset (active low) is applied. + // Slave register write enable is asserted when valid address and data are available + // and the slave is ready to accept the write address and write data. + assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID; + + always @( posedge S_AXI_ACLK ) + begin + if ( S_AXI_ARESETN == 1'b0 ) + begin + slv_reg0 <= 0; + slv_reg1 <= 0; + slv_reg2 <= 0; + slv_reg3 <= 0; + slv_reg4 <= 0; + slv_reg5 <= 0; + slv_reg6 <= 0; + slv_reg7 <= 0; + slv_reg8 <= 0; + slv_reg9 <= 0; + slv_reg10 <= 0; + slv_reg11 <= 0; + slv_reg12 <= 0; + slv_reg13 <= 0; + slv_reg14 <= 0; + slv_reg15 <= 0; + slv_reg16 <= 0; + slv_reg17 <= 0; + slv_reg18 <= 0; + slv_reg19 <= 0; + slv_reg20 <= 0; + slv_reg21 <= 0; + slv_reg22 <= 0; + slv_reg23 <= 0; + slv_reg24 <= 0; + slv_reg25 <= 0; + slv_reg26 <= 0; + slv_reg27 <= 0; + slv_reg28 <= 0; + slv_reg29 <= 0; + slv_reg30 <= 0; + slv_reg31 <= 0; + end + else begin + if (slv_reg_wren) + begin + case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) + 5'h00: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 0 + slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h01: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 1 + slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h02: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 2 + slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h03: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 3 + slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h04: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 4 + slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h05: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 5 + slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h06: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 6 + slv_reg6[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h07: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 7 + slv_reg7[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h08: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 8 + slv_reg8[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h09: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 9 + slv_reg9[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h0A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 10 + slv_reg10[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h0B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 11 + slv_reg11[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h0C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 12 + slv_reg12[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h0D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 13 + slv_reg13[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h0E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 14 + slv_reg14[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h0F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 15 + slv_reg15[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h10: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 16 + slv_reg16[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h11: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 17 + slv_reg17[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h12: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 18 + slv_reg18[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h13: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 19 + slv_reg19[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h14: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 20 + slv_reg20[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h15: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 21 + slv_reg21[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h16: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 22 + slv_reg22[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h17: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 23 + slv_reg23[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h18: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 24 + slv_reg24[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h19: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 25 + slv_reg25[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h1A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 26 + slv_reg26[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h1B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 27 + slv_reg27[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h1C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 28 + slv_reg28[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h1D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 29 + slv_reg29[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h1E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 30 + slv_reg30[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h1F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 31 + slv_reg31[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + default : begin + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + slv_reg16 <= slv_reg16; + slv_reg17 <= slv_reg17; + slv_reg18 <= slv_reg18; + slv_reg19 <= slv_reg19; + slv_reg20 <= slv_reg20; + slv_reg21 <= slv_reg21; + slv_reg22 <= slv_reg22; + slv_reg23 <= slv_reg23; + slv_reg24 <= slv_reg24; + slv_reg25 <= slv_reg25; + slv_reg26 <= slv_reg26; + slv_reg27 <= slv_reg27; + slv_reg28 <= slv_reg28; + slv_reg29 <= slv_reg29; + slv_reg30 <= slv_reg30; + slv_reg31 <= slv_reg31; + end + endcase + end + end + end + + // Implement write response logic generation + // The write response and response valid signals are asserted by the slave + // when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + // This marks the acceptance of address and indicates the status of + // write transaction. + + always @( posedge S_AXI_ACLK ) + begin + if ( S_AXI_ARESETN == 1'b0 ) + begin + axi_bvalid <= 0; + axi_bresp <= 2'b0; + end + else + begin + if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID) + begin + // indicates a valid write response is available + axi_bvalid <= 1'b1; + axi_bresp <= 2'b0; // 'OKAY' response + end // work error responses in future + else + begin + if (S_AXI_BREADY && axi_bvalid) + //check if bready is asserted while bvalid is high) + //(there is a possibility that bready is always asserted high) + begin + axi_bvalid <= 1'b0; + end + end + end + end + + // Implement axi_arready generation + // axi_arready is asserted for one S_AXI_ACLK clock cycle when + // S_AXI_ARVALID is asserted. axi_awready is + // de-asserted when reset (active low) is asserted. + // The read address is also latched when S_AXI_ARVALID is + // asserted. axi_araddr is reset to zero on reset assertion. + + always @( posedge S_AXI_ACLK ) + begin + if ( S_AXI_ARESETN == 1'b0 ) + begin + axi_arready <= 1'b0; + axi_araddr <= 32'b0; + end + else + begin + if (~axi_arready && S_AXI_ARVALID) + begin + // indicates that the slave has acceped the valid read address + axi_arready <= 1'b1; + // Read address latching + axi_araddr <= S_AXI_ARADDR; + end + else + begin + axi_arready <= 1'b0; + end + end + end + + // Implement axi_arvalid generation + // axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + // S_AXI_ARVALID and axi_arready are asserted. The slave registers + // data are available on the axi_rdata bus at this instance. The + // assertion of axi_rvalid marks the validity of read data on the + // bus and axi_rresp indicates the status of read transaction.axi_rvalid + // is deasserted on reset (active low). axi_rresp and axi_rdata are + // cleared to zero on reset (active low). + always @( posedge S_AXI_ACLK ) + begin + if ( S_AXI_ARESETN == 1'b0 ) + begin + axi_rvalid <= 0; + axi_rresp <= 0; + end + else + begin + if (axi_arready && S_AXI_ARVALID && ~axi_rvalid) + begin + // Valid read data is available at the read data bus + axi_rvalid <= 1'b1; + axi_rresp <= 2'b0; // 'OKAY' response + end + else if (axi_rvalid && S_AXI_RREADY) + begin + // Read data is accepted by the master + axi_rvalid <= 1'b0; + end + end + end + + // Implement memory mapped register select and read logic generation + // Slave register read enable is asserted when valid address is available + // and the slave is ready to accept the read address. + assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid; + always @(*) + begin + // Address decoding for reading registers + case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) + 5'h00 : reg_data_out <= slv_reg0; + 5'h01 : reg_data_out <= slv_reg1; + 5'h02 : reg_data_out <= slv_reg2; + 5'h03 : reg_data_out <= slv_reg3; + 5'h04 : reg_data_out <= slv_reg4; + 5'h05 : reg_data_out <= slv_reg5; + 5'h06 : reg_data_out <= slv_reg6; + 5'h07 : reg_data_out <= slv_reg7; + 5'h08 : reg_data_out <= slv_reg8; + 5'h09 : reg_data_out <= slv_reg9; + 5'h0A : reg_data_out <= slv_reg10; + 5'h0B : reg_data_out <= slv_reg11; + 5'h0C : reg_data_out <= slv_reg12; + 5'h0D : reg_data_out <= slv_reg13; + 5'h0E : reg_data_out <= slv_reg14; + 5'h0F : reg_data_out <= slv_reg15; + 5'h10 : reg_data_out <= slv_reg16; + 5'h11 : reg_data_out <= slv_reg17; + 5'h12 : reg_data_out <= slv_reg18; + 5'h13 : reg_data_out <= slv_reg19; + 5'h14 : reg_data_out <= slv_reg20; + 5'h15 : reg_data_out <= slv_reg21; + 5'h16 : reg_data_out <= slv_reg22; + 5'h17 : reg_data_out <= slv_reg23; + 5'h18 : reg_data_out <= slv_reg24; + 5'h19 : reg_data_out <= slv_reg25; + 5'h1A : reg_data_out <= slv_reg26; + 5'h1B : reg_data_out <= slv_reg27; + 5'h1C : reg_data_out <= slv_reg28; + 5'h1D : reg_data_out <= slv_reg29; + 5'h1E : reg_data_out <= slv_reg30; + 5'h1F : reg_data_out <= slv_reg31; + default : reg_data_out <= 0; + endcase + end + + // Output register or memory read data + always @( posedge S_AXI_ACLK ) + begin + if ( S_AXI_ARESETN == 1'b0 ) + begin + axi_rdata <= 0; + end + else + begin + // When there is a valid read address (S_AXI_ARVALID) with + // acceptance of read address by the slave (axi_arready), + // output the read dada + if (slv_reg_rden) + begin + axi_rdata <= reg_data_out; // register read data + end + end + end + + // Add user logic here + + // User logic ends + + endmodule diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/sim/NewExtInst_TOP.protoinst b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/sim/NewExtInst_TOP.protoinst new file mode 100644 index 0000000..98e9271 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/sim/NewExtInst_TOP.protoinst @@ -0,0 +1,656 @@ +{ + "version": "1.0", + "modules": { + "NewExtInst_TOP": { + "proto_instances": { + "/SPI_Con_0/S00_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "s00_axi_aclk"}, + "ARADDR": { "actual": "s00_axi_araddr[6:0]"}, + "ARESETN": { "actual": "s00_axi_aresetn"}, + "ARPROT": { "actual": "s00_axi_arprot[2:0]"}, + "ARREADY": { "actual": "s00_axi_arready"}, + "ARVALID": { "actual": "s00_axi_arvalid"}, + "AWADDR": { "actual": "s00_axi_awaddr[6:0]"}, + "AWPROT": { "actual": "s00_axi_awprot[2:0]"}, + "AWREADY": { "actual": "s00_axi_awready"}, + "AWVALID": { "actual": "s00_axi_awvalid"}, + "BREADY": { "actual": "s00_axi_bready"}, + "BRESP": { "actual": "s00_axi_bresp[1:0]"}, + "BVALID": { "actual": "s00_axi_bvalid"}, + "RDATA": { "actual": "s00_axi_rdata[31:0]"}, + "RREADY": { "actual": "s00_axi_rready"}, + "RRESP": { "actual": "s00_axi_rresp[1:0]"}, + "RVALID": { "actual": "s00_axi_rvalid"}, + "WDATA": { "actual": "s00_axi_wdata[31:0]"}, + "WREADY": { "actual": "s00_axi_wready"}, + "WSTRB": { "actual": "s00_axi_wstrb[3:0]"}, + "WVALID": { "actual": "s00_axi_wvalid"} + } + }, + "/SPI_Con_1/S00_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "s00_axi_aclk"}, + "ARADDR": { "actual": "s00_axi_araddr[6:0]"}, + "ARESETN": { "actual": "s00_axi_aresetn"}, + "ARPROT": { "actual": "s00_axi_arprot[2:0]"}, + "ARREADY": { "actual": "s00_axi_arready"}, + "ARVALID": { "actual": "s00_axi_arvalid"}, + "AWADDR": { "actual": "s00_axi_awaddr[6:0]"}, + "AWPROT": { "actual": "s00_axi_awprot[2:0]"}, + "AWREADY": { "actual": "s00_axi_awready"}, + "AWVALID": { "actual": "s00_axi_awvalid"}, + "BREADY": { "actual": "s00_axi_bready"}, + "BRESP": { "actual": "s00_axi_bresp[1:0]"}, + "BVALID": { "actual": "s00_axi_bvalid"}, + "RDATA": { "actual": "s00_axi_rdata[31:0]"}, + "RREADY": { "actual": "s00_axi_rready"}, + "RRESP": { "actual": "s00_axi_rresp[1:0]"}, + "RVALID": { "actual": "s00_axi_rvalid"}, + "WDATA": { "actual": "s00_axi_wdata[31:0]"}, + "WREADY": { "actual": "s00_axi_wready"}, + "WSTRB": { "actual": "s00_axi_wstrb[3:0]"}, + "WVALID": { "actual": "s00_axi_wvalid"} + } + }, + "/SPI_Con_2/S00_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "s00_axi_aclk"}, + "ARADDR": { "actual": "s00_axi_araddr[6:0]"}, + "ARESETN": { "actual": "s00_axi_aresetn"}, + "ARPROT": { "actual": "s00_axi_arprot[2:0]"}, + "ARREADY": { "actual": "s00_axi_arready"}, + "ARVALID": { "actual": "s00_axi_arvalid"}, + "AWADDR": { "actual": "s00_axi_awaddr[6:0]"}, + "AWPROT": { "actual": "s00_axi_awprot[2:0]"}, + "AWREADY": { "actual": "s00_axi_awready"}, + "AWVALID": { "actual": "s00_axi_awvalid"}, + "BREADY": { "actual": "s00_axi_bready"}, + "BRESP": { "actual": "s00_axi_bresp[1:0]"}, + "BVALID": { "actual": "s00_axi_bvalid"}, + "RDATA": { "actual": "s00_axi_rdata[31:0]"}, + "RREADY": { "actual": "s00_axi_rready"}, + "RRESP": { "actual": "s00_axi_rresp[1:0]"}, + "RVALID": { "actual": "s00_axi_rvalid"}, + "WDATA": { "actual": "s00_axi_wdata[31:0]"}, + "WREADY": { "actual": "s00_axi_wready"}, + "WSTRB": { "actual": "s00_axi_wstrb[3:0]"}, + "WVALID": { "actual": "s00_axi_wvalid"} + } + }, + "/processing_system7_0/M_AXI_GP0": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "M_AXI_GP0_ACLK"}, + "ARADDR": { "actual": "M_AXI_GP0_ARADDR[31:0]"}, + "ARBURST": { "actual": "M_AXI_GP0_ARBURST[1:0]"}, + "ARCACHE": { "actual": "M_AXI_GP0_ARCACHE[3:0]"}, + "ARID": { "actual": "M_AXI_GP0_ARID[11:0]"}, + "ARLEN": { "actual": "M_AXI_GP0_ARLEN[3:0]"}, + "ARLOCK": { "actual": "M_AXI_GP0_ARLOCK[1:0]"}, + "ARPROT": { "actual": "M_AXI_GP0_ARPROT[2:0]"}, + "ARQOS": { "actual": "M_AXI_GP0_ARQOS[3:0]"}, + "ARREADY": { "actual": "M_AXI_GP0_ARREADY"}, + "ARSIZE": { "actual": "M_AXI_GP0_ARSIZE[2:0]"}, + "ARVALID": { "actual": "M_AXI_GP0_ARVALID"}, + "AWADDR": { "actual": "M_AXI_GP0_AWADDR[31:0]"}, + "AWBURST": { "actual": "M_AXI_GP0_AWBURST[1:0]"}, + "AWCACHE": { "actual": "M_AXI_GP0_AWCACHE[3:0]"}, + "AWID": { "actual": "M_AXI_GP0_AWID[11:0]"}, + "AWLEN": { "actual": "M_AXI_GP0_AWLEN[3:0]"}, + "AWLOCK": { "actual": "M_AXI_GP0_AWLOCK[1:0]"}, + "AWPROT": { "actual": "M_AXI_GP0_AWPROT[2:0]"}, + "AWQOS": { "actual": "M_AXI_GP0_AWQOS[3:0]"}, + "AWREADY": { "actual": "M_AXI_GP0_AWREADY"}, + "AWSIZE": { "actual": "M_AXI_GP0_AWSIZE[2:0]"}, + "AWVALID": { "actual": "M_AXI_GP0_AWVALID"}, + "BID": { "actual": "M_AXI_GP0_BID[11:0]"}, + "BREADY": { "actual": "M_AXI_GP0_BREADY"}, + "BRESP": { "actual": "M_AXI_GP0_BRESP[1:0]"}, + "BVALID": { "actual": "M_AXI_GP0_BVALID"}, + "RDATA": { "actual": "M_AXI_GP0_RDATA[31:0]"}, + "RID": { "actual": "M_AXI_GP0_RID[11:0]"}, + "RLAST": { "actual": "M_AXI_GP0_RLAST"}, + "RREADY": { "actual": "M_AXI_GP0_RREADY"}, + "RRESP": { "actual": "M_AXI_GP0_RRESP[1:0]"}, + "RVALID": { "actual": "M_AXI_GP0_RVALID"}, + "WDATA": { "actual": "M_AXI_GP0_WDATA[31:0]"}, + "WID": { "actual": "M_AXI_GP0_WID[11:0]"}, + "WLAST": { "actual": "M_AXI_GP0_WLAST"}, + "WREADY": { "actual": "M_AXI_GP0_WREADY"}, + "WSTRB": { "actual": "M_AXI_GP0_WSTRB[3:0]"}, + "WVALID": { "actual": "M_AXI_GP0_WVALID"} + } + }, + "/ps7_0_axi_periph/M00_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "M00_ACLK"}, + "ARADDR": { "actual": "M00_AXI_araddr[31:0]"}, + "ARESETN": { "actual": "ARESETN"}, + "ARPROT": { "actual": "M00_AXI_arprot[2:0]"}, + "ARREADY": { "actual": "M00_AXI_arready[0:0]"}, + "ARVALID": { "actual": "M00_AXI_arvalid[0:0]"}, + "AWADDR": { "actual": "M00_AXI_awaddr[31:0]"}, + "AWPROT": { "actual": "M00_AXI_awprot[2:0]"}, + "AWREADY": { "actual": "M00_AXI_awready[0:0]"}, + "AWVALID": { "actual": "M00_AXI_awvalid[0:0]"}, + "BREADY": { "actual": "M00_AXI_bready[0:0]"}, + "BRESP": { "actual": "M00_AXI_bresp[1:0]"}, + "BVALID": { "actual": "M00_AXI_bvalid[0:0]"}, + "RDATA": { "actual": "M00_AXI_rdata[31:0]"}, + "RREADY": { "actual": "M00_AXI_rready[0:0]"}, + "RRESP": { "actual": "M00_AXI_rresp[1:0]"}, + "RVALID": { "actual": "M00_AXI_rvalid[0:0]"}, + "WDATA": { "actual": "M00_AXI_wdata[31:0]"}, + "WREADY": { "actual": "M00_AXI_wready[0:0]"}, + "WSTRB": { "actual": "M00_AXI_wstrb[3:0]"}, + "WVALID": { "actual": "M00_AXI_wvalid[0:0]"} + } + }, + "/ps7_0_axi_periph/M01_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "M01_ACLK"}, + "ARADDR": { "actual": "M01_AXI_araddr[63:32]"}, + "ARESETN": { "actual": "ARESETN"}, + "ARPROT": { "actual": "M01_AXI_arprot[5:3]"}, + "ARREADY": { "actual": "M01_AXI_arready[1:1]"}, + "ARVALID": { "actual": "M01_AXI_arvalid[1:1]"}, + "AWADDR": { "actual": "M01_AXI_awaddr[63:32]"}, + "AWPROT": { "actual": "M01_AXI_awprot[5:3]"}, + "AWREADY": { "actual": "M01_AXI_awready[1:1]"}, + "AWVALID": { "actual": "M01_AXI_awvalid[1:1]"}, + "BREADY": { "actual": "M01_AXI_bready[1:1]"}, + "BRESP": { "actual": "M01_AXI_bresp[3:2]"}, + "BVALID": { "actual": "M01_AXI_bvalid[1:1]"}, + "RDATA": { "actual": "M01_AXI_rdata[63:32]"}, + "RREADY": { "actual": "M01_AXI_rready[1:1]"}, + "RRESP": { "actual": "M01_AXI_rresp[3:2]"}, + "RVALID": { "actual": "M01_AXI_rvalid[1:1]"}, + "WDATA": { "actual": "M01_AXI_wdata[63:32]"}, + "WREADY": { "actual": "M01_AXI_wready[1:1]"}, + "WSTRB": { "actual": "M01_AXI_wstrb[7:4]"}, + "WVALID": { "actual": "M01_AXI_wvalid[1:1]"} + } + }, + "/ps7_0_axi_periph/M02_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "M02_ACLK"}, + "ARADDR": { "actual": "M02_AXI_araddr[95:64]"}, + "ARESETN": { "actual": "ARESETN"}, + "ARPROT": { "actual": "M02_AXI_arprot[8:6]"}, + "ARREADY": { "actual": "M02_AXI_arready[2:2]"}, + "ARVALID": { "actual": "M02_AXI_arvalid[2:2]"}, + "AWADDR": { "actual": "M02_AXI_awaddr[95:64]"}, + "AWPROT": { "actual": "M02_AXI_awprot[8:6]"}, + "AWREADY": { "actual": "M02_AXI_awready[2:2]"}, + "AWVALID": { "actual": "M02_AXI_awvalid[2:2]"}, + "BREADY": { "actual": "M02_AXI_bready[2:2]"}, + "BRESP": { "actual": "M02_AXI_bresp[5:4]"}, + "BVALID": { "actual": "M02_AXI_bvalid[2:2]"}, + "RDATA": { "actual": "M02_AXI_rdata[95:64]"}, + "RREADY": { "actual": "M02_AXI_rready[2:2]"}, + "RRESP": { "actual": "M02_AXI_rresp[5:4]"}, + "RVALID": { "actual": "M02_AXI_rvalid[2:2]"}, + "WDATA": { "actual": "M02_AXI_wdata[95:64]"}, + "WREADY": { "actual": "M02_AXI_wready[2:2]"}, + "WSTRB": { "actual": "M02_AXI_wstrb[11:8]"}, + "WVALID": { "actual": "M02_AXI_wvalid[2:2]"} + } + }, + "/ps7_0_axi_periph/S00_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "S00_ACLK"}, + "ARADDR": { "actual": "S00_AXI_araddr[31:0]"}, + "ARBURST": { "actual": "S00_AXI_arburst[1:0]"}, + "ARCACHE": { "actual": "S00_AXI_arcache[3:0]"}, + "ARESETN": { "actual": "ARESETN"}, + "ARID": { "actual": "S00_AXI_arid[11:0]"}, + "ARLEN": { "actual": "S00_AXI_arlen[7:0]"}, + "ARLOCK": { "actual": "S00_AXI_arlock[0:0]"}, + "ARPROT": { "actual": "S00_AXI_arprot[2:0]"}, + "ARQOS": { "actual": "S00_AXI_arqos[3:0]"}, + "ARREADY": { "actual": "S00_AXI_arready"}, + "ARSIZE": { "actual": "S00_AXI_arsize[2:0]"}, + "ARVALID": { "actual": "S00_AXI_arvalid"}, + "AWADDR": { "actual": "S00_AXI_awaddr[31:0]"}, + "AWBURST": { "actual": "S00_AXI_awburst[1:0]"}, + "AWCACHE": { "actual": "S00_AXI_awcache[3:0]"}, + "AWID": { "actual": "S00_AXI_awid[11:0]"}, + "AWLEN": { "actual": "S00_AXI_awlen[7:0]"}, + "AWLOCK": { "actual": "S00_AXI_awlock[0:0]"}, + "AWPROT": { "actual": "S00_AXI_awprot[2:0]"}, + "AWQOS": { "actual": "S00_AXI_awqos[3:0]"}, + "AWREADY": { "actual": "S00_AXI_awready"}, + "AWSIZE": { "actual": "S00_AXI_awsize[2:0]"}, + "AWVALID": { "actual": "S00_AXI_awvalid"}, + "BID": { "actual": "S00_AXI_bid[11:0]"}, + "BREADY": { "actual": "S00_AXI_bready"}, + "BRESP": { "actual": "S00_AXI_bresp[1:0]"}, + "BVALID": { "actual": "S00_AXI_bvalid"}, + "RDATA": { "actual": "S00_AXI_rdata[31:0]"}, + "RID": { "actual": "S00_AXI_rid[11:0]"}, + "RLAST": { "actual": "S00_AXI_rlast"}, + "RREADY": { "actual": "S00_AXI_rready"}, + "RRESP": { "actual": "S00_AXI_rresp[1:0]"}, + "RVALID": { "actual": "S00_AXI_rvalid"}, + "WDATA": { "actual": "S00_AXI_wdata[31:0]"}, + "WID": { "actual": "S00_AXI_wid[11:0]"}, + "WLAST": { "actual": "S00_AXI_wlast"}, + "WREADY": { "actual": "S00_AXI_wready"}, + "WSTRB": { "actual": "S00_AXI_wstrb[3:0]"}, + "WVALID": { "actual": "S00_AXI_wvalid"} + } + }, + "/ps7_0_axi_periph/m00_couplers/M_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "M_ACLK"}, + "ARADDR": { "actual": "M_AXI_araddr[31:0]"}, + "ARESETN": { "actual": "M_ARESETN"}, + "ARPROT": { "actual": "M_AXI_arprot[2:0]"}, + "ARREADY": { "actual": "M_AXI_arready[0:0]"}, + "ARVALID": { "actual": "M_AXI_arvalid[0:0]"}, + "AWADDR": { "actual": "M_AXI_awaddr[31:0]"}, + "AWPROT": { "actual": "M_AXI_awprot[2:0]"}, + "AWREADY": { "actual": "M_AXI_awready[0:0]"}, + "AWVALID": { "actual": "M_AXI_awvalid[0:0]"}, + "BREADY": { "actual": "M_AXI_bready[0:0]"}, + "BRESP": { "actual": "M_AXI_bresp[1:0]"}, + "BVALID": { "actual": "M_AXI_bvalid[0:0]"}, + "RDATA": { "actual": "M_AXI_rdata[31:0]"}, + "RREADY": { "actual": "M_AXI_rready[0:0]"}, + "RRESP": { "actual": "M_AXI_rresp[1:0]"}, + "RVALID": { "actual": "M_AXI_rvalid[0:0]"}, + "WDATA": { "actual": "M_AXI_wdata[31:0]"}, + "WREADY": { "actual": "M_AXI_wready[0:0]"}, + "WSTRB": { "actual": "M_AXI_wstrb[3:0]"}, + "WVALID": { "actual": "M_AXI_wvalid[0:0]"} + } + }, + "/ps7_0_axi_periph/m00_couplers/S_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "S_ACLK"}, + "ARADDR": { "actual": "S_AXI_araddr[31:0]"}, + "ARESETN": { "actual": "S_ARESETN"}, + "ARPROT": { "actual": "S_AXI_arprot[2:0]"}, + "ARREADY": { "actual": "S_AXI_arready[0:0]"}, + "ARVALID": { "actual": "S_AXI_arvalid[0:0]"}, + "AWADDR": { "actual": "S_AXI_awaddr[31:0]"}, + "AWPROT": { "actual": "S_AXI_awprot[2:0]"}, + "AWREADY": { "actual": "S_AXI_awready[0:0]"}, + "AWVALID": { "actual": "S_AXI_awvalid[0:0]"}, + "BREADY": { "actual": "S_AXI_bready[0:0]"}, + "BRESP": { "actual": "S_AXI_bresp[1:0]"}, + "BVALID": { "actual": "S_AXI_bvalid[0:0]"}, + "RDATA": { "actual": "S_AXI_rdata[31:0]"}, + "RREADY": { "actual": "S_AXI_rready[0:0]"}, + "RRESP": { "actual": "S_AXI_rresp[1:0]"}, + "RVALID": { "actual": "S_AXI_rvalid[0:0]"}, + "WDATA": { "actual": "S_AXI_wdata[31:0]"}, + "WREADY": { "actual": "S_AXI_wready[0:0]"}, + "WSTRB": { "actual": "S_AXI_wstrb[3:0]"}, + "WVALID": { "actual": "S_AXI_wvalid[0:0]"} + } + }, + "/ps7_0_axi_periph/m01_couplers/M_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "M_ACLK"}, + "ARADDR": { "actual": "M_AXI_araddr[63:32]"}, + "ARESETN": { "actual": "M_ARESETN"}, + "ARPROT": { "actual": "M_AXI_arprot[5:3]"}, + "ARREADY": { "actual": "M_AXI_arready[1:1]"}, + "ARVALID": { "actual": "M_AXI_arvalid[1:1]"}, + "AWADDR": { "actual": "M_AXI_awaddr[63:32]"}, + "AWPROT": { "actual": "M_AXI_awprot[5:3]"}, + "AWREADY": { "actual": "M_AXI_awready[1:1]"}, + "AWVALID": { "actual": "M_AXI_awvalid[1:1]"}, + "BREADY": { "actual": "M_AXI_bready[1:1]"}, + "BRESP": { "actual": "M_AXI_bresp[3:2]"}, + "BVALID": { "actual": "M_AXI_bvalid[1:1]"}, + "RDATA": { "actual": "M_AXI_rdata[63:32]"}, + "RREADY": { "actual": "M_AXI_rready[1:1]"}, + "RRESP": { "actual": "M_AXI_rresp[3:2]"}, + "RVALID": { "actual": "M_AXI_rvalid[1:1]"}, + "WDATA": { "actual": "M_AXI_wdata[63:32]"}, + "WREADY": { "actual": "M_AXI_wready[1:1]"}, + "WSTRB": { "actual": "M_AXI_wstrb[7:4]"}, + "WVALID": { "actual": "M_AXI_wvalid[1:1]"} + } + }, + "/ps7_0_axi_periph/m01_couplers/S_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "S_ACLK"}, + "ARADDR": { "actual": "S_AXI_araddr[63:32]"}, + "ARESETN": { "actual": "S_ARESETN"}, + "ARPROT": { "actual": "S_AXI_arprot[5:3]"}, + "ARREADY": { "actual": "S_AXI_arready[1:1]"}, + "ARVALID": { "actual": "S_AXI_arvalid[1:1]"}, + "AWADDR": { "actual": "S_AXI_awaddr[63:32]"}, + "AWPROT": { "actual": "S_AXI_awprot[5:3]"}, + "AWREADY": { "actual": "S_AXI_awready[1:1]"}, + "AWVALID": { "actual": "S_AXI_awvalid[1:1]"}, + "BREADY": { "actual": "S_AXI_bready[1:1]"}, + "BRESP": { "actual": "S_AXI_bresp[3:2]"}, + "BVALID": { "actual": "S_AXI_bvalid[1:1]"}, + "RDATA": { "actual": "S_AXI_rdata[63:32]"}, + "RREADY": { "actual": "S_AXI_rready[1:1]"}, + "RRESP": { "actual": "S_AXI_rresp[3:2]"}, + "RVALID": { "actual": "S_AXI_rvalid[1:1]"}, + "WDATA": { "actual": "S_AXI_wdata[63:32]"}, + "WREADY": { "actual": "S_AXI_wready[1:1]"}, + "WSTRB": { "actual": "S_AXI_wstrb[7:4]"}, + "WVALID": { "actual": "S_AXI_wvalid[1:1]"} + } + }, + "/ps7_0_axi_periph/m02_couplers/M_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "M_ACLK"}, + "ARADDR": { "actual": "M_AXI_araddr[95:64]"}, + "ARESETN": { "actual": "M_ARESETN"}, + "ARPROT": { "actual": "M_AXI_arprot[8:6]"}, + "ARREADY": { "actual": "M_AXI_arready[2:2]"}, + "ARVALID": { "actual": "M_AXI_arvalid[2:2]"}, + "AWADDR": { "actual": "M_AXI_awaddr[95:64]"}, + "AWPROT": { "actual": "M_AXI_awprot[8:6]"}, + "AWREADY": { "actual": "M_AXI_awready[2:2]"}, + "AWVALID": { "actual": "M_AXI_awvalid[2:2]"}, + "BREADY": { "actual": "M_AXI_bready[2:2]"}, + "BRESP": { "actual": "M_AXI_bresp[5:4]"}, + "BVALID": { "actual": "M_AXI_bvalid[2:2]"}, + "RDATA": { "actual": "M_AXI_rdata[95:64]"}, + "RREADY": { "actual": "M_AXI_rready[2:2]"}, + "RRESP": { "actual": "M_AXI_rresp[5:4]"}, + "RVALID": { "actual": "M_AXI_rvalid[2:2]"}, + "WDATA": { "actual": "M_AXI_wdata[95:64]"}, + "WREADY": { "actual": "M_AXI_wready[2:2]"}, + "WSTRB": { "actual": "M_AXI_wstrb[11:8]"}, + "WVALID": { "actual": "M_AXI_wvalid[2:2]"} + } + }, + "/ps7_0_axi_periph/m02_couplers/S_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "S_ACLK"}, + "ARADDR": { "actual": "S_AXI_araddr[95:64]"}, + "ARESETN": { "actual": "S_ARESETN"}, + "ARPROT": { "actual": "S_AXI_arprot[8:6]"}, + "ARREADY": { "actual": "S_AXI_arready[2:2]"}, + "ARVALID": { "actual": "S_AXI_arvalid[2:2]"}, + "AWADDR": { "actual": "S_AXI_awaddr[95:64]"}, + "AWPROT": { "actual": "S_AXI_awprot[8:6]"}, + "AWREADY": { "actual": "S_AXI_awready[2:2]"}, + "AWVALID": { "actual": "S_AXI_awvalid[2:2]"}, + "BREADY": { "actual": "S_AXI_bready[2:2]"}, + "BRESP": { "actual": "S_AXI_bresp[5:4]"}, + "BVALID": { "actual": "S_AXI_bvalid[2:2]"}, + "RDATA": { "actual": "S_AXI_rdata[95:64]"}, + "RREADY": { "actual": "S_AXI_rready[2:2]"}, + "RRESP": { "actual": "S_AXI_rresp[5:4]"}, + "RVALID": { "actual": "S_AXI_rvalid[2:2]"}, + "WDATA": { "actual": "S_AXI_wdata[95:64]"}, + "WREADY": { "actual": "S_AXI_wready[2:2]"}, + "WSTRB": { "actual": "S_AXI_wstrb[11:8]"}, + "WVALID": { "actual": "S_AXI_wvalid[2:2]"} + } + }, + "/ps7_0_axi_periph/s00_couplers/M_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "M_ACLK"}, + "ARADDR": { "actual": "M_AXI_araddr[31:0]"}, + "ARESETN": { "actual": "M_ARESETN"}, + "ARPROT": { "actual": "M_AXI_arprot[2:0]"}, + "ARREADY": { "actual": "M_AXI_arready"}, + "ARVALID": { "actual": "M_AXI_arvalid"}, + "AWADDR": { "actual": "M_AXI_awaddr[31:0]"}, + "AWPROT": { "actual": "M_AXI_awprot[2:0]"}, + "AWREADY": { "actual": "M_AXI_awready"}, + "AWVALID": { "actual": "M_AXI_awvalid"}, + "BREADY": { "actual": "M_AXI_bready"}, + "BRESP": { "actual": "M_AXI_bresp[1:0]"}, + "BVALID": { "actual": "M_AXI_bvalid"}, + "RDATA": { "actual": "M_AXI_rdata[31:0]"}, + "RREADY": { "actual": "M_AXI_rready"}, + "RRESP": { "actual": "M_AXI_rresp[1:0]"}, + "RVALID": { "actual": "M_AXI_rvalid"}, + "WDATA": { "actual": "M_AXI_wdata[31:0]"}, + "WREADY": { "actual": "M_AXI_wready"}, + "WSTRB": { "actual": "M_AXI_wstrb[3:0]"}, + "WVALID": { "actual": "M_AXI_wvalid"} + } + }, + "/ps7_0_axi_periph/s00_couplers/S_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "S_ACLK"}, + "ARADDR": { "actual": "S_AXI_araddr[31:0]"}, + "ARBURST": { "actual": "S_AXI_arburst[1:0]"}, + "ARCACHE": { "actual": "S_AXI_arcache[3:0]"}, + "ARESETN": { "actual": "S_ARESETN"}, + "ARID": { "actual": "S_AXI_arid[11:0]"}, + "ARLEN": { "actual": "S_AXI_arlen[7:0]"}, + "ARLOCK": { "actual": "S_AXI_arlock[0:0]"}, + "ARPROT": { "actual": "S_AXI_arprot[2:0]"}, + "ARQOS": { "actual": "S_AXI_arqos[3:0]"}, + "ARREADY": { "actual": "S_AXI_arready"}, + "ARSIZE": { "actual": "S_AXI_arsize[2:0]"}, + "ARVALID": { "actual": "S_AXI_arvalid"}, + "AWADDR": { "actual": "S_AXI_awaddr[31:0]"}, + "AWBURST": { "actual": "S_AXI_awburst[1:0]"}, + "AWCACHE": { "actual": "S_AXI_awcache[3:0]"}, + "AWID": { "actual": "S_AXI_awid[11:0]"}, + "AWLEN": { "actual": "S_AXI_awlen[7:0]"}, + "AWLOCK": { "actual": "S_AXI_awlock[0:0]"}, + "AWPROT": { "actual": "S_AXI_awprot[2:0]"}, + "AWQOS": { "actual": "S_AXI_awqos[3:0]"}, + "AWREADY": { "actual": "S_AXI_awready"}, + "AWSIZE": { "actual": "S_AXI_awsize[2:0]"}, + "AWVALID": { "actual": "S_AXI_awvalid"}, + "BID": { "actual": "S_AXI_bid[11:0]"}, + "BREADY": { "actual": "S_AXI_bready"}, + "BRESP": { "actual": "S_AXI_bresp[1:0]"}, + "BVALID": { "actual": "S_AXI_bvalid"}, + "RDATA": { "actual": "S_AXI_rdata[31:0]"}, + "RID": { "actual": "S_AXI_rid[11:0]"}, + "RLAST": { "actual": "S_AXI_rlast"}, + "RREADY": { "actual": "S_AXI_rready"}, + "RRESP": { "actual": "S_AXI_rresp[1:0]"}, + "RVALID": { "actual": "S_AXI_rvalid"}, + "WDATA": { "actual": "S_AXI_wdata[31:0]"}, + "WID": { "actual": "S_AXI_wid[11:0]"}, + "WLAST": { "actual": "S_AXI_wlast"}, + "WREADY": { "actual": "S_AXI_wready"}, + "WSTRB": { "actual": "S_AXI_wstrb[3:0]"}, + "WVALID": { "actual": "S_AXI_wvalid"} + } + }, + "/ps7_0_axi_periph/s00_couplers/auto_pc/M_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "aclk"}, + "ARADDR": { "actual": "m_axi_araddr[31:0]"}, + "ARESETN": { "actual": "aresetn"}, + "ARPROT": { "actual": "m_axi_arprot[2:0]"}, + "ARREADY": { "actual": "m_axi_arready"}, + "ARVALID": { "actual": "m_axi_arvalid"}, + "AWADDR": { "actual": "m_axi_awaddr[31:0]"}, + "AWPROT": { "actual": "m_axi_awprot[2:0]"}, + "AWREADY": { "actual": "m_axi_awready"}, + "AWVALID": { "actual": "m_axi_awvalid"}, + "BREADY": { "actual": "m_axi_bready"}, + "BRESP": { "actual": "m_axi_bresp[1:0]"}, + "BVALID": { "actual": "m_axi_bvalid"}, + "RDATA": { "actual": "m_axi_rdata[31:0]"}, + "RREADY": { "actual": "m_axi_rready"}, + "RRESP": { "actual": "m_axi_rresp[1:0]"}, + "RVALID": { "actual": "m_axi_rvalid"}, + "WDATA": { "actual": "m_axi_wdata[31:0]"}, + "WREADY": { "actual": "m_axi_wready"}, + "WSTRB": { "actual": "m_axi_wstrb[3:0]"}, + "WVALID": { "actual": "m_axi_wvalid"} + } + }, + "/ps7_0_axi_periph/s00_couplers/auto_pc/S_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "aclk"}, + "ARADDR": { "actual": "s_axi_araddr[31:0]"}, + "ARBURST": { "actual": "s_axi_arburst[1:0]"}, + "ARCACHE": { "actual": "s_axi_arcache[3:0]"}, + "ARESETN": { "actual": "aresetn"}, + "ARID": { "actual": "s_axi_arid[11:0]"}, + "ARLEN": { "actual": "s_axi_arlen[3:0]"}, + "ARLOCK": { "actual": "s_axi_arlock[1:0]"}, + "ARPROT": { "actual": "s_axi_arprot[2:0]"}, + "ARQOS": { "actual": "s_axi_arqos[3:0]"}, + "ARREADY": { "actual": "s_axi_arready"}, + "ARSIZE": { "actual": "s_axi_arsize[2:0]"}, + "ARVALID": { "actual": "s_axi_arvalid"}, + "AWADDR": { "actual": "s_axi_awaddr[31:0]"}, + "AWBURST": { "actual": "s_axi_awburst[1:0]"}, + "AWCACHE": { "actual": "s_axi_awcache[3:0]"}, + "AWID": { "actual": "s_axi_awid[11:0]"}, + "AWLEN": { "actual": "s_axi_awlen[3:0]"}, + "AWLOCK": { "actual": "s_axi_awlock[1:0]"}, + "AWPROT": { "actual": "s_axi_awprot[2:0]"}, + "AWQOS": { "actual": "s_axi_awqos[3:0]"}, + "AWREADY": { "actual": "s_axi_awready"}, + "AWSIZE": { "actual": "s_axi_awsize[2:0]"}, + "AWVALID": { "actual": "s_axi_awvalid"}, + "BID": { "actual": "s_axi_bid[11:0]"}, + "BREADY": { "actual": "s_axi_bready"}, + "BRESP": { "actual": "s_axi_bresp[1:0]"}, + "BVALID": { "actual": "s_axi_bvalid"}, + "RDATA": { "actual": "s_axi_rdata[31:0]"}, + "RID": { "actual": "s_axi_rid[11:0]"}, + "RLAST": { "actual": "s_axi_rlast"}, + "RREADY": { "actual": "s_axi_rready"}, + "RRESP": { "actual": "s_axi_rresp[1:0]"}, + "RVALID": { "actual": "s_axi_rvalid"}, + "WDATA": { "actual": "s_axi_wdata[31:0]"}, + "WID": { "actual": "s_axi_wid[11:0]"}, + "WLAST": { "actual": "s_axi_wlast"}, + "WREADY": { "actual": "s_axi_wready"}, + "WSTRB": { "actual": "s_axi_wstrb[3:0]"}, + "WVALID": { "actual": "s_axi_wvalid"} + } + }, + "/ps7_0_axi_periph/xbar/M00_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "aclk"}, + "ARADDR": { "actual": "m_axi_araddr[31:0]"}, + "ARESETN": { "actual": "aresetn"}, + "ARPROT": { "actual": "m_axi_arprot[2:0]"}, + "ARREADY": { "actual": "m_axi_arready[0:0]"}, + "ARVALID": { "actual": "m_axi_arvalid[0:0]"}, + "AWADDR": { "actual": "m_axi_awaddr[31:0]"}, + "AWPROT": { "actual": "m_axi_awprot[2:0]"}, + "AWREADY": { "actual": "m_axi_awready[0:0]"}, + "AWVALID": { "actual": "m_axi_awvalid[0:0]"}, + "BREADY": { "actual": "m_axi_bready[0:0]"}, + "BRESP": { "actual": "m_axi_bresp[1:0]"}, + "BVALID": { "actual": "m_axi_bvalid[0:0]"}, + "RDATA": { "actual": "m_axi_rdata[31:0]"}, + "RREADY": { "actual": "m_axi_rready[0:0]"}, + "RRESP": { "actual": "m_axi_rresp[1:0]"}, + "RVALID": { "actual": "m_axi_rvalid[0:0]"}, + "WDATA": { "actual": "m_axi_wdata[31:0]"}, + "WREADY": { "actual": "m_axi_wready[0:0]"}, + "WSTRB": { "actual": "m_axi_wstrb[3:0]"}, + "WVALID": { "actual": "m_axi_wvalid[0:0]"} + } + }, + "/ps7_0_axi_periph/xbar/M01_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "aclk"}, + "ARADDR": { "actual": "m_axi_araddr[63:32]"}, + "ARESETN": { "actual": "aresetn"}, + "ARPROT": { "actual": "m_axi_arprot[5:3]"}, + "ARREADY": { "actual": "m_axi_arready[1:1]"}, + "ARVALID": { "actual": "m_axi_arvalid[1:1]"}, + "AWADDR": { "actual": "m_axi_awaddr[63:32]"}, + "AWPROT": { "actual": "m_axi_awprot[5:3]"}, + "AWREADY": { "actual": "m_axi_awready[1:1]"}, + "AWVALID": { "actual": "m_axi_awvalid[1:1]"}, + "BREADY": { "actual": "m_axi_bready[1:1]"}, + "BRESP": { "actual": "m_axi_bresp[3:2]"}, + "BVALID": { "actual": "m_axi_bvalid[1:1]"}, + "RDATA": { "actual": "m_axi_rdata[63:32]"}, + "RREADY": { "actual": "m_axi_rready[1:1]"}, + "RRESP": { "actual": "m_axi_rresp[3:2]"}, + "RVALID": { "actual": "m_axi_rvalid[1:1]"}, + "WDATA": { "actual": "m_axi_wdata[63:32]"}, + "WREADY": { "actual": "m_axi_wready[1:1]"}, + "WSTRB": { "actual": "m_axi_wstrb[7:4]"}, + "WVALID": { "actual": "m_axi_wvalid[1:1]"} + } + }, + "/ps7_0_axi_periph/xbar/M02_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "aclk"}, + "ARADDR": { "actual": "m_axi_araddr[95:64]"}, + "ARESETN": { "actual": "aresetn"}, + "ARPROT": { "actual": "m_axi_arprot[8:6]"}, + "ARREADY": { "actual": "m_axi_arready[2:2]"}, + "ARVALID": { "actual": "m_axi_arvalid[2:2]"}, + "AWADDR": { "actual": "m_axi_awaddr[95:64]"}, + "AWPROT": { "actual": "m_axi_awprot[8:6]"}, + "AWREADY": { "actual": "m_axi_awready[2:2]"}, + "AWVALID": { "actual": "m_axi_awvalid[2:2]"}, + "BREADY": { "actual": "m_axi_bready[2:2]"}, + "BRESP": { "actual": "m_axi_bresp[5:4]"}, + "BVALID": { "actual": "m_axi_bvalid[2:2]"}, + "RDATA": { "actual": "m_axi_rdata[95:64]"}, + "RREADY": { "actual": "m_axi_rready[2:2]"}, + "RRESP": { "actual": "m_axi_rresp[5:4]"}, + "RVALID": { "actual": "m_axi_rvalid[2:2]"}, + "WDATA": { "actual": "m_axi_wdata[95:64]"}, + "WREADY": { "actual": "m_axi_wready[2:2]"}, + "WSTRB": { "actual": "m_axi_wstrb[11:8]"}, + "WVALID": { "actual": "m_axi_wvalid[2:2]"} + } + }, + "/ps7_0_axi_periph/xbar/S00_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "aclk"}, + "ARADDR": { "actual": "s_axi_araddr[31:0]"}, + "ARESETN": { "actual": "aresetn"}, + "ARPROT": { "actual": "s_axi_arprot[2:0]"}, + "ARREADY": { "actual": "s_axi_arready[0:0]"}, + "ARVALID": { "actual": "s_axi_arvalid[0:0]"}, + "AWADDR": { "actual": "s_axi_awaddr[31:0]"}, + "AWPROT": { "actual": "s_axi_awprot[2:0]"}, + "AWREADY": { "actual": "s_axi_awready[0:0]"}, + "AWVALID": { "actual": "s_axi_awvalid[0:0]"}, + "BREADY": { "actual": "s_axi_bready[0:0]"}, + "BRESP": { "actual": "s_axi_bresp[1:0]"}, + "BVALID": { "actual": "s_axi_bvalid[0:0]"}, + "RDATA": { "actual": "s_axi_rdata[31:0]"}, + "RREADY": { "actual": "s_axi_rready[0:0]"}, + "RRESP": { "actual": "s_axi_rresp[1:0]"}, + "RVALID": { "actual": "s_axi_rvalid[0:0]"}, + "WDATA": { "actual": "s_axi_wdata[31:0]"}, + "WREADY": { "actual": "s_axi_wready[0:0]"}, + "WSTRB": { "actual": "s_axi_wstrb[3:0]"}, + "WVALID": { "actual": "s_axi_wvalid[0:0]"} + } + } + } + } + } +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/sim/NewExtInst_TOP.v b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/sim/NewExtInst_TOP.v new file mode 100644 index 0000000..e10a484 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/bd/NewExtInst_TOP/sim/NewExtInst_TOP.v @@ -0,0 +1,1955 @@ +//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +//Date : Fri May 15 15:32:21 2026 +//Host : mkb running 64-bit unknown +//Command : generate_target NewExtInst_TOP.bd +//Design : NewExtInst_TOP +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CORE_GENERATION_INFO = "NewExtInst_TOP,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=NewExtInst_TOP,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=14,numReposBlks=9,numNonXlnxBlks=0,numHierBlks=5,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=3,da_board_cnt=2,da_clkrst_cnt=1,da_ps7_cnt=1,synth_mode=Hierarchical}" *) (* HW_HANDOFF = "NewExtInst_TOP.hwdef" *) +module NewExtInst_TOP + (DDR_addr, + DDR_ba, + DDR_cas_n, + DDR_ck_n, + DDR_ck_p, + DDR_cke, + DDR_cs_n, + DDR_dm, + DDR_dq, + DDR_dqs_n, + DDR_dqs_p, + DDR_odt, + DDR_ras_n, + DDR_reset_n, + DDR_we_n, + FIXED_IO_ddr_vrn, + FIXED_IO_ddr_vrp, + FIXED_IO_mio, + FIXED_IO_ps_clk, + FIXED_IO_ps_porb, + FIXED_IO_ps_srstb, + i_miso_0, + i_miso_1, + i_miso_2, + o_cs_0, + o_cs_1, + o_cs_2, + o_mosi_0, + o_mosi_1, + o_mosi_2, + o_sclk_0, + o_sclk_1, + o_sclk_2); + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250" *) inout [14:0]DDR_addr; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_ba; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_cas_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_ck_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_ck_p; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_cke; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_cs_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_dm; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_dq; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_dqs_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) inout [3:0]DDR_dqs_p; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_odt; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_ras_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_reset_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_we_n; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout FIXED_IO_ddr_vrn; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout FIXED_IO_ddr_vrp; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]FIXED_IO_mio; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout FIXED_IO_ps_clk; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) inout FIXED_IO_ps_porb; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout FIXED_IO_ps_srstb; + input i_miso_0; + input i_miso_1; + input i_miso_2; + output o_cs_0; + output o_cs_1; + output o_cs_2; + output o_mosi_0; + output o_mosi_1; + output o_mosi_2; + output o_sclk_0; + output o_sclk_1; + output o_sclk_2; + + wire SPI_Con_0_o_cs; + wire SPI_Con_0_o_mosi; + wire SPI_Con_0_o_sclk; + wire SPI_Con_1_o_cs; + wire SPI_Con_1_o_mosi; + wire SPI_Con_1_o_sclk; + wire SPI_Con_2_o_cs; + wire SPI_Con_2_o_mosi; + wire SPI_Con_2_o_sclk; + wire clk_wiz_0_clk_out1; + wire clk_wiz_0_locked; + wire i_miso_0_1; + wire i_miso_1_1; + wire i_miso_2_1; + wire [0:0]proc_sys_reset_0_peripheral_reset; + wire [14:0]processing_system7_0_DDR_ADDR; + wire [2:0]processing_system7_0_DDR_BA; + wire processing_system7_0_DDR_CAS_N; + wire processing_system7_0_DDR_CKE; + wire processing_system7_0_DDR_CK_N; + wire processing_system7_0_DDR_CK_P; + wire processing_system7_0_DDR_CS_N; + wire [3:0]processing_system7_0_DDR_DM; + wire [31:0]processing_system7_0_DDR_DQ; + wire [3:0]processing_system7_0_DDR_DQS_N; + wire [3:0]processing_system7_0_DDR_DQS_P; + wire processing_system7_0_DDR_ODT; + wire processing_system7_0_DDR_RAS_N; + wire processing_system7_0_DDR_RESET_N; + wire processing_system7_0_DDR_WE_N; + wire processing_system7_0_FCLK_CLK0; + wire processing_system7_0_FCLK_RESET0_N; + wire processing_system7_0_FIXED_IO_DDR_VRN; + wire processing_system7_0_FIXED_IO_DDR_VRP; + wire [53:0]processing_system7_0_FIXED_IO_MIO; + wire processing_system7_0_FIXED_IO_PS_CLK; + wire processing_system7_0_FIXED_IO_PS_PORB; + wire processing_system7_0_FIXED_IO_PS_SRSTB; + wire [31:0]processing_system7_0_M_AXI_GP0_ARADDR; + wire [1:0]processing_system7_0_M_AXI_GP0_ARBURST; + wire [3:0]processing_system7_0_M_AXI_GP0_ARCACHE; + wire [11:0]processing_system7_0_M_AXI_GP0_ARID; + wire [3:0]processing_system7_0_M_AXI_GP0_ARLEN; + wire [1:0]processing_system7_0_M_AXI_GP0_ARLOCK; + wire [2:0]processing_system7_0_M_AXI_GP0_ARPROT; + wire [3:0]processing_system7_0_M_AXI_GP0_ARQOS; + wire processing_system7_0_M_AXI_GP0_ARREADY; + wire [2:0]processing_system7_0_M_AXI_GP0_ARSIZE; + wire processing_system7_0_M_AXI_GP0_ARVALID; + wire [31:0]processing_system7_0_M_AXI_GP0_AWADDR; + wire [1:0]processing_system7_0_M_AXI_GP0_AWBURST; + wire [3:0]processing_system7_0_M_AXI_GP0_AWCACHE; + wire [11:0]processing_system7_0_M_AXI_GP0_AWID; + wire [3:0]processing_system7_0_M_AXI_GP0_AWLEN; + wire [1:0]processing_system7_0_M_AXI_GP0_AWLOCK; + wire [2:0]processing_system7_0_M_AXI_GP0_AWPROT; + wire [3:0]processing_system7_0_M_AXI_GP0_AWQOS; + wire processing_system7_0_M_AXI_GP0_AWREADY; + wire [2:0]processing_system7_0_M_AXI_GP0_AWSIZE; + wire processing_system7_0_M_AXI_GP0_AWVALID; + wire [11:0]processing_system7_0_M_AXI_GP0_BID; + wire processing_system7_0_M_AXI_GP0_BREADY; + wire [1:0]processing_system7_0_M_AXI_GP0_BRESP; + wire processing_system7_0_M_AXI_GP0_BVALID; + wire [31:0]processing_system7_0_M_AXI_GP0_RDATA; + wire [11:0]processing_system7_0_M_AXI_GP0_RID; + wire processing_system7_0_M_AXI_GP0_RLAST; + wire processing_system7_0_M_AXI_GP0_RREADY; + wire [1:0]processing_system7_0_M_AXI_GP0_RRESP; + wire processing_system7_0_M_AXI_GP0_RVALID; + wire [31:0]processing_system7_0_M_AXI_GP0_WDATA; + wire [11:0]processing_system7_0_M_AXI_GP0_WID; + wire processing_system7_0_M_AXI_GP0_WLAST; + wire processing_system7_0_M_AXI_GP0_WREADY; + wire [3:0]processing_system7_0_M_AXI_GP0_WSTRB; + wire processing_system7_0_M_AXI_GP0_WVALID; + wire [31:0]ps7_0_axi_periph_M00_AXI_ARADDR; + wire [2:0]ps7_0_axi_periph_M00_AXI_ARPROT; + wire ps7_0_axi_periph_M00_AXI_ARREADY; + wire [0:0]ps7_0_axi_periph_M00_AXI_ARVALID; + wire [31:0]ps7_0_axi_periph_M00_AXI_AWADDR; + wire [2:0]ps7_0_axi_periph_M00_AXI_AWPROT; + wire ps7_0_axi_periph_M00_AXI_AWREADY; + wire [0:0]ps7_0_axi_periph_M00_AXI_AWVALID; + wire [0:0]ps7_0_axi_periph_M00_AXI_BREADY; + wire [1:0]ps7_0_axi_periph_M00_AXI_BRESP; + wire ps7_0_axi_periph_M00_AXI_BVALID; + wire [31:0]ps7_0_axi_periph_M00_AXI_RDATA; + wire [0:0]ps7_0_axi_periph_M00_AXI_RREADY; + wire [1:0]ps7_0_axi_periph_M00_AXI_RRESP; + wire ps7_0_axi_periph_M00_AXI_RVALID; + wire [31:0]ps7_0_axi_periph_M00_AXI_WDATA; + wire ps7_0_axi_periph_M00_AXI_WREADY; + wire [3:0]ps7_0_axi_periph_M00_AXI_WSTRB; + wire [0:0]ps7_0_axi_periph_M00_AXI_WVALID; + wire [31:0]ps7_0_axi_periph_M01_AXI_ARADDR; + wire [2:0]ps7_0_axi_periph_M01_AXI_ARPROT; + wire ps7_0_axi_periph_M01_AXI_ARREADY; + wire [0:0]ps7_0_axi_periph_M01_AXI_ARVALID; + wire [31:0]ps7_0_axi_periph_M01_AXI_AWADDR; + wire [2:0]ps7_0_axi_periph_M01_AXI_AWPROT; + wire ps7_0_axi_periph_M01_AXI_AWREADY; + wire [0:0]ps7_0_axi_periph_M01_AXI_AWVALID; + wire [0:0]ps7_0_axi_periph_M01_AXI_BREADY; + wire [1:0]ps7_0_axi_periph_M01_AXI_BRESP; + wire ps7_0_axi_periph_M01_AXI_BVALID; + wire [31:0]ps7_0_axi_periph_M01_AXI_RDATA; + wire [0:0]ps7_0_axi_periph_M01_AXI_RREADY; + wire [1:0]ps7_0_axi_periph_M01_AXI_RRESP; + wire ps7_0_axi_periph_M01_AXI_RVALID; + wire [31:0]ps7_0_axi_periph_M01_AXI_WDATA; + wire ps7_0_axi_periph_M01_AXI_WREADY; + wire [3:0]ps7_0_axi_periph_M01_AXI_WSTRB; + wire [0:0]ps7_0_axi_periph_M01_AXI_WVALID; + wire [31:0]ps7_0_axi_periph_M02_AXI_ARADDR; + wire [2:0]ps7_0_axi_periph_M02_AXI_ARPROT; + wire ps7_0_axi_periph_M02_AXI_ARREADY; + wire [0:0]ps7_0_axi_periph_M02_AXI_ARVALID; + wire [31:0]ps7_0_axi_periph_M02_AXI_AWADDR; + wire [2:0]ps7_0_axi_periph_M02_AXI_AWPROT; + wire ps7_0_axi_periph_M02_AXI_AWREADY; + wire [0:0]ps7_0_axi_periph_M02_AXI_AWVALID; + wire [0:0]ps7_0_axi_periph_M02_AXI_BREADY; + wire [1:0]ps7_0_axi_periph_M02_AXI_BRESP; + wire ps7_0_axi_periph_M02_AXI_BVALID; + wire [31:0]ps7_0_axi_periph_M02_AXI_RDATA; + wire [0:0]ps7_0_axi_periph_M02_AXI_RREADY; + wire [1:0]ps7_0_axi_periph_M02_AXI_RRESP; + wire ps7_0_axi_periph_M02_AXI_RVALID; + wire [31:0]ps7_0_axi_periph_M02_AXI_WDATA; + wire ps7_0_axi_periph_M02_AXI_WREADY; + wire [3:0]ps7_0_axi_periph_M02_AXI_WSTRB; + wire [0:0]ps7_0_axi_periph_M02_AXI_WVALID; + wire [0:0]rst_clk_wiz_0_100M_peripheral_aresetn; + + assign i_miso_0_1 = i_miso_0; + assign i_miso_1_1 = i_miso_1; + assign i_miso_2_1 = i_miso_2; + assign o_cs_0 = SPI_Con_0_o_cs; + assign o_cs_1 = SPI_Con_1_o_cs; + assign o_cs_2 = SPI_Con_2_o_cs; + assign o_mosi_0 = SPI_Con_0_o_mosi; + assign o_mosi_1 = SPI_Con_1_o_mosi; + assign o_mosi_2 = SPI_Con_2_o_mosi; + assign o_sclk_0 = SPI_Con_0_o_sclk; + assign o_sclk_1 = SPI_Con_1_o_sclk; + assign o_sclk_2 = SPI_Con_2_o_sclk; + NewExtInst_TOP_SPI_Con_0_0 SPI_Con_0 + (.i_miso(i_miso_0_1), + .o_cs(SPI_Con_0_o_cs), + .o_mosi(SPI_Con_0_o_mosi), + .o_sclk(SPI_Con_0_o_sclk), + .s00_axi_aclk(clk_wiz_0_clk_out1), + .s00_axi_araddr(ps7_0_axi_periph_M00_AXI_ARADDR[6:0]), + .s00_axi_aresetn(rst_clk_wiz_0_100M_peripheral_aresetn), + .s00_axi_arprot(ps7_0_axi_periph_M00_AXI_ARPROT), + .s00_axi_arready(ps7_0_axi_periph_M00_AXI_ARREADY), + .s00_axi_arvalid(ps7_0_axi_periph_M00_AXI_ARVALID), + .s00_axi_awaddr(ps7_0_axi_periph_M00_AXI_AWADDR[6:0]), + .s00_axi_awprot(ps7_0_axi_periph_M00_AXI_AWPROT), + .s00_axi_awready(ps7_0_axi_periph_M00_AXI_AWREADY), + .s00_axi_awvalid(ps7_0_axi_periph_M00_AXI_AWVALID), + .s00_axi_bready(ps7_0_axi_periph_M00_AXI_BREADY), + .s00_axi_bresp(ps7_0_axi_periph_M00_AXI_BRESP), + .s00_axi_bvalid(ps7_0_axi_periph_M00_AXI_BVALID), + .s00_axi_rdata(ps7_0_axi_periph_M00_AXI_RDATA), + .s00_axi_rready(ps7_0_axi_periph_M00_AXI_RREADY), + .s00_axi_rresp(ps7_0_axi_periph_M00_AXI_RRESP), + .s00_axi_rvalid(ps7_0_axi_periph_M00_AXI_RVALID), + .s00_axi_wdata(ps7_0_axi_periph_M00_AXI_WDATA), + .s00_axi_wready(ps7_0_axi_periph_M00_AXI_WREADY), + .s00_axi_wstrb(ps7_0_axi_periph_M00_AXI_WSTRB), + .s00_axi_wvalid(ps7_0_axi_periph_M00_AXI_WVALID)); + NewExtInst_TOP_SPI_Con_0_1 SPI_Con_1 + (.i_miso(i_miso_1_1), + .o_cs(SPI_Con_1_o_cs), + .o_mosi(SPI_Con_1_o_mosi), + .o_sclk(SPI_Con_1_o_sclk), + .s00_axi_aclk(clk_wiz_0_clk_out1), + .s00_axi_araddr(ps7_0_axi_periph_M01_AXI_ARADDR[6:0]), + .s00_axi_aresetn(rst_clk_wiz_0_100M_peripheral_aresetn), + .s00_axi_arprot(ps7_0_axi_periph_M01_AXI_ARPROT), + .s00_axi_arready(ps7_0_axi_periph_M01_AXI_ARREADY), + .s00_axi_arvalid(ps7_0_axi_periph_M01_AXI_ARVALID), + .s00_axi_awaddr(ps7_0_axi_periph_M01_AXI_AWADDR[6:0]), + .s00_axi_awprot(ps7_0_axi_periph_M01_AXI_AWPROT), + .s00_axi_awready(ps7_0_axi_periph_M01_AXI_AWREADY), + .s00_axi_awvalid(ps7_0_axi_periph_M01_AXI_AWVALID), + .s00_axi_bready(ps7_0_axi_periph_M01_AXI_BREADY), + .s00_axi_bresp(ps7_0_axi_periph_M01_AXI_BRESP), + .s00_axi_bvalid(ps7_0_axi_periph_M01_AXI_BVALID), + .s00_axi_rdata(ps7_0_axi_periph_M01_AXI_RDATA), + .s00_axi_rready(ps7_0_axi_periph_M01_AXI_RREADY), + .s00_axi_rresp(ps7_0_axi_periph_M01_AXI_RRESP), + .s00_axi_rvalid(ps7_0_axi_periph_M01_AXI_RVALID), + .s00_axi_wdata(ps7_0_axi_periph_M01_AXI_WDATA), + .s00_axi_wready(ps7_0_axi_periph_M01_AXI_WREADY), + .s00_axi_wstrb(ps7_0_axi_periph_M01_AXI_WSTRB), + .s00_axi_wvalid(ps7_0_axi_periph_M01_AXI_WVALID)); + NewExtInst_TOP_SPI_Con_0_2 SPI_Con_2 + (.i_miso(i_miso_2_1), + .o_cs(SPI_Con_2_o_cs), + .o_mosi(SPI_Con_2_o_mosi), + .o_sclk(SPI_Con_2_o_sclk), + .s00_axi_aclk(clk_wiz_0_clk_out1), + .s00_axi_araddr(ps7_0_axi_periph_M02_AXI_ARADDR[6:0]), + .s00_axi_aresetn(rst_clk_wiz_0_100M_peripheral_aresetn), + .s00_axi_arprot(ps7_0_axi_periph_M02_AXI_ARPROT), + .s00_axi_arready(ps7_0_axi_periph_M02_AXI_ARREADY), + .s00_axi_arvalid(ps7_0_axi_periph_M02_AXI_ARVALID), + .s00_axi_awaddr(ps7_0_axi_periph_M02_AXI_AWADDR[6:0]), + .s00_axi_awprot(ps7_0_axi_periph_M02_AXI_AWPROT), + .s00_axi_awready(ps7_0_axi_periph_M02_AXI_AWREADY), + .s00_axi_awvalid(ps7_0_axi_periph_M02_AXI_AWVALID), + .s00_axi_bready(ps7_0_axi_periph_M02_AXI_BREADY), + .s00_axi_bresp(ps7_0_axi_periph_M02_AXI_BRESP), + .s00_axi_bvalid(ps7_0_axi_periph_M02_AXI_BVALID), + .s00_axi_rdata(ps7_0_axi_periph_M02_AXI_RDATA), + .s00_axi_rready(ps7_0_axi_periph_M02_AXI_RREADY), + .s00_axi_rresp(ps7_0_axi_periph_M02_AXI_RRESP), + .s00_axi_rvalid(ps7_0_axi_periph_M02_AXI_RVALID), + .s00_axi_wdata(ps7_0_axi_periph_M02_AXI_WDATA), + .s00_axi_wready(ps7_0_axi_periph_M02_AXI_WREADY), + .s00_axi_wstrb(ps7_0_axi_periph_M02_AXI_WSTRB), + .s00_axi_wvalid(ps7_0_axi_periph_M02_AXI_WVALID)); + NewExtInst_TOP_clk_wiz_0_0 clk_wiz_0 + (.clk_in1(processing_system7_0_FCLK_CLK0), + .clk_out1(clk_wiz_0_clk_out1), + .locked(clk_wiz_0_locked), + .reset(proc_sys_reset_0_peripheral_reset)); + NewExtInst_TOP_proc_sys_reset_0_0 proc_sys_reset_0 + (.aux_reset_in(1'b1), + .dcm_locked(1'b1), + .ext_reset_in(processing_system7_0_FCLK_RESET0_N), + .mb_debug_sys_rst(1'b0), + .peripheral_reset(proc_sys_reset_0_peripheral_reset), + .slowest_sync_clk(processing_system7_0_FCLK_CLK0)); + NewExtInst_TOP_processing_system7_0_0 processing_system7_0 + (.DDR_Addr(DDR_addr[14:0]), + .DDR_BankAddr(DDR_ba[2:0]), + .DDR_CAS_n(DDR_cas_n), + .DDR_CKE(DDR_cke), + .DDR_CS_n(DDR_cs_n), + .DDR_Clk(DDR_ck_p), + .DDR_Clk_n(DDR_ck_n), + .DDR_DM(DDR_dm[3:0]), + .DDR_DQ(DDR_dq[31:0]), + .DDR_DQS(DDR_dqs_p[3:0]), + .DDR_DQS_n(DDR_dqs_n[3:0]), + .DDR_DRSTB(DDR_reset_n), + .DDR_ODT(DDR_odt), + .DDR_RAS_n(DDR_ras_n), + .DDR_VRN(FIXED_IO_ddr_vrn), + .DDR_VRP(FIXED_IO_ddr_vrp), + .DDR_WEB(DDR_we_n), + .FCLK_CLK0(processing_system7_0_FCLK_CLK0), + .FCLK_RESET0_N(processing_system7_0_FCLK_RESET0_N), + .MIO(FIXED_IO_mio[53:0]), + .M_AXI_GP0_ACLK(clk_wiz_0_clk_out1), + .M_AXI_GP0_ARADDR(processing_system7_0_M_AXI_GP0_ARADDR), + .M_AXI_GP0_ARBURST(processing_system7_0_M_AXI_GP0_ARBURST), + .M_AXI_GP0_ARCACHE(processing_system7_0_M_AXI_GP0_ARCACHE), + .M_AXI_GP0_ARID(processing_system7_0_M_AXI_GP0_ARID), + .M_AXI_GP0_ARLEN(processing_system7_0_M_AXI_GP0_ARLEN), + .M_AXI_GP0_ARLOCK(processing_system7_0_M_AXI_GP0_ARLOCK), + .M_AXI_GP0_ARPROT(processing_system7_0_M_AXI_GP0_ARPROT), + .M_AXI_GP0_ARQOS(processing_system7_0_M_AXI_GP0_ARQOS), + .M_AXI_GP0_ARREADY(processing_system7_0_M_AXI_GP0_ARREADY), + .M_AXI_GP0_ARSIZE(processing_system7_0_M_AXI_GP0_ARSIZE), + .M_AXI_GP0_ARVALID(processing_system7_0_M_AXI_GP0_ARVALID), + .M_AXI_GP0_AWADDR(processing_system7_0_M_AXI_GP0_AWADDR), + .M_AXI_GP0_AWBURST(processing_system7_0_M_AXI_GP0_AWBURST), + .M_AXI_GP0_AWCACHE(processing_system7_0_M_AXI_GP0_AWCACHE), + .M_AXI_GP0_AWID(processing_system7_0_M_AXI_GP0_AWID), + .M_AXI_GP0_AWLEN(processing_system7_0_M_AXI_GP0_AWLEN), + .M_AXI_GP0_AWLOCK(processing_system7_0_M_AXI_GP0_AWLOCK), + .M_AXI_GP0_AWPROT(processing_system7_0_M_AXI_GP0_AWPROT), + .M_AXI_GP0_AWQOS(processing_system7_0_M_AXI_GP0_AWQOS), + .M_AXI_GP0_AWREADY(processing_system7_0_M_AXI_GP0_AWREADY), + .M_AXI_GP0_AWSIZE(processing_system7_0_M_AXI_GP0_AWSIZE), + .M_AXI_GP0_AWVALID(processing_system7_0_M_AXI_GP0_AWVALID), + .M_AXI_GP0_BID(processing_system7_0_M_AXI_GP0_BID), + .M_AXI_GP0_BREADY(processing_system7_0_M_AXI_GP0_BREADY), + .M_AXI_GP0_BRESP(processing_system7_0_M_AXI_GP0_BRESP), + .M_AXI_GP0_BVALID(processing_system7_0_M_AXI_GP0_BVALID), + .M_AXI_GP0_RDATA(processing_system7_0_M_AXI_GP0_RDATA), + .M_AXI_GP0_RID(processing_system7_0_M_AXI_GP0_RID), + .M_AXI_GP0_RLAST(processing_system7_0_M_AXI_GP0_RLAST), + .M_AXI_GP0_RREADY(processing_system7_0_M_AXI_GP0_RREADY), + .M_AXI_GP0_RRESP(processing_system7_0_M_AXI_GP0_RRESP), + .M_AXI_GP0_RVALID(processing_system7_0_M_AXI_GP0_RVALID), + .M_AXI_GP0_WDATA(processing_system7_0_M_AXI_GP0_WDATA), + .M_AXI_GP0_WID(processing_system7_0_M_AXI_GP0_WID), + .M_AXI_GP0_WLAST(processing_system7_0_M_AXI_GP0_WLAST), + .M_AXI_GP0_WREADY(processing_system7_0_M_AXI_GP0_WREADY), + .M_AXI_GP0_WSTRB(processing_system7_0_M_AXI_GP0_WSTRB), + .M_AXI_GP0_WVALID(processing_system7_0_M_AXI_GP0_WVALID), + .PS_CLK(FIXED_IO_ps_clk), + .PS_PORB(FIXED_IO_ps_porb), + .PS_SRSTB(FIXED_IO_ps_srstb)); + NewExtInst_TOP_ps7_0_axi_periph_0 ps7_0_axi_periph + (.ACLK(clk_wiz_0_clk_out1), + .ARESETN(rst_clk_wiz_0_100M_peripheral_aresetn), + .M00_ACLK(clk_wiz_0_clk_out1), + .M00_ARESETN(rst_clk_wiz_0_100M_peripheral_aresetn), + .M00_AXI_araddr(ps7_0_axi_periph_M00_AXI_ARADDR), + .M00_AXI_arprot(ps7_0_axi_periph_M00_AXI_ARPROT), + .M00_AXI_arready(ps7_0_axi_periph_M00_AXI_ARREADY), + .M00_AXI_arvalid(ps7_0_axi_periph_M00_AXI_ARVALID), + .M00_AXI_awaddr(ps7_0_axi_periph_M00_AXI_AWADDR), + .M00_AXI_awprot(ps7_0_axi_periph_M00_AXI_AWPROT), + .M00_AXI_awready(ps7_0_axi_periph_M00_AXI_AWREADY), + .M00_AXI_awvalid(ps7_0_axi_periph_M00_AXI_AWVALID), + .M00_AXI_bready(ps7_0_axi_periph_M00_AXI_BREADY), + .M00_AXI_bresp(ps7_0_axi_periph_M00_AXI_BRESP), + .M00_AXI_bvalid(ps7_0_axi_periph_M00_AXI_BVALID), + .M00_AXI_rdata(ps7_0_axi_periph_M00_AXI_RDATA), + .M00_AXI_rready(ps7_0_axi_periph_M00_AXI_RREADY), + .M00_AXI_rresp(ps7_0_axi_periph_M00_AXI_RRESP), + .M00_AXI_rvalid(ps7_0_axi_periph_M00_AXI_RVALID), + .M00_AXI_wdata(ps7_0_axi_periph_M00_AXI_WDATA), + .M00_AXI_wready(ps7_0_axi_periph_M00_AXI_WREADY), + .M00_AXI_wstrb(ps7_0_axi_periph_M00_AXI_WSTRB), + .M00_AXI_wvalid(ps7_0_axi_periph_M00_AXI_WVALID), + .M01_ACLK(clk_wiz_0_clk_out1), + .M01_ARESETN(rst_clk_wiz_0_100M_peripheral_aresetn), + .M01_AXI_araddr(ps7_0_axi_periph_M01_AXI_ARADDR), + .M01_AXI_arprot(ps7_0_axi_periph_M01_AXI_ARPROT), + .M01_AXI_arready(ps7_0_axi_periph_M01_AXI_ARREADY), + .M01_AXI_arvalid(ps7_0_axi_periph_M01_AXI_ARVALID), + .M01_AXI_awaddr(ps7_0_axi_periph_M01_AXI_AWADDR), + .M01_AXI_awprot(ps7_0_axi_periph_M01_AXI_AWPROT), + .M01_AXI_awready(ps7_0_axi_periph_M01_AXI_AWREADY), + .M01_AXI_awvalid(ps7_0_axi_periph_M01_AXI_AWVALID), + .M01_AXI_bready(ps7_0_axi_periph_M01_AXI_BREADY), + .M01_AXI_bresp(ps7_0_axi_periph_M01_AXI_BRESP), + .M01_AXI_bvalid(ps7_0_axi_periph_M01_AXI_BVALID), + .M01_AXI_rdata(ps7_0_axi_periph_M01_AXI_RDATA), + .M01_AXI_rready(ps7_0_axi_periph_M01_AXI_RREADY), + .M01_AXI_rresp(ps7_0_axi_periph_M01_AXI_RRESP), + .M01_AXI_rvalid(ps7_0_axi_periph_M01_AXI_RVALID), + .M01_AXI_wdata(ps7_0_axi_periph_M01_AXI_WDATA), + .M01_AXI_wready(ps7_0_axi_periph_M01_AXI_WREADY), + .M01_AXI_wstrb(ps7_0_axi_periph_M01_AXI_WSTRB), + .M01_AXI_wvalid(ps7_0_axi_periph_M01_AXI_WVALID), + .M02_ACLK(clk_wiz_0_clk_out1), + .M02_ARESETN(rst_clk_wiz_0_100M_peripheral_aresetn), + .M02_AXI_araddr(ps7_0_axi_periph_M02_AXI_ARADDR), + .M02_AXI_arprot(ps7_0_axi_periph_M02_AXI_ARPROT), + .M02_AXI_arready(ps7_0_axi_periph_M02_AXI_ARREADY), + .M02_AXI_arvalid(ps7_0_axi_periph_M02_AXI_ARVALID), + .M02_AXI_awaddr(ps7_0_axi_periph_M02_AXI_AWADDR), + .M02_AXI_awprot(ps7_0_axi_periph_M02_AXI_AWPROT), + .M02_AXI_awready(ps7_0_axi_periph_M02_AXI_AWREADY), + .M02_AXI_awvalid(ps7_0_axi_periph_M02_AXI_AWVALID), + .M02_AXI_bready(ps7_0_axi_periph_M02_AXI_BREADY), + .M02_AXI_bresp(ps7_0_axi_periph_M02_AXI_BRESP), + .M02_AXI_bvalid(ps7_0_axi_periph_M02_AXI_BVALID), + .M02_AXI_rdata(ps7_0_axi_periph_M02_AXI_RDATA), + .M02_AXI_rready(ps7_0_axi_periph_M02_AXI_RREADY), + .M02_AXI_rresp(ps7_0_axi_periph_M02_AXI_RRESP), + .M02_AXI_rvalid(ps7_0_axi_periph_M02_AXI_RVALID), + .M02_AXI_wdata(ps7_0_axi_periph_M02_AXI_WDATA), + .M02_AXI_wready(ps7_0_axi_periph_M02_AXI_WREADY), + .M02_AXI_wstrb(ps7_0_axi_periph_M02_AXI_WSTRB), + .M02_AXI_wvalid(ps7_0_axi_periph_M02_AXI_WVALID), + .S00_ACLK(clk_wiz_0_clk_out1), + .S00_ARESETN(rst_clk_wiz_0_100M_peripheral_aresetn), + .S00_AXI_araddr(processing_system7_0_M_AXI_GP0_ARADDR), + .S00_AXI_arburst(processing_system7_0_M_AXI_GP0_ARBURST), + .S00_AXI_arcache(processing_system7_0_M_AXI_GP0_ARCACHE), + .S00_AXI_arid(processing_system7_0_M_AXI_GP0_ARID), + .S00_AXI_arlen(processing_system7_0_M_AXI_GP0_ARLEN), + .S00_AXI_arlock(processing_system7_0_M_AXI_GP0_ARLOCK), + .S00_AXI_arprot(processing_system7_0_M_AXI_GP0_ARPROT), + .S00_AXI_arqos(processing_system7_0_M_AXI_GP0_ARQOS), + .S00_AXI_arready(processing_system7_0_M_AXI_GP0_ARREADY), + .S00_AXI_arsize(processing_system7_0_M_AXI_GP0_ARSIZE), + .S00_AXI_arvalid(processing_system7_0_M_AXI_GP0_ARVALID), + .S00_AXI_awaddr(processing_system7_0_M_AXI_GP0_AWADDR), + .S00_AXI_awburst(processing_system7_0_M_AXI_GP0_AWBURST), + .S00_AXI_awcache(processing_system7_0_M_AXI_GP0_AWCACHE), + .S00_AXI_awid(processing_system7_0_M_AXI_GP0_AWID), + .S00_AXI_awlen(processing_system7_0_M_AXI_GP0_AWLEN), + .S00_AXI_awlock(processing_system7_0_M_AXI_GP0_AWLOCK), + .S00_AXI_awprot(processing_system7_0_M_AXI_GP0_AWPROT), + .S00_AXI_awqos(processing_system7_0_M_AXI_GP0_AWQOS), + .S00_AXI_awready(processing_system7_0_M_AXI_GP0_AWREADY), + .S00_AXI_awsize(processing_system7_0_M_AXI_GP0_AWSIZE), + .S00_AXI_awvalid(processing_system7_0_M_AXI_GP0_AWVALID), + .S00_AXI_bid(processing_system7_0_M_AXI_GP0_BID), + .S00_AXI_bready(processing_system7_0_M_AXI_GP0_BREADY), + .S00_AXI_bresp(processing_system7_0_M_AXI_GP0_BRESP), + .S00_AXI_bvalid(processing_system7_0_M_AXI_GP0_BVALID), + .S00_AXI_rdata(processing_system7_0_M_AXI_GP0_RDATA), + .S00_AXI_rid(processing_system7_0_M_AXI_GP0_RID), + .S00_AXI_rlast(processing_system7_0_M_AXI_GP0_RLAST), + .S00_AXI_rready(processing_system7_0_M_AXI_GP0_RREADY), + .S00_AXI_rresp(processing_system7_0_M_AXI_GP0_RRESP), + .S00_AXI_rvalid(processing_system7_0_M_AXI_GP0_RVALID), + .S00_AXI_wdata(processing_system7_0_M_AXI_GP0_WDATA), + .S00_AXI_wid(processing_system7_0_M_AXI_GP0_WID), + .S00_AXI_wlast(processing_system7_0_M_AXI_GP0_WLAST), + .S00_AXI_wready(processing_system7_0_M_AXI_GP0_WREADY), + .S00_AXI_wstrb(processing_system7_0_M_AXI_GP0_WSTRB), + .S00_AXI_wvalid(processing_system7_0_M_AXI_GP0_WVALID)); + NewExtInst_TOP_rst_clk_wiz_0_100M_0 rst_clk_wiz_0_100M + (.aux_reset_in(1'b1), + .dcm_locked(clk_wiz_0_locked), + .ext_reset_in(proc_sys_reset_0_peripheral_reset), + .mb_debug_sys_rst(1'b0), + .peripheral_aresetn(rst_clk_wiz_0_100M_peripheral_aresetn), + .slowest_sync_clk(clk_wiz_0_clk_out1)); +endmodule + +module NewExtInst_TOP_ps7_0_axi_periph_0 + (ACLK, + ARESETN, + M00_ACLK, + M00_ARESETN, + M00_AXI_araddr, + M00_AXI_arprot, + M00_AXI_arready, + M00_AXI_arvalid, + M00_AXI_awaddr, + M00_AXI_awprot, + M00_AXI_awready, + M00_AXI_awvalid, + M00_AXI_bready, + M00_AXI_bresp, + M00_AXI_bvalid, + M00_AXI_rdata, + M00_AXI_rready, + M00_AXI_rresp, + M00_AXI_rvalid, + M00_AXI_wdata, + M00_AXI_wready, + M00_AXI_wstrb, + M00_AXI_wvalid, + M01_ACLK, + M01_ARESETN, + M01_AXI_araddr, + M01_AXI_arprot, + M01_AXI_arready, + M01_AXI_arvalid, + M01_AXI_awaddr, + M01_AXI_awprot, + M01_AXI_awready, + M01_AXI_awvalid, + M01_AXI_bready, + M01_AXI_bresp, + M01_AXI_bvalid, + M01_AXI_rdata, + M01_AXI_rready, + M01_AXI_rresp, + M01_AXI_rvalid, + M01_AXI_wdata, + M01_AXI_wready, + M01_AXI_wstrb, + M01_AXI_wvalid, + M02_ACLK, + M02_ARESETN, + M02_AXI_araddr, + M02_AXI_arprot, + M02_AXI_arready, + M02_AXI_arvalid, + M02_AXI_awaddr, + M02_AXI_awprot, + M02_AXI_awready, + M02_AXI_awvalid, + M02_AXI_bready, + M02_AXI_bresp, + M02_AXI_bvalid, + M02_AXI_rdata, + M02_AXI_rready, + M02_AXI_rresp, + M02_AXI_rvalid, + M02_AXI_wdata, + M02_AXI_wready, + M02_AXI_wstrb, + M02_AXI_wvalid, + S00_ACLK, + S00_ARESETN, + S00_AXI_araddr, + S00_AXI_arburst, + S00_AXI_arcache, + S00_AXI_arid, + S00_AXI_arlen, + S00_AXI_arlock, + S00_AXI_arprot, + S00_AXI_arqos, + S00_AXI_arready, + S00_AXI_arsize, + S00_AXI_arvalid, + S00_AXI_awaddr, + S00_AXI_awburst, + S00_AXI_awcache, + S00_AXI_awid, + S00_AXI_awlen, + S00_AXI_awlock, + S00_AXI_awprot, + S00_AXI_awqos, + S00_AXI_awready, + S00_AXI_awsize, + S00_AXI_awvalid, + S00_AXI_bid, + S00_AXI_bready, + S00_AXI_bresp, + S00_AXI_bvalid, + S00_AXI_rdata, + S00_AXI_rid, + S00_AXI_rlast, + S00_AXI_rready, + S00_AXI_rresp, + S00_AXI_rvalid, + S00_AXI_wdata, + S00_AXI_wid, + S00_AXI_wlast, + S00_AXI_wready, + S00_AXI_wstrb, + S00_AXI_wvalid); + input ACLK; + input ARESETN; + input M00_ACLK; + input M00_ARESETN; + output [31:0]M00_AXI_araddr; + output [2:0]M00_AXI_arprot; + input [0:0]M00_AXI_arready; + output [0:0]M00_AXI_arvalid; + output [31:0]M00_AXI_awaddr; + output [2:0]M00_AXI_awprot; + input [0:0]M00_AXI_awready; + output [0:0]M00_AXI_awvalid; + output [0:0]M00_AXI_bready; + input [1:0]M00_AXI_bresp; + input [0:0]M00_AXI_bvalid; + input [31:0]M00_AXI_rdata; + output [0:0]M00_AXI_rready; + input [1:0]M00_AXI_rresp; + input [0:0]M00_AXI_rvalid; + output [31:0]M00_AXI_wdata; + input [0:0]M00_AXI_wready; + output [3:0]M00_AXI_wstrb; + output [0:0]M00_AXI_wvalid; + input M01_ACLK; + input M01_ARESETN; + output [31:0]M01_AXI_araddr; + output [2:0]M01_AXI_arprot; + input [0:0]M01_AXI_arready; + output [0:0]M01_AXI_arvalid; + output [31:0]M01_AXI_awaddr; + output [2:0]M01_AXI_awprot; + input [0:0]M01_AXI_awready; + output [0:0]M01_AXI_awvalid; + output [0:0]M01_AXI_bready; + input [1:0]M01_AXI_bresp; + input [0:0]M01_AXI_bvalid; + input [31:0]M01_AXI_rdata; + output [0:0]M01_AXI_rready; + input [1:0]M01_AXI_rresp; + input [0:0]M01_AXI_rvalid; + output [31:0]M01_AXI_wdata; + input [0:0]M01_AXI_wready; + output [3:0]M01_AXI_wstrb; + output [0:0]M01_AXI_wvalid; + input M02_ACLK; + input M02_ARESETN; + output [31:0]M02_AXI_araddr; + output [2:0]M02_AXI_arprot; + input [0:0]M02_AXI_arready; + output [0:0]M02_AXI_arvalid; + output [31:0]M02_AXI_awaddr; + output [2:0]M02_AXI_awprot; + input [0:0]M02_AXI_awready; + output [0:0]M02_AXI_awvalid; + output [0:0]M02_AXI_bready; + input [1:0]M02_AXI_bresp; + input [0:0]M02_AXI_bvalid; + input [31:0]M02_AXI_rdata; + output [0:0]M02_AXI_rready; + input [1:0]M02_AXI_rresp; + input [0:0]M02_AXI_rvalid; + output [31:0]M02_AXI_wdata; + input [0:0]M02_AXI_wready; + output [3:0]M02_AXI_wstrb; + output [0:0]M02_AXI_wvalid; + input S00_ACLK; + input S00_ARESETN; + input [31:0]S00_AXI_araddr; + input [1:0]S00_AXI_arburst; + input [3:0]S00_AXI_arcache; + input [11:0]S00_AXI_arid; + input [3:0]S00_AXI_arlen; + input [1:0]S00_AXI_arlock; + input [2:0]S00_AXI_arprot; + input [3:0]S00_AXI_arqos; + output S00_AXI_arready; + input [2:0]S00_AXI_arsize; + input S00_AXI_arvalid; + input [31:0]S00_AXI_awaddr; + input [1:0]S00_AXI_awburst; + input [3:0]S00_AXI_awcache; + input [11:0]S00_AXI_awid; + input [3:0]S00_AXI_awlen; + input [1:0]S00_AXI_awlock; + input [2:0]S00_AXI_awprot; + input [3:0]S00_AXI_awqos; + output S00_AXI_awready; + input [2:0]S00_AXI_awsize; + input S00_AXI_awvalid; + output [11:0]S00_AXI_bid; + input S00_AXI_bready; + output [1:0]S00_AXI_bresp; + output S00_AXI_bvalid; + output [31:0]S00_AXI_rdata; + output [11:0]S00_AXI_rid; + output S00_AXI_rlast; + input S00_AXI_rready; + output [1:0]S00_AXI_rresp; + output S00_AXI_rvalid; + input [31:0]S00_AXI_wdata; + input [11:0]S00_AXI_wid; + input S00_AXI_wlast; + output S00_AXI_wready; + input [3:0]S00_AXI_wstrb; + input S00_AXI_wvalid; + + wire [31:0]m00_couplers_to_ps7_0_axi_periph_ARADDR; + wire [2:0]m00_couplers_to_ps7_0_axi_periph_ARPROT; + wire [0:0]m00_couplers_to_ps7_0_axi_periph_ARREADY; + wire [0:0]m00_couplers_to_ps7_0_axi_periph_ARVALID; + wire [31:0]m00_couplers_to_ps7_0_axi_periph_AWADDR; + wire [2:0]m00_couplers_to_ps7_0_axi_periph_AWPROT; + wire [0:0]m00_couplers_to_ps7_0_axi_periph_AWREADY; + wire [0:0]m00_couplers_to_ps7_0_axi_periph_AWVALID; + wire [0:0]m00_couplers_to_ps7_0_axi_periph_BREADY; + wire [1:0]m00_couplers_to_ps7_0_axi_periph_BRESP; + wire [0:0]m00_couplers_to_ps7_0_axi_periph_BVALID; + wire [31:0]m00_couplers_to_ps7_0_axi_periph_RDATA; + wire [0:0]m00_couplers_to_ps7_0_axi_periph_RREADY; + wire [1:0]m00_couplers_to_ps7_0_axi_periph_RRESP; + wire [0:0]m00_couplers_to_ps7_0_axi_periph_RVALID; + wire [31:0]m00_couplers_to_ps7_0_axi_periph_WDATA; + wire [0:0]m00_couplers_to_ps7_0_axi_periph_WREADY; + wire [3:0]m00_couplers_to_ps7_0_axi_periph_WSTRB; + wire [0:0]m00_couplers_to_ps7_0_axi_periph_WVALID; + wire [31:0]m01_couplers_to_ps7_0_axi_periph_ARADDR; + wire [2:0]m01_couplers_to_ps7_0_axi_periph_ARPROT; + wire [0:0]m01_couplers_to_ps7_0_axi_periph_ARREADY; + wire [0:0]m01_couplers_to_ps7_0_axi_periph_ARVALID; + wire [31:0]m01_couplers_to_ps7_0_axi_periph_AWADDR; + wire [2:0]m01_couplers_to_ps7_0_axi_periph_AWPROT; + wire [0:0]m01_couplers_to_ps7_0_axi_periph_AWREADY; + wire [0:0]m01_couplers_to_ps7_0_axi_periph_AWVALID; + wire [0:0]m01_couplers_to_ps7_0_axi_periph_BREADY; + wire [1:0]m01_couplers_to_ps7_0_axi_periph_BRESP; + wire [0:0]m01_couplers_to_ps7_0_axi_periph_BVALID; + wire [31:0]m01_couplers_to_ps7_0_axi_periph_RDATA; + wire [0:0]m01_couplers_to_ps7_0_axi_periph_RREADY; + wire [1:0]m01_couplers_to_ps7_0_axi_periph_RRESP; + wire [0:0]m01_couplers_to_ps7_0_axi_periph_RVALID; + wire [31:0]m01_couplers_to_ps7_0_axi_periph_WDATA; + wire [0:0]m01_couplers_to_ps7_0_axi_periph_WREADY; + wire [3:0]m01_couplers_to_ps7_0_axi_periph_WSTRB; + wire [0:0]m01_couplers_to_ps7_0_axi_periph_WVALID; + wire [31:0]m02_couplers_to_ps7_0_axi_periph_ARADDR; + wire [2:0]m02_couplers_to_ps7_0_axi_periph_ARPROT; + wire [0:0]m02_couplers_to_ps7_0_axi_periph_ARREADY; + wire [0:0]m02_couplers_to_ps7_0_axi_periph_ARVALID; + wire [31:0]m02_couplers_to_ps7_0_axi_periph_AWADDR; + wire [2:0]m02_couplers_to_ps7_0_axi_periph_AWPROT; + wire [0:0]m02_couplers_to_ps7_0_axi_periph_AWREADY; + wire [0:0]m02_couplers_to_ps7_0_axi_periph_AWVALID; + wire [0:0]m02_couplers_to_ps7_0_axi_periph_BREADY; + wire [1:0]m02_couplers_to_ps7_0_axi_periph_BRESP; + wire [0:0]m02_couplers_to_ps7_0_axi_periph_BVALID; + wire [31:0]m02_couplers_to_ps7_0_axi_periph_RDATA; + wire [0:0]m02_couplers_to_ps7_0_axi_periph_RREADY; + wire [1:0]m02_couplers_to_ps7_0_axi_periph_RRESP; + wire [0:0]m02_couplers_to_ps7_0_axi_periph_RVALID; + wire [31:0]m02_couplers_to_ps7_0_axi_periph_WDATA; + wire [0:0]m02_couplers_to_ps7_0_axi_periph_WREADY; + wire [3:0]m02_couplers_to_ps7_0_axi_periph_WSTRB; + wire [0:0]m02_couplers_to_ps7_0_axi_periph_WVALID; + wire ps7_0_axi_periph_ACLK_net; + wire ps7_0_axi_periph_ARESETN_net; + wire [31:0]ps7_0_axi_periph_to_s00_couplers_ARADDR; + wire [1:0]ps7_0_axi_periph_to_s00_couplers_ARBURST; + wire [3:0]ps7_0_axi_periph_to_s00_couplers_ARCACHE; + wire [11:0]ps7_0_axi_periph_to_s00_couplers_ARID; + wire [3:0]ps7_0_axi_periph_to_s00_couplers_ARLEN; + wire [1:0]ps7_0_axi_periph_to_s00_couplers_ARLOCK; + wire [2:0]ps7_0_axi_periph_to_s00_couplers_ARPROT; + wire [3:0]ps7_0_axi_periph_to_s00_couplers_ARQOS; + wire ps7_0_axi_periph_to_s00_couplers_ARREADY; + wire [2:0]ps7_0_axi_periph_to_s00_couplers_ARSIZE; + wire ps7_0_axi_periph_to_s00_couplers_ARVALID; + wire [31:0]ps7_0_axi_periph_to_s00_couplers_AWADDR; + wire [1:0]ps7_0_axi_periph_to_s00_couplers_AWBURST; + wire [3:0]ps7_0_axi_periph_to_s00_couplers_AWCACHE; + wire [11:0]ps7_0_axi_periph_to_s00_couplers_AWID; + wire [3:0]ps7_0_axi_periph_to_s00_couplers_AWLEN; + wire [1:0]ps7_0_axi_periph_to_s00_couplers_AWLOCK; + wire [2:0]ps7_0_axi_periph_to_s00_couplers_AWPROT; + wire [3:0]ps7_0_axi_periph_to_s00_couplers_AWQOS; + wire ps7_0_axi_periph_to_s00_couplers_AWREADY; + wire [2:0]ps7_0_axi_periph_to_s00_couplers_AWSIZE; + wire ps7_0_axi_periph_to_s00_couplers_AWVALID; + wire [11:0]ps7_0_axi_periph_to_s00_couplers_BID; + wire ps7_0_axi_periph_to_s00_couplers_BREADY; + wire [1:0]ps7_0_axi_periph_to_s00_couplers_BRESP; + wire ps7_0_axi_periph_to_s00_couplers_BVALID; + wire [31:0]ps7_0_axi_periph_to_s00_couplers_RDATA; + wire [11:0]ps7_0_axi_periph_to_s00_couplers_RID; + wire ps7_0_axi_periph_to_s00_couplers_RLAST; + wire ps7_0_axi_periph_to_s00_couplers_RREADY; + wire [1:0]ps7_0_axi_periph_to_s00_couplers_RRESP; + wire ps7_0_axi_periph_to_s00_couplers_RVALID; + wire [31:0]ps7_0_axi_periph_to_s00_couplers_WDATA; + wire [11:0]ps7_0_axi_periph_to_s00_couplers_WID; + wire ps7_0_axi_periph_to_s00_couplers_WLAST; + wire ps7_0_axi_periph_to_s00_couplers_WREADY; + wire [3:0]ps7_0_axi_periph_to_s00_couplers_WSTRB; + wire ps7_0_axi_periph_to_s00_couplers_WVALID; + wire [31:0]s00_couplers_to_xbar_ARADDR; + wire [2:0]s00_couplers_to_xbar_ARPROT; + wire [0:0]s00_couplers_to_xbar_ARREADY; + wire s00_couplers_to_xbar_ARVALID; + wire [31:0]s00_couplers_to_xbar_AWADDR; + wire [2:0]s00_couplers_to_xbar_AWPROT; + wire [0:0]s00_couplers_to_xbar_AWREADY; + wire s00_couplers_to_xbar_AWVALID; + wire s00_couplers_to_xbar_BREADY; + wire [1:0]s00_couplers_to_xbar_BRESP; + wire [0:0]s00_couplers_to_xbar_BVALID; + wire [31:0]s00_couplers_to_xbar_RDATA; + wire s00_couplers_to_xbar_RREADY; + wire [1:0]s00_couplers_to_xbar_RRESP; + wire [0:0]s00_couplers_to_xbar_RVALID; + wire [31:0]s00_couplers_to_xbar_WDATA; + wire [0:0]s00_couplers_to_xbar_WREADY; + wire [3:0]s00_couplers_to_xbar_WSTRB; + wire s00_couplers_to_xbar_WVALID; + wire [31:0]xbar_to_m00_couplers_ARADDR; + wire [2:0]xbar_to_m00_couplers_ARPROT; + wire [0:0]xbar_to_m00_couplers_ARREADY; + wire [0:0]xbar_to_m00_couplers_ARVALID; + wire [31:0]xbar_to_m00_couplers_AWADDR; + wire [2:0]xbar_to_m00_couplers_AWPROT; + wire [0:0]xbar_to_m00_couplers_AWREADY; + wire [0:0]xbar_to_m00_couplers_AWVALID; + wire [0:0]xbar_to_m00_couplers_BREADY; + wire [1:0]xbar_to_m00_couplers_BRESP; + wire [0:0]xbar_to_m00_couplers_BVALID; + wire [31:0]xbar_to_m00_couplers_RDATA; + wire [0:0]xbar_to_m00_couplers_RREADY; + wire [1:0]xbar_to_m00_couplers_RRESP; + wire [0:0]xbar_to_m00_couplers_RVALID; + wire [31:0]xbar_to_m00_couplers_WDATA; + wire [0:0]xbar_to_m00_couplers_WREADY; + wire [3:0]xbar_to_m00_couplers_WSTRB; + wire [0:0]xbar_to_m00_couplers_WVALID; + wire [63:32]xbar_to_m01_couplers_ARADDR; + wire [5:3]xbar_to_m01_couplers_ARPROT; + wire [0:0]xbar_to_m01_couplers_ARREADY; + wire [1:1]xbar_to_m01_couplers_ARVALID; + wire [63:32]xbar_to_m01_couplers_AWADDR; + wire [5:3]xbar_to_m01_couplers_AWPROT; + wire [0:0]xbar_to_m01_couplers_AWREADY; + wire [1:1]xbar_to_m01_couplers_AWVALID; + wire [1:1]xbar_to_m01_couplers_BREADY; + wire [1:0]xbar_to_m01_couplers_BRESP; + wire [0:0]xbar_to_m01_couplers_BVALID; + wire [31:0]xbar_to_m01_couplers_RDATA; + wire [1:1]xbar_to_m01_couplers_RREADY; + wire [1:0]xbar_to_m01_couplers_RRESP; + wire [0:0]xbar_to_m01_couplers_RVALID; + wire [63:32]xbar_to_m01_couplers_WDATA; + wire [0:0]xbar_to_m01_couplers_WREADY; + wire [7:4]xbar_to_m01_couplers_WSTRB; + wire [1:1]xbar_to_m01_couplers_WVALID; + wire [95:64]xbar_to_m02_couplers_ARADDR; + wire [8:6]xbar_to_m02_couplers_ARPROT; + wire [0:0]xbar_to_m02_couplers_ARREADY; + wire [2:2]xbar_to_m02_couplers_ARVALID; + wire [95:64]xbar_to_m02_couplers_AWADDR; + wire [8:6]xbar_to_m02_couplers_AWPROT; + wire [0:0]xbar_to_m02_couplers_AWREADY; + wire [2:2]xbar_to_m02_couplers_AWVALID; + wire [2:2]xbar_to_m02_couplers_BREADY; + wire [1:0]xbar_to_m02_couplers_BRESP; + wire [0:0]xbar_to_m02_couplers_BVALID; + wire [31:0]xbar_to_m02_couplers_RDATA; + wire [2:2]xbar_to_m02_couplers_RREADY; + wire [1:0]xbar_to_m02_couplers_RRESP; + wire [0:0]xbar_to_m02_couplers_RVALID; + wire [95:64]xbar_to_m02_couplers_WDATA; + wire [0:0]xbar_to_m02_couplers_WREADY; + wire [11:8]xbar_to_m02_couplers_WSTRB; + wire [2:2]xbar_to_m02_couplers_WVALID; + + assign M00_AXI_araddr[31:0] = m00_couplers_to_ps7_0_axi_periph_ARADDR; + assign M00_AXI_arprot[2:0] = m00_couplers_to_ps7_0_axi_periph_ARPROT; + assign M00_AXI_arvalid[0] = m00_couplers_to_ps7_0_axi_periph_ARVALID; + assign M00_AXI_awaddr[31:0] = m00_couplers_to_ps7_0_axi_periph_AWADDR; + assign M00_AXI_awprot[2:0] = m00_couplers_to_ps7_0_axi_periph_AWPROT; + assign M00_AXI_awvalid[0] = m00_couplers_to_ps7_0_axi_periph_AWVALID; + assign M00_AXI_bready[0] = m00_couplers_to_ps7_0_axi_periph_BREADY; + assign M00_AXI_rready[0] = m00_couplers_to_ps7_0_axi_periph_RREADY; + assign M00_AXI_wdata[31:0] = m00_couplers_to_ps7_0_axi_periph_WDATA; + assign M00_AXI_wstrb[3:0] = m00_couplers_to_ps7_0_axi_periph_WSTRB; + assign M00_AXI_wvalid[0] = m00_couplers_to_ps7_0_axi_periph_WVALID; + assign M01_AXI_araddr[31:0] = m01_couplers_to_ps7_0_axi_periph_ARADDR; + assign M01_AXI_arprot[2:0] = m01_couplers_to_ps7_0_axi_periph_ARPROT; + assign M01_AXI_arvalid[0] = m01_couplers_to_ps7_0_axi_periph_ARVALID; + assign M01_AXI_awaddr[31:0] = m01_couplers_to_ps7_0_axi_periph_AWADDR; + assign M01_AXI_awprot[2:0] = m01_couplers_to_ps7_0_axi_periph_AWPROT; + assign M01_AXI_awvalid[0] = m01_couplers_to_ps7_0_axi_periph_AWVALID; + assign M01_AXI_bready[0] = m01_couplers_to_ps7_0_axi_periph_BREADY; + assign M01_AXI_rready[0] = m01_couplers_to_ps7_0_axi_periph_RREADY; + assign M01_AXI_wdata[31:0] = m01_couplers_to_ps7_0_axi_periph_WDATA; + assign M01_AXI_wstrb[3:0] = m01_couplers_to_ps7_0_axi_periph_WSTRB; + assign M01_AXI_wvalid[0] = m01_couplers_to_ps7_0_axi_periph_WVALID; + assign M02_AXI_araddr[31:0] = m02_couplers_to_ps7_0_axi_periph_ARADDR; + assign M02_AXI_arprot[2:0] = m02_couplers_to_ps7_0_axi_periph_ARPROT; + assign M02_AXI_arvalid[0] = m02_couplers_to_ps7_0_axi_periph_ARVALID; + assign M02_AXI_awaddr[31:0] = m02_couplers_to_ps7_0_axi_periph_AWADDR; + assign M02_AXI_awprot[2:0] = m02_couplers_to_ps7_0_axi_periph_AWPROT; + assign M02_AXI_awvalid[0] = m02_couplers_to_ps7_0_axi_periph_AWVALID; + assign M02_AXI_bready[0] = m02_couplers_to_ps7_0_axi_periph_BREADY; + assign M02_AXI_rready[0] = m02_couplers_to_ps7_0_axi_periph_RREADY; + assign M02_AXI_wdata[31:0] = m02_couplers_to_ps7_0_axi_periph_WDATA; + assign M02_AXI_wstrb[3:0] = m02_couplers_to_ps7_0_axi_periph_WSTRB; + assign M02_AXI_wvalid[0] = m02_couplers_to_ps7_0_axi_periph_WVALID; + assign S00_AXI_arready = ps7_0_axi_periph_to_s00_couplers_ARREADY; + assign S00_AXI_awready = ps7_0_axi_periph_to_s00_couplers_AWREADY; + assign S00_AXI_bid[11:0] = ps7_0_axi_periph_to_s00_couplers_BID; + assign S00_AXI_bresp[1:0] = ps7_0_axi_periph_to_s00_couplers_BRESP; + assign S00_AXI_bvalid = ps7_0_axi_periph_to_s00_couplers_BVALID; + assign S00_AXI_rdata[31:0] = ps7_0_axi_periph_to_s00_couplers_RDATA; + assign S00_AXI_rid[11:0] = ps7_0_axi_periph_to_s00_couplers_RID; + assign S00_AXI_rlast = ps7_0_axi_periph_to_s00_couplers_RLAST; + assign S00_AXI_rresp[1:0] = ps7_0_axi_periph_to_s00_couplers_RRESP; + assign S00_AXI_rvalid = ps7_0_axi_periph_to_s00_couplers_RVALID; + assign S00_AXI_wready = ps7_0_axi_periph_to_s00_couplers_WREADY; + assign m00_couplers_to_ps7_0_axi_periph_ARREADY = M00_AXI_arready[0]; + assign m00_couplers_to_ps7_0_axi_periph_AWREADY = M00_AXI_awready[0]; + assign m00_couplers_to_ps7_0_axi_periph_BRESP = M00_AXI_bresp[1:0]; + assign m00_couplers_to_ps7_0_axi_periph_BVALID = M00_AXI_bvalid[0]; + assign m00_couplers_to_ps7_0_axi_periph_RDATA = M00_AXI_rdata[31:0]; + assign m00_couplers_to_ps7_0_axi_periph_RRESP = M00_AXI_rresp[1:0]; + assign m00_couplers_to_ps7_0_axi_periph_RVALID = M00_AXI_rvalid[0]; + assign m00_couplers_to_ps7_0_axi_periph_WREADY = M00_AXI_wready[0]; + assign m01_couplers_to_ps7_0_axi_periph_ARREADY = M01_AXI_arready[0]; + assign m01_couplers_to_ps7_0_axi_periph_AWREADY = M01_AXI_awready[0]; + assign m01_couplers_to_ps7_0_axi_periph_BRESP = M01_AXI_bresp[1:0]; + assign m01_couplers_to_ps7_0_axi_periph_BVALID = M01_AXI_bvalid[0]; + assign m01_couplers_to_ps7_0_axi_periph_RDATA = M01_AXI_rdata[31:0]; + assign m01_couplers_to_ps7_0_axi_periph_RRESP = M01_AXI_rresp[1:0]; + assign m01_couplers_to_ps7_0_axi_periph_RVALID = M01_AXI_rvalid[0]; + assign m01_couplers_to_ps7_0_axi_periph_WREADY = M01_AXI_wready[0]; + assign m02_couplers_to_ps7_0_axi_periph_ARREADY = M02_AXI_arready[0]; + assign m02_couplers_to_ps7_0_axi_periph_AWREADY = M02_AXI_awready[0]; + assign m02_couplers_to_ps7_0_axi_periph_BRESP = M02_AXI_bresp[1:0]; + assign m02_couplers_to_ps7_0_axi_periph_BVALID = M02_AXI_bvalid[0]; + assign m02_couplers_to_ps7_0_axi_periph_RDATA = M02_AXI_rdata[31:0]; + assign m02_couplers_to_ps7_0_axi_periph_RRESP = M02_AXI_rresp[1:0]; + assign m02_couplers_to_ps7_0_axi_periph_RVALID = M02_AXI_rvalid[0]; + assign m02_couplers_to_ps7_0_axi_periph_WREADY = M02_AXI_wready[0]; + assign ps7_0_axi_periph_ACLK_net = ACLK; + assign ps7_0_axi_periph_ARESETN_net = ARESETN; + assign ps7_0_axi_periph_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0]; + assign ps7_0_axi_periph_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0]; + assign ps7_0_axi_periph_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0]; + assign ps7_0_axi_periph_to_s00_couplers_ARID = S00_AXI_arid[11:0]; + assign ps7_0_axi_periph_to_s00_couplers_ARLEN = S00_AXI_arlen[3:0]; + assign ps7_0_axi_periph_to_s00_couplers_ARLOCK = S00_AXI_arlock[1:0]; + assign ps7_0_axi_periph_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0]; + assign ps7_0_axi_periph_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0]; + assign ps7_0_axi_periph_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0]; + assign ps7_0_axi_periph_to_s00_couplers_ARVALID = S00_AXI_arvalid; + assign ps7_0_axi_periph_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0]; + assign ps7_0_axi_periph_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0]; + assign ps7_0_axi_periph_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0]; + assign ps7_0_axi_periph_to_s00_couplers_AWID = S00_AXI_awid[11:0]; + assign ps7_0_axi_periph_to_s00_couplers_AWLEN = S00_AXI_awlen[3:0]; + assign ps7_0_axi_periph_to_s00_couplers_AWLOCK = S00_AXI_awlock[1:0]; + assign ps7_0_axi_periph_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0]; + assign ps7_0_axi_periph_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0]; + assign ps7_0_axi_periph_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0]; + assign ps7_0_axi_periph_to_s00_couplers_AWVALID = S00_AXI_awvalid; + assign ps7_0_axi_periph_to_s00_couplers_BREADY = S00_AXI_bready; + assign ps7_0_axi_periph_to_s00_couplers_RREADY = S00_AXI_rready; + assign ps7_0_axi_periph_to_s00_couplers_WDATA = S00_AXI_wdata[31:0]; + assign ps7_0_axi_periph_to_s00_couplers_WID = S00_AXI_wid[11:0]; + assign ps7_0_axi_periph_to_s00_couplers_WLAST = S00_AXI_wlast; + assign ps7_0_axi_periph_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0]; + assign ps7_0_axi_periph_to_s00_couplers_WVALID = S00_AXI_wvalid; + m00_couplers_imp_IFHBBD m00_couplers + (.M_ACLK(ps7_0_axi_periph_ACLK_net), + .M_ARESETN(ps7_0_axi_periph_ARESETN_net), + .M_AXI_araddr(m00_couplers_to_ps7_0_axi_periph_ARADDR), + .M_AXI_arprot(m00_couplers_to_ps7_0_axi_periph_ARPROT), + .M_AXI_arready(m00_couplers_to_ps7_0_axi_periph_ARREADY), + .M_AXI_arvalid(m00_couplers_to_ps7_0_axi_periph_ARVALID), + .M_AXI_awaddr(m00_couplers_to_ps7_0_axi_periph_AWADDR), + .M_AXI_awprot(m00_couplers_to_ps7_0_axi_periph_AWPROT), + .M_AXI_awready(m00_couplers_to_ps7_0_axi_periph_AWREADY), + .M_AXI_awvalid(m00_couplers_to_ps7_0_axi_periph_AWVALID), + .M_AXI_bready(m00_couplers_to_ps7_0_axi_periph_BREADY), + .M_AXI_bresp(m00_couplers_to_ps7_0_axi_periph_BRESP), + .M_AXI_bvalid(m00_couplers_to_ps7_0_axi_periph_BVALID), + .M_AXI_rdata(m00_couplers_to_ps7_0_axi_periph_RDATA), + .M_AXI_rready(m00_couplers_to_ps7_0_axi_periph_RREADY), + .M_AXI_rresp(m00_couplers_to_ps7_0_axi_periph_RRESP), + .M_AXI_rvalid(m00_couplers_to_ps7_0_axi_periph_RVALID), + .M_AXI_wdata(m00_couplers_to_ps7_0_axi_periph_WDATA), + .M_AXI_wready(m00_couplers_to_ps7_0_axi_periph_WREADY), + .M_AXI_wstrb(m00_couplers_to_ps7_0_axi_periph_WSTRB), + .M_AXI_wvalid(m00_couplers_to_ps7_0_axi_periph_WVALID), + .S_ACLK(ps7_0_axi_periph_ACLK_net), + .S_ARESETN(ps7_0_axi_periph_ARESETN_net), + .S_AXI_araddr(xbar_to_m00_couplers_ARADDR), + .S_AXI_arprot(xbar_to_m00_couplers_ARPROT), + .S_AXI_arready(xbar_to_m00_couplers_ARREADY), + .S_AXI_arvalid(xbar_to_m00_couplers_ARVALID), + .S_AXI_awaddr(xbar_to_m00_couplers_AWADDR), + .S_AXI_awprot(xbar_to_m00_couplers_AWPROT), + .S_AXI_awready(xbar_to_m00_couplers_AWREADY), + .S_AXI_awvalid(xbar_to_m00_couplers_AWVALID), + .S_AXI_bready(xbar_to_m00_couplers_BREADY), + .S_AXI_bresp(xbar_to_m00_couplers_BRESP), + .S_AXI_bvalid(xbar_to_m00_couplers_BVALID), + .S_AXI_rdata(xbar_to_m00_couplers_RDATA), + .S_AXI_rready(xbar_to_m00_couplers_RREADY), + .S_AXI_rresp(xbar_to_m00_couplers_RRESP), + .S_AXI_rvalid(xbar_to_m00_couplers_RVALID), + .S_AXI_wdata(xbar_to_m00_couplers_WDATA), + .S_AXI_wready(xbar_to_m00_couplers_WREADY), + .S_AXI_wstrb(xbar_to_m00_couplers_WSTRB), + .S_AXI_wvalid(xbar_to_m00_couplers_WVALID)); + m01_couplers_imp_1I6NMI6 m01_couplers + (.M_ACLK(ps7_0_axi_periph_ACLK_net), + .M_ARESETN(ps7_0_axi_periph_ARESETN_net), + .M_AXI_araddr(m01_couplers_to_ps7_0_axi_periph_ARADDR), + .M_AXI_arprot(m01_couplers_to_ps7_0_axi_periph_ARPROT), + .M_AXI_arready(m01_couplers_to_ps7_0_axi_periph_ARREADY), + .M_AXI_arvalid(m01_couplers_to_ps7_0_axi_periph_ARVALID), + .M_AXI_awaddr(m01_couplers_to_ps7_0_axi_periph_AWADDR), + .M_AXI_awprot(m01_couplers_to_ps7_0_axi_periph_AWPROT), + .M_AXI_awready(m01_couplers_to_ps7_0_axi_periph_AWREADY), + .M_AXI_awvalid(m01_couplers_to_ps7_0_axi_periph_AWVALID), + .M_AXI_bready(m01_couplers_to_ps7_0_axi_periph_BREADY), + .M_AXI_bresp(m01_couplers_to_ps7_0_axi_periph_BRESP), + .M_AXI_bvalid(m01_couplers_to_ps7_0_axi_periph_BVALID), + .M_AXI_rdata(m01_couplers_to_ps7_0_axi_periph_RDATA), + .M_AXI_rready(m01_couplers_to_ps7_0_axi_periph_RREADY), + .M_AXI_rresp(m01_couplers_to_ps7_0_axi_periph_RRESP), + .M_AXI_rvalid(m01_couplers_to_ps7_0_axi_periph_RVALID), + .M_AXI_wdata(m01_couplers_to_ps7_0_axi_periph_WDATA), + .M_AXI_wready(m01_couplers_to_ps7_0_axi_periph_WREADY), + .M_AXI_wstrb(m01_couplers_to_ps7_0_axi_periph_WSTRB), + .M_AXI_wvalid(m01_couplers_to_ps7_0_axi_periph_WVALID), + .S_ACLK(ps7_0_axi_periph_ACLK_net), + .S_ARESETN(ps7_0_axi_periph_ARESETN_net), + .S_AXI_araddr(xbar_to_m01_couplers_ARADDR), + .S_AXI_arprot(xbar_to_m01_couplers_ARPROT), + .S_AXI_arready(xbar_to_m01_couplers_ARREADY), + .S_AXI_arvalid(xbar_to_m01_couplers_ARVALID), + .S_AXI_awaddr(xbar_to_m01_couplers_AWADDR), + .S_AXI_awprot(xbar_to_m01_couplers_AWPROT), + .S_AXI_awready(xbar_to_m01_couplers_AWREADY), + .S_AXI_awvalid(xbar_to_m01_couplers_AWVALID), + .S_AXI_bready(xbar_to_m01_couplers_BREADY), + .S_AXI_bresp(xbar_to_m01_couplers_BRESP), + .S_AXI_bvalid(xbar_to_m01_couplers_BVALID), + .S_AXI_rdata(xbar_to_m01_couplers_RDATA), + .S_AXI_rready(xbar_to_m01_couplers_RREADY), + .S_AXI_rresp(xbar_to_m01_couplers_RRESP), + .S_AXI_rvalid(xbar_to_m01_couplers_RVALID), + .S_AXI_wdata(xbar_to_m01_couplers_WDATA), + .S_AXI_wready(xbar_to_m01_couplers_WREADY), + .S_AXI_wstrb(xbar_to_m01_couplers_WSTRB), + .S_AXI_wvalid(xbar_to_m01_couplers_WVALID)); + m02_couplers_imp_173O0AU m02_couplers + (.M_ACLK(ps7_0_axi_periph_ACLK_net), + .M_ARESETN(ps7_0_axi_periph_ARESETN_net), + .M_AXI_araddr(m02_couplers_to_ps7_0_axi_periph_ARADDR), + .M_AXI_arprot(m02_couplers_to_ps7_0_axi_periph_ARPROT), + .M_AXI_arready(m02_couplers_to_ps7_0_axi_periph_ARREADY), + .M_AXI_arvalid(m02_couplers_to_ps7_0_axi_periph_ARVALID), + .M_AXI_awaddr(m02_couplers_to_ps7_0_axi_periph_AWADDR), + .M_AXI_awprot(m02_couplers_to_ps7_0_axi_periph_AWPROT), + .M_AXI_awready(m02_couplers_to_ps7_0_axi_periph_AWREADY), + .M_AXI_awvalid(m02_couplers_to_ps7_0_axi_periph_AWVALID), + .M_AXI_bready(m02_couplers_to_ps7_0_axi_periph_BREADY), + .M_AXI_bresp(m02_couplers_to_ps7_0_axi_periph_BRESP), + .M_AXI_bvalid(m02_couplers_to_ps7_0_axi_periph_BVALID), + .M_AXI_rdata(m02_couplers_to_ps7_0_axi_periph_RDATA), + .M_AXI_rready(m02_couplers_to_ps7_0_axi_periph_RREADY), + .M_AXI_rresp(m02_couplers_to_ps7_0_axi_periph_RRESP), + .M_AXI_rvalid(m02_couplers_to_ps7_0_axi_periph_RVALID), + .M_AXI_wdata(m02_couplers_to_ps7_0_axi_periph_WDATA), + .M_AXI_wready(m02_couplers_to_ps7_0_axi_periph_WREADY), + .M_AXI_wstrb(m02_couplers_to_ps7_0_axi_periph_WSTRB), + .M_AXI_wvalid(m02_couplers_to_ps7_0_axi_periph_WVALID), + .S_ACLK(ps7_0_axi_periph_ACLK_net), + .S_ARESETN(ps7_0_axi_periph_ARESETN_net), + .S_AXI_araddr(xbar_to_m02_couplers_ARADDR), + .S_AXI_arprot(xbar_to_m02_couplers_ARPROT), + .S_AXI_arready(xbar_to_m02_couplers_ARREADY), + .S_AXI_arvalid(xbar_to_m02_couplers_ARVALID), + .S_AXI_awaddr(xbar_to_m02_couplers_AWADDR), + .S_AXI_awprot(xbar_to_m02_couplers_AWPROT), + .S_AXI_awready(xbar_to_m02_couplers_AWREADY), + .S_AXI_awvalid(xbar_to_m02_couplers_AWVALID), + .S_AXI_bready(xbar_to_m02_couplers_BREADY), + .S_AXI_bresp(xbar_to_m02_couplers_BRESP), + .S_AXI_bvalid(xbar_to_m02_couplers_BVALID), + .S_AXI_rdata(xbar_to_m02_couplers_RDATA), + .S_AXI_rready(xbar_to_m02_couplers_RREADY), + .S_AXI_rresp(xbar_to_m02_couplers_RRESP), + .S_AXI_rvalid(xbar_to_m02_couplers_RVALID), + .S_AXI_wdata(xbar_to_m02_couplers_WDATA), + .S_AXI_wready(xbar_to_m02_couplers_WREADY), + .S_AXI_wstrb(xbar_to_m02_couplers_WSTRB), + .S_AXI_wvalid(xbar_to_m02_couplers_WVALID)); + s00_couplers_imp_10AESJG s00_couplers + (.M_ACLK(ps7_0_axi_periph_ACLK_net), + .M_ARESETN(ps7_0_axi_periph_ARESETN_net), + .M_AXI_araddr(s00_couplers_to_xbar_ARADDR), + .M_AXI_arprot(s00_couplers_to_xbar_ARPROT), + .M_AXI_arready(s00_couplers_to_xbar_ARREADY), + .M_AXI_arvalid(s00_couplers_to_xbar_ARVALID), + .M_AXI_awaddr(s00_couplers_to_xbar_AWADDR), + .M_AXI_awprot(s00_couplers_to_xbar_AWPROT), + .M_AXI_awready(s00_couplers_to_xbar_AWREADY), + .M_AXI_awvalid(s00_couplers_to_xbar_AWVALID), + .M_AXI_bready(s00_couplers_to_xbar_BREADY), + .M_AXI_bresp(s00_couplers_to_xbar_BRESP), + .M_AXI_bvalid(s00_couplers_to_xbar_BVALID), + .M_AXI_rdata(s00_couplers_to_xbar_RDATA), + .M_AXI_rready(s00_couplers_to_xbar_RREADY), + .M_AXI_rresp(s00_couplers_to_xbar_RRESP), + .M_AXI_rvalid(s00_couplers_to_xbar_RVALID), + .M_AXI_wdata(s00_couplers_to_xbar_WDATA), + .M_AXI_wready(s00_couplers_to_xbar_WREADY), + .M_AXI_wstrb(s00_couplers_to_xbar_WSTRB), + .M_AXI_wvalid(s00_couplers_to_xbar_WVALID), + .S_ACLK(ps7_0_axi_periph_ACLK_net), + .S_ARESETN(ps7_0_axi_periph_ARESETN_net), + .S_AXI_araddr(ps7_0_axi_periph_to_s00_couplers_ARADDR), + .S_AXI_arburst(ps7_0_axi_periph_to_s00_couplers_ARBURST), + .S_AXI_arcache(ps7_0_axi_periph_to_s00_couplers_ARCACHE), + .S_AXI_arid(ps7_0_axi_periph_to_s00_couplers_ARID), + .S_AXI_arlen(ps7_0_axi_periph_to_s00_couplers_ARLEN), + .S_AXI_arlock(ps7_0_axi_periph_to_s00_couplers_ARLOCK), + .S_AXI_arprot(ps7_0_axi_periph_to_s00_couplers_ARPROT), + .S_AXI_arqos(ps7_0_axi_periph_to_s00_couplers_ARQOS), + .S_AXI_arready(ps7_0_axi_periph_to_s00_couplers_ARREADY), + .S_AXI_arsize(ps7_0_axi_periph_to_s00_couplers_ARSIZE), + .S_AXI_arvalid(ps7_0_axi_periph_to_s00_couplers_ARVALID), + .S_AXI_awaddr(ps7_0_axi_periph_to_s00_couplers_AWADDR), + .S_AXI_awburst(ps7_0_axi_periph_to_s00_couplers_AWBURST), + .S_AXI_awcache(ps7_0_axi_periph_to_s00_couplers_AWCACHE), + .S_AXI_awid(ps7_0_axi_periph_to_s00_couplers_AWID), + .S_AXI_awlen(ps7_0_axi_periph_to_s00_couplers_AWLEN), + .S_AXI_awlock(ps7_0_axi_periph_to_s00_couplers_AWLOCK), + .S_AXI_awprot(ps7_0_axi_periph_to_s00_couplers_AWPROT), + .S_AXI_awqos(ps7_0_axi_periph_to_s00_couplers_AWQOS), + .S_AXI_awready(ps7_0_axi_periph_to_s00_couplers_AWREADY), + .S_AXI_awsize(ps7_0_axi_periph_to_s00_couplers_AWSIZE), + .S_AXI_awvalid(ps7_0_axi_periph_to_s00_couplers_AWVALID), + .S_AXI_bid(ps7_0_axi_periph_to_s00_couplers_BID), + .S_AXI_bready(ps7_0_axi_periph_to_s00_couplers_BREADY), + .S_AXI_bresp(ps7_0_axi_periph_to_s00_couplers_BRESP), + .S_AXI_bvalid(ps7_0_axi_periph_to_s00_couplers_BVALID), + .S_AXI_rdata(ps7_0_axi_periph_to_s00_couplers_RDATA), + .S_AXI_rid(ps7_0_axi_periph_to_s00_couplers_RID), + .S_AXI_rlast(ps7_0_axi_periph_to_s00_couplers_RLAST), + .S_AXI_rready(ps7_0_axi_periph_to_s00_couplers_RREADY), + .S_AXI_rresp(ps7_0_axi_periph_to_s00_couplers_RRESP), + .S_AXI_rvalid(ps7_0_axi_periph_to_s00_couplers_RVALID), + .S_AXI_wdata(ps7_0_axi_periph_to_s00_couplers_WDATA), + .S_AXI_wid(ps7_0_axi_periph_to_s00_couplers_WID), + .S_AXI_wlast(ps7_0_axi_periph_to_s00_couplers_WLAST), + .S_AXI_wready(ps7_0_axi_periph_to_s00_couplers_WREADY), + .S_AXI_wstrb(ps7_0_axi_periph_to_s00_couplers_WSTRB), + .S_AXI_wvalid(ps7_0_axi_periph_to_s00_couplers_WVALID)); + NewExtInst_TOP_xbar_0 xbar + (.aclk(ps7_0_axi_periph_ACLK_net), + .aresetn(ps7_0_axi_periph_ARESETN_net), + .m_axi_araddr({xbar_to_m02_couplers_ARADDR,xbar_to_m01_couplers_ARADDR,xbar_to_m00_couplers_ARADDR}), + .m_axi_arprot({xbar_to_m02_couplers_ARPROT,xbar_to_m01_couplers_ARPROT,xbar_to_m00_couplers_ARPROT}), + .m_axi_arready({xbar_to_m02_couplers_ARREADY,xbar_to_m01_couplers_ARREADY,xbar_to_m00_couplers_ARREADY}), + .m_axi_arvalid({xbar_to_m02_couplers_ARVALID,xbar_to_m01_couplers_ARVALID,xbar_to_m00_couplers_ARVALID}), + .m_axi_awaddr({xbar_to_m02_couplers_AWADDR,xbar_to_m01_couplers_AWADDR,xbar_to_m00_couplers_AWADDR}), + .m_axi_awprot({xbar_to_m02_couplers_AWPROT,xbar_to_m01_couplers_AWPROT,xbar_to_m00_couplers_AWPROT}), + .m_axi_awready({xbar_to_m02_couplers_AWREADY,xbar_to_m01_couplers_AWREADY,xbar_to_m00_couplers_AWREADY}), + .m_axi_awvalid({xbar_to_m02_couplers_AWVALID,xbar_to_m01_couplers_AWVALID,xbar_to_m00_couplers_AWVALID}), + .m_axi_bready({xbar_to_m02_couplers_BREADY,xbar_to_m01_couplers_BREADY,xbar_to_m00_couplers_BREADY}), + .m_axi_bresp({xbar_to_m02_couplers_BRESP,xbar_to_m01_couplers_BRESP,xbar_to_m00_couplers_BRESP}), + .m_axi_bvalid({xbar_to_m02_couplers_BVALID,xbar_to_m01_couplers_BVALID,xbar_to_m00_couplers_BVALID}), + .m_axi_rdata({xbar_to_m02_couplers_RDATA,xbar_to_m01_couplers_RDATA,xbar_to_m00_couplers_RDATA}), + .m_axi_rready({xbar_to_m02_couplers_RREADY,xbar_to_m01_couplers_RREADY,xbar_to_m00_couplers_RREADY}), + .m_axi_rresp({xbar_to_m02_couplers_RRESP,xbar_to_m01_couplers_RRESP,xbar_to_m00_couplers_RRESP}), + .m_axi_rvalid({xbar_to_m02_couplers_RVALID,xbar_to_m01_couplers_RVALID,xbar_to_m00_couplers_RVALID}), + .m_axi_wdata({xbar_to_m02_couplers_WDATA,xbar_to_m01_couplers_WDATA,xbar_to_m00_couplers_WDATA}), + .m_axi_wready({xbar_to_m02_couplers_WREADY,xbar_to_m01_couplers_WREADY,xbar_to_m00_couplers_WREADY}), + .m_axi_wstrb({xbar_to_m02_couplers_WSTRB,xbar_to_m01_couplers_WSTRB,xbar_to_m00_couplers_WSTRB}), + .m_axi_wvalid({xbar_to_m02_couplers_WVALID,xbar_to_m01_couplers_WVALID,xbar_to_m00_couplers_WVALID}), + .s_axi_araddr(s00_couplers_to_xbar_ARADDR), + .s_axi_arprot(s00_couplers_to_xbar_ARPROT), + .s_axi_arready(s00_couplers_to_xbar_ARREADY), + .s_axi_arvalid(s00_couplers_to_xbar_ARVALID), + .s_axi_awaddr(s00_couplers_to_xbar_AWADDR), + .s_axi_awprot(s00_couplers_to_xbar_AWPROT), + .s_axi_awready(s00_couplers_to_xbar_AWREADY), + .s_axi_awvalid(s00_couplers_to_xbar_AWVALID), + .s_axi_bready(s00_couplers_to_xbar_BREADY), + .s_axi_bresp(s00_couplers_to_xbar_BRESP), + .s_axi_bvalid(s00_couplers_to_xbar_BVALID), + .s_axi_rdata(s00_couplers_to_xbar_RDATA), + .s_axi_rready(s00_couplers_to_xbar_RREADY), + .s_axi_rresp(s00_couplers_to_xbar_RRESP), + .s_axi_rvalid(s00_couplers_to_xbar_RVALID), + .s_axi_wdata(s00_couplers_to_xbar_WDATA), + .s_axi_wready(s00_couplers_to_xbar_WREADY), + .s_axi_wstrb(s00_couplers_to_xbar_WSTRB), + .s_axi_wvalid(s00_couplers_to_xbar_WVALID)); +endmodule + +module m00_couplers_imp_IFHBBD + (M_ACLK, + M_ARESETN, + M_AXI_araddr, + M_AXI_arprot, + M_AXI_arready, + M_AXI_arvalid, + M_AXI_awaddr, + M_AXI_awprot, + M_AXI_awready, + M_AXI_awvalid, + M_AXI_bready, + M_AXI_bresp, + M_AXI_bvalid, + M_AXI_rdata, + M_AXI_rready, + M_AXI_rresp, + M_AXI_rvalid, + M_AXI_wdata, + M_AXI_wready, + M_AXI_wstrb, + M_AXI_wvalid, + S_ACLK, + S_ARESETN, + S_AXI_araddr, + S_AXI_arprot, + S_AXI_arready, + S_AXI_arvalid, + S_AXI_awaddr, + S_AXI_awprot, + S_AXI_awready, + S_AXI_awvalid, + S_AXI_bready, + S_AXI_bresp, + S_AXI_bvalid, + S_AXI_rdata, + S_AXI_rready, + S_AXI_rresp, + S_AXI_rvalid, + S_AXI_wdata, + S_AXI_wready, + S_AXI_wstrb, + S_AXI_wvalid); + input M_ACLK; + input M_ARESETN; + output [31:0]M_AXI_araddr; + output [2:0]M_AXI_arprot; + input [0:0]M_AXI_arready; + output [0:0]M_AXI_arvalid; + output [31:0]M_AXI_awaddr; + output [2:0]M_AXI_awprot; + input [0:0]M_AXI_awready; + output [0:0]M_AXI_awvalid; + output [0:0]M_AXI_bready; + input [1:0]M_AXI_bresp; + input [0:0]M_AXI_bvalid; + input [31:0]M_AXI_rdata; + output [0:0]M_AXI_rready; + input [1:0]M_AXI_rresp; + input [0:0]M_AXI_rvalid; + output [31:0]M_AXI_wdata; + input [0:0]M_AXI_wready; + output [3:0]M_AXI_wstrb; + output [0:0]M_AXI_wvalid; + input S_ACLK; + input S_ARESETN; + input [31:0]S_AXI_araddr; + input [2:0]S_AXI_arprot; + output [0:0]S_AXI_arready; + input [0:0]S_AXI_arvalid; + input [31:0]S_AXI_awaddr; + input [2:0]S_AXI_awprot; + output [0:0]S_AXI_awready; + input [0:0]S_AXI_awvalid; + input [0:0]S_AXI_bready; + output [1:0]S_AXI_bresp; + output [0:0]S_AXI_bvalid; + output [31:0]S_AXI_rdata; + input [0:0]S_AXI_rready; + output [1:0]S_AXI_rresp; + output [0:0]S_AXI_rvalid; + input [31:0]S_AXI_wdata; + output [0:0]S_AXI_wready; + input [3:0]S_AXI_wstrb; + input [0:0]S_AXI_wvalid; + + wire [31:0]m00_couplers_to_m00_couplers_ARADDR; + wire [2:0]m00_couplers_to_m00_couplers_ARPROT; + wire [0:0]m00_couplers_to_m00_couplers_ARREADY; + wire [0:0]m00_couplers_to_m00_couplers_ARVALID; + wire [31:0]m00_couplers_to_m00_couplers_AWADDR; + wire [2:0]m00_couplers_to_m00_couplers_AWPROT; + wire [0:0]m00_couplers_to_m00_couplers_AWREADY; + wire [0:0]m00_couplers_to_m00_couplers_AWVALID; + wire [0:0]m00_couplers_to_m00_couplers_BREADY; + wire [1:0]m00_couplers_to_m00_couplers_BRESP; + wire [0:0]m00_couplers_to_m00_couplers_BVALID; + wire [31:0]m00_couplers_to_m00_couplers_RDATA; + wire [0:0]m00_couplers_to_m00_couplers_RREADY; + wire [1:0]m00_couplers_to_m00_couplers_RRESP; + wire [0:0]m00_couplers_to_m00_couplers_RVALID; + wire [31:0]m00_couplers_to_m00_couplers_WDATA; + wire [0:0]m00_couplers_to_m00_couplers_WREADY; + wire [3:0]m00_couplers_to_m00_couplers_WSTRB; + wire [0:0]m00_couplers_to_m00_couplers_WVALID; + + assign M_AXI_araddr[31:0] = m00_couplers_to_m00_couplers_ARADDR; + assign M_AXI_arprot[2:0] = m00_couplers_to_m00_couplers_ARPROT; + assign M_AXI_arvalid[0] = m00_couplers_to_m00_couplers_ARVALID; + assign M_AXI_awaddr[31:0] = m00_couplers_to_m00_couplers_AWADDR; + assign M_AXI_awprot[2:0] = m00_couplers_to_m00_couplers_AWPROT; + assign M_AXI_awvalid[0] = m00_couplers_to_m00_couplers_AWVALID; + assign M_AXI_bready[0] = m00_couplers_to_m00_couplers_BREADY; + assign M_AXI_rready[0] = m00_couplers_to_m00_couplers_RREADY; + assign M_AXI_wdata[31:0] = m00_couplers_to_m00_couplers_WDATA; + assign M_AXI_wstrb[3:0] = m00_couplers_to_m00_couplers_WSTRB; + assign M_AXI_wvalid[0] = m00_couplers_to_m00_couplers_WVALID; + assign S_AXI_arready[0] = m00_couplers_to_m00_couplers_ARREADY; + assign S_AXI_awready[0] = m00_couplers_to_m00_couplers_AWREADY; + assign S_AXI_bresp[1:0] = m00_couplers_to_m00_couplers_BRESP; + assign S_AXI_bvalid[0] = m00_couplers_to_m00_couplers_BVALID; + assign S_AXI_rdata[31:0] = m00_couplers_to_m00_couplers_RDATA; + assign S_AXI_rresp[1:0] = m00_couplers_to_m00_couplers_RRESP; + assign S_AXI_rvalid[0] = m00_couplers_to_m00_couplers_RVALID; + assign S_AXI_wready[0] = m00_couplers_to_m00_couplers_WREADY; + assign m00_couplers_to_m00_couplers_ARADDR = S_AXI_araddr[31:0]; + assign m00_couplers_to_m00_couplers_ARPROT = S_AXI_arprot[2:0]; + assign m00_couplers_to_m00_couplers_ARREADY = M_AXI_arready[0]; + assign m00_couplers_to_m00_couplers_ARVALID = S_AXI_arvalid[0]; + assign m00_couplers_to_m00_couplers_AWADDR = S_AXI_awaddr[31:0]; + assign m00_couplers_to_m00_couplers_AWPROT = S_AXI_awprot[2:0]; + assign m00_couplers_to_m00_couplers_AWREADY = M_AXI_awready[0]; + assign m00_couplers_to_m00_couplers_AWVALID = S_AXI_awvalid[0]; + assign m00_couplers_to_m00_couplers_BREADY = S_AXI_bready[0]; + assign m00_couplers_to_m00_couplers_BRESP = M_AXI_bresp[1:0]; + assign m00_couplers_to_m00_couplers_BVALID = M_AXI_bvalid[0]; + assign m00_couplers_to_m00_couplers_RDATA = M_AXI_rdata[31:0]; + assign m00_couplers_to_m00_couplers_RREADY = S_AXI_rready[0]; + assign m00_couplers_to_m00_couplers_RRESP = M_AXI_rresp[1:0]; + assign m00_couplers_to_m00_couplers_RVALID = M_AXI_rvalid[0]; + assign m00_couplers_to_m00_couplers_WDATA = S_AXI_wdata[31:0]; + assign m00_couplers_to_m00_couplers_WREADY = M_AXI_wready[0]; + assign m00_couplers_to_m00_couplers_WSTRB = S_AXI_wstrb[3:0]; + assign m00_couplers_to_m00_couplers_WVALID = S_AXI_wvalid[0]; +endmodule + +module m01_couplers_imp_1I6NMI6 + (M_ACLK, + M_ARESETN, + M_AXI_araddr, + M_AXI_arprot, + M_AXI_arready, + M_AXI_arvalid, + M_AXI_awaddr, + M_AXI_awprot, + M_AXI_awready, + M_AXI_awvalid, + M_AXI_bready, + M_AXI_bresp, + M_AXI_bvalid, + M_AXI_rdata, + M_AXI_rready, + M_AXI_rresp, + M_AXI_rvalid, + M_AXI_wdata, + M_AXI_wready, + M_AXI_wstrb, + M_AXI_wvalid, + S_ACLK, + S_ARESETN, + S_AXI_araddr, + S_AXI_arprot, + S_AXI_arready, + S_AXI_arvalid, + S_AXI_awaddr, + S_AXI_awprot, + S_AXI_awready, + S_AXI_awvalid, + S_AXI_bready, + S_AXI_bresp, + S_AXI_bvalid, + S_AXI_rdata, + S_AXI_rready, + S_AXI_rresp, + S_AXI_rvalid, + S_AXI_wdata, + S_AXI_wready, + S_AXI_wstrb, + S_AXI_wvalid); + input M_ACLK; + input M_ARESETN; + output [31:0]M_AXI_araddr; + output [2:0]M_AXI_arprot; + input [0:0]M_AXI_arready; + output [0:0]M_AXI_arvalid; + output [31:0]M_AXI_awaddr; + output [2:0]M_AXI_awprot; + input [0:0]M_AXI_awready; + output [0:0]M_AXI_awvalid; + output [0:0]M_AXI_bready; + input [1:0]M_AXI_bresp; + input [0:0]M_AXI_bvalid; + input [31:0]M_AXI_rdata; + output [0:0]M_AXI_rready; + input [1:0]M_AXI_rresp; + input [0:0]M_AXI_rvalid; + output [31:0]M_AXI_wdata; + input [0:0]M_AXI_wready; + output [3:0]M_AXI_wstrb; + output [0:0]M_AXI_wvalid; + input S_ACLK; + input S_ARESETN; + input [31:0]S_AXI_araddr; + input [2:0]S_AXI_arprot; + output [0:0]S_AXI_arready; + input [0:0]S_AXI_arvalid; + input [31:0]S_AXI_awaddr; + input [2:0]S_AXI_awprot; + output [0:0]S_AXI_awready; + input [0:0]S_AXI_awvalid; + input [0:0]S_AXI_bready; + output [1:0]S_AXI_bresp; + output [0:0]S_AXI_bvalid; + output [31:0]S_AXI_rdata; + input [0:0]S_AXI_rready; + output [1:0]S_AXI_rresp; + output [0:0]S_AXI_rvalid; + input [31:0]S_AXI_wdata; + output [0:0]S_AXI_wready; + input [3:0]S_AXI_wstrb; + input [0:0]S_AXI_wvalid; + + wire [31:0]m01_couplers_to_m01_couplers_ARADDR; + wire [2:0]m01_couplers_to_m01_couplers_ARPROT; + wire [0:0]m01_couplers_to_m01_couplers_ARREADY; + wire [0:0]m01_couplers_to_m01_couplers_ARVALID; + wire [31:0]m01_couplers_to_m01_couplers_AWADDR; + wire [2:0]m01_couplers_to_m01_couplers_AWPROT; + wire [0:0]m01_couplers_to_m01_couplers_AWREADY; + wire [0:0]m01_couplers_to_m01_couplers_AWVALID; + wire [0:0]m01_couplers_to_m01_couplers_BREADY; + wire [1:0]m01_couplers_to_m01_couplers_BRESP; + wire [0:0]m01_couplers_to_m01_couplers_BVALID; + wire [31:0]m01_couplers_to_m01_couplers_RDATA; + wire [0:0]m01_couplers_to_m01_couplers_RREADY; + wire [1:0]m01_couplers_to_m01_couplers_RRESP; + wire [0:0]m01_couplers_to_m01_couplers_RVALID; + wire [31:0]m01_couplers_to_m01_couplers_WDATA; + wire [0:0]m01_couplers_to_m01_couplers_WREADY; + wire [3:0]m01_couplers_to_m01_couplers_WSTRB; + wire [0:0]m01_couplers_to_m01_couplers_WVALID; + + assign M_AXI_araddr[31:0] = m01_couplers_to_m01_couplers_ARADDR; + assign M_AXI_arprot[2:0] = m01_couplers_to_m01_couplers_ARPROT; + assign M_AXI_arvalid[0] = m01_couplers_to_m01_couplers_ARVALID; + assign M_AXI_awaddr[31:0] = m01_couplers_to_m01_couplers_AWADDR; + assign M_AXI_awprot[2:0] = m01_couplers_to_m01_couplers_AWPROT; + assign M_AXI_awvalid[0] = m01_couplers_to_m01_couplers_AWVALID; + assign M_AXI_bready[0] = m01_couplers_to_m01_couplers_BREADY; + assign M_AXI_rready[0] = m01_couplers_to_m01_couplers_RREADY; + assign M_AXI_wdata[31:0] = m01_couplers_to_m01_couplers_WDATA; + assign M_AXI_wstrb[3:0] = m01_couplers_to_m01_couplers_WSTRB; + assign M_AXI_wvalid[0] = m01_couplers_to_m01_couplers_WVALID; + assign S_AXI_arready[0] = m01_couplers_to_m01_couplers_ARREADY; + assign S_AXI_awready[0] = m01_couplers_to_m01_couplers_AWREADY; + assign S_AXI_bresp[1:0] = m01_couplers_to_m01_couplers_BRESP; + assign S_AXI_bvalid[0] = m01_couplers_to_m01_couplers_BVALID; + assign S_AXI_rdata[31:0] = m01_couplers_to_m01_couplers_RDATA; + assign S_AXI_rresp[1:0] = m01_couplers_to_m01_couplers_RRESP; + assign S_AXI_rvalid[0] = m01_couplers_to_m01_couplers_RVALID; + assign S_AXI_wready[0] = m01_couplers_to_m01_couplers_WREADY; + assign m01_couplers_to_m01_couplers_ARADDR = S_AXI_araddr[31:0]; + assign m01_couplers_to_m01_couplers_ARPROT = S_AXI_arprot[2:0]; + assign m01_couplers_to_m01_couplers_ARREADY = M_AXI_arready[0]; + assign m01_couplers_to_m01_couplers_ARVALID = S_AXI_arvalid[0]; + assign m01_couplers_to_m01_couplers_AWADDR = S_AXI_awaddr[31:0]; + assign m01_couplers_to_m01_couplers_AWPROT = S_AXI_awprot[2:0]; + assign m01_couplers_to_m01_couplers_AWREADY = M_AXI_awready[0]; + assign m01_couplers_to_m01_couplers_AWVALID = S_AXI_awvalid[0]; + assign m01_couplers_to_m01_couplers_BREADY = S_AXI_bready[0]; + assign m01_couplers_to_m01_couplers_BRESP = M_AXI_bresp[1:0]; + assign m01_couplers_to_m01_couplers_BVALID = M_AXI_bvalid[0]; + assign m01_couplers_to_m01_couplers_RDATA = M_AXI_rdata[31:0]; + assign m01_couplers_to_m01_couplers_RREADY = S_AXI_rready[0]; + assign m01_couplers_to_m01_couplers_RRESP = M_AXI_rresp[1:0]; + assign m01_couplers_to_m01_couplers_RVALID = M_AXI_rvalid[0]; + assign m01_couplers_to_m01_couplers_WDATA = S_AXI_wdata[31:0]; + assign m01_couplers_to_m01_couplers_WREADY = M_AXI_wready[0]; + assign m01_couplers_to_m01_couplers_WSTRB = S_AXI_wstrb[3:0]; + assign m01_couplers_to_m01_couplers_WVALID = S_AXI_wvalid[0]; +endmodule + +module m02_couplers_imp_173O0AU + (M_ACLK, + M_ARESETN, + M_AXI_araddr, + M_AXI_arprot, + M_AXI_arready, + M_AXI_arvalid, + M_AXI_awaddr, + M_AXI_awprot, + M_AXI_awready, + M_AXI_awvalid, + M_AXI_bready, + M_AXI_bresp, + M_AXI_bvalid, + M_AXI_rdata, + M_AXI_rready, + M_AXI_rresp, + M_AXI_rvalid, + M_AXI_wdata, + M_AXI_wready, + M_AXI_wstrb, + M_AXI_wvalid, + S_ACLK, + S_ARESETN, + S_AXI_araddr, + S_AXI_arprot, + S_AXI_arready, + S_AXI_arvalid, + S_AXI_awaddr, + S_AXI_awprot, + S_AXI_awready, + S_AXI_awvalid, + S_AXI_bready, + S_AXI_bresp, + S_AXI_bvalid, + S_AXI_rdata, + S_AXI_rready, + S_AXI_rresp, + S_AXI_rvalid, + S_AXI_wdata, + S_AXI_wready, + S_AXI_wstrb, + S_AXI_wvalid); + input M_ACLK; + input M_ARESETN; + output [31:0]M_AXI_araddr; + output [2:0]M_AXI_arprot; + input [0:0]M_AXI_arready; + output [0:0]M_AXI_arvalid; + output [31:0]M_AXI_awaddr; + output [2:0]M_AXI_awprot; + input [0:0]M_AXI_awready; + output [0:0]M_AXI_awvalid; + output [0:0]M_AXI_bready; + input [1:0]M_AXI_bresp; + input [0:0]M_AXI_bvalid; + input [31:0]M_AXI_rdata; + output [0:0]M_AXI_rready; + input [1:0]M_AXI_rresp; + input [0:0]M_AXI_rvalid; + output [31:0]M_AXI_wdata; + input [0:0]M_AXI_wready; + output [3:0]M_AXI_wstrb; + output [0:0]M_AXI_wvalid; + input S_ACLK; + input S_ARESETN; + input [31:0]S_AXI_araddr; + input [2:0]S_AXI_arprot; + output [0:0]S_AXI_arready; + input [0:0]S_AXI_arvalid; + input [31:0]S_AXI_awaddr; + input [2:0]S_AXI_awprot; + output [0:0]S_AXI_awready; + input [0:0]S_AXI_awvalid; + input [0:0]S_AXI_bready; + output [1:0]S_AXI_bresp; + output [0:0]S_AXI_bvalid; + output [31:0]S_AXI_rdata; + input [0:0]S_AXI_rready; + output [1:0]S_AXI_rresp; + output [0:0]S_AXI_rvalid; + input [31:0]S_AXI_wdata; + output [0:0]S_AXI_wready; + input [3:0]S_AXI_wstrb; + input [0:0]S_AXI_wvalid; + + wire [31:0]m02_couplers_to_m02_couplers_ARADDR; + wire [2:0]m02_couplers_to_m02_couplers_ARPROT; + wire [0:0]m02_couplers_to_m02_couplers_ARREADY; + wire [0:0]m02_couplers_to_m02_couplers_ARVALID; + wire [31:0]m02_couplers_to_m02_couplers_AWADDR; + wire [2:0]m02_couplers_to_m02_couplers_AWPROT; + wire [0:0]m02_couplers_to_m02_couplers_AWREADY; + wire [0:0]m02_couplers_to_m02_couplers_AWVALID; + wire [0:0]m02_couplers_to_m02_couplers_BREADY; + wire [1:0]m02_couplers_to_m02_couplers_BRESP; + wire [0:0]m02_couplers_to_m02_couplers_BVALID; + wire [31:0]m02_couplers_to_m02_couplers_RDATA; + wire [0:0]m02_couplers_to_m02_couplers_RREADY; + wire [1:0]m02_couplers_to_m02_couplers_RRESP; + wire [0:0]m02_couplers_to_m02_couplers_RVALID; + wire [31:0]m02_couplers_to_m02_couplers_WDATA; + wire [0:0]m02_couplers_to_m02_couplers_WREADY; + wire [3:0]m02_couplers_to_m02_couplers_WSTRB; + wire [0:0]m02_couplers_to_m02_couplers_WVALID; + + assign M_AXI_araddr[31:0] = m02_couplers_to_m02_couplers_ARADDR; + assign M_AXI_arprot[2:0] = m02_couplers_to_m02_couplers_ARPROT; + assign M_AXI_arvalid[0] = m02_couplers_to_m02_couplers_ARVALID; + assign M_AXI_awaddr[31:0] = m02_couplers_to_m02_couplers_AWADDR; + assign M_AXI_awprot[2:0] = m02_couplers_to_m02_couplers_AWPROT; + assign M_AXI_awvalid[0] = m02_couplers_to_m02_couplers_AWVALID; + assign M_AXI_bready[0] = m02_couplers_to_m02_couplers_BREADY; + assign M_AXI_rready[0] = m02_couplers_to_m02_couplers_RREADY; + assign M_AXI_wdata[31:0] = m02_couplers_to_m02_couplers_WDATA; + assign M_AXI_wstrb[3:0] = m02_couplers_to_m02_couplers_WSTRB; + assign M_AXI_wvalid[0] = m02_couplers_to_m02_couplers_WVALID; + assign S_AXI_arready[0] = m02_couplers_to_m02_couplers_ARREADY; + assign S_AXI_awready[0] = m02_couplers_to_m02_couplers_AWREADY; + assign S_AXI_bresp[1:0] = m02_couplers_to_m02_couplers_BRESP; + assign S_AXI_bvalid[0] = m02_couplers_to_m02_couplers_BVALID; + assign S_AXI_rdata[31:0] = m02_couplers_to_m02_couplers_RDATA; + assign S_AXI_rresp[1:0] = m02_couplers_to_m02_couplers_RRESP; + assign S_AXI_rvalid[0] = m02_couplers_to_m02_couplers_RVALID; + assign S_AXI_wready[0] = m02_couplers_to_m02_couplers_WREADY; + assign m02_couplers_to_m02_couplers_ARADDR = S_AXI_araddr[31:0]; + assign m02_couplers_to_m02_couplers_ARPROT = S_AXI_arprot[2:0]; + assign m02_couplers_to_m02_couplers_ARREADY = M_AXI_arready[0]; + assign m02_couplers_to_m02_couplers_ARVALID = S_AXI_arvalid[0]; + assign m02_couplers_to_m02_couplers_AWADDR = S_AXI_awaddr[31:0]; + assign m02_couplers_to_m02_couplers_AWPROT = S_AXI_awprot[2:0]; + assign m02_couplers_to_m02_couplers_AWREADY = M_AXI_awready[0]; + assign m02_couplers_to_m02_couplers_AWVALID = S_AXI_awvalid[0]; + assign m02_couplers_to_m02_couplers_BREADY = S_AXI_bready[0]; + assign m02_couplers_to_m02_couplers_BRESP = M_AXI_bresp[1:0]; + assign m02_couplers_to_m02_couplers_BVALID = M_AXI_bvalid[0]; + assign m02_couplers_to_m02_couplers_RDATA = M_AXI_rdata[31:0]; + assign m02_couplers_to_m02_couplers_RREADY = S_AXI_rready[0]; + assign m02_couplers_to_m02_couplers_RRESP = M_AXI_rresp[1:0]; + assign m02_couplers_to_m02_couplers_RVALID = M_AXI_rvalid[0]; + assign m02_couplers_to_m02_couplers_WDATA = S_AXI_wdata[31:0]; + assign m02_couplers_to_m02_couplers_WREADY = M_AXI_wready[0]; + assign m02_couplers_to_m02_couplers_WSTRB = S_AXI_wstrb[3:0]; + assign m02_couplers_to_m02_couplers_WVALID = S_AXI_wvalid[0]; +endmodule + +module s00_couplers_imp_10AESJG + (M_ACLK, + M_ARESETN, + M_AXI_araddr, + M_AXI_arprot, + M_AXI_arready, + M_AXI_arvalid, + M_AXI_awaddr, + M_AXI_awprot, + M_AXI_awready, + M_AXI_awvalid, + M_AXI_bready, + M_AXI_bresp, + M_AXI_bvalid, + M_AXI_rdata, + M_AXI_rready, + M_AXI_rresp, + M_AXI_rvalid, + M_AXI_wdata, + M_AXI_wready, + M_AXI_wstrb, + M_AXI_wvalid, + S_ACLK, + S_ARESETN, + S_AXI_araddr, + S_AXI_arburst, + S_AXI_arcache, + S_AXI_arid, + S_AXI_arlen, + S_AXI_arlock, + S_AXI_arprot, + S_AXI_arqos, + S_AXI_arready, + S_AXI_arsize, + S_AXI_arvalid, + S_AXI_awaddr, + S_AXI_awburst, + S_AXI_awcache, + S_AXI_awid, + S_AXI_awlen, + S_AXI_awlock, + S_AXI_awprot, + S_AXI_awqos, + S_AXI_awready, + S_AXI_awsize, + S_AXI_awvalid, + S_AXI_bid, + S_AXI_bready, + S_AXI_bresp, + S_AXI_bvalid, + S_AXI_rdata, + S_AXI_rid, + S_AXI_rlast, + S_AXI_rready, + S_AXI_rresp, + S_AXI_rvalid, + S_AXI_wdata, + S_AXI_wid, + S_AXI_wlast, + S_AXI_wready, + S_AXI_wstrb, + S_AXI_wvalid); + input M_ACLK; + input M_ARESETN; + output [31:0]M_AXI_araddr; + output [2:0]M_AXI_arprot; + input M_AXI_arready; + output M_AXI_arvalid; + output [31:0]M_AXI_awaddr; + output [2:0]M_AXI_awprot; + input M_AXI_awready; + output M_AXI_awvalid; + output M_AXI_bready; + input [1:0]M_AXI_bresp; + input M_AXI_bvalid; + input [31:0]M_AXI_rdata; + output M_AXI_rready; + input [1:0]M_AXI_rresp; + input M_AXI_rvalid; + output [31:0]M_AXI_wdata; + input M_AXI_wready; + output [3:0]M_AXI_wstrb; + output M_AXI_wvalid; + input S_ACLK; + input S_ARESETN; + input [31:0]S_AXI_araddr; + input [1:0]S_AXI_arburst; + input [3:0]S_AXI_arcache; + input [11:0]S_AXI_arid; + input [3:0]S_AXI_arlen; + input [1:0]S_AXI_arlock; + input [2:0]S_AXI_arprot; + input [3:0]S_AXI_arqos; + output S_AXI_arready; + input [2:0]S_AXI_arsize; + input S_AXI_arvalid; + input [31:0]S_AXI_awaddr; + input [1:0]S_AXI_awburst; + input [3:0]S_AXI_awcache; + input [11:0]S_AXI_awid; + input [3:0]S_AXI_awlen; + input [1:0]S_AXI_awlock; + input [2:0]S_AXI_awprot; + input [3:0]S_AXI_awqos; + output S_AXI_awready; + input [2:0]S_AXI_awsize; + input S_AXI_awvalid; + output [11:0]S_AXI_bid; + input S_AXI_bready; + output [1:0]S_AXI_bresp; + output S_AXI_bvalid; + output [31:0]S_AXI_rdata; + output [11:0]S_AXI_rid; + output S_AXI_rlast; + input S_AXI_rready; + output [1:0]S_AXI_rresp; + output S_AXI_rvalid; + input [31:0]S_AXI_wdata; + input [11:0]S_AXI_wid; + input S_AXI_wlast; + output S_AXI_wready; + input [3:0]S_AXI_wstrb; + input S_AXI_wvalid; + + wire S_ACLK_1; + wire S_ARESETN_1; + wire [31:0]auto_pc_to_s00_couplers_ARADDR; + wire [2:0]auto_pc_to_s00_couplers_ARPROT; + wire auto_pc_to_s00_couplers_ARREADY; + wire auto_pc_to_s00_couplers_ARVALID; + wire [31:0]auto_pc_to_s00_couplers_AWADDR; + wire [2:0]auto_pc_to_s00_couplers_AWPROT; + wire auto_pc_to_s00_couplers_AWREADY; + wire auto_pc_to_s00_couplers_AWVALID; + wire auto_pc_to_s00_couplers_BREADY; + wire [1:0]auto_pc_to_s00_couplers_BRESP; + wire auto_pc_to_s00_couplers_BVALID; + wire [31:0]auto_pc_to_s00_couplers_RDATA; + wire auto_pc_to_s00_couplers_RREADY; + wire [1:0]auto_pc_to_s00_couplers_RRESP; + wire auto_pc_to_s00_couplers_RVALID; + wire [31:0]auto_pc_to_s00_couplers_WDATA; + wire auto_pc_to_s00_couplers_WREADY; + wire [3:0]auto_pc_to_s00_couplers_WSTRB; + wire auto_pc_to_s00_couplers_WVALID; + wire [31:0]s00_couplers_to_auto_pc_ARADDR; + wire [1:0]s00_couplers_to_auto_pc_ARBURST; + wire [3:0]s00_couplers_to_auto_pc_ARCACHE; + wire [11:0]s00_couplers_to_auto_pc_ARID; + wire [3:0]s00_couplers_to_auto_pc_ARLEN; + wire [1:0]s00_couplers_to_auto_pc_ARLOCK; + wire [2:0]s00_couplers_to_auto_pc_ARPROT; + wire [3:0]s00_couplers_to_auto_pc_ARQOS; + wire s00_couplers_to_auto_pc_ARREADY; + wire [2:0]s00_couplers_to_auto_pc_ARSIZE; + wire s00_couplers_to_auto_pc_ARVALID; + wire [31:0]s00_couplers_to_auto_pc_AWADDR; + wire [1:0]s00_couplers_to_auto_pc_AWBURST; + wire [3:0]s00_couplers_to_auto_pc_AWCACHE; + wire [11:0]s00_couplers_to_auto_pc_AWID; + wire [3:0]s00_couplers_to_auto_pc_AWLEN; + wire [1:0]s00_couplers_to_auto_pc_AWLOCK; + wire [2:0]s00_couplers_to_auto_pc_AWPROT; + wire [3:0]s00_couplers_to_auto_pc_AWQOS; + wire s00_couplers_to_auto_pc_AWREADY; + wire [2:0]s00_couplers_to_auto_pc_AWSIZE; + wire s00_couplers_to_auto_pc_AWVALID; + wire [11:0]s00_couplers_to_auto_pc_BID; + wire s00_couplers_to_auto_pc_BREADY; + wire [1:0]s00_couplers_to_auto_pc_BRESP; + wire s00_couplers_to_auto_pc_BVALID; + wire [31:0]s00_couplers_to_auto_pc_RDATA; + wire [11:0]s00_couplers_to_auto_pc_RID; + wire s00_couplers_to_auto_pc_RLAST; + wire s00_couplers_to_auto_pc_RREADY; + wire [1:0]s00_couplers_to_auto_pc_RRESP; + wire s00_couplers_to_auto_pc_RVALID; + wire [31:0]s00_couplers_to_auto_pc_WDATA; + wire [11:0]s00_couplers_to_auto_pc_WID; + wire s00_couplers_to_auto_pc_WLAST; + wire s00_couplers_to_auto_pc_WREADY; + wire [3:0]s00_couplers_to_auto_pc_WSTRB; + wire s00_couplers_to_auto_pc_WVALID; + + assign M_AXI_araddr[31:0] = auto_pc_to_s00_couplers_ARADDR; + assign M_AXI_arprot[2:0] = auto_pc_to_s00_couplers_ARPROT; + assign M_AXI_arvalid = auto_pc_to_s00_couplers_ARVALID; + assign M_AXI_awaddr[31:0] = auto_pc_to_s00_couplers_AWADDR; + assign M_AXI_awprot[2:0] = auto_pc_to_s00_couplers_AWPROT; + assign M_AXI_awvalid = auto_pc_to_s00_couplers_AWVALID; + assign M_AXI_bready = auto_pc_to_s00_couplers_BREADY; + assign M_AXI_rready = auto_pc_to_s00_couplers_RREADY; + assign M_AXI_wdata[31:0] = auto_pc_to_s00_couplers_WDATA; + assign M_AXI_wstrb[3:0] = auto_pc_to_s00_couplers_WSTRB; + assign M_AXI_wvalid = auto_pc_to_s00_couplers_WVALID; + assign S_ACLK_1 = S_ACLK; + assign S_ARESETN_1 = S_ARESETN; + assign S_AXI_arready = s00_couplers_to_auto_pc_ARREADY; + assign S_AXI_awready = s00_couplers_to_auto_pc_AWREADY; + assign S_AXI_bid[11:0] = s00_couplers_to_auto_pc_BID; + assign S_AXI_bresp[1:0] = s00_couplers_to_auto_pc_BRESP; + assign S_AXI_bvalid = s00_couplers_to_auto_pc_BVALID; + assign S_AXI_rdata[31:0] = s00_couplers_to_auto_pc_RDATA; + assign S_AXI_rid[11:0] = s00_couplers_to_auto_pc_RID; + assign S_AXI_rlast = s00_couplers_to_auto_pc_RLAST; + assign S_AXI_rresp[1:0] = s00_couplers_to_auto_pc_RRESP; + assign S_AXI_rvalid = s00_couplers_to_auto_pc_RVALID; + assign S_AXI_wready = s00_couplers_to_auto_pc_WREADY; + assign auto_pc_to_s00_couplers_ARREADY = M_AXI_arready; + assign auto_pc_to_s00_couplers_AWREADY = M_AXI_awready; + assign auto_pc_to_s00_couplers_BRESP = M_AXI_bresp[1:0]; + assign auto_pc_to_s00_couplers_BVALID = M_AXI_bvalid; + assign auto_pc_to_s00_couplers_RDATA = M_AXI_rdata[31:0]; + assign auto_pc_to_s00_couplers_RRESP = M_AXI_rresp[1:0]; + assign auto_pc_to_s00_couplers_RVALID = M_AXI_rvalid; + assign auto_pc_to_s00_couplers_WREADY = M_AXI_wready; + assign s00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0]; + assign s00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0]; + assign s00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0]; + assign s00_couplers_to_auto_pc_ARID = S_AXI_arid[11:0]; + assign s00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[3:0]; + assign s00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[1:0]; + assign s00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0]; + assign s00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0]; + assign s00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0]; + assign s00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid; + assign s00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0]; + assign s00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0]; + assign s00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0]; + assign s00_couplers_to_auto_pc_AWID = S_AXI_awid[11:0]; + assign s00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[3:0]; + assign s00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[1:0]; + assign s00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0]; + assign s00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0]; + assign s00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0]; + assign s00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid; + assign s00_couplers_to_auto_pc_BREADY = S_AXI_bready; + assign s00_couplers_to_auto_pc_RREADY = S_AXI_rready; + assign s00_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0]; + assign s00_couplers_to_auto_pc_WID = S_AXI_wid[11:0]; + assign s00_couplers_to_auto_pc_WLAST = S_AXI_wlast; + assign s00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0]; + assign s00_couplers_to_auto_pc_WVALID = S_AXI_wvalid; + NewExtInst_TOP_auto_pc_0 auto_pc + (.aclk(S_ACLK_1), + .aresetn(S_ARESETN_1), + .m_axi_araddr(auto_pc_to_s00_couplers_ARADDR), + .m_axi_arprot(auto_pc_to_s00_couplers_ARPROT), + .m_axi_arready(auto_pc_to_s00_couplers_ARREADY), + .m_axi_arvalid(auto_pc_to_s00_couplers_ARVALID), + .m_axi_awaddr(auto_pc_to_s00_couplers_AWADDR), + .m_axi_awprot(auto_pc_to_s00_couplers_AWPROT), + .m_axi_awready(auto_pc_to_s00_couplers_AWREADY), + .m_axi_awvalid(auto_pc_to_s00_couplers_AWVALID), + .m_axi_bready(auto_pc_to_s00_couplers_BREADY), + .m_axi_bresp(auto_pc_to_s00_couplers_BRESP), + .m_axi_bvalid(auto_pc_to_s00_couplers_BVALID), + .m_axi_rdata(auto_pc_to_s00_couplers_RDATA), + .m_axi_rready(auto_pc_to_s00_couplers_RREADY), + .m_axi_rresp(auto_pc_to_s00_couplers_RRESP), + .m_axi_rvalid(auto_pc_to_s00_couplers_RVALID), + .m_axi_wdata(auto_pc_to_s00_couplers_WDATA), + .m_axi_wready(auto_pc_to_s00_couplers_WREADY), + .m_axi_wstrb(auto_pc_to_s00_couplers_WSTRB), + .m_axi_wvalid(auto_pc_to_s00_couplers_WVALID), + .s_axi_araddr(s00_couplers_to_auto_pc_ARADDR), + .s_axi_arburst(s00_couplers_to_auto_pc_ARBURST), + .s_axi_arcache(s00_couplers_to_auto_pc_ARCACHE), + .s_axi_arid(s00_couplers_to_auto_pc_ARID), + .s_axi_arlen(s00_couplers_to_auto_pc_ARLEN), + .s_axi_arlock(s00_couplers_to_auto_pc_ARLOCK), + .s_axi_arprot(s00_couplers_to_auto_pc_ARPROT), + .s_axi_arqos(s00_couplers_to_auto_pc_ARQOS), + .s_axi_arready(s00_couplers_to_auto_pc_ARREADY), + .s_axi_arsize(s00_couplers_to_auto_pc_ARSIZE), + .s_axi_arvalid(s00_couplers_to_auto_pc_ARVALID), + .s_axi_awaddr(s00_couplers_to_auto_pc_AWADDR), + .s_axi_awburst(s00_couplers_to_auto_pc_AWBURST), + .s_axi_awcache(s00_couplers_to_auto_pc_AWCACHE), + .s_axi_awid(s00_couplers_to_auto_pc_AWID), + .s_axi_awlen(s00_couplers_to_auto_pc_AWLEN), + .s_axi_awlock(s00_couplers_to_auto_pc_AWLOCK), + .s_axi_awprot(s00_couplers_to_auto_pc_AWPROT), + .s_axi_awqos(s00_couplers_to_auto_pc_AWQOS), + .s_axi_awready(s00_couplers_to_auto_pc_AWREADY), + .s_axi_awsize(s00_couplers_to_auto_pc_AWSIZE), + .s_axi_awvalid(s00_couplers_to_auto_pc_AWVALID), + .s_axi_bid(s00_couplers_to_auto_pc_BID), + .s_axi_bready(s00_couplers_to_auto_pc_BREADY), + .s_axi_bresp(s00_couplers_to_auto_pc_BRESP), + .s_axi_bvalid(s00_couplers_to_auto_pc_BVALID), + .s_axi_rdata(s00_couplers_to_auto_pc_RDATA), + .s_axi_rid(s00_couplers_to_auto_pc_RID), + .s_axi_rlast(s00_couplers_to_auto_pc_RLAST), + .s_axi_rready(s00_couplers_to_auto_pc_RREADY), + .s_axi_rresp(s00_couplers_to_auto_pc_RRESP), + .s_axi_rvalid(s00_couplers_to_auto_pc_RVALID), + .s_axi_wdata(s00_couplers_to_auto_pc_WDATA), + .s_axi_wid(s00_couplers_to_auto_pc_WID), + .s_axi_wlast(s00_couplers_to_auto_pc_WLAST), + .s_axi_wready(s00_couplers_to_auto_pc_WREADY), + .s_axi_wstrb(s00_couplers_to_auto_pc_WSTRB), + .s_axi_wvalid(s00_couplers_to_auto_pc_WVALID)); +endmodule diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/Makefile b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/Makefile new file mode 100755 index 0000000..33394b3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/Makefile @@ -0,0 +1,26 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +INCLUDEFILES=*.h +LIBSOURCES=*.c +OUTS = *.o + +libs: + echo "Compiling SPI_Con..." + $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} + make clean + +include: + ${CP} $(INCLUDEFILES) $(INCLUDEDIR) + +clean: + rm -rf ${OUTS} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/NewExtInst_TOP.bda b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/NewExtInst_TOP.bda new file mode 100755 index 0000000..ab7b1f9 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/NewExtInst_TOP.bda @@ -0,0 +1,272 @@ +{ + "graphjs": { + "version": "1.0", + "keys": [ + { + "abrv": "VH", + "name": "vert_hid", + "type": "int", + "for": "node" + }, + { + "abrv": "VM", + "name": "vert_name", + "type": "string", + "for": "node" + }, + { + "abrv": "VT", + "name": "vert_type", + "type": "string", + "for": "node" + }, + { + "abrv": "BA", + "name": "base_addr", + "type": "string", + "for": "node" + }, + { + "abrv": "HA", + "name": "high_addr", + "type": "string", + "for": "node" + }, + { + "abrv": "BP", + "name": "base_param", + "type": "string", + "for": "node" + }, + { + "abrv": "HP", + "name": "high_param", + "type": "string", + "for": "node" + }, + { + "abrv": "MA", + "name": "master_addrspace", + "type": "string", + "for": "node" + }, + { + "abrv": "MX", + "name": "master_instance", + "type": "string", + "for": "node" + }, + { + "abrv": "MI", + "name": "master_interface", + "type": "string", + "for": "node" + }, + { + "abrv": "MS", + "name": "master_segment", + "type": "string", + "for": "node" + }, + { + "abrv": "MV", + "name": "master_vlnv", + "type": "string", + "for": "node" + }, + { + "abrv": "SX", + "name": "slave_instance", + "type": "string", + "for": "node" + }, + { + "abrv": "SI", + "name": "slave_interface", + "type": "string", + "for": "node" + }, + { + "abrv": "MM", + "name": "slave_memmap", + "type": "string", + "for": "node" + }, + { + "abrv": "SS", + "name": "slave_segment", + "type": "string", + "for": "node" + }, + { + "abrv": "SV", + "name": "slave_vlnv", + "type": "string", + "for": "node" + }, + { + "abrv": "TM", + "name": "memory_type", + "type": "string", + "for": "node" + }, + { + "abrv": "TU", + "name": "usage_type", + "type": "string", + "for": "node" + }, + { + "abrv": "LT", + "name": "lock_type", + "type": "string", + "for": "node" + }, + { + "abrv": "BT", + "name": "boot_type", + "type": "string", + "for": "node" + }, + { + "abrv": "EH", + "name": "edge_hid", + "type": "int", + "for": "edge" + } + ], + "vertice_type_order": [ + { + "abrv": "BC", + "desc": "Block Container" + }, + { + "abrv": "PR", + "desc": "Parital Reference" + }, + { + "abrv": "VR", + "desc": "Variant" + }, + { + "abrv": "PM", + "desc": "Variant Permutations" + }, + { + "abrv": "CX", + "desc": "Boundary Connection" + }, + { + "abrv": "AC", + "desc": "Assignment Coordinate" + }, + { + "abrv": "ACE", + "desc": "Excluded Assign Coordinate" + }, + { + "abrv": "APX", + "desc": "Boundary Aperture" + }, + { + "abrv": "CIP", + "desc": "High level Processing System" + } + ], + "vertices": { + "V0": { + "VM": "NewExtInst_TOP", + "VT": "BC" + }, + "V1": { + "VH": "2", + "VM": "NewExtInst_TOP", + "VT": "VR" + }, + "V2": { + "VH": "2", + "VT": "PM", + "TU": "active" + }, + "V3": { + "VT": "AC", + "BA": "0x43C00000", + "HA": "0x43C0FFFF", + "BP": "C_S00_AXI_BASEADDR", + "HP": "C_S00_AXI_HIGHADDR", + "MA": "Data", + "MX": "/processing_system7_0", + "MI": "M_AXI_GP0", + "MS": "SEG_SPI_Con_0_S00_AXI_reg", + "MV": "xilinx.com:ip:processing_system7:5.5", + "SX": "/SPI_Con_0", + "SI": "S00_AXI", + "SS": "S00_AXI_reg", + "SV": "xilinx.com:user:SPI_Con:1.0", + "TM": "both", + "TU": "register" + }, + "V4": { + "VT": "AC", + "BA": "0x43C10000", + "HA": "0x43C1FFFF", + "BP": "C_S00_AXI_BASEADDR", + "HP": "C_S00_AXI_HIGHADDR", + "MA": "Data", + "MX": "/processing_system7_0", + "MI": "M_AXI_GP0", + "MS": "SEG_SPI_Con_1_S00_AXI_reg", + "MV": "xilinx.com:ip:processing_system7:5.5", + "SX": "/SPI_Con_1", + "SI": "S00_AXI", + "SS": "S00_AXI_reg", + "SV": "xilinx.com:user:SPI_Con:1.0", + "TM": "both", + "TU": "register" + }, + "V5": { + "VT": "AC", + "BA": "0x43C20000", + "HA": "0x43C2FFFF", + "BP": "C_S00_AXI_BASEADDR", + "HP": "C_S00_AXI_HIGHADDR", + "MA": "Data", + "MX": "/processing_system7_0", + "MI": "M_AXI_GP0", + "MS": "SEG_SPI_Con_2_S00_AXI_reg", + "MV": "xilinx.com:ip:processing_system7:5.5", + "SX": "/SPI_Con_2", + "SI": "S00_AXI", + "SS": "S00_AXI_reg", + "SV": "xilinx.com:user:SPI_Con:1.0", + "TM": "both", + "TU": "register" + } + }, + "edges": [ + { + "src": "V0", + "trg": "V1" + }, + { + "src": "V1", + "trg": "V2" + }, + { + "src": "V3", + "trg": "V2", + "EH": "2" + }, + { + "src": "V4", + "trg": "V2", + "EH": "2" + }, + { + "src": "V5", + "trg": "V2", + "EH": "2" + } + ] + } +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/SPI_Con.h b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/SPI_Con.h new file mode 100755 index 0000000..5278bdd --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/SPI_Con.h @@ -0,0 +1,107 @@ + +#ifndef SPI_CON_H +#define SPI_CON_H + + +/****************** Include Files ********************/ +#include "xil_types.h" +#include "xstatus.h" + +#define SPI_CON_S00_AXI_SLV_REG0_OFFSET 0 +#define SPI_CON_S00_AXI_SLV_REG1_OFFSET 4 +#define SPI_CON_S00_AXI_SLV_REG2_OFFSET 8 +#define SPI_CON_S00_AXI_SLV_REG3_OFFSET 12 +#define SPI_CON_S00_AXI_SLV_REG4_OFFSET 16 +#define SPI_CON_S00_AXI_SLV_REG5_OFFSET 20 +#define SPI_CON_S00_AXI_SLV_REG6_OFFSET 24 +#define SPI_CON_S00_AXI_SLV_REG7_OFFSET 28 +#define SPI_CON_S00_AXI_SLV_REG8_OFFSET 32 +#define SPI_CON_S00_AXI_SLV_REG9_OFFSET 36 +#define SPI_CON_S00_AXI_SLV_REG10_OFFSET 40 +#define SPI_CON_S00_AXI_SLV_REG11_OFFSET 44 +#define SPI_CON_S00_AXI_SLV_REG12_OFFSET 48 +#define SPI_CON_S00_AXI_SLV_REG13_OFFSET 52 +#define SPI_CON_S00_AXI_SLV_REG14_OFFSET 56 +#define SPI_CON_S00_AXI_SLV_REG15_OFFSET 60 +#define SPI_CON_S00_AXI_SLV_REG16_OFFSET 64 +#define SPI_CON_S00_AXI_SLV_REG17_OFFSET 68 +#define SPI_CON_S00_AXI_SLV_REG18_OFFSET 72 +#define SPI_CON_S00_AXI_SLV_REG19_OFFSET 76 +#define SPI_CON_S00_AXI_SLV_REG20_OFFSET 80 +#define SPI_CON_S00_AXI_SLV_REG21_OFFSET 84 +#define SPI_CON_S00_AXI_SLV_REG22_OFFSET 88 +#define SPI_CON_S00_AXI_SLV_REG23_OFFSET 92 +#define SPI_CON_S00_AXI_SLV_REG24_OFFSET 96 +#define SPI_CON_S00_AXI_SLV_REG25_OFFSET 100 +#define SPI_CON_S00_AXI_SLV_REG26_OFFSET 104 +#define SPI_CON_S00_AXI_SLV_REG27_OFFSET 108 +#define SPI_CON_S00_AXI_SLV_REG28_OFFSET 112 +#define SPI_CON_S00_AXI_SLV_REG29_OFFSET 116 +#define SPI_CON_S00_AXI_SLV_REG30_OFFSET 120 +#define SPI_CON_S00_AXI_SLV_REG31_OFFSET 124 + + +/**************************** Type Definitions *****************************/ +/** + * + * Write a value to a SPI_CON register. A 32 bit write is performed. + * If the component is implemented in a smaller width, only the least + * significant data is written. + * + * @param BaseAddress is the base address of the SPI_CONdevice. + * @param RegOffset is the register offset from the base to write to. + * @param Data is the data written to the register. + * + * @return None. + * + * @note + * C-style signature: + * void SPI_CON_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data) + * + */ +#define SPI_CON_mWriteReg(BaseAddress, RegOffset, Data) \ + Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data)) + +/** + * + * Read a value from a SPI_CON register. A 32 bit read is performed. + * If the component is implemented in a smaller width, only the least + * significant data is read from the register. The most significant data + * will be read as 0. + * + * @param BaseAddress is the base address of the SPI_CON device. + * @param RegOffset is the register offset from the base to write to. + * + * @return Data is the data from the register. + * + * @note + * C-style signature: + * u32 SPI_CON_mReadReg(u32 BaseAddress, unsigned RegOffset) + * + */ +#define SPI_CON_mReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (RegOffset)) + +/************************** Function Prototypes ****************************/ +/** + * + * Run a self-test on the driver/device. Note this may be a destructive test if + * resets of the device are performed. + * + * If the hardware system is not built correctly, this function may never + * return to the caller. + * + * @param baseaddr_p is the base address of the SPI_CON instance to be worked on. + * + * @return + * + * - XST_SUCCESS if all self-test code passed + * - XST_FAILURE if any self-test code failed + * + * @note Caching must be turned off for this function to work. + * @note Self test may fail if data memory and device are not on the same bus. + * + */ +XStatus SPI_CON_Reg_SelfTest(void * baseaddr_p); + +#endif // SPI_CON_H diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/SPI_Con.mdd b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/SPI_Con.mdd new file mode 100755 index 0000000..4bd813f --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/SPI_Con.mdd @@ -0,0 +1,10 @@ + + +OPTION psf_version = 2.1; + +BEGIN DRIVER SPI_Con + OPTION supported_peripherals = (SPI_Con); + OPTION copyfiles = all; + OPTION VERSION = 1.0; + OPTION NAME = SPI_Con; +END DRIVER diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/SPI_Con.tcl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/SPI_Con.tcl new file mode 100755 index 0000000..7f913c9 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/SPI_Con.tcl @@ -0,0 +1,5 @@ + + +proc generate {drv_handle} { + xdefine_include_file $drv_handle "xparameters.h" "SPI_Con" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR" +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/libps7.dll b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/libps7.dll new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/libps7.dll @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/libps7.so b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/libps7.so new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/libps7.so @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/libremoteport.dll b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/libremoteport.dll new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/libremoteport.dll @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/libremoteport.so b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/libremoteport.so new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/libremoteport.so @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/ps7_init.h b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/ps7_init.h new file mode 100755 index 0000000..224d7ea --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/ps7_init.h @@ -0,0 +1,117 @@ +/****************************************************************************** +* +* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + + + + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 142857132 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 25000000 +#define FPGA1_FREQ 50000000 +#define FPGA2_FREQ 100000000 +#define FPGA3_FREQ 200000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/ps7_init.html b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/ps7_init.html new file mode 100755 index 0000000..9ca53bd --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/ps7_init.html @@ -0,0 +1,125613 @@ + + + + +Zynq PS configuration detail + + + +
+
+ +
  • +
    Zynq PS Register Summary Viewer +
    +
    • +     +
    +
    +
    + +
    Zynq PS7 Summary Report +
    +     +
    User Configurations +
    +
    + +
    MIO Configurations +
    +     +
    + +
    CLK Configurations +
    +     +
    + +
    DDR Configurations +
    +     +
    + +
    SMC Configurations +
    +     +
    +
    +
    Select Version: + +
    +
    +
    Zynq Register View +
    +
    + +
    MIO Registers +
    +     + +
    PLL Registers +
    +     + +
    Clock Registers +
    +     + +
    DDR Registers +
    +     + +
    Peripherals Registers +
    +     +
    +
    This design is targeted for xc7z035 board (part number: xc7z035ffg676-2) + +
    +

    Zynq Design Summary

    + + + + + + + + + + + + + + + + + + + + + +
    +Device + +xc7z035 +
    +SpeedGrade + +-2 +
    +Part + +xc7z035ffg676-2 +
    +Description + +Zynq PS Configuration Report with register details +
    +Vendor + +Xilinx +
    +

    MIO Table View

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +MIO Pin + +Peripheral + +Signal + +IO Type + +Speed + +Pullup + +Direction +
    +MIO 0 + +SD 1 + +wp + +LVCMOS 3.3V + +slow + +enabled + +in +
    +MIO 1 + +Quad SPI Flash + +qspi0_ss_b + +LVCMOS 3.3V + +slow + +enabled + +out +
    +MIO 2 + +Quad SPI Flash + +qspi0_io[0] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 3 + +Quad SPI Flash + +qspi0_io[1] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 4 + +Quad SPI Flash + +qspi0_io[2] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 5 + +Quad SPI Flash + +qspi0_io[3]/HOLD_B + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 6 + +Quad SPI Flash + +qspi0_sclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 7 + + + + + + + + + + + + +
    +MIO 8 + +Quad SPI Flash + +qspi_fbclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 9 + +SD 1 + +cd + +LVCMOS 3.3V + +slow + +enabled + +in +
    +MIO 10 + +SD 1 + +data[0] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 11 + +SD 1 + +cmd + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 12 + +SD 1 + +clk + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 13 + +SD 1 + +data[1] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 14 + +SD 1 + +data[2] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 15 + +SD 1 + +data[3] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 16 + +Enet 0 + +tx_clk + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 17 + +Enet 0 + +txd[0] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 18 + +Enet 0 + +txd[1] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 19 + +Enet 0 + +txd[2] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 20 + +Enet 0 + +txd[3] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 21 + +Enet 0 + +tx_ctl + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 22 + +Enet 0 + +rx_clk + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 23 + +Enet 0 + +rxd[0] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 24 + +Enet 0 + +rxd[1] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 25 + +Enet 0 + +rxd[2] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 26 + +Enet 0 + +rxd[3] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 27 + +Enet 0 + +rx_ctl + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 28 + + + + + + + + + + + + +
    +MIO 29 + + + + + + + + + + + + +
    +MIO 30 + + + + + + + + + + + + +
    +MIO 31 + + + + + + + + + + + + +
    +MIO 32 + + + + + + + + + + + + +
    +MIO 33 + + + + + + + + + + + + +
    +MIO 34 + + + + + + + + + + + + +
    +MIO 35 + + + + + + + + + + + + +
    +MIO 36 + + + + + + + + + + + + +
    +MIO 37 + + + + + + + + + + + + +
    +MIO 38 + + + + + + + + + + + + +
    +MIO 39 + + + + + + + + + + + + +
    +MIO 40 + +SD 0 + +clk + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 41 + +SD 0 + +cmd + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 42 + +SD 0 + +data[0] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 43 + +SD 0 + +data[1] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 44 + +SD 0 + +data[2] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 45 + +SD 0 + +data[3] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 46 + +SD 0 + +wp + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 47 + +SD 0 + +cd + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 48 + +UART 1 + +tx + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 49 + +UART 1 + +rx + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 50 + + + + + + + + + + + + +
    +MIO 51 + + + + + + + + + + + + +
    +MIO 52 + +Enet 0 + +mdc + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 53 + +Enet 0 + +mdio + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +

    DDR Memory information

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Parameter name + +Value + +Description +
    +Enable DDR + +1 + +Enable DDR Controller of Zynq PS +
    +Memory Part + +MT41J256M16 RE-125 + + +
    +DRAM bus width + +32 Bit + +Select the desired data width. Refer to the Thechnical Reference Manual(TRM) for a detailed list of supported DDR data widths +
    +ECC + +Disabled + +ECC is supported only for data width of 16-bit +
    +BURST Length (lppdr only) + +8 + +Select the burst Length. It refers to the amount of data read/written after a read/write command is presented to the controller +
    +Internal Vref + +0 + + +
    +Operating Frequency (MHz) + +533.333333 + +Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade +
    +HIGH temperature + +Normal (0-85) + +Select the operating temparature +
    +DRAM IC bus width + +16 Bits + +Provide the width of the DRAM chip +
    +DRAM Device Capacity + +4096 MBits + + +
    +Speed Bin + +DDR3_1066F + +Provide the Speed Bin +
    +BANK Address Count + +3 + +Defines the bank to which an active an ACTIVE, READ, WRITE, or Precharge Command is being applied +
    +ROW Address Count + +15 + +Provide the Row address for ACTIVE commands +
    +COLUMN Address Count + +10 + +Provide the Row address for READ/WRITE commands +
    +CAS Latency + +7 + +Select the Column Access Strobe (CAS) Latency. It refers to the amount of time it takes for data to appear on the pins of the memory module +
    +CAS Write Latency + +6 + +Select the CAS Write Latency +
    +RAS to CAS Delay + +7 + +Provide the row address to column address delay time. tRCD is t he time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS) +
    +RECHARGE Time + +7 + +Precharge Time (tRP) is the number of clock cycles needed o terminate acces s to an open row of memory, and open access to the next row +
    +tRC (ns ) + +48.91 + +Provide the Row cycle time tRC (ns) +
    +tRASmin ( ns ) + +35.0 + +tRASmin (ns) is the minimum number of clock cycles required between an Active command and issuing the Precharge command +
    +tFAW + +40.0 + +It restricts the number of activates that can be done within a certain window of time +
    +ADDITIVE Latency + +0 + +Provide the Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths +
    +Write levelling + +1 + + +
    +Read gate + +1 + + +
    +Read gate + +1 + + +
    +DQS to Clock delay [0] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [1] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [2] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [3] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +Board delay [0] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [1] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [2] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [3] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +

    PS Clocks information

    +

    PS Reference Clock : 33.333333

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Peripheral + +PLL source + +Frequency (MHz) +
    +CPU 6x Freq (MHz) + +ARM PLL + +666.666687 +
    +QSPI Flash Freq (MHz) + +IO PLL + +142.857132 +
    +ENET0 Freq (MHz) + +IO PLL + +125.000000 +
    +SDIO Freq (MHz) + +IO PLL + +100.000000 +
    +SDIO Freq (MHz) + +IO PLL + +100.000000 +
    +UART Freq (MHz) + +IO PLL + +100.000000 +
    +FPGA0 Freq (MHz) + +IO PLL + +25.000000 +
    +FPGA1 Freq (MHz) + +IO PLL + +50.000000 +
    +FPGA2 Freq (MHz) + +IO PLL + +100.000000 +
    +FPGA3 Freq (MHz) + +IO PLL + +200.000000 +
    +

    ps7_pll_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: ARM PLL 10: DDR PLL 11: IO PLL This field is reset by POR only. +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for programming the PLL. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock and Rx Signals Select +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +FPGA1_CLK_CTRL + + +0XF8000180 + +32 + +RW + +0x000000 + +PL Clock 1 Output control +
    + +FPGA2_CLK_CTRL + + +0XF8000190 + +32 + +RW + +0x000000 + +PL Clock 2 output control +
    + +FPGA3_CLK_CTRL + + +0XF80001A0 + +32 + +RW + +0x000000 + +PL Clock 3 output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source of the Rx clock, control and data signals: 0: MIO 1: EMIO +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock and Rx Signals Select +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +7 + +700 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +701 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a03 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +5 + +500000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +500800 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )FPGA1_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA1_CLK_CTRL + +0XF8000180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA1_CLK_CTRL@0XF8000180 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 1 Output control +
    +

    +

    Register ( slcr )FPGA2_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA2_CLK_CTRL + +0XF8000190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +2 + +200000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA2_CLK_CTRL@0XF8000190 + +31:0 + +3f03f30 + + + +200500 + +PL Clock 2 output control +
    +

    +

    Register ( slcr )FPGA3_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA3_CLK_CTRL + +0XF80001A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA3_CLK_CTRL@0XF80001A0 + +31:0 + +3f03f30 + + + +100500 + +PL Clock 3 output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ratio: (When this register changes, no access are allowed to OCM.) 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +1 + +800 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec0c4d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +82 + +82 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reserved_reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Reserved. Do not modify. +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +Two_rank_cfg@0XF8006004 + +31:0 + +7ffff + + + +1082 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a1 + +2840 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4285b + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +13 + +13 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d3 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. In non-LPDDR mode, the minimum DRAM Write Latency (DDR2) supported is 3. In LPDDR mode, the required DRAM Write Latency of 1 is supported. Since write latency (CWL) min is 3, and DDR2 CWL is CL-1, the min (DDR2) CL supported is 4 +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +f + +3c00 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +5 + +28000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +5 + +2800000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +7282bce5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_en_dfi_dram_clk_disable + +23:23 + +800000 + +0 + +0 + +Enables the assertion of ddrc_dfi_dram_clk_disable. In DDR2/DDR3, only asserted in Self Refresh. In mDDR/LPDDR2, can be asserted in following: - during normal operation (Clock Stop), - in Power Down - in Self Refresh - In Deep Power Down +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +7fdffffc + + + +270872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffc3 + + + +0 + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2: Value loaded into EMR2 register DDR3: Value loaded into MR2 register LPDDR2: Value loaded into MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2: Value loaded into EMR3 register DDR3: Value loaded into MR3 register. Set Bit[2:0] to 3'b000. These bits are set appropriately by the Controller during Read Data eye training and Read DQS gate leveling. LPDDR2: Unused +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +b30 + +b30 + +DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2: Value loaded into EMR1register. (Bits[9:7] are for OCD and the setting in this reg is ignored. Controller sets this bits appropriately during initialization DDR3: Value loaded into MR1 register. Set Bit[7] to 0. This bit is set appropriately by the Controller during Write Leveling LPDDR2: Value loaded into MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40b30 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 8, Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 7, Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 6, Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 5, Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reserved_reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +Reserved. Do not modify. +
    +reserved_reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Reserved. Do not modify. +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3f03f + + + +3c008 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +10000 + + + +0 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum d'128) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_2d@0XF80060B4 + +31:0 + +200 + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of uncorrectable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on board topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +0: Use reg_phy_ctrl_slave_ratio for address/command timing slave DLL 1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_64@0XF8006190 + +31:0 + +6ffffefe + + + +40080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. This feature should only be enabled after LPDDR2 initialization is completed +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff5 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Powerdown mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQ pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQS pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +Drive and Slew controls for Clock pins of the DDR Interface +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SD1_WP_CD_SEL + + +0XF8000834 + +32 + +RW + +0x000000 + +SDIO 1 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQ pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQS pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for Clock pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1x: Enable External VREF for upper 16 bits +
    +reserved_VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Reserved. Do not modify. +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +reserved_REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +1 + + + +1 + +DDR IOB DCI Config +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialize flops in DCI system +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDR IOB DCI Config +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +DCI System Enable. Set to 1 if any IOs in DDR IO Bank use DCI Termination. DDR2, DDR3 and LPDDR2 (Silicon Revision 2.0+) configurations require this bit set to 1 +
    +reserved_VRP_TRI + +2:2 + +4 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_TRI + +3:3 + +8 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRP_OUT + +4:4 + +10 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT1 + +15:14 + +c000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update Mode. Use the values in the Calibration Table. +
    +reserved_INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_CLK + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLN + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLP + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_RST + +25:25 + +2000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7feffff + + + +823 + +DDR IOB DCI Config +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. 0: disable 1: enable +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables Pullup on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3f01 + + + +1601 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3f01 + + + +1601 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1680 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1680 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait, Input 10: NAND Flash IO Bit 7, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 12 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1680 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5, Input/Output 10: NAND Flash IO Bit 3, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 13 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1680 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1680 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1680 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1, Output 10: NAND Flash IO Bit 8, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2, Output 10: NAND Flash IO Bit 9, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110 TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3, Output 10: NAND Flash IO Bit 10, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6, Output 10: NAND Flash IO Bit 13, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3f01 + + + +1201 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +2e + +2e + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f002e + +SDIO 0 WP CD select +
    +

    +

    Register ( slcr )SD1_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD1_WP_CD_SEL + +0XF8000834 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO1_WP_SEL + +5:0 + +3f + +0 + +0 + +SDIO 1 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO1_CD_SEL + +21:16 + +3f0000 + +9 + +90000 + +SDIO 1 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD1_WP_CD_SEL@0XF8000834 + +31:0 + +3f003f + + + +90000 + +SDIO 1 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +Baud Rate Divider Register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud Rate Generator Register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control Register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode Register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +Baud Rate Divider Register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud Rate Generator Register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter 1: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: enable 1: disable, regardless of the value of RXEN +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed. +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed. +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control Register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +3ff + + + +20 + +UART Mode Register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes . If not set, then external pull up is required on HOLDb and WPn pins . Note that this bit doesn't affect the quad(4-bit) mode as Controller always drives these pins in quad mode. It is highly recommended to set this bit always(irrespective of mode of operation) while using QSPI +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This register controls which POR timer the PL will use for power-up. 0 - Use 64k timer 1 - Use 4k timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    ENET RESET

    +

    I2C RESET

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_LVL_INP_EN_0 + +3:3 + +8 + +1 + +8 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_0 + +2:2 + +4 + +1 + +4 + +Level shifter enable to drive signals from PS to PL +
    +USER_LVL_INP_EN_1 + +1:1 + +2 + +1 + +2 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_1 + +0:0 + +1 + +1 + +1 + +Level shifter enable to drive signals from PS to PL +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +Reserved. Do not modify. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +PL Reset 3 (FCLKRESETN3 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN3 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +PL Reset 2 (FCLKRESETN2 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN2 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +PL Reset 1 (FCLKRESETN1 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN1 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +PL Reset 0 (FCLKRESETN0 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN0 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    AFI2 SECURE REGISTER

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_3_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: CPU PLL 10: divided DDR PLL 11: IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +FPGA1_CLK_CTRL + + +0XF8000180 + +32 + +RW + +0x000000 + +PL Clock 1 Output control +
    + +FPGA2_CLK_CTRL + + +0XF8000190 + +32 + +RW + +0x000000 + +PL Clock 2 output control +
    + +FPGA3_CLK_CTRL + + +0XF80001A0 + +32 + +RW + +0x000000 + +PL Clock 3 output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source to generate the Rx clock: 0: MIO Rx clock, 1: EMIO Rx clock +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +7 + +700 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +701 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a03 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +5 + +500000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +500800 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )FPGA1_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA1_CLK_CTRL + +0XF8000180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA1_CLK_CTRL@0XF8000180 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 1 Output control +
    +

    +

    Register ( slcr )FPGA2_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA2_CLK_CTRL + +0XF8000190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +2 + +200000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA2_CLK_CTRL@0XF8000190 + +31:0 + +3f03f30 + + + +200500 + +PL Clock 2 output control +
    +

    +

    Register ( slcr )FPGA3_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA3_CLK_CTRL + +0XF80001A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA3_CLK_CTRL@0XF80001A0 + +31:0 + +3f03f30 + + + +100500 + +PL Clock 3 output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ration: 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +1 + +800 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec0c4d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config0 + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config1 + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 1. +
    + +PHY_Config2 + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 2. +
    + +PHY_Config3 + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 3. +
    + +phy_init_ratio0 + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio1 + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 1. +
    + +phy_init_ratio2 + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 2. +
    + +phy_init_ratio3 + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 3. +
    + +phy_rd_dqs_cfg0 + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg1 + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 1. +
    + +phy_rd_dqs_cfg2 + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 2. +
    + +phy_rd_dqs_cfg3 + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 3. +
    + +phy_wr_dqs_cfg0 + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg1 + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 1. +
    + +phy_wr_dqs_cfg2 + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 2. +
    + +phy_wr_dqs_cfg3 + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 3. +
    + +phy_we_cfg0 + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg1 + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 1. +
    + +phy_we_cfg2 + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 2. +
    + +phy_we_cfg3 + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 3. +
    + +wr_data_slv0 + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv1 + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 1. +
    + +wr_data_slv2 + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 2. +
    + +wr_data_slv3 + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 3. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port0 + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port1 + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 1. +
    + +axi_priority_wr_port2 + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 2. +
    + +axi_priority_wr_port3 + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 3. +
    + +axi_priority_rd_port0 + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port1 + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 1. +
    + +axi_priority_rd_port2 + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 2. +
    + +axi_priority_rd_port3 + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 3. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +82 + +82 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Rank configuration: 01: One Rank of DDR 11: Two Ranks of DDR Others: reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +Block read/write scheduling cycle count when Write requires changing ODT settings 00: 1 cycle 01: 2 cycles 10: 3 cycles others: reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0: schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1: schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81082 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a1 + +2840 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4285b + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +13 + +13 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d3 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +f + +3c00 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +5 + +28000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +5 + +2800000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +7282bce5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1: sdram device 0: non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: stop_clk will never be asserted. 1: enable the assertion of stop_clk to the PHY whenever a clock is not required +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2 and DDR3: Value written into the DRAM EMR2 register. LPDDR2: Value written into the DRAM MR3 register. +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2 and DDR3: Value written into the DRAM EMR3 register. LPDDR2: not used. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +b30 + +b30 + +DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2 and DDR3: Value written into the DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. LPDDR2: Value written into the DRAM MR2 register. +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40b30 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODTs must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config0 + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config0@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config1 + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config1@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 1. +
    +

    +

    Register ( slcr )PHY_Config2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config2 + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config2@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 2. +
    +

    +

    Register ( slcr )PHY_Config3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config3 + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config3@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_init_ratio0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio0 + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio0@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio1 + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio1@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 1. +
    +

    +

    Register ( slcr )phy_init_ratio2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio2 + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio2@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 2. +
    +

    +

    Register ( slcr )phy_init_ratio3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio3 + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio3@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 3. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg0 + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg0@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg1 + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg1@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg2 + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg2@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg3 + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg3@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg0 + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg0@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg1 + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg1@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg2 + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg2@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg3 + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg3@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_we_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg0 + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg0@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg1 + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg1@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 1. +
    +

    +

    Register ( slcr )phy_we_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg2 + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg2@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 2. +
    +

    +

    Register ( slcr )phy_we_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg3 + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg3@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 3. +
    +

    +

    Register ( slcr )wr_data_slv0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv0 + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv0@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv1 + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv1@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 1. +
    +

    +

    Register ( slcr )wr_data_slv2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv2 + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv2@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 2. +
    +

    +

    Register ( slcr )wr_data_slv3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv3 + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv3@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 3. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +0: (default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) 1: assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 0: Each Rank uses its own delay 1: Rank 0 delays are used for all ranks +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1: enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port0 + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port0@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port1 + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port1@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 1. +
    +

    +

    Register ( slcr )axi_priority_wr_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port2 + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port2@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 2. +
    +

    +

    Register ( slcr )axi_priority_wr_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port3 + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port3@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 3. +
    +

    +

    Register ( slcr )axi_priority_rd_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port0 + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port0@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port1 + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port1@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 1. +
    +

    +

    Register ( slcr )axi_priority_rd_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port2 + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port2@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 2. +
    +

    +

    Register ( slcr )axi_priority_rd_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port3 + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port3@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 3. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +0:All bank refresh Per bank refresh allows traffic to flow to other banks. 1:Per bank refresh Per bank refresh is not supported on all LPDDR2 devices. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Power-down mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 0 +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 1 +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDR IOB Slew for Address +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDR IOB Slew for Data +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDR IOB Slew for Diff +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDR IOB Slew for Clock +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SD1_WP_CD_SEL + + +0XF8000834 + +32 + +RW + +0x000000 + +SDIO 1 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 0 +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 1 +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDR IOB Slew for Address +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Data +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Diff +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Clock +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1X: Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors x0: Disable VREF pull-up for lower 16 bits x1: Enable VREF pull-up for lower 16 bits 0x: Disable VREF pull-up for upper 16 bits 1x: Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Enable test mode for VRP and VRN: 00: VRP/VRN test mode not used 11: VRP/VRN test mode enabled using vref based receiver. VRP/VRN control is set using the VRN_OUT, VRP_OUT, VRN_TRI, VRP_TRI fields in the DDRIOB_DCI_CTRL register +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0: no pull-up 1: enable pull-up +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. 0: disable 1: enable +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables pull-up on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3f01 + + + +1601 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3f01 + + + +1601 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1680 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1680 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait 10: NAND Flash IO Bit 7 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 12 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1680 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5 10: NAND Flash IO Bit 3 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 13 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1680 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1680 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1680 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1 10: NAND Flash IO Bit 8 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Output 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2 10: NAND Flash IO Bit 9 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110 TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3 10: NAND Flash IO Bit 10 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6 10: NAND Flash IO Bit 13 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3f01 + + + +1201 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +2e + +2e + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f002e + +SDIO 0 WP CD select +
    +

    +

    Register ( slcr )SD1_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD1_WP_CD_SEL + +0XF8000834 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO1_WP_SEL + +5:0 + +3f + +0 + +0 + +SDIO 1 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO1_CD_SEL + +21:16 + +3f0000 + +9 + +90000 + +SDIO 1 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD1_WP_CD_SEL@0XF8000834 + +31:0 + +3f003f + + + +90000 + +SDIO 1 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass 2 - 65535: baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: start break transmission, 1: stop break transmission. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: 1: start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 0: receiver timeout counter disabled, 1: receiver timeout counter is restarted. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter, 0: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter, 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: disable, 1: enable +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable, 1: enable. When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: 1: transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: 1: receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode: 0: Default UART mode 1: Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select: 0: APB clock, pclk 1: a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: 00: normal 01: automatic cho 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: 0: clock source is uart_clk 1: clock source is uart_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    ENET RESET

    +

    I2C RESET

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset: 0: No reset 1: ACP AXI interface reset output asserted +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0: No reset 1: AXDS3AXI interface reset output asserted +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0: No reset 1: AXDS2 AXI interface reset output asserted +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0: No reset 1: AXDS1 AXI interface reset output asserted +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0: No reset 1: AXDS0 AXI interface reset output asserted +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0: No reset 1: FPGA slave interface 1 reset is asserted +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0: No reset 1: FPGA slave interface 0 reset is asserted +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface: 1: soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0: No reset 1: FPGA master interface 1 reset is asserted +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0: No reset 1: FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 3 peripheral request reset output asserted +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 2 peripheral request reset output asserted +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 1 peripheral request reset output asserted +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 0 peripheral request reset output asserted +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0: No reset 1: FPGA 3 top level reset output asserted +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0: No reset 1: FPGA 2 top level reset output asserted +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0: No reset 1: FPGA 1 top level reset output asserted +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0: No reset 1: FPGA 0 top level reset output asserted +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_2_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CORTEX A9 Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status. 0 - ARM PLL out of lock. 1 - ARM PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is CPU PLL. 10 - Source for generated clock is DDR divided clock. 11 - Source for generated clock is IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CORTEX A9 Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status. 0 - DDR PLL out of lock. 1 - DDR PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Divisor value for the ddr_3xclk +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk) +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status. 0 - IO PLL out of lock. 1 - IO PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 RX Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Linear Quad-SPI Reference Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Reference Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Reference Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP 2X Clock Contol +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +FPGA 0 Output Clock Control +
    + +FPGA1_CLK_CTRL + + +0XF8000180 + +32 + +RW + +0x000000 + +FPGA 1 Output Clock Control +
    + +FPGA2_CLK_CTRL + + +0XF8000190 + +32 + +RW + +0x000000 + +FPGA 2 Output Clock Control +
    + +FPGA3_CLK_CTRL + + +0XF80001A0 + +32 + +RW + +0x000000 + +FPGA 3 Output Clock Control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +6:2:1 ratio clock, if set +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Selects the source used to generate the clock. 0 - Source for generated clock is GEM 0 MIO RX clock. 1 - Source for generated clock is GEM 0 FMIO RX clock. +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +Gigabit Ethernet MAC 0 RX Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source used to generate the clock. 1xx - Source for generated clock is Ethernet 0 FMIO clock. 00x - Source for generated clock is IO PLL. 010 - Source for generated clock is ARM PLL. 011 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +7 + +700 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +701 + +Linear Quad-SPI Reference Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO 0 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +SDIO 1 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a03 + +SDIO Reference Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Reference Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active 0 - Clock is disabled 1 - Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP 2X Clock Contol +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +5 + +500000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +500800 + +FPGA 0 Output Clock Control +
    +

    +

    Register ( slcr )FPGA1_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA1_CLK_CTRL + +0XF8000180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA1_CLK_CTRL@0XF8000180 + +31:0 + +3f03f30 + + + +400500 + +FPGA 1 Output Clock Control +
    +

    +

    Register ( slcr )FPGA2_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA2_CLK_CTRL + +0XF8000190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +2 + +200000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA2_CLK_CTRL@0XF8000190 + +31:0 + +3f03f30 + + + +200500 + +FPGA 2 Output Clock Control +
    +

    +

    Register ( slcr )FPGA3_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA3_CLK_CTRL + +0XF80001A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA3_CLK_CTRL@0XF80001A0 + +31:0 + +3f03f30 + + + +100500 + +FPGA 3 Output Clock Control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Enable the 6:2:1 mode. 1 for 6:3:2:1. 0 for 4:2:2:1. +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +6:2:1 ratio clock, if set +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet MAC 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet MAC 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +1 + +800 + +SDIO 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +LQSPI AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec0c4d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two rank configuration register +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control register +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control register +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control register +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters register 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters register 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters register 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters register 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters register 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM initialization parameters register +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access register +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access register +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM burst 8 read/write register +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ register +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM bank address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT register +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO register +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration register +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold register +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller register 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller register 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller register 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller register 4 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters register +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters register +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown register +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control register +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug register +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing register +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear register +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction register +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status register +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count register +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub register +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control register (2) +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control register (3) +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask register +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 Register +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 Register +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 Register +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 Register +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control Register +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +82 + +82 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Only present for multi-rank configurations. Each bit represents one rank. 1=populated; 0=unpopulated 01 = One Rank 11 = Two Ranks Others = Reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +00 = block read/write scheduling for 1-cycle when Write requires changing ODT settings 01 = block read/write scheduling for 2 cycles when Write requires changing ODT settings 10 = block read/write scheduling for 3 cycles when Write requires changing ODT settings 11 = Reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0 = schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1 = schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81082 + +Two rank configuration register +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of clocks that the HPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control register +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control register +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control register +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a1 + +2840 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks DRAM RELATED +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4285b + +DRAM Parameters register 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +13 + +13 + +Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. LPDDR2 mode: Set this to the larger of tCKE or tCKESR. Non-LPDDR2 designs: Set this to tCKE value. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d3 + +DRAM Parameters register 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2/3 -> WL -1 LPDDR -> 1 LPDDR2 ->WL Where WL = Write Latency of DRAM DRAM RELATED. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. non-LPDDR2 -> RL + BL/2 + 2 - WL LPDDR2 -> RL + BL/2 + RU(tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +f + +3c00 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +5 + +28000 + +tXP: Minimum time after power down exit to any operation. DRAM RELATED. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +5 + +2800000 + +Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency DRAM RELATED +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +7282bce5 + +DRAM Parameters register 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1 DRAM RELATED +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1 = sdram device 0 = non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-mobile DRAM device in use. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +1=enable the assertion of stop_clk to the PHY whenever a clock is not required by LPDDR/ LPDDR2. 0=stop_clk will never be asserted. Note: This is only present for implementations supporting LPDDR/LPDDR2 devices. +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Set to RL. Time from Read command to Read data on DRAM interface. Unit: clocks This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. RL = Read Latency of DRAM Note: This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1 = disable the pad power down feature 0 = Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters register 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1 = DDRC will use 2T timing 0 = DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1 = Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and 'ddrc_reg_mr_wr_busy' is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +Mode register address - for non-LPDDR2 modes. This register is don't care in LPDDR2 mode 00 = MR0 01 = MR1 10 = MR2 11 = MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +Mode register write data - for non-LPDDR2 modes. For LPDDR2, these 16-bits are interpreted as Writes: \'7bMR Addr[7:0], MR Data[7:0]\'7d. Reads: \'7bMR Addr[7:0], Don't Care[7:0]\'7d +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 1 = Indicates that mode register write / read operation is in progress. 0 = Indicates that the core can initiate a mode register write / read operation. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 1 = read 0 = write +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 1'b0 by default. This bit will be cleared (1'b0), whenever a Mode Register Read command is issued. This bit will be set to 1'b1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters register 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands DRAM RELATED Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM initialization parameters register +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +Non LPDDR2- Value to be loaded into DRAM EMR2 registers. For LPDDR2 - Value to Write to the MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +Non LPDDR2- Value to be loaded into DRAM EMR3 registers. Used in non-LPDDR2 designs only. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access register +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +b30 + +b30 + +Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +Non LPDDR2-Value to be loaded into DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. For LPDDR2 - Value to Write to the MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40b30 + +DRAM EMR, MR access register +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +This controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. In LPDDR and LPDDR2, Burst length of 16 is supported only in Half Bus Width mode. Every input read/write command has 4 cycles of data associated with it and that is not enough data for doing Burst Length16 in Full Bus Width mode. 0010 - Burst length of 4 0100 - Burst length of 8 1000 - Burst length of 16 (only supported for LPDDR AND LPDDR2) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM burst 8 read/write register +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Active Low signal. When asserted (0), all incoming transactions will be forced to low priority. Forcing the incoming transactions to low priority implicitly turns OFF Bypass. Otherwise, HPR is allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. This bit is intended to be switched on-the-fly +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ register +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14 Internal Base: 5 The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Selects the address bits used as DRAM bank address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Selects the address bits used as DRAM column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Selects the address bits used as DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODT's must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT register +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1 = stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO register +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration register +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable for LPDDR and LPDDR2 modes. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold register +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +When 1, disable Write Combine +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to '0', auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller register 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +1 - Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on 'urgent' input coming from AXI master. 0 - Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 1'b0. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller register 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) Only present in designs that support DDR3 and LPDDR2 devices. +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Only present in designs that support DDR3 devices +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. Only present in designs that support DDR3 devices. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller register 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller register 4 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters register +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters register +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +1 - Controller puts the DRAM into Deep Powerdown mode when the transaction store is empty. 0 - Brings Controller out of Deep Powerdown mode Present only in designs configured to support LPDDR or LPDDR2 FOR PERFORMANCE ONLY. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown register +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +1 = Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0 = Write leveling disabled. +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +1 = Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0= Read DQS gate leveling is disabled. +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +1 = Read Data Eye training mode has been enabled as part of init sequence. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control register +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1 - Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0 - Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug register +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. Non-LPDDR -> RL-1 LPDDR -> RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing register +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear register +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when a correctable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction register +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when an uncorrectable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status register +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count register +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 3'b000 (No ECC) and 3'b100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 3'b100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 - No ECC, 001 - Reserved 010 - Parity 011 - Reserved 100 - SEC/DED over 1-beat 101 - SEC/DED over multiple beats 110 - Device Correction 111 - Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +This feature is NOT supported. Only default value works. 1 - Disable ECC scrubs 0 - Enable ECC scrubs Valid only when reg_ddrc_ecc_mode = 3'b100. +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub register +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +1 = run scan test at full clock speed but with less coverage 0 = run scan test at slow clock speed but with high coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 2'b00: constant pattern (0 repeated on each DQ bit) 2'b01: low freq pattern (00001111 repeated on each DQ bit) 2'b10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +1=assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) 0=(default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0 = Select algorithm # 1'b1 = Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 1- Rank 0 delays are used for all ranks 0- Each Rank uses its own delay +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-LPDDR DRAM device in use. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1=enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control register (2) +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control register (3) +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +This register must be set based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask register +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +1=LPDDR2 DRAM device in Use. 0=non-LPDDR2 device in use Present only in designs configured to support LPDDR2. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +1:Per bank refresh 0:All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported on all LPDDR2 devices. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 Register +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. Present only in designs configured to support LPDDR2. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 Register +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 Register +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 Register +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control Register +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0 = DDRC Init 1 = Normal operation 2 = Power-down mode 3 = Self-refresh mode 4 and above = deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDRIOB Address 0 Configuartion Register +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDRIOB Address 1 Configuration Register +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDRIOB Differential Clock Configuration Register +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Address Register +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Data Register +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Differential Strobe Register +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Clcok Register +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDRIOB DDR Control Register +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Control for Pin 0 +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Control for Pin 1 +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Control for Pin 2 +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Control for Pin 3 +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Control for Pin 4 +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Control for Pin 5 +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Control for Pin 6 +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Control for Pin 8 +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Control for Pin 9 +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Control for Pin 10 +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Control for Pin 11 +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Control for Pin 12 +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Control for Pin 13 +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Control for Pin 14 +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Control for Pin 15 +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Control for Pin 16 +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Control for Pin 17 +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Control for Pin 18 +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Control for Pin 19 +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Control for Pin 20 +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Control for Pin 21 +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Control for Pin 22 +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Control for Pin 23 +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Control for Pin 24 +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Control for Pin 25 +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Control for Pin 26 +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Control for Pin 27 +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Control for Pin 40 +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Control for Pin 41 +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Control for Pin 42 +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Control for Pin 43 +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Control for Pin 44 +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Control for Pin 45 +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Control for Pin 46 +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Control for Pin 47 +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Control for Pin 48 +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Control for Pin 49 +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Control for Pin 52 +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Control for Pin 53 +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select register +
    + +SD1_WP_CD_SEL + + +0XF8000834 + +32 + +RW + +0x000000 + +SDIO 1 WP CD select register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDRIOB Address 0 Configuartion Register +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDRIOB Address 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDRIOB Differential Clock Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDRIOB Drive Slew Address Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Data Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Differential Strobe Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Clcok Register +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output 0001 - VREF = 0.6V for LPDDR2 with 1.2V IO 0010 - VREF = 0.675V for LPDDR3 1.35 V IO 0100 - VREF = 0.75V for DDR3 with 1.5V IO 1000 - VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input X0 - Disable External VREF for lower 16 bits X1 - Enable External VREF for lower 16 bits 0X - Disable External VREF for upper 16 bits 1X - Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors X0 - Disable VREF pull-up for lower 16 bits X1 - Enable VREF pull-up for lower 16 bits 0X - Disable VREF pull-up for upper 16 bits 1X - Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0 - VRP/VRN not used 1 - VRP/VRN used as refio +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +73ff + + + +260 + +DDRIOB DDR Control Register +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3f01 + + + +1601 + +MIO Control for Pin 0 +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Control for Pin 1 +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 2 +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Control for Pin 3 +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 4 +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 5 +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 6 +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 8 +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3f01 + + + +1601 + +MIO Control for Pin 9 +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 10 +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 11 +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_wait- (SRAM Wait State indicator) 2= nand, Input, smc_nand_data_in[7]- (NAND Data Bus) = nand, Output, smc_nand_data_out[7]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 12 +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[5]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[5]- (SRAM Data) 2= nand, Input, smc_nand_data_in[3]- (NAND Data Bus) = nand, Output, smc_nand_data_out[3]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 13 +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 14 +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 15 +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[4]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[1]- (SRAM Address) 2= nand, Input, smc_nand_data_in[8]- (NAND Data Bus) = nand, Output, smc_nand_data_out[8]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 16 +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[5]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[2]- (SRAM Address) 2= nand, Input, smc_nand_data_in[9]- (NAND Data Bus) = nand, Output, smc_nand_data_out[9]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 17 +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[6]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[3]- (SRAM Address) 2= nand, Input, smc_nand_data_in[10]- (NAND Data Bus) = nand, Output, smc_nand_data_out[10]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 18 +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 19 +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 20 +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[6]- (SRAM Address) 2= nand, Input, smc_nand_data_in[13]- (NAND Data Bus) = nand, Output, smc_nand_data_out[13]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 21 +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 22 +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 23 +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 24 +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 25 +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 26 +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 27 +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 40 +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 41 +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 42 +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 43 +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 44 +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 45 +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3f01 + + + +1201 + +MIO Control for Pin 46 +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Control for Pin 47 +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Control for Pin 48 +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Control for Pin 49 +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 52 +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 53 +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +2e + +2e + +SDIO0 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO0 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f002e + +SDIO 0 WP CD select register +
    +

    +

    Register ( slcr )SD1_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD1_WP_CD_SEL + +0XF8000834 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO1_WP_SEL + +5:0 + +3f + +0 + +0 + +SDIO1 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SDIO1_CD_SEL + +21:16 + +3f0000 + +9 + +90000 + +SDIO1 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SD1_WP_CD_SEL@0XF8000834 + +31:0 + +3f003f + + + +90000 + +SDIO 1 WP CD select register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value 0 = Disables baud_sample 1 = Clock divisor bypass 2 - 65535 = baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break. 1 = stop transmission of the break. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break 1 = start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter 1 = receiver timeout counter is restarted +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable. 1, the transmitter is disabled +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable. 1, the transmitter is enabled, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable. 1= receiver is enabled +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable. 1=the receiver logic is enabled, provided RXDIS field is set to 0 +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for TX data path. 1=the transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for RX data path 1=receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode 0 : Default UART mode 1 : Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select 0 : APB clock, pclk 1 : a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode 00 = normal 01 = automatic cho 10 = local loopback 11 = remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits 00 = 1 stop bit 01 = 1.5 stop bits 10 = 2 stop bits 11 = reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select. 000 = even parity 001 = odd parity 010 = forced to 0 parity (space) 011 = forced to 1 parity (mark) 1xx = no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select 11 = 6 bits 10 = 7 bits 01 / 00 = 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +clock source select 1 = clock source is uart_clk/8 0 = clock source is uart_clk +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    ENET RESET

    +

    I2C RESET

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset. 0 - No reset. 1 - ACP AXI interface reset output asserted. +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS3AXI interface reset output asserted. +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS2 AXI interface reset output asserted. +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS1 AXI interface reset output asserted. +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS0 AXI interface reset output asserted. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 1 reset is asserted. +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 0 reset is asserted. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface 1 soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0 - No reset. 1 - FPGA master interface 1 reset is asserted. +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0 - No reset. 1 - FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 3 peripheral request reset output asserted. +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 2 peripheral request reset output asserted. +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 1 peripheral request reset output asserted. +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 0 peripheral request reset output asserted. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0 - No reset. 1 - FPGA 3 top level reset output asserted. +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0 - No reset. 1 - FPGA 2 top level reset output asserted. +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0 - No reset. 1 - FPGA 1 top level reset output asserted. +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0 - No reset. 1 - FPGA 0 top level reset output asserted. +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_1_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/ps7_init.tcl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/ps7_init.tcl new file mode 100755 index 0000000..85a6f34 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/ps7_init.tcl @@ -0,0 +1,781 @@ +proc ps7_pll_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000701 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00500800 + mask_write 0XF8000180 0x03F03F30 0x00400500 + mask_write 0XF8000190 0x03F03F30 0x00200500 + mask_write 0XF80001A0 0x03F03F30 0x00100500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_3_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x0007FFFF 0x00001082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006024 0x0FFFFFC3 0x00000000 + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00000003 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x0003F03F 0x0003C008 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x00010000 0x00000000 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x00000200 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFCF 0x40000001 + mask_write 0XF800611C 0x7FFFFFCF 0x40000001 + mask_write 0XF8006120 0x7FFFFFCF 0x40000001 + mask_write 0XF8006124 0x7FFFFFCF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0x6FFFFEFE 0x00040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000703FF 0x000003FF + mask_write 0XF800620C 0x000703FF 0x000003FF + mask_write 0XF8006210 0x000703FF 0x000003FF + mask_write 0XF8006214 0x000703FF 0x000003FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF5 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000001 0x00000001 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001601 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003F01 0x00001601 + mask_write 0XF8000728 0x00003FFF 0x00001680 + mask_write 0XF800072C 0x00003FFF 0x00001680 + mask_write 0XF8000730 0x00003FFF 0x00001680 + mask_write 0XF8000734 0x00003FFF 0x00001680 + mask_write 0XF8000738 0x00003FFF 0x00001680 + mask_write 0XF800073C 0x00003FFF 0x00001680 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003F01 0x00001201 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F002E + mask_write 0XF8000834 0x003F003F 0x00090000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x000003FF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 +} +proc ps7_post_config_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_3_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000701 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00500800 + mask_write 0XF8000180 0x03F03F30 0x00400500 + mask_write 0XF8000190 0x03F03F30 0x00200500 + mask_write 0XF80001A0 0x03F03F30 0x00100500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_2_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001601 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003F01 0x00001601 + mask_write 0XF8000728 0x00003FFF 0x00001680 + mask_write 0XF800072C 0x00003FFF 0x00001680 + mask_write 0XF8000730 0x00003FFF 0x00001680 + mask_write 0XF8000734 0x00003FFF 0x00001680 + mask_write 0XF8000738 0x00003FFF 0x00001680 + mask_write 0XF800073C 0x00003FFF 0x00001680 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003F01 0x00001201 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F002E + mask_write 0XF8000834 0x003F003F 0x00090000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 +} +proc ps7_post_config_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_2_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000701 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00500800 + mask_write 0XF8000180 0x03F03F30 0x00400500 + mask_write 0XF8000190 0x03F03F30 0x00200500 + mask_write 0XF80001A0 0x03F03F30 0x00100500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_1_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x000073FF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001601 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003F01 0x00001601 + mask_write 0XF8000728 0x00003FFF 0x00001680 + mask_write 0XF800072C 0x00003FFF 0x00001680 + mask_write 0XF8000730 0x00003FFF 0x00001680 + mask_write 0XF8000734 0x00003FFF 0x00001680 + mask_write 0XF8000738 0x00003FFF 0x00001680 + mask_write 0XF800073C 0x00003FFF 0x00001680 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003F01 0x00001201 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F002E + mask_write 0XF8000834 0x003F003F 0x00090000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 +} +proc ps7_post_config_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_1_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +set PCW_SILICON_VER_1_0 "0x0" +set PCW_SILICON_VER_2_0 "0x1" +set PCW_SILICON_VER_3_0 "0x2" +set APU_FREQ 666666666 + + + +proc mask_poll { addr mask } { + set count 1 + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + while { $maskedval == 0 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + set count [ expr { $count + 1 } ] + if { $count == 100000000 } { + puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask" + break + } + } +} + + + +proc mask_delay { addr val } { + set delay [ get_number_of_cycles_for_delay $val ] + perf_reset_and_start_timer + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + while { $maskedval == 1 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + } + perf_reset_clock +} + +proc ps_version { } { + set si_ver "0x[string range [mrd 0xF8007080] end-8 end]" + set mask_sil_ver "0x[expr {$si_ver >> 28}]" + return $mask_sil_ver; +} + +proc ps7_post_config {} { + set saved_mode [configparams force-mem-accesses] + configparams force-mem-accesses 1 + + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_post_config_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_post_config_2_0 + } else { + ps7_post_config_3_0 + } + configparams force-mem-accesses $saved_mode +} + +proc ps7_debug {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_debug_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_debug_2_0 + } else { + ps7_debug_3_0 + } +} +proc ps7_init {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_mio_init_data_1_0 + ps7_pll_init_data_1_0 + ps7_clock_init_data_1_0 + ps7_ddr_init_data_1_0 + ps7_peripherals_init_data_1_0 + #puts "PCW Silicon Version : 1.0" + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_mio_init_data_2_0 + ps7_pll_init_data_2_0 + ps7_clock_init_data_2_0 + ps7_ddr_init_data_2_0 + ps7_peripherals_init_data_2_0 + #puts "PCW Silicon Version : 2.0" + } else { + ps7_mio_init_data_3_0 + ps7_pll_init_data_3_0 + ps7_clock_init_data_3_0 + ps7_ddr_init_data_3_0 + ps7_peripherals_init_data_3_0 + #puts "PCW Silicon Version : 3.0" + } +} + + +# For delay calculation using global timer + +# start timer + proc perf_start_clock { } { + + #writing SCU_GLOBAL_TIMER_CONTROL register + + mask_write 0xF8F00208 0x00000109 0x00000009 +} + +# stop timer and reset timer count regs + proc perf_reset_clock { } { + perf_disable_clock + mask_write 0xF8F00200 0xFFFFFFFF 0x00000000 + mask_write 0xF8F00204 0xFFFFFFFF 0x00000000 +} + +# Compute mask for given delay in miliseconds +proc get_number_of_cycles_for_delay { delay } { + + # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + variable APU_FREQ + return [ expr ($delay * $APU_FREQ /(2 * 1000))] +} + + +# stop timer +proc perf_disable_clock {} { + mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 +} + +proc perf_reset_and_start_timer {} { + perf_reset_clock + perf_start_clock +} + + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/ps7_init_gpl.h b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/ps7_init_gpl.h new file mode 100755 index 0000000..45a7839 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/ps7_init_gpl.h @@ -0,0 +1,131 @@ +/****************************************************************************** +* +* Copyright (C) 2010-2020 +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, see +* +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init_gpl.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + + + + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 142857132 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 25000000 +#define FPGA1_FREQ 50000000 +#define FPGA2_FREQ 100000000 +#define FPGA3_FREQ 200000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/xilinx-zynq.cc b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/xilinx-zynq.cc new file mode 100755 index 0000000..14e40f9 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/mem_init_files/xilinx-zynq.cc @@ -0,0 +1,106 @@ +/* + * Xilinx SystemC/TLM-2.0 Zynq Wrapper. + * + * Written by Edgar E. Iglesias + * + * Copyright (c) 2016, Xilinx Inc. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#define SC_INCLUDE_DYNAMIC_PROCESSES + +#include + +#include "tlm_utils/simple_initiator_socket.h" +#include "tlm_utils/simple_target_socket.h" + +using namespace sc_core; +using namespace std; + +#include "xilinx-zynq.h" +#include + +//xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr, +// Iremoteport_tlm_sync *sync) +// : remoteport_tlm(name, -1, sk_descr, sync), +xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr) + : remoteport_tlm(name, -1, sk_descr), + rp_m_axi_gp0("rp_m_axi_gp0"), + rp_m_axi_gp1("rp_m_axi_gp1"), + rp_s_axi_gp0("rp_s_axi_gp0"), + rp_s_axi_gp1("rp_s_axi_gp1"), + rp_s_axi_hp0("rp_s_axi_hp0"), + rp_s_axi_hp1("rp_s_axi_hp1"), + rp_s_axi_hp2("rp_s_axi_hp2"), + rp_s_axi_hp3("rp_s_axi_hp3"), + rp_s_axi_acp("rp_s_axi_acp"), + rp_wires_in("wires_in", 20, 0), + rp_wires_out("wires_out", 0, 17), + rp_irq_out("irq_out", 0, 28), + pl2ps_irq("pl2ps_irq", 20), + ps2pl_irq("ps2pl_irq", 28), + ps2pl_rst("ps2pl_rst", 17) +{ + int i; + + m_axi_gp[0] = &rp_m_axi_gp0.sk; + m_axi_gp[1] = &rp_m_axi_gp1.sk; + + s_axi_gp[0] = &rp_s_axi_gp0.sk; + s_axi_gp[1] = &rp_s_axi_gp1.sk; + + s_axi_hp[0] = &rp_s_axi_hp0.sk; + s_axi_hp[1] = &rp_s_axi_hp1.sk; + s_axi_hp[2] = &rp_s_axi_hp2.sk; + s_axi_hp[3] = &rp_s_axi_hp3.sk; + s_axi_acp = &rp_s_axi_acp.sk; + + /* PL to PS Interrupt signals. */ + for (i = 0; i < 20; i++) { + rp_wires_in.wires_in[i](pl2ps_irq[i]); + } + + /* PS to PL Interrupt signals. */ + for (i = 0; i < 28; i++) { + rp_irq_out.wires_out[i](ps2pl_irq[i]); + } + + /* PS to PL resets. */ + for (i = 0; i < 17; i++) { + rp_wires_out.wires_out[i](ps2pl_rst[i]); + } + + register_dev(0, &rp_s_axi_gp0); + register_dev(1, &rp_s_axi_gp1); + + register_dev(2, &rp_s_axi_hp0); + register_dev(3, &rp_s_axi_hp1); + register_dev(4, &rp_s_axi_hp2); + register_dev(5, &rp_s_axi_hp3); + + register_dev(6, &rp_s_axi_acp); + + register_dev(7, &rp_m_axi_gp0); + register_dev(8, &rp_m_axi_gp1); + register_dev(9, &rp_wires_in); + register_dev(10, &rp_wires_out); + register_dev(11, &rp_irq_out); +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/Makefile b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/Makefile new file mode 100755 index 0000000..33394b3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/Makefile @@ -0,0 +1,26 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +INCLUDEFILES=*.h +LIBSOURCES=*.c +OUTS = *.o + +libs: + echo "Compiling SPI_Con..." + $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} + make clean + +include: + ${CP} $(INCLUDEFILES) $(INCLUDEDIR) + +clean: + rm -rf ${OUTS} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/NewExtInst_TOP.bda b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/NewExtInst_TOP.bda new file mode 100755 index 0000000..ab7b1f9 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/NewExtInst_TOP.bda @@ -0,0 +1,272 @@ +{ + "graphjs": { + "version": "1.0", + "keys": [ + { + "abrv": "VH", + "name": "vert_hid", + "type": "int", + "for": "node" + }, + { + "abrv": "VM", + "name": "vert_name", + "type": "string", + "for": "node" + }, + { + "abrv": "VT", + "name": "vert_type", + "type": "string", + "for": "node" + }, + { + "abrv": "BA", + "name": "base_addr", + "type": "string", + "for": "node" + }, + { + "abrv": "HA", + "name": "high_addr", + "type": "string", + "for": "node" + }, + { + "abrv": "BP", + "name": "base_param", + "type": "string", + "for": "node" + }, + { + "abrv": "HP", + "name": "high_param", + "type": "string", + "for": "node" + }, + { + "abrv": "MA", + "name": "master_addrspace", + "type": "string", + "for": "node" + }, + { + "abrv": "MX", + "name": "master_instance", + "type": "string", + "for": "node" + }, + { + "abrv": "MI", + "name": "master_interface", + "type": "string", + "for": "node" + }, + { + "abrv": "MS", + "name": "master_segment", + "type": "string", + "for": "node" + }, + { + "abrv": "MV", + "name": "master_vlnv", + "type": "string", + "for": "node" + }, + { + "abrv": "SX", + "name": "slave_instance", + "type": "string", + "for": "node" + }, + { + "abrv": "SI", + "name": "slave_interface", + "type": "string", + "for": "node" + }, + { + "abrv": "MM", + "name": "slave_memmap", + "type": "string", + "for": "node" + }, + { + "abrv": "SS", + "name": "slave_segment", + "type": "string", + "for": "node" + }, + { + "abrv": "SV", + "name": "slave_vlnv", + "type": "string", + "for": "node" + }, + { + "abrv": "TM", + "name": "memory_type", + "type": "string", + "for": "node" + }, + { + "abrv": "TU", + "name": "usage_type", + "type": "string", + "for": "node" + }, + { + "abrv": "LT", + "name": "lock_type", + "type": "string", + "for": "node" + }, + { + "abrv": "BT", + "name": "boot_type", + "type": "string", + "for": "node" + }, + { + "abrv": "EH", + "name": "edge_hid", + "type": "int", + "for": "edge" + } + ], + "vertice_type_order": [ + { + "abrv": "BC", + "desc": "Block Container" + }, + { + "abrv": "PR", + "desc": "Parital Reference" + }, + { + "abrv": "VR", + "desc": "Variant" + }, + { + "abrv": "PM", + "desc": "Variant Permutations" + }, + { + "abrv": "CX", + "desc": "Boundary Connection" + }, + { + "abrv": "AC", + "desc": "Assignment Coordinate" + }, + { + "abrv": "ACE", + "desc": "Excluded Assign Coordinate" + }, + { + "abrv": "APX", + "desc": "Boundary Aperture" + }, + { + "abrv": "CIP", + "desc": "High level Processing System" + } + ], + "vertices": { + "V0": { + "VM": "NewExtInst_TOP", + "VT": "BC" + }, + "V1": { + "VH": "2", + "VM": "NewExtInst_TOP", + "VT": "VR" + }, + "V2": { + "VH": "2", + "VT": "PM", + "TU": "active" + }, + "V3": { + "VT": "AC", + "BA": "0x43C00000", + "HA": "0x43C0FFFF", + "BP": "C_S00_AXI_BASEADDR", + "HP": "C_S00_AXI_HIGHADDR", + "MA": "Data", + "MX": "/processing_system7_0", + "MI": "M_AXI_GP0", + "MS": "SEG_SPI_Con_0_S00_AXI_reg", + "MV": "xilinx.com:ip:processing_system7:5.5", + "SX": "/SPI_Con_0", + "SI": "S00_AXI", + "SS": "S00_AXI_reg", + "SV": "xilinx.com:user:SPI_Con:1.0", + "TM": "both", + "TU": "register" + }, + "V4": { + "VT": "AC", + "BA": "0x43C10000", + "HA": "0x43C1FFFF", + "BP": "C_S00_AXI_BASEADDR", + "HP": "C_S00_AXI_HIGHADDR", + "MA": "Data", + "MX": "/processing_system7_0", + "MI": "M_AXI_GP0", + "MS": "SEG_SPI_Con_1_S00_AXI_reg", + "MV": "xilinx.com:ip:processing_system7:5.5", + "SX": "/SPI_Con_1", + "SI": "S00_AXI", + "SS": "S00_AXI_reg", + "SV": "xilinx.com:user:SPI_Con:1.0", + "TM": "both", + "TU": "register" + }, + "V5": { + "VT": "AC", + "BA": "0x43C20000", + "HA": "0x43C2FFFF", + "BP": "C_S00_AXI_BASEADDR", + "HP": "C_S00_AXI_HIGHADDR", + "MA": "Data", + "MX": "/processing_system7_0", + "MI": "M_AXI_GP0", + "MS": "SEG_SPI_Con_2_S00_AXI_reg", + "MV": "xilinx.com:ip:processing_system7:5.5", + "SX": "/SPI_Con_2", + "SI": "S00_AXI", + "SS": "S00_AXI_reg", + "SV": "xilinx.com:user:SPI_Con:1.0", + "TM": "both", + "TU": "register" + } + }, + "edges": [ + { + "src": "V0", + "trg": "V1" + }, + { + "src": "V1", + "trg": "V2" + }, + { + "src": "V3", + "trg": "V2", + "EH": "2" + }, + { + "src": "V4", + "trg": "V2", + "EH": "2" + }, + { + "src": "V5", + "trg": "V2", + "EH": "2" + } + ] + } +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/NewExtInst_TOP.sh b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/NewExtInst_TOP.sh new file mode 100755 index 0000000..4623992 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/NewExtInst_TOP.sh @@ -0,0 +1,258 @@ +#!/usr/bin/env bash +#********************************************************************************************************** +# Vivado (TM) v2023.2 (64-bit) +# +# Script generated by Vivado on Fri May 15 15:32:22 CST 2026 +# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 +# +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# +# Filename : NewExtInst_TOP.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script generated by export_simulation Tcl command +# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the +# design. The script will copy the library mapping file from the compiled library directory, +# create design library directories and library mappings in the mapping file. +# +# Usage : NewExtInst_TOP.sh +# NewExtInst_TOP.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]* +# NewExtInst_TOP.sh [-reset_run] +# NewExtInst_TOP.sh [-reset_log] +# NewExtInst_TOP.sh [-help] +# +# * The -noclean_files switch is deprecated and will not peform any function (by default, the +# simulator generated files will not be removed unless -reset_run switch is used) +# +# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library +# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help' +# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path +# switch with the directory path where the library is created while generating the script +# with export_simulation. +# +# Alternatively, you can set the library path by setting the following project property:- +# +# set_property compxlib._compiled_library_dir [current_project] +# +# You can also point to the simulation library by either setting the 'lib_map_path' global +# variable in this script or specify it with the '-lib_map_path' switch while executing this +# script (type 'NewExtInst_TOP.sh -help' for more information). +# +# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the +# generated script, but if design is targetted for system simulation containing SystemC/C++/C +# sources, then the library path MUST be specified upfront when calling export_simulation. +# +# For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************** + +# script info +echo -e "NewExtInst_TOP.sh - Script generated by export_simulation (Vivado v2023.2 (64-bit)-id)\n" + +# main steps +run() +{ + check_args $* + setup + if [[ ($b_step == 1) ]]; then + case $step in + "compile" ) + init_lib + compile + ;; + "simulate" ) + simulate + ;; + * ) + echo -e "ERROR: Invalid or missing step '$step' (type \"./NewExtInst_TOP.sh -help\" for more information)\n" + exit 1 + esac + else + init_lib + compile + simulate + fi +} + +# RUN_STEP: +compile() +{ + runvsimsa -do "do {compile.do}" 2>&1 | tee -a compile.log +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + # delete previous files for a clean rerun + if [[ ($b_reset_run == 1) ]]; then + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + fi + + # delete previous log files + if [[ ($b_reset_log == 1) ]]; then + reset_log + echo -e "INFO: Simulation run log files deleted.\n" + exit 0 + fi + + # add any setup/initialization commands here:- + + # + +} + +# simulator index file/library directory processing +init_lib() +{ + if [[ ($b_keep_index == 1) ]]; then + # keep previous design library mappings + true + else + # map simulator index file + map_setup_file + fi +} + +# map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# delete generated log files from the previous run +reset_log() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# check switch argument value +check_arg_value() +{ + if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "simulate")) ]];then + echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then + echo -e "ERROR: Simulation library directory path not specified (type \"./NewExtInst_TOP.sh -help\" for more information)\n" + exit 1 + fi +} + +# check command line arguments +check_args() +{ + arg_count=$# + if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then + usage + fi + while [[ "$#" -gt 0 ]]; do + case $1 in + -step) check_arg_value $1 $2;step=$2; b_step=1; shift;; + -lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;; + -gen_bypass) b_gen_bypass=1 ;; + -reset_run) b_reset_run=1 ;; + -reset_log) b_reset_log=1 ;; + -keep_index) b_keep_index=1 ;; + -noclean_files) b_noclean_files=1 ;; + -help|-h) ;; + *) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;; + esac + shift + done + + # -reset_run is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then + echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -reset_log is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then + echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -keep_index is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then + echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -noclean_files is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then + echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi +} + +# script usage +usage() +{ + msg="Usage: NewExtInst_TOP.sh [-help]\n\ +Usage: NewExtInst_TOP.sh [-step]\n\ +Usage: NewExtInst_TOP.sh [-lib_map_path]\n\ +Usage: NewExtInst_TOP.sh [-reset_run]\n\ +Usage: NewExtInst_TOP.sh [-reset_log]\n\ +Usage: NewExtInst_TOP.sh [-keep_index]\n\ +Usage: NewExtInst_TOP.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-step ] -- Execute specified step (compile, simulate)\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\ +file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\ +NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\ +NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\ +[-reset_log] -- Delete simulator generated log files from the previous run\n\n\ +[-keep_index] -- Keep simulator index file settings from the previous run\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n" + echo -e $msg + exit 0 +} + +# initialize globals +step="" +lib_map_path="" +b_step=0 +b_lib_map_path=0 +b_gen_bypass=0 +b_reset_run=0 +b_reset_log=0 +b_keep_index=0 +b_noclean_files=0 + +# launch script +run $* diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/NewExtInst_TOP.udo b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/NewExtInst_TOP.udo new file mode 100644 index 0000000..e69de29 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/README.txt b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/README.txt new file mode 100644 index 0000000..1d27b8b --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/README.txt @@ -0,0 +1,50 @@ +################################################################################ +# Vivado (TM) v2023.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and how to fetch design source file details +# from the file_info.txt file. +# +# Generated by export_simulation on Fri May 15 15:32:22 CST 2026 +# +################################################################################ + +1. Steps to run the generated simulation script + +From the shell prompt in the current directory, issue the following command:- + +./NewExtInst_TOP.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first calls the 'check_args' function, the purpose of which +is to verify the generated script arguments and print error if incorrect switch +is specified. The 'run' function then calls the 'setup' function, the purpose of +which is to specify custom or initialization commands. The function also executes +following sub-functions:- +'reset_run' if -reset_run switch is specified. +'reset_log' if -reset_log switch is specified. + +The purpose of 'reset_run' function' is to delete the simulator generated design +data from the previous run and the purpose of 'reset_log' function' is to delete +the simulator generated log files. + +The 'run' function then calls the 'init_lib' function, the purpose of which is to +create design library mappings and directories. This function is called before the +'compile' step. By default, if '-step' switch is specified with the script then the +script will execute that specfic step, else it will execute all steps applicable +for the target simulator. + +For more information on the script, please type './NewExtInst_TOP.sh -help' + +2. Design source file information + +export_simulation generates a 'file_info.txt' file that contains design file information +based on the compile order when export_simulation was executed from Vivado. The file +contains information about the file name, type, library it is compiled into, whether +it is part of the IP, associated library, file path information in a comma separated +format. This file can be parsed to extract the required information for generating a +custom script or can be read from verification test infra. + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/SPI_Con.h b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/SPI_Con.h new file mode 100755 index 0000000..5278bdd --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/SPI_Con.h @@ -0,0 +1,107 @@ + +#ifndef SPI_CON_H +#define SPI_CON_H + + +/****************** Include Files ********************/ +#include "xil_types.h" +#include "xstatus.h" + +#define SPI_CON_S00_AXI_SLV_REG0_OFFSET 0 +#define SPI_CON_S00_AXI_SLV_REG1_OFFSET 4 +#define SPI_CON_S00_AXI_SLV_REG2_OFFSET 8 +#define SPI_CON_S00_AXI_SLV_REG3_OFFSET 12 +#define SPI_CON_S00_AXI_SLV_REG4_OFFSET 16 +#define SPI_CON_S00_AXI_SLV_REG5_OFFSET 20 +#define SPI_CON_S00_AXI_SLV_REG6_OFFSET 24 +#define SPI_CON_S00_AXI_SLV_REG7_OFFSET 28 +#define SPI_CON_S00_AXI_SLV_REG8_OFFSET 32 +#define SPI_CON_S00_AXI_SLV_REG9_OFFSET 36 +#define SPI_CON_S00_AXI_SLV_REG10_OFFSET 40 +#define SPI_CON_S00_AXI_SLV_REG11_OFFSET 44 +#define SPI_CON_S00_AXI_SLV_REG12_OFFSET 48 +#define SPI_CON_S00_AXI_SLV_REG13_OFFSET 52 +#define SPI_CON_S00_AXI_SLV_REG14_OFFSET 56 +#define SPI_CON_S00_AXI_SLV_REG15_OFFSET 60 +#define SPI_CON_S00_AXI_SLV_REG16_OFFSET 64 +#define SPI_CON_S00_AXI_SLV_REG17_OFFSET 68 +#define SPI_CON_S00_AXI_SLV_REG18_OFFSET 72 +#define SPI_CON_S00_AXI_SLV_REG19_OFFSET 76 +#define SPI_CON_S00_AXI_SLV_REG20_OFFSET 80 +#define SPI_CON_S00_AXI_SLV_REG21_OFFSET 84 +#define SPI_CON_S00_AXI_SLV_REG22_OFFSET 88 +#define SPI_CON_S00_AXI_SLV_REG23_OFFSET 92 +#define SPI_CON_S00_AXI_SLV_REG24_OFFSET 96 +#define SPI_CON_S00_AXI_SLV_REG25_OFFSET 100 +#define SPI_CON_S00_AXI_SLV_REG26_OFFSET 104 +#define SPI_CON_S00_AXI_SLV_REG27_OFFSET 108 +#define SPI_CON_S00_AXI_SLV_REG28_OFFSET 112 +#define SPI_CON_S00_AXI_SLV_REG29_OFFSET 116 +#define SPI_CON_S00_AXI_SLV_REG30_OFFSET 120 +#define SPI_CON_S00_AXI_SLV_REG31_OFFSET 124 + + +/**************************** Type Definitions *****************************/ +/** + * + * Write a value to a SPI_CON register. A 32 bit write is performed. + * If the component is implemented in a smaller width, only the least + * significant data is written. + * + * @param BaseAddress is the base address of the SPI_CONdevice. + * @param RegOffset is the register offset from the base to write to. + * @param Data is the data written to the register. + * + * @return None. + * + * @note + * C-style signature: + * void SPI_CON_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data) + * + */ +#define SPI_CON_mWriteReg(BaseAddress, RegOffset, Data) \ + Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data)) + +/** + * + * Read a value from a SPI_CON register. A 32 bit read is performed. + * If the component is implemented in a smaller width, only the least + * significant data is read from the register. The most significant data + * will be read as 0. + * + * @param BaseAddress is the base address of the SPI_CON device. + * @param RegOffset is the register offset from the base to write to. + * + * @return Data is the data from the register. + * + * @note + * C-style signature: + * u32 SPI_CON_mReadReg(u32 BaseAddress, unsigned RegOffset) + * + */ +#define SPI_CON_mReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (RegOffset)) + +/************************** Function Prototypes ****************************/ +/** + * + * Run a self-test on the driver/device. Note this may be a destructive test if + * resets of the device are performed. + * + * If the hardware system is not built correctly, this function may never + * return to the caller. + * + * @param baseaddr_p is the base address of the SPI_CON instance to be worked on. + * + * @return + * + * - XST_SUCCESS if all self-test code passed + * - XST_FAILURE if any self-test code failed + * + * @note Caching must be turned off for this function to work. + * @note Self test may fail if data memory and device are not on the same bus. + * + */ +XStatus SPI_CON_Reg_SelfTest(void * baseaddr_p); + +#endif // SPI_CON_H diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/SPI_Con.mdd b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/SPI_Con.mdd new file mode 100755 index 0000000..4bd813f --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/SPI_Con.mdd @@ -0,0 +1,10 @@ + + +OPTION psf_version = 2.1; + +BEGIN DRIVER SPI_Con + OPTION supported_peripherals = (SPI_Con); + OPTION copyfiles = all; + OPTION VERSION = 1.0; + OPTION NAME = SPI_Con; +END DRIVER diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/SPI_Con.tcl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/SPI_Con.tcl new file mode 100755 index 0000000..7f913c9 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/SPI_Con.tcl @@ -0,0 +1,5 @@ + + +proc generate {drv_handle} { + xdefine_include_file $drv_handle "xparameters.h" "SPI_Con" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR" +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/file_info.txt b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/file_info.txt new file mode 100644 index 0000000..7320d80 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/file_info.txt @@ -0,0 +1,39 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" 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+fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_9,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.vhd,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_9,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi_data_fifo_v2_1_vl_rfs.v,verilog,axi_data_fifo_v2_1_28,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi_crossbar_v2_1_vl_rfs.v,verilog,axi_crossbar_v2_1_30,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +NewExtInst_TOP_xbar_0.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/sim/NewExtInst_TOP_xbar_0.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +NewExtInst_TOP_rst_clk_wiz_0_100M_0.vhd,vhdl,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/sim/NewExtInst_TOP_rst_clk_wiz_0_100M_0.vhd,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi_protocol_converter_v2_1_vl_rfs.v,verilog,axi_protocol_converter_v2_1_29,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +NewExtInst_TOP_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_auto_pc_0/sim/NewExtInst_TOP_auto_pc_0.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +NewExtInst_TOP.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/sim/NewExtInst_TOP.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/glbl.v b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/libps7.dll b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/libps7.dll new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/libps7.dll @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/libps7.so b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/libps7.so new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/libps7.so @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/libremoteport.dll b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/libremoteport.dll new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/libremoteport.dll @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/libremoteport.so b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/libremoteport.so new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/libremoteport.so @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/ps7_init.h b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/ps7_init.h new file mode 100755 index 0000000..224d7ea --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/ps7_init.h @@ -0,0 +1,117 @@ +/****************************************************************************** +* +* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + + + + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 142857132 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 25000000 +#define FPGA1_FREQ 50000000 +#define FPGA2_FREQ 100000000 +#define FPGA3_FREQ 200000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/ps7_init.html b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/ps7_init.html new file mode 100755 index 0000000..9ca53bd --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/ps7_init.html @@ -0,0 +1,125613 @@ + + + + +Zynq PS configuration detail + + + +

    +
    + +
  • +
    Zynq PS Register Summary Viewer +
    +
    • +     +
    +
    +
    + +
    Zynq PS7 Summary Report +
    +     +
    User Configurations +
    +
    + +
    MIO Configurations +
    +     +
    + +
    CLK Configurations +
    +     +
    + +
    DDR Configurations +
    +     +
    + +
    SMC Configurations +
    +     +
    +
    +
    Select Version: + +
    +
    +
    Zynq Register View +
    +
    + +
    MIO Registers +
    +     + +
    PLL Registers +
    +     + +
    Clock Registers +
    +     + +
    DDR Registers +
    +     + +
    Peripherals Registers +
    +     +
    +
    This design is targeted for xc7z035 board (part number: xc7z035ffg676-2) + +
    +

    Zynq Design Summary

    + + + + + + + + + + + + + + + + + + + + + +
    +Device + +xc7z035 +
    +SpeedGrade + +-2 +
    +Part + +xc7z035ffg676-2 +
    +Description + +Zynq PS Configuration Report with register details +
    +Vendor + +Xilinx +
    +

    MIO Table View

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +MIO Pin + +Peripheral + +Signal + +IO Type + +Speed + +Pullup + +Direction +
    +MIO 0 + +SD 1 + +wp + +LVCMOS 3.3V + +slow + +enabled + +in +
    +MIO 1 + +Quad SPI Flash + +qspi0_ss_b + +LVCMOS 3.3V + +slow + +enabled + +out +
    +MIO 2 + +Quad SPI Flash + +qspi0_io[0] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 3 + +Quad SPI Flash + +qspi0_io[1] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 4 + +Quad SPI Flash + +qspi0_io[2] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 5 + +Quad SPI Flash + +qspi0_io[3]/HOLD_B + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 6 + +Quad SPI Flash + +qspi0_sclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 7 + + + + + + + + + + + + +
    +MIO 8 + +Quad SPI Flash + +qspi_fbclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 9 + +SD 1 + +cd + +LVCMOS 3.3V + +slow + +enabled + +in +
    +MIO 10 + +SD 1 + +data[0] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 11 + +SD 1 + +cmd + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 12 + +SD 1 + +clk + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 13 + +SD 1 + +data[1] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 14 + +SD 1 + +data[2] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 15 + +SD 1 + +data[3] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 16 + +Enet 0 + +tx_clk + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 17 + +Enet 0 + +txd[0] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 18 + +Enet 0 + +txd[1] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 19 + +Enet 0 + +txd[2] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 20 + +Enet 0 + +txd[3] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 21 + +Enet 0 + +tx_ctl + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 22 + +Enet 0 + +rx_clk + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 23 + +Enet 0 + +rxd[0] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 24 + +Enet 0 + +rxd[1] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 25 + +Enet 0 + +rxd[2] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 26 + +Enet 0 + +rxd[3] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 27 + +Enet 0 + +rx_ctl + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 28 + + + + + + + + + + + + +
    +MIO 29 + + + + + + + + + + + + +
    +MIO 30 + + + + + + + + + + + + +
    +MIO 31 + + + + + + + + + + + + +
    +MIO 32 + + + + + + + + + + + + +
    +MIO 33 + + + + + + + + + + + + +
    +MIO 34 + + + + + + + + + + + + +
    +MIO 35 + + + + + + + + + + + + +
    +MIO 36 + + + + + + + + + + + + +
    +MIO 37 + + + + + + + + + + + + +
    +MIO 38 + + + + + + + + + + + + +
    +MIO 39 + + + + + + + + + + + + +
    +MIO 40 + +SD 0 + +clk + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 41 + +SD 0 + +cmd + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 42 + +SD 0 + +data[0] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 43 + +SD 0 + +data[1] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 44 + +SD 0 + +data[2] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 45 + +SD 0 + +data[3] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 46 + +SD 0 + +wp + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 47 + +SD 0 + +cd + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 48 + +UART 1 + +tx + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 49 + +UART 1 + +rx + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 50 + + + + + + + + + + + + +
    +MIO 51 + + + + + + + + + + + + +
    +MIO 52 + +Enet 0 + +mdc + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 53 + +Enet 0 + +mdio + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +

    DDR Memory information

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Parameter name + +Value + +Description +
    +Enable DDR + +1 + +Enable DDR Controller of Zynq PS +
    +Memory Part + +MT41J256M16 RE-125 + + +
    +DRAM bus width + +32 Bit + +Select the desired data width. Refer to the Thechnical Reference Manual(TRM) for a detailed list of supported DDR data widths +
    +ECC + +Disabled + +ECC is supported only for data width of 16-bit +
    +BURST Length (lppdr only) + +8 + +Select the burst Length. It refers to the amount of data read/written after a read/write command is presented to the controller +
    +Internal Vref + +0 + + +
    +Operating Frequency (MHz) + +533.333333 + +Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade +
    +HIGH temperature + +Normal (0-85) + +Select the operating temparature +
    +DRAM IC bus width + +16 Bits + +Provide the width of the DRAM chip +
    +DRAM Device Capacity + +4096 MBits + + +
    +Speed Bin + +DDR3_1066F + +Provide the Speed Bin +
    +BANK Address Count + +3 + +Defines the bank to which an active an ACTIVE, READ, WRITE, or Precharge Command is being applied +
    +ROW Address Count + +15 + +Provide the Row address for ACTIVE commands +
    +COLUMN Address Count + +10 + +Provide the Row address for READ/WRITE commands +
    +CAS Latency + +7 + +Select the Column Access Strobe (CAS) Latency. It refers to the amount of time it takes for data to appear on the pins of the memory module +
    +CAS Write Latency + +6 + +Select the CAS Write Latency +
    +RAS to CAS Delay + +7 + +Provide the row address to column address delay time. tRCD is t he time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS) +
    +RECHARGE Time + +7 + +Precharge Time (tRP) is the number of clock cycles needed o terminate acces s to an open row of memory, and open access to the next row +
    +tRC (ns ) + +48.91 + +Provide the Row cycle time tRC (ns) +
    +tRASmin ( ns ) + +35.0 + +tRASmin (ns) is the minimum number of clock cycles required between an Active command and issuing the Precharge command +
    +tFAW + +40.0 + +It restricts the number of activates that can be done within a certain window of time +
    +ADDITIVE Latency + +0 + +Provide the Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths +
    +Write levelling + +1 + + +
    +Read gate + +1 + + +
    +Read gate + +1 + + +
    +DQS to Clock delay [0] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [1] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [2] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [3] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +Board delay [0] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [1] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [2] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [3] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +

    PS Clocks information

    +

    PS Reference Clock : 33.333333

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Peripheral + +PLL source + +Frequency (MHz) +
    +CPU 6x Freq (MHz) + +ARM PLL + +666.666687 +
    +QSPI Flash Freq (MHz) + +IO PLL + +142.857132 +
    +ENET0 Freq (MHz) + +IO PLL + +125.000000 +
    +SDIO Freq (MHz) + +IO PLL + +100.000000 +
    +SDIO Freq (MHz) + +IO PLL + +100.000000 +
    +UART Freq (MHz) + +IO PLL + +100.000000 +
    +FPGA0 Freq (MHz) + +IO PLL + +25.000000 +
    +FPGA1 Freq (MHz) + +IO PLL + +50.000000 +
    +FPGA2 Freq (MHz) + +IO PLL + +100.000000 +
    +FPGA3 Freq (MHz) + +IO PLL + +200.000000 +
    +

    ps7_pll_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: ARM PLL 10: DDR PLL 11: IO PLL This field is reset by POR only. +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for programming the PLL. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock and Rx Signals Select +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +FPGA1_CLK_CTRL + + +0XF8000180 + +32 + +RW + +0x000000 + +PL Clock 1 Output control +
    + +FPGA2_CLK_CTRL + + +0XF8000190 + +32 + +RW + +0x000000 + +PL Clock 2 output control +
    + +FPGA3_CLK_CTRL + + +0XF80001A0 + +32 + +RW + +0x000000 + +PL Clock 3 output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source of the Rx clock, control and data signals: 0: MIO 1: EMIO +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock and Rx Signals Select +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +7 + +700 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +701 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a03 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +5 + +500000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +500800 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )FPGA1_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA1_CLK_CTRL + +0XF8000180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA1_CLK_CTRL@0XF8000180 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 1 Output control +
    +

    +

    Register ( slcr )FPGA2_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA2_CLK_CTRL + +0XF8000190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +2 + +200000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA2_CLK_CTRL@0XF8000190 + +31:0 + +3f03f30 + + + +200500 + +PL Clock 2 output control +
    +

    +

    Register ( slcr )FPGA3_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA3_CLK_CTRL + +0XF80001A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA3_CLK_CTRL@0XF80001A0 + +31:0 + +3f03f30 + + + +100500 + +PL Clock 3 output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ratio: (When this register changes, no access are allowed to OCM.) 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +1 + +800 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec0c4d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +82 + +82 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reserved_reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Reserved. Do not modify. +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +Two_rank_cfg@0XF8006004 + +31:0 + +7ffff + + + +1082 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a1 + +2840 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4285b + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +13 + +13 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d3 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. In non-LPDDR mode, the minimum DRAM Write Latency (DDR2) supported is 3. In LPDDR mode, the required DRAM Write Latency of 1 is supported. Since write latency (CWL) min is 3, and DDR2 CWL is CL-1, the min (DDR2) CL supported is 4 +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +f + +3c00 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +5 + +28000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +5 + +2800000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +7282bce5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_en_dfi_dram_clk_disable + +23:23 + +800000 + +0 + +0 + +Enables the assertion of ddrc_dfi_dram_clk_disable. In DDR2/DDR3, only asserted in Self Refresh. In mDDR/LPDDR2, can be asserted in following: - during normal operation (Clock Stop), - in Power Down - in Self Refresh - In Deep Power Down +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +7fdffffc + + + +270872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffc3 + + + +0 + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2: Value loaded into EMR2 register DDR3: Value loaded into MR2 register LPDDR2: Value loaded into MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2: Value loaded into EMR3 register DDR3: Value loaded into MR3 register. Set Bit[2:0] to 3'b000. These bits are set appropriately by the Controller during Read Data eye training and Read DQS gate leveling. LPDDR2: Unused +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +b30 + +b30 + +DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2: Value loaded into EMR1register. (Bits[9:7] are for OCD and the setting in this reg is ignored. Controller sets this bits appropriately during initialization DDR3: Value loaded into MR1 register. Set Bit[7] to 0. This bit is set appropriately by the Controller during Write Leveling LPDDR2: Value loaded into MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40b30 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 8, Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 7, Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 6, Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 5, Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reserved_reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +Reserved. Do not modify. +
    +reserved_reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Reserved. Do not modify. +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3f03f + + + +3c008 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +10000 + + + +0 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum d'128) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_2d@0XF80060B4 + +31:0 + +200 + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of uncorrectable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on board topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +0: Use reg_phy_ctrl_slave_ratio for address/command timing slave DLL 1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_64@0XF8006190 + +31:0 + +6ffffefe + + + +40080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. This feature should only be enabled after LPDDR2 initialization is completed +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff5 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Powerdown mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQ pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQS pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +Drive and Slew controls for Clock pins of the DDR Interface +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SD1_WP_CD_SEL + + +0XF8000834 + +32 + +RW + +0x000000 + +SDIO 1 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQ pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQS pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for Clock pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1x: Enable External VREF for upper 16 bits +
    +reserved_VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Reserved. Do not modify. +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +reserved_REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +1 + + + +1 + +DDR IOB DCI Config +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialize flops in DCI system +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDR IOB DCI Config +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +DCI System Enable. Set to 1 if any IOs in DDR IO Bank use DCI Termination. DDR2, DDR3 and LPDDR2 (Silicon Revision 2.0+) configurations require this bit set to 1 +
    +reserved_VRP_TRI + +2:2 + +4 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_TRI + +3:3 + +8 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRP_OUT + +4:4 + +10 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT1 + +15:14 + +c000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update Mode. Use the values in the Calibration Table. +
    +reserved_INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_CLK + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLN + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLP + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_RST + +25:25 + +2000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7feffff + + + +823 + +DDR IOB DCI Config +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. 0: disable 1: enable +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables Pullup on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3f01 + + + +1601 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3f01 + + + +1601 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1680 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1680 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait, Input 10: NAND Flash IO Bit 7, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 12 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1680 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5, Input/Output 10: NAND Flash IO Bit 3, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 13 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1680 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1680 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1680 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1, Output 10: NAND Flash IO Bit 8, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2, Output 10: NAND Flash IO Bit 9, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110 TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3, Output 10: NAND Flash IO Bit 10, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6, Output 10: NAND Flash IO Bit 13, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3f01 + + + +1201 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +2e + +2e + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f002e + +SDIO 0 WP CD select +
    +

    +

    Register ( slcr )SD1_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD1_WP_CD_SEL + +0XF8000834 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO1_WP_SEL + +5:0 + +3f + +0 + +0 + +SDIO 1 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO1_CD_SEL + +21:16 + +3f0000 + +9 + +90000 + +SDIO 1 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD1_WP_CD_SEL@0XF8000834 + +31:0 + +3f003f + + + +90000 + +SDIO 1 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +Baud Rate Divider Register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud Rate Generator Register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control Register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode Register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +Baud Rate Divider Register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud Rate Generator Register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter 1: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: enable 1: disable, regardless of the value of RXEN +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed. +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed. +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control Register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +3ff + + + +20 + +UART Mode Register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes . If not set, then external pull up is required on HOLDb and WPn pins . Note that this bit doesn't affect the quad(4-bit) mode as Controller always drives these pins in quad mode. It is highly recommended to set this bit always(irrespective of mode of operation) while using QSPI +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This register controls which POR timer the PL will use for power-up. 0 - Use 64k timer 1 - Use 4k timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    ENET RESET

    +

    I2C RESET

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_LVL_INP_EN_0 + +3:3 + +8 + +1 + +8 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_0 + +2:2 + +4 + +1 + +4 + +Level shifter enable to drive signals from PS to PL +
    +USER_LVL_INP_EN_1 + +1:1 + +2 + +1 + +2 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_1 + +0:0 + +1 + +1 + +1 + +Level shifter enable to drive signals from PS to PL +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +Reserved. Do not modify. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +PL Reset 3 (FCLKRESETN3 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN3 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +PL Reset 2 (FCLKRESETN2 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN2 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +PL Reset 1 (FCLKRESETN1 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN1 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +PL Reset 0 (FCLKRESETN0 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN0 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    AFI2 SECURE REGISTER

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_3_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: CPU PLL 10: divided DDR PLL 11: IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +FPGA1_CLK_CTRL + + +0XF8000180 + +32 + +RW + +0x000000 + +PL Clock 1 Output control +
    + +FPGA2_CLK_CTRL + + +0XF8000190 + +32 + +RW + +0x000000 + +PL Clock 2 output control +
    + +FPGA3_CLK_CTRL + + +0XF80001A0 + +32 + +RW + +0x000000 + +PL Clock 3 output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source to generate the Rx clock: 0: MIO Rx clock, 1: EMIO Rx clock +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +7 + +700 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +701 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a03 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +5 + +500000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +500800 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )FPGA1_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA1_CLK_CTRL + +0XF8000180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA1_CLK_CTRL@0XF8000180 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 1 Output control +
    +

    +

    Register ( slcr )FPGA2_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA2_CLK_CTRL + +0XF8000190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +2 + +200000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA2_CLK_CTRL@0XF8000190 + +31:0 + +3f03f30 + + + +200500 + +PL Clock 2 output control +
    +

    +

    Register ( slcr )FPGA3_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA3_CLK_CTRL + +0XF80001A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA3_CLK_CTRL@0XF80001A0 + +31:0 + +3f03f30 + + + +100500 + +PL Clock 3 output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ration: 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +1 + +800 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec0c4d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config0 + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config1 + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 1. +
    + +PHY_Config2 + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 2. +
    + +PHY_Config3 + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 3. +
    + +phy_init_ratio0 + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio1 + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 1. +
    + +phy_init_ratio2 + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 2. +
    + +phy_init_ratio3 + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 3. +
    + +phy_rd_dqs_cfg0 + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg1 + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 1. +
    + +phy_rd_dqs_cfg2 + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 2. +
    + +phy_rd_dqs_cfg3 + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 3. +
    + +phy_wr_dqs_cfg0 + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg1 + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 1. +
    + +phy_wr_dqs_cfg2 + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 2. +
    + +phy_wr_dqs_cfg3 + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 3. +
    + +phy_we_cfg0 + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg1 + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 1. +
    + +phy_we_cfg2 + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 2. +
    + +phy_we_cfg3 + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 3. +
    + +wr_data_slv0 + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv1 + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 1. +
    + +wr_data_slv2 + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 2. +
    + +wr_data_slv3 + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 3. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port0 + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port1 + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 1. +
    + +axi_priority_wr_port2 + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 2. +
    + +axi_priority_wr_port3 + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 3. +
    + +axi_priority_rd_port0 + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port1 + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 1. +
    + +axi_priority_rd_port2 + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 2. +
    + +axi_priority_rd_port3 + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 3. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +82 + +82 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Rank configuration: 01: One Rank of DDR 11: Two Ranks of DDR Others: reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +Block read/write scheduling cycle count when Write requires changing ODT settings 00: 1 cycle 01: 2 cycles 10: 3 cycles others: reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0: schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1: schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81082 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a1 + +2840 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4285b + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +13 + +13 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d3 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +f + +3c00 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +5 + +28000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +5 + +2800000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +7282bce5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1: sdram device 0: non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: stop_clk will never be asserted. 1: enable the assertion of stop_clk to the PHY whenever a clock is not required +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2 and DDR3: Value written into the DRAM EMR2 register. LPDDR2: Value written into the DRAM MR3 register. +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2 and DDR3: Value written into the DRAM EMR3 register. LPDDR2: not used. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +b30 + +b30 + +DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2 and DDR3: Value written into the DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. LPDDR2: Value written into the DRAM MR2 register. +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40b30 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODTs must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config0 + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config0@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config1 + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config1@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 1. +
    +

    +

    Register ( slcr )PHY_Config2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config2 + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config2@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 2. +
    +

    +

    Register ( slcr )PHY_Config3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config3 + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config3@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_init_ratio0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio0 + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio0@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio1 + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio1@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 1. +
    +

    +

    Register ( slcr )phy_init_ratio2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio2 + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio2@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 2. +
    +

    +

    Register ( slcr )phy_init_ratio3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio3 + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio3@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 3. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg0 + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg0@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg1 + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg1@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg2 + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg2@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg3 + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg3@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg0 + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg0@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg1 + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg1@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg2 + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg2@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg3 + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg3@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_we_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg0 + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg0@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg1 + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg1@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 1. +
    +

    +

    Register ( slcr )phy_we_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg2 + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg2@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 2. +
    +

    +

    Register ( slcr )phy_we_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg3 + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg3@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 3. +
    +

    +

    Register ( slcr )wr_data_slv0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv0 + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv0@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv1 + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv1@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 1. +
    +

    +

    Register ( slcr )wr_data_slv2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv2 + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv2@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 2. +
    +

    +

    Register ( slcr )wr_data_slv3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv3 + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv3@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 3. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +0: (default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) 1: assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 0: Each Rank uses its own delay 1: Rank 0 delays are used for all ranks +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1: enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port0 + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port0@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port1 + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port1@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 1. +
    +

    +

    Register ( slcr )axi_priority_wr_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port2 + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port2@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 2. +
    +

    +

    Register ( slcr )axi_priority_wr_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port3 + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port3@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 3. +
    +

    +

    Register ( slcr )axi_priority_rd_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port0 + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port0@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port1 + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port1@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 1. +
    +

    +

    Register ( slcr )axi_priority_rd_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port2 + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port2@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 2. +
    +

    +

    Register ( slcr )axi_priority_rd_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port3 + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port3@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 3. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +0:All bank refresh Per bank refresh allows traffic to flow to other banks. 1:Per bank refresh Per bank refresh is not supported on all LPDDR2 devices. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Power-down mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 0 +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 1 +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDR IOB Slew for Address +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDR IOB Slew for Data +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDR IOB Slew for Diff +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDR IOB Slew for Clock +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SD1_WP_CD_SEL + + +0XF8000834 + +32 + +RW + +0x000000 + +SDIO 1 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 0 +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 1 +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDR IOB Slew for Address +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Data +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Diff +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Clock +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1X: Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors x0: Disable VREF pull-up for lower 16 bits x1: Enable VREF pull-up for lower 16 bits 0x: Disable VREF pull-up for upper 16 bits 1x: Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Enable test mode for VRP and VRN: 00: VRP/VRN test mode not used 11: VRP/VRN test mode enabled using vref based receiver. VRP/VRN control is set using the VRN_OUT, VRP_OUT, VRN_TRI, VRP_TRI fields in the DDRIOB_DCI_CTRL register +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0: no pull-up 1: enable pull-up +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. 0: disable 1: enable +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables pull-up on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3f01 + + + +1601 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3f01 + + + +1601 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1680 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1680 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait 10: NAND Flash IO Bit 7 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 12 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1680 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5 10: NAND Flash IO Bit 3 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 13 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1680 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1680 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1680 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1 10: NAND Flash IO Bit 8 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Output 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2 10: NAND Flash IO Bit 9 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110 TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3 10: NAND Flash IO Bit 10 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6 10: NAND Flash IO Bit 13 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3f01 + + + +1201 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +2e + +2e + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f002e + +SDIO 0 WP CD select +
    +

    +

    Register ( slcr )SD1_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD1_WP_CD_SEL + +0XF8000834 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO1_WP_SEL + +5:0 + +3f + +0 + +0 + +SDIO 1 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO1_CD_SEL + +21:16 + +3f0000 + +9 + +90000 + +SDIO 1 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD1_WP_CD_SEL@0XF8000834 + +31:0 + +3f003f + + + +90000 + +SDIO 1 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass 2 - 65535: baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: start break transmission, 1: stop break transmission. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: 1: start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 0: receiver timeout counter disabled, 1: receiver timeout counter is restarted. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter, 0: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter, 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: disable, 1: enable +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable, 1: enable. When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: 1: transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: 1: receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode: 0: Default UART mode 1: Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select: 0: APB clock, pclk 1: a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: 00: normal 01: automatic cho 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: 0: clock source is uart_clk 1: clock source is uart_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    ENET RESET

    +

    I2C RESET

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset: 0: No reset 1: ACP AXI interface reset output asserted +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0: No reset 1: AXDS3AXI interface reset output asserted +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0: No reset 1: AXDS2 AXI interface reset output asserted +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0: No reset 1: AXDS1 AXI interface reset output asserted +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0: No reset 1: AXDS0 AXI interface reset output asserted +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0: No reset 1: FPGA slave interface 1 reset is asserted +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0: No reset 1: FPGA slave interface 0 reset is asserted +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface: 1: soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0: No reset 1: FPGA master interface 1 reset is asserted +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0: No reset 1: FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 3 peripheral request reset output asserted +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 2 peripheral request reset output asserted +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 1 peripheral request reset output asserted +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 0 peripheral request reset output asserted +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0: No reset 1: FPGA 3 top level reset output asserted +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0: No reset 1: FPGA 2 top level reset output asserted +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0: No reset 1: FPGA 1 top level reset output asserted +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0: No reset 1: FPGA 0 top level reset output asserted +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_2_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CORTEX A9 Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status. 0 - ARM PLL out of lock. 1 - ARM PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is CPU PLL. 10 - Source for generated clock is DDR divided clock. 11 - Source for generated clock is IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CORTEX A9 Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status. 0 - DDR PLL out of lock. 1 - DDR PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Divisor value for the ddr_3xclk +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk) +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status. 0 - IO PLL out of lock. 1 - IO PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 RX Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Linear Quad-SPI Reference Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Reference Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Reference Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP 2X Clock Contol +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +FPGA 0 Output Clock Control +
    + +FPGA1_CLK_CTRL + + +0XF8000180 + +32 + +RW + +0x000000 + +FPGA 1 Output Clock Control +
    + +FPGA2_CLK_CTRL + + +0XF8000190 + +32 + +RW + +0x000000 + +FPGA 2 Output Clock Control +
    + +FPGA3_CLK_CTRL + + +0XF80001A0 + +32 + +RW + +0x000000 + +FPGA 3 Output Clock Control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +6:2:1 ratio clock, if set +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Selects the source used to generate the clock. 0 - Source for generated clock is GEM 0 MIO RX clock. 1 - Source for generated clock is GEM 0 FMIO RX clock. +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +Gigabit Ethernet MAC 0 RX Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source used to generate the clock. 1xx - Source for generated clock is Ethernet 0 FMIO clock. 00x - Source for generated clock is IO PLL. 010 - Source for generated clock is ARM PLL. 011 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +7 + +700 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +701 + +Linear Quad-SPI Reference Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO 0 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +SDIO 1 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a03 + +SDIO Reference Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Reference Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active 0 - Clock is disabled 1 - Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP 2X Clock Contol +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +5 + +500000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +500800 + +FPGA 0 Output Clock Control +
    +

    +

    Register ( slcr )FPGA1_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA1_CLK_CTRL + +0XF8000180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA1_CLK_CTRL@0XF8000180 + +31:0 + +3f03f30 + + + +400500 + +FPGA 1 Output Clock Control +
    +

    +

    Register ( slcr )FPGA2_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA2_CLK_CTRL + +0XF8000190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +2 + +200000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA2_CLK_CTRL@0XF8000190 + +31:0 + +3f03f30 + + + +200500 + +FPGA 2 Output Clock Control +
    +

    +

    Register ( slcr )FPGA3_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA3_CLK_CTRL + +0XF80001A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA3_CLK_CTRL@0XF80001A0 + +31:0 + +3f03f30 + + + +100500 + +FPGA 3 Output Clock Control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Enable the 6:2:1 mode. 1 for 6:3:2:1. 0 for 4:2:2:1. +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +6:2:1 ratio clock, if set +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet MAC 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet MAC 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +1 + +800 + +SDIO 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +LQSPI AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec0c4d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two rank configuration register +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control register +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control register +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control register +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters register 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters register 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters register 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters register 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters register 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM initialization parameters register +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access register +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access register +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM burst 8 read/write register +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ register +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM bank address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT register +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO register +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration register +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold register +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller register 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller register 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller register 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller register 4 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters register +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters register +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown register +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control register +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug register +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing register +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear register +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction register +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status register +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count register +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub register +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control register (2) +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control register (3) +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask register +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 Register +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 Register +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 Register +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 Register +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control Register +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +82 + +82 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Only present for multi-rank configurations. Each bit represents one rank. 1=populated; 0=unpopulated 01 = One Rank 11 = Two Ranks Others = Reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +00 = block read/write scheduling for 1-cycle when Write requires changing ODT settings 01 = block read/write scheduling for 2 cycles when Write requires changing ODT settings 10 = block read/write scheduling for 3 cycles when Write requires changing ODT settings 11 = Reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0 = schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1 = schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81082 + +Two rank configuration register +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of clocks that the HPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control register +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control register +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control register +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a1 + +2840 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks DRAM RELATED +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4285b + +DRAM Parameters register 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +13 + +13 + +Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. LPDDR2 mode: Set this to the larger of tCKE or tCKESR. Non-LPDDR2 designs: Set this to tCKE value. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d3 + +DRAM Parameters register 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2/3 -> WL -1 LPDDR -> 1 LPDDR2 ->WL Where WL = Write Latency of DRAM DRAM RELATED. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. non-LPDDR2 -> RL + BL/2 + 2 - WL LPDDR2 -> RL + BL/2 + RU(tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +f + +3c00 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +5 + +28000 + +tXP: Minimum time after power down exit to any operation. DRAM RELATED. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +5 + +2800000 + +Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency DRAM RELATED +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +7282bce5 + +DRAM Parameters register 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1 DRAM RELATED +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1 = sdram device 0 = non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-mobile DRAM device in use. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +1=enable the assertion of stop_clk to the PHY whenever a clock is not required by LPDDR/ LPDDR2. 0=stop_clk will never be asserted. Note: This is only present for implementations supporting LPDDR/LPDDR2 devices. +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Set to RL. Time from Read command to Read data on DRAM interface. Unit: clocks This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. RL = Read Latency of DRAM Note: This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1 = disable the pad power down feature 0 = Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters register 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1 = DDRC will use 2T timing 0 = DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1 = Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and 'ddrc_reg_mr_wr_busy' is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +Mode register address - for non-LPDDR2 modes. This register is don't care in LPDDR2 mode 00 = MR0 01 = MR1 10 = MR2 11 = MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +Mode register write data - for non-LPDDR2 modes. For LPDDR2, these 16-bits are interpreted as Writes: \'7bMR Addr[7:0], MR Data[7:0]\'7d. Reads: \'7bMR Addr[7:0], Don't Care[7:0]\'7d +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 1 = Indicates that mode register write / read operation is in progress. 0 = Indicates that the core can initiate a mode register write / read operation. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 1 = read 0 = write +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 1'b0 by default. This bit will be cleared (1'b0), whenever a Mode Register Read command is issued. This bit will be set to 1'b1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters register 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands DRAM RELATED Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM initialization parameters register +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +Non LPDDR2- Value to be loaded into DRAM EMR2 registers. For LPDDR2 - Value to Write to the MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +Non LPDDR2- Value to be loaded into DRAM EMR3 registers. Used in non-LPDDR2 designs only. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access register +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +b30 + +b30 + +Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +Non LPDDR2-Value to be loaded into DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. For LPDDR2 - Value to Write to the MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40b30 + +DRAM EMR, MR access register +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +This controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. In LPDDR and LPDDR2, Burst length of 16 is supported only in Half Bus Width mode. Every input read/write command has 4 cycles of data associated with it and that is not enough data for doing Burst Length16 in Full Bus Width mode. 0010 - Burst length of 4 0100 - Burst length of 8 1000 - Burst length of 16 (only supported for LPDDR AND LPDDR2) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM burst 8 read/write register +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Active Low signal. When asserted (0), all incoming transactions will be forced to low priority. Forcing the incoming transactions to low priority implicitly turns OFF Bypass. Otherwise, HPR is allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. This bit is intended to be switched on-the-fly +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ register +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14 Internal Base: 5 The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Selects the address bits used as DRAM bank address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Selects the address bits used as DRAM column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Selects the address bits used as DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODT's must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT register +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1 = stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO register +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration register +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable for LPDDR and LPDDR2 modes. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold register +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +When 1, disable Write Combine +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to '0', auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller register 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +1 - Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on 'urgent' input coming from AXI master. 0 - Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 1'b0. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller register 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) Only present in designs that support DDR3 and LPDDR2 devices. +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Only present in designs that support DDR3 devices +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. Only present in designs that support DDR3 devices. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller register 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller register 4 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters register +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters register +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +1 - Controller puts the DRAM into Deep Powerdown mode when the transaction store is empty. 0 - Brings Controller out of Deep Powerdown mode Present only in designs configured to support LPDDR or LPDDR2 FOR PERFORMANCE ONLY. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown register +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +1 = Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0 = Write leveling disabled. +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +1 = Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0= Read DQS gate leveling is disabled. +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +1 = Read Data Eye training mode has been enabled as part of init sequence. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control register +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1 - Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0 - Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug register +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. Non-LPDDR -> RL-1 LPDDR -> RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing register +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear register +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when a correctable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction register +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when an uncorrectable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status register +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count register +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 3'b000 (No ECC) and 3'b100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 3'b100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 - No ECC, 001 - Reserved 010 - Parity 011 - Reserved 100 - SEC/DED over 1-beat 101 - SEC/DED over multiple beats 110 - Device Correction 111 - Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +This feature is NOT supported. Only default value works. 1 - Disable ECC scrubs 0 - Enable ECC scrubs Valid only when reg_ddrc_ecc_mode = 3'b100. +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub register +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +1 = run scan test at full clock speed but with less coverage 0 = run scan test at slow clock speed but with high coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 2'b00: constant pattern (0 repeated on each DQ bit) 2'b01: low freq pattern (00001111 repeated on each DQ bit) 2'b10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +1=assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) 0=(default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0 = Select algorithm # 1'b1 = Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 1- Rank 0 delays are used for all ranks 0- Each Rank uses its own delay +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-LPDDR DRAM device in use. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1=enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control register (2) +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control register (3) +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +This register must be set based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask register +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +1=LPDDR2 DRAM device in Use. 0=non-LPDDR2 device in use Present only in designs configured to support LPDDR2. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +1:Per bank refresh 0:All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported on all LPDDR2 devices. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 Register +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. Present only in designs configured to support LPDDR2. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 Register +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 Register +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 Register +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control Register +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0 = DDRC Init 1 = Normal operation 2 = Power-down mode 3 = Self-refresh mode 4 and above = deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDRIOB Address 0 Configuartion Register +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDRIOB Address 1 Configuration Register +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDRIOB Differential Clock Configuration Register +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Address Register +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Data Register +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Differential Strobe Register +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Clcok Register +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDRIOB DDR Control Register +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Control for Pin 0 +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Control for Pin 1 +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Control for Pin 2 +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Control for Pin 3 +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Control for Pin 4 +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Control for Pin 5 +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Control for Pin 6 +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Control for Pin 8 +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Control for Pin 9 +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Control for Pin 10 +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Control for Pin 11 +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Control for Pin 12 +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Control for Pin 13 +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Control for Pin 14 +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Control for Pin 15 +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Control for Pin 16 +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Control for Pin 17 +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Control for Pin 18 +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Control for Pin 19 +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Control for Pin 20 +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Control for Pin 21 +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Control for Pin 22 +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Control for Pin 23 +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Control for Pin 24 +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Control for Pin 25 +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Control for Pin 26 +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Control for Pin 27 +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Control for Pin 40 +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Control for Pin 41 +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Control for Pin 42 +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Control for Pin 43 +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Control for Pin 44 +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Control for Pin 45 +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Control for Pin 46 +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Control for Pin 47 +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Control for Pin 48 +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Control for Pin 49 +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Control for Pin 52 +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Control for Pin 53 +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select register +
    + +SD1_WP_CD_SEL + + +0XF8000834 + +32 + +RW + +0x000000 + +SDIO 1 WP CD select register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDRIOB Address 0 Configuartion Register +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDRIOB Address 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDRIOB Differential Clock Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDRIOB Drive Slew Address Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Data Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Differential Strobe Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Clcok Register +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output 0001 - VREF = 0.6V for LPDDR2 with 1.2V IO 0010 - VREF = 0.675V for LPDDR3 1.35 V IO 0100 - VREF = 0.75V for DDR3 with 1.5V IO 1000 - VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input X0 - Disable External VREF for lower 16 bits X1 - Enable External VREF for lower 16 bits 0X - Disable External VREF for upper 16 bits 1X - Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors X0 - Disable VREF pull-up for lower 16 bits X1 - Enable VREF pull-up for lower 16 bits 0X - Disable VREF pull-up for upper 16 bits 1X - Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0 - VRP/VRN not used 1 - VRP/VRN used as refio +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +73ff + + + +260 + +DDRIOB DDR Control Register +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3f01 + + + +1601 + +MIO Control for Pin 0 +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Control for Pin 1 +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 2 +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Control for Pin 3 +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 4 +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 5 +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 6 +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 8 +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3f01 + + + +1601 + +MIO Control for Pin 9 +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 10 +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 11 +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_wait- (SRAM Wait State indicator) 2= nand, Input, smc_nand_data_in[7]- (NAND Data Bus) = nand, Output, smc_nand_data_out[7]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 12 +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[5]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[5]- (SRAM Data) 2= nand, Input, smc_nand_data_in[3]- (NAND Data Bus) = nand, Output, smc_nand_data_out[3]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 13 +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 14 +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 15 +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[4]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[1]- (SRAM Address) 2= nand, Input, smc_nand_data_in[8]- (NAND Data Bus) = nand, Output, smc_nand_data_out[8]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 16 +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[5]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[2]- (SRAM Address) 2= nand, Input, smc_nand_data_in[9]- (NAND Data Bus) = nand, Output, smc_nand_data_out[9]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 17 +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[6]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[3]- (SRAM Address) 2= nand, Input, smc_nand_data_in[10]- (NAND Data Bus) = nand, Output, smc_nand_data_out[10]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 18 +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 19 +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 20 +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[6]- (SRAM Address) 2= nand, Input, smc_nand_data_in[13]- (NAND Data Bus) = nand, Output, smc_nand_data_out[13]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 21 +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 22 +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 23 +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 24 +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 25 +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 26 +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 27 +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 40 +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 41 +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 42 +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 43 +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 44 +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 45 +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3f01 + + + +1201 + +MIO Control for Pin 46 +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Control for Pin 47 +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Control for Pin 48 +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Control for Pin 49 +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 52 +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 53 +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +2e + +2e + +SDIO0 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO0 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f002e + +SDIO 0 WP CD select register +
    +

    +

    Register ( slcr )SD1_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD1_WP_CD_SEL + +0XF8000834 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO1_WP_SEL + +5:0 + +3f + +0 + +0 + +SDIO1 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SDIO1_CD_SEL + +21:16 + +3f0000 + +9 + +90000 + +SDIO1 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SD1_WP_CD_SEL@0XF8000834 + +31:0 + +3f003f + + + +90000 + +SDIO 1 WP CD select register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value 0 = Disables baud_sample 1 = Clock divisor bypass 2 - 65535 = baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break. 1 = stop transmission of the break. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break 1 = start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter 1 = receiver timeout counter is restarted +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable. 1, the transmitter is disabled +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable. 1, the transmitter is enabled, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable. 1= receiver is enabled +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable. 1=the receiver logic is enabled, provided RXDIS field is set to 0 +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for TX data path. 1=the transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for RX data path 1=receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode 0 : Default UART mode 1 : Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select 0 : APB clock, pclk 1 : a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode 00 = normal 01 = automatic cho 10 = local loopback 11 = remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits 00 = 1 stop bit 01 = 1.5 stop bits 10 = 2 stop bits 11 = reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select. 000 = even parity 001 = odd parity 010 = forced to 0 parity (space) 011 = forced to 1 parity (mark) 1xx = no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select 11 = 6 bits 10 = 7 bits 01 / 00 = 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +clock source select 1 = clock source is uart_clk/8 0 = clock source is uart_clk +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    ENET RESET

    +

    I2C RESET

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset. 0 - No reset. 1 - ACP AXI interface reset output asserted. +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS3AXI interface reset output asserted. +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS2 AXI interface reset output asserted. +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS1 AXI interface reset output asserted. +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS0 AXI interface reset output asserted. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 1 reset is asserted. +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 0 reset is asserted. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface 1 soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0 - No reset. 1 - FPGA master interface 1 reset is asserted. +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0 - No reset. 1 - FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 3 peripheral request reset output asserted. +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 2 peripheral request reset output asserted. +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 1 peripheral request reset output asserted. +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 0 peripheral request reset output asserted. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0 - No reset. 1 - FPGA 3 top level reset output asserted. +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0 - No reset. 1 - FPGA 2 top level reset output asserted. +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0 - No reset. 1 - FPGA 1 top level reset output asserted. +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0 - No reset. 1 - FPGA 0 top level reset output asserted. +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_1_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/ps7_init.tcl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/ps7_init.tcl new file mode 100755 index 0000000..85a6f34 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/ps7_init.tcl @@ -0,0 +1,781 @@ +proc ps7_pll_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000701 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00500800 + mask_write 0XF8000180 0x03F03F30 0x00400500 + mask_write 0XF8000190 0x03F03F30 0x00200500 + mask_write 0XF80001A0 0x03F03F30 0x00100500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_3_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x0007FFFF 0x00001082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006024 0x0FFFFFC3 0x00000000 + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00000003 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x0003F03F 0x0003C008 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x00010000 0x00000000 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x00000200 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFCF 0x40000001 + mask_write 0XF800611C 0x7FFFFFCF 0x40000001 + mask_write 0XF8006120 0x7FFFFFCF 0x40000001 + mask_write 0XF8006124 0x7FFFFFCF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0x6FFFFEFE 0x00040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000703FF 0x000003FF + mask_write 0XF800620C 0x000703FF 0x000003FF + mask_write 0XF8006210 0x000703FF 0x000003FF + mask_write 0XF8006214 0x000703FF 0x000003FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF5 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000001 0x00000001 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001601 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003F01 0x00001601 + mask_write 0XF8000728 0x00003FFF 0x00001680 + mask_write 0XF800072C 0x00003FFF 0x00001680 + mask_write 0XF8000730 0x00003FFF 0x00001680 + mask_write 0XF8000734 0x00003FFF 0x00001680 + mask_write 0XF8000738 0x00003FFF 0x00001680 + mask_write 0XF800073C 0x00003FFF 0x00001680 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003F01 0x00001201 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F002E + mask_write 0XF8000834 0x003F003F 0x00090000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x000003FF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 +} +proc ps7_post_config_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_3_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000701 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00500800 + mask_write 0XF8000180 0x03F03F30 0x00400500 + mask_write 0XF8000190 0x03F03F30 0x00200500 + mask_write 0XF80001A0 0x03F03F30 0x00100500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_2_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001601 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003F01 0x00001601 + mask_write 0XF8000728 0x00003FFF 0x00001680 + mask_write 0XF800072C 0x00003FFF 0x00001680 + mask_write 0XF8000730 0x00003FFF 0x00001680 + mask_write 0XF8000734 0x00003FFF 0x00001680 + mask_write 0XF8000738 0x00003FFF 0x00001680 + mask_write 0XF800073C 0x00003FFF 0x00001680 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003F01 0x00001201 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F002E + mask_write 0XF8000834 0x003F003F 0x00090000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 +} +proc ps7_post_config_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_2_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000701 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00500800 + mask_write 0XF8000180 0x03F03F30 0x00400500 + mask_write 0XF8000190 0x03F03F30 0x00200500 + mask_write 0XF80001A0 0x03F03F30 0x00100500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_1_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x000073FF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001601 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003F01 0x00001601 + mask_write 0XF8000728 0x00003FFF 0x00001680 + mask_write 0XF800072C 0x00003FFF 0x00001680 + mask_write 0XF8000730 0x00003FFF 0x00001680 + mask_write 0XF8000734 0x00003FFF 0x00001680 + mask_write 0XF8000738 0x00003FFF 0x00001680 + mask_write 0XF800073C 0x00003FFF 0x00001680 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003F01 0x00001201 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F002E + mask_write 0XF8000834 0x003F003F 0x00090000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 +} +proc ps7_post_config_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_1_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +set PCW_SILICON_VER_1_0 "0x0" +set PCW_SILICON_VER_2_0 "0x1" +set PCW_SILICON_VER_3_0 "0x2" +set APU_FREQ 666666666 + + + +proc mask_poll { addr mask } { + set count 1 + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + while { $maskedval == 0 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + set count [ expr { $count + 1 } ] + if { $count == 100000000 } { + puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask" + break + } + } +} + + + +proc mask_delay { addr val } { + set delay [ get_number_of_cycles_for_delay $val ] + perf_reset_and_start_timer + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + while { $maskedval == 1 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + } + perf_reset_clock +} + +proc ps_version { } { + set si_ver "0x[string range [mrd 0xF8007080] end-8 end]" + set mask_sil_ver "0x[expr {$si_ver >> 28}]" + return $mask_sil_ver; +} + +proc ps7_post_config {} { + set saved_mode [configparams force-mem-accesses] + configparams force-mem-accesses 1 + + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_post_config_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_post_config_2_0 + } else { + ps7_post_config_3_0 + } + configparams force-mem-accesses $saved_mode +} + +proc ps7_debug {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_debug_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_debug_2_0 + } else { + ps7_debug_3_0 + } +} +proc ps7_init {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_mio_init_data_1_0 + ps7_pll_init_data_1_0 + ps7_clock_init_data_1_0 + ps7_ddr_init_data_1_0 + ps7_peripherals_init_data_1_0 + #puts "PCW Silicon Version : 1.0" + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_mio_init_data_2_0 + ps7_pll_init_data_2_0 + ps7_clock_init_data_2_0 + ps7_ddr_init_data_2_0 + ps7_peripherals_init_data_2_0 + #puts "PCW Silicon Version : 2.0" + } else { + ps7_mio_init_data_3_0 + ps7_pll_init_data_3_0 + ps7_clock_init_data_3_0 + ps7_ddr_init_data_3_0 + ps7_peripherals_init_data_3_0 + #puts "PCW Silicon Version : 3.0" + } +} + + +# For delay calculation using global timer + +# start timer + proc perf_start_clock { } { + + #writing SCU_GLOBAL_TIMER_CONTROL register + + mask_write 0xF8F00208 0x00000109 0x00000009 +} + +# stop timer and reset timer count regs + proc perf_reset_clock { } { + perf_disable_clock + mask_write 0xF8F00200 0xFFFFFFFF 0x00000000 + mask_write 0xF8F00204 0xFFFFFFFF 0x00000000 +} + +# Compute mask for given delay in miliseconds +proc get_number_of_cycles_for_delay { delay } { + + # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + variable APU_FREQ + return [ expr ($delay * $APU_FREQ /(2 * 1000))] +} + + +# stop timer +proc perf_disable_clock {} { + mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 +} + +proc perf_reset_and_start_timer {} { + perf_reset_clock + perf_start_clock +} + + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/ps7_init_gpl.h b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/ps7_init_gpl.h new file mode 100755 index 0000000..45a7839 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/ps7_init_gpl.h @@ -0,0 +1,131 @@ +/****************************************************************************** +* +* Copyright (C) 2010-2020 +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, see +* +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init_gpl.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + + + + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 142857132 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 25000000 +#define FPGA1_FREQ 50000000 +#define FPGA2_FREQ 100000000 +#define FPGA3_FREQ 200000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/xilinx-zynq.cc b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/xilinx-zynq.cc new file mode 100755 index 0000000..14e40f9 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/xilinx-zynq.cc @@ -0,0 +1,106 @@ +/* + * Xilinx SystemC/TLM-2.0 Zynq Wrapper. + * + * Written by Edgar E. Iglesias + * + * Copyright (c) 2016, Xilinx Inc. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#define SC_INCLUDE_DYNAMIC_PROCESSES + +#include + +#include "tlm_utils/simple_initiator_socket.h" +#include "tlm_utils/simple_target_socket.h" + +using namespace sc_core; +using namespace std; + +#include "xilinx-zynq.h" +#include + +//xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr, +// Iremoteport_tlm_sync *sync) +// : remoteport_tlm(name, -1, sk_descr, sync), +xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr) + : remoteport_tlm(name, -1, sk_descr), + rp_m_axi_gp0("rp_m_axi_gp0"), + rp_m_axi_gp1("rp_m_axi_gp1"), + rp_s_axi_gp0("rp_s_axi_gp0"), + rp_s_axi_gp1("rp_s_axi_gp1"), + rp_s_axi_hp0("rp_s_axi_hp0"), + rp_s_axi_hp1("rp_s_axi_hp1"), + rp_s_axi_hp2("rp_s_axi_hp2"), + rp_s_axi_hp3("rp_s_axi_hp3"), + rp_s_axi_acp("rp_s_axi_acp"), + rp_wires_in("wires_in", 20, 0), + rp_wires_out("wires_out", 0, 17), + rp_irq_out("irq_out", 0, 28), + pl2ps_irq("pl2ps_irq", 20), + ps2pl_irq("ps2pl_irq", 28), + ps2pl_rst("ps2pl_rst", 17) +{ + int i; + + m_axi_gp[0] = &rp_m_axi_gp0.sk; + m_axi_gp[1] = &rp_m_axi_gp1.sk; + + s_axi_gp[0] = &rp_s_axi_gp0.sk; + s_axi_gp[1] = &rp_s_axi_gp1.sk; + + s_axi_hp[0] = &rp_s_axi_hp0.sk; + s_axi_hp[1] = &rp_s_axi_hp1.sk; + s_axi_hp[2] = &rp_s_axi_hp2.sk; + s_axi_hp[3] = &rp_s_axi_hp3.sk; + s_axi_acp = &rp_s_axi_acp.sk; + + /* PL to PS Interrupt signals. */ + for (i = 0; i < 20; i++) { + rp_wires_in.wires_in[i](pl2ps_irq[i]); + } + + /* PS to PL Interrupt signals. */ + for (i = 0; i < 28; i++) { + rp_irq_out.wires_out[i](ps2pl_irq[i]); + } + + /* PS to PL resets. */ + for (i = 0; i < 17; i++) { + rp_wires_out.wires_out[i](ps2pl_rst[i]); + } + + register_dev(0, &rp_s_axi_gp0); + register_dev(1, &rp_s_axi_gp1); + + register_dev(2, &rp_s_axi_hp0); + register_dev(3, &rp_s_axi_hp1); + register_dev(4, &rp_s_axi_hp2); + register_dev(5, &rp_s_axi_hp3); + + register_dev(6, &rp_s_axi_acp); + + register_dev(7, &rp_m_axi_gp0); + register_dev(8, &rp_m_axi_gp1); + register_dev(9, &rp_wires_in); + register_dev(10, &rp_wires_out); + register_dev(11, &rp_irq_out); +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/Makefile b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/Makefile new file mode 100755 index 0000000..33394b3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/Makefile @@ -0,0 +1,26 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +INCLUDEFILES=*.h +LIBSOURCES=*.c +OUTS = *.o + +libs: + echo "Compiling SPI_Con..." + $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} + make clean + +include: + ${CP} $(INCLUDEFILES) $(INCLUDEDIR) + +clean: + rm -rf ${OUTS} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/NewExtInst_TOP.bda b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/NewExtInst_TOP.bda new file mode 100755 index 0000000..ab7b1f9 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/NewExtInst_TOP.bda @@ -0,0 +1,272 @@ +{ + "graphjs": { + "version": "1.0", + "keys": [ + { + "abrv": "VH", + "name": "vert_hid", + "type": "int", + "for": "node" + }, + { + "abrv": "VM", + "name": "vert_name", + "type": "string", + "for": "node" + }, + { + "abrv": "VT", + "name": "vert_type", + "type": "string", + "for": "node" + }, + { + "abrv": "BA", + "name": "base_addr", + "type": "string", + "for": "node" + }, + { + "abrv": "HA", + "name": "high_addr", + "type": "string", + "for": "node" + }, + { + "abrv": "BP", + "name": "base_param", + "type": "string", + "for": "node" + }, + { + "abrv": "HP", + "name": "high_param", + "type": "string", + "for": "node" + }, + { + "abrv": "MA", + "name": "master_addrspace", + "type": "string", + "for": "node" + }, + { + "abrv": "MX", + "name": "master_instance", + "type": "string", + "for": "node" + }, + { + "abrv": "MI", + "name": "master_interface", + "type": "string", + "for": "node" + }, + { + "abrv": "MS", + "name": "master_segment", + "type": "string", + "for": "node" + }, + { + "abrv": "MV", + "name": "master_vlnv", + "type": "string", + "for": "node" + }, + { + "abrv": "SX", + "name": "slave_instance", + "type": "string", + "for": "node" + }, + { + "abrv": "SI", + "name": "slave_interface", + "type": "string", + "for": "node" + }, + { + "abrv": "MM", + "name": "slave_memmap", + "type": "string", + "for": "node" + }, + { + "abrv": "SS", + "name": "slave_segment", + "type": "string", + "for": "node" + }, + { + "abrv": "SV", + "name": "slave_vlnv", + "type": "string", + "for": "node" + }, + { + "abrv": "TM", + "name": "memory_type", + "type": "string", + "for": "node" + }, + { + "abrv": "TU", + "name": "usage_type", + "type": "string", + "for": "node" + }, + { + "abrv": "LT", + "name": "lock_type", + "type": "string", + "for": "node" + }, + { + "abrv": "BT", + "name": "boot_type", + "type": "string", + "for": "node" + }, + { + "abrv": "EH", + "name": "edge_hid", + "type": "int", + "for": "edge" + } + ], + "vertice_type_order": [ + { + "abrv": "BC", + "desc": "Block Container" + }, + { + "abrv": "PR", + "desc": "Parital Reference" + }, + { + "abrv": "VR", + "desc": "Variant" + }, + { + "abrv": "PM", + "desc": "Variant Permutations" + }, + { + "abrv": "CX", + "desc": "Boundary Connection" + }, + { + "abrv": "AC", + "desc": "Assignment Coordinate" + }, + { + "abrv": "ACE", + "desc": "Excluded Assign Coordinate" + }, + { + "abrv": "APX", + "desc": "Boundary Aperture" + }, + { + "abrv": "CIP", + "desc": "High level Processing System" + } + ], + "vertices": { + "V0": { + "VM": "NewExtInst_TOP", + "VT": "BC" + }, + "V1": { + "VH": "2", + "VM": "NewExtInst_TOP", + "VT": "VR" + }, + "V2": { + "VH": "2", + "VT": "PM", + "TU": "active" + }, + "V3": { + "VT": "AC", + "BA": "0x43C00000", + "HA": "0x43C0FFFF", + "BP": "C_S00_AXI_BASEADDR", + "HP": "C_S00_AXI_HIGHADDR", + "MA": "Data", + "MX": "/processing_system7_0", + "MI": "M_AXI_GP0", + "MS": "SEG_SPI_Con_0_S00_AXI_reg", + "MV": "xilinx.com:ip:processing_system7:5.5", + "SX": "/SPI_Con_0", + "SI": "S00_AXI", + "SS": "S00_AXI_reg", + "SV": "xilinx.com:user:SPI_Con:1.0", + "TM": "both", + "TU": "register" + }, + "V4": { + "VT": "AC", + "BA": "0x43C10000", + "HA": "0x43C1FFFF", + "BP": "C_S00_AXI_BASEADDR", + "HP": "C_S00_AXI_HIGHADDR", + "MA": "Data", + "MX": "/processing_system7_0", + "MI": "M_AXI_GP0", + "MS": "SEG_SPI_Con_1_S00_AXI_reg", + "MV": "xilinx.com:ip:processing_system7:5.5", + "SX": "/SPI_Con_1", + "SI": "S00_AXI", + "SS": "S00_AXI_reg", + "SV": "xilinx.com:user:SPI_Con:1.0", + "TM": "both", + "TU": "register" + }, + "V5": { + "VT": "AC", + "BA": "0x43C20000", + "HA": "0x43C2FFFF", + "BP": "C_S00_AXI_BASEADDR", + "HP": "C_S00_AXI_HIGHADDR", + "MA": "Data", + "MX": "/processing_system7_0", + "MI": "M_AXI_GP0", + "MS": "SEG_SPI_Con_2_S00_AXI_reg", + "MV": "xilinx.com:ip:processing_system7:5.5", + "SX": "/SPI_Con_2", + "SI": "S00_AXI", + "SS": "S00_AXI_reg", + "SV": "xilinx.com:user:SPI_Con:1.0", + "TM": "both", + "TU": "register" + } + }, + "edges": [ + { + "src": "V0", + "trg": "V1" + }, + { + "src": "V1", + "trg": "V2" + }, + { + "src": "V3", + "trg": "V2", + "EH": "2" + }, + { + "src": "V4", + "trg": "V2", + "EH": "2" + }, + { + "src": "V5", + "trg": "V2", + "EH": "2" + } + ] + } +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/NewExtInst_TOP.sh b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/NewExtInst_TOP.sh new file mode 100755 index 0000000..ecd6868 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/NewExtInst_TOP.sh @@ -0,0 +1,287 @@ +#!/usr/bin/env bash +#********************************************************************************************************** +# Vivado (TM) v2023.2 (64-bit) +# +# Script generated by Vivado on Fri May 15 15:32:22 CST 2026 +# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 +# +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# +# Filename : NewExtInst_TOP.sh +# Simulator : Siemens ModelSim Simulator +# Description : Simulation script generated by export_simulation Tcl command +# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the +# design. The script will copy the library mapping file from the compiled library directory, +# create design library directories and library mappings in the mapping file. +# +# Usage : NewExtInst_TOP.sh +# NewExtInst_TOP.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]* +# NewExtInst_TOP.sh [-reset_run] +# NewExtInst_TOP.sh [-reset_log] +# NewExtInst_TOP.sh [-help] +# +# * The -noclean_files switch is deprecated and will not peform any function (by default, the +# simulator generated files will not be removed unless -reset_run switch is used) +# +# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library +# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help' +# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path +# switch with the directory path where the library is created while generating the script +# with export_simulation. +# +# Alternatively, you can set the library path by setting the following project property:- +# +# set_property compxlib._compiled_library_dir [current_project] +# +# You can also point to the simulation library by either setting the 'lib_map_path' global +# variable in this script or specify it with the '-lib_map_path' switch while executing this +# script (type 'NewExtInst_TOP.sh -help' for more information). +# +# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the +# generated script, but if design is targetted for system simulation containing SystemC/C++/C +# sources, then the library path MUST be specified upfront when calling export_simulation. +# +# For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************** + +# catch pipeline exit status +set -Eeuo pipefail + +# script info +echo -e "NewExtInst_TOP.sh - Script generated by export_simulation (Vivado v2023.2 (64-bit)-id)\n" + +# main steps +run() +{ + check_args $* + setup + if [[ ($b_step == 1) ]]; then + case $step in + "compile" ) + init_lib + compile + ;; + "simulate" ) + simulate + ;; + * ) + echo -e "ERROR: Invalid or missing step '$step' (type \"./NewExtInst_TOP.sh -help\" for more information)\n" + exit 1 + esac + else + init_lib + compile + simulate + fi +} + +# RUN_STEP: +compile() +{ + source compile.do 2>&1 | tee -a compile.log +} + +# RUN_STEP: +simulate() +{ + vsim -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + # delete previous files for a clean rerun + if [[ ($b_reset_run == 1) ]]; then + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + fi + + # delete previous log files + if [[ ($b_reset_log == 1) ]]; then + reset_log + echo -e "INFO: Simulation run log files deleted.\n" + exit 0 + fi + + # add any setup/initialization commands here:- + + # + +} + +# simulator index file/library directory processing +init_lib() +{ + if [[ ($b_keep_index == 1) ]]; then + # keep previous simulator index file + true + else + # copy simulator index file to current directory + copy_setup_file + fi + + if [[ ($lib_map_path != "") ]]; then + ref_lib_dir=$lib_map_path + fi + + if [[ ($b_keep_index == 1) ]]; then + # do not recreate design library directories + true + else + # create design library directories + create_lib_dir + fi +} + +# copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($lib_map_path == "") ]]; then + lib_map_path="/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/compile_simlib/modelsim" + fi + + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + fi +} + +# create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + mkdir $lib_dir +} + +# delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# delete generated log files from the previous run +reset_log() +{ + files_to_remove=(compile.log elaborate.log simulate.log) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# check switch argument value +check_arg_value() +{ + if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "simulate")) ]];then + echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then + echo -e "ERROR: Simulation library directory path not specified (type \"./NewExtInst_TOP.sh -help\" for more information)\n" + exit 1 + fi +} + +# check command line arguments +check_args() +{ + arg_count=$# + if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then + usage + fi + while [[ "$#" -gt 0 ]]; do + case $1 in + -step) check_arg_value $1 $2;step=$2; b_step=1; shift;; + -lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;; + -gen_bypass) b_gen_bypass=1 ;; + -reset_run) b_reset_run=1 ;; + -reset_log) b_reset_log=1 ;; + -keep_index) b_keep_index=1 ;; + -noclean_files) b_noclean_files=1 ;; + -help|-h) ;; + *) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;; + esac + shift + done + + # -reset_run is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then + echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -reset_log is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then + echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -keep_index is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then + echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -noclean_files is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then + echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi +} + +# script usage +usage() +{ + msg="Usage: NewExtInst_TOP.sh [-help]\n\ +Usage: NewExtInst_TOP.sh [-step]\n\ +Usage: NewExtInst_TOP.sh [-lib_map_path]\n\ +Usage: NewExtInst_TOP.sh [-reset_run]\n\ +Usage: NewExtInst_TOP.sh [-reset_log]\n\ +Usage: NewExtInst_TOP.sh [-keep_index]\n\ +Usage: NewExtInst_TOP.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-step ] -- Execute specified step (compile, simulate)\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\ +file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\ +NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\ +NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\ +[-reset_log] -- Delete simulator generated log files from the previous run\n\n\ +[-keep_index] -- Keep simulator index file settings from the previous run\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n" + echo -e $msg + exit 0 +} + +# initialize globals +step="" +lib_map_path="" +b_step=0 +b_lib_map_path=0 +b_gen_bypass=0 +b_reset_run=0 +b_reset_log=0 +b_keep_index=0 +b_noclean_files=0 + +# launch script +run $* diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/NewExtInst_TOP.udo b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/NewExtInst_TOP.udo new file mode 100644 index 0000000..e69de29 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/README.txt b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/README.txt new file mode 100644 index 0000000..1d27b8b --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/README.txt @@ -0,0 +1,50 @@ +################################################################################ +# Vivado (TM) v2023.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and how to fetch design source file details +# from the file_info.txt file. +# +# Generated by export_simulation on Fri May 15 15:32:22 CST 2026 +# +################################################################################ + +1. Steps to run the generated simulation script + +From the shell prompt in the current directory, issue the following command:- + +./NewExtInst_TOP.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first calls the 'check_args' function, the purpose of which +is to verify the generated script arguments and print error if incorrect switch +is specified. The 'run' function then calls the 'setup' function, the purpose of +which is to specify custom or initialization commands. The function also executes +following sub-functions:- +'reset_run' if -reset_run switch is specified. +'reset_log' if -reset_log switch is specified. + +The purpose of 'reset_run' function' is to delete the simulator generated design +data from the previous run and the purpose of 'reset_log' function' is to delete +the simulator generated log files. + +The 'run' function then calls the 'init_lib' function, the purpose of which is to +create design library mappings and directories. This function is called before the +'compile' step. By default, if '-step' switch is specified with the script then the +script will execute that specfic step, else it will execute all steps applicable +for the target simulator. + +For more information on the script, please type './NewExtInst_TOP.sh -help' + +2. Design source file information + +export_simulation generates a 'file_info.txt' file that contains design file information +based on the compile order when export_simulation was executed from Vivado. The file +contains information about the file name, type, library it is compiled into, whether +it is part of the IP, associated library, file path information in a comma separated +format. This file can be parsed to extract the required information for generating a +custom script or can be read from verification test infra. + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/SPI_Con.h b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/SPI_Con.h new file mode 100755 index 0000000..5278bdd --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/SPI_Con.h @@ -0,0 +1,107 @@ + +#ifndef SPI_CON_H +#define SPI_CON_H + + +/****************** Include Files ********************/ +#include "xil_types.h" +#include "xstatus.h" + +#define SPI_CON_S00_AXI_SLV_REG0_OFFSET 0 +#define SPI_CON_S00_AXI_SLV_REG1_OFFSET 4 +#define SPI_CON_S00_AXI_SLV_REG2_OFFSET 8 +#define SPI_CON_S00_AXI_SLV_REG3_OFFSET 12 +#define SPI_CON_S00_AXI_SLV_REG4_OFFSET 16 +#define SPI_CON_S00_AXI_SLV_REG5_OFFSET 20 +#define SPI_CON_S00_AXI_SLV_REG6_OFFSET 24 +#define SPI_CON_S00_AXI_SLV_REG7_OFFSET 28 +#define SPI_CON_S00_AXI_SLV_REG8_OFFSET 32 +#define SPI_CON_S00_AXI_SLV_REG9_OFFSET 36 +#define SPI_CON_S00_AXI_SLV_REG10_OFFSET 40 +#define SPI_CON_S00_AXI_SLV_REG11_OFFSET 44 +#define SPI_CON_S00_AXI_SLV_REG12_OFFSET 48 +#define SPI_CON_S00_AXI_SLV_REG13_OFFSET 52 +#define SPI_CON_S00_AXI_SLV_REG14_OFFSET 56 +#define SPI_CON_S00_AXI_SLV_REG15_OFFSET 60 +#define SPI_CON_S00_AXI_SLV_REG16_OFFSET 64 +#define SPI_CON_S00_AXI_SLV_REG17_OFFSET 68 +#define SPI_CON_S00_AXI_SLV_REG18_OFFSET 72 +#define SPI_CON_S00_AXI_SLV_REG19_OFFSET 76 +#define SPI_CON_S00_AXI_SLV_REG20_OFFSET 80 +#define SPI_CON_S00_AXI_SLV_REG21_OFFSET 84 +#define SPI_CON_S00_AXI_SLV_REG22_OFFSET 88 +#define SPI_CON_S00_AXI_SLV_REG23_OFFSET 92 +#define SPI_CON_S00_AXI_SLV_REG24_OFFSET 96 +#define SPI_CON_S00_AXI_SLV_REG25_OFFSET 100 +#define SPI_CON_S00_AXI_SLV_REG26_OFFSET 104 +#define SPI_CON_S00_AXI_SLV_REG27_OFFSET 108 +#define SPI_CON_S00_AXI_SLV_REG28_OFFSET 112 +#define SPI_CON_S00_AXI_SLV_REG29_OFFSET 116 +#define SPI_CON_S00_AXI_SLV_REG30_OFFSET 120 +#define SPI_CON_S00_AXI_SLV_REG31_OFFSET 124 + + +/**************************** Type Definitions *****************************/ +/** + * + * Write a value to a SPI_CON register. A 32 bit write is performed. + * If the component is implemented in a smaller width, only the least + * significant data is written. + * + * @param BaseAddress is the base address of the SPI_CONdevice. + * @param RegOffset is the register offset from the base to write to. + * @param Data is the data written to the register. + * + * @return None. + * + * @note + * C-style signature: + * void SPI_CON_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data) + * + */ +#define SPI_CON_mWriteReg(BaseAddress, RegOffset, Data) \ + Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data)) + +/** + * + * Read a value from a SPI_CON register. A 32 bit read is performed. + * If the component is implemented in a smaller width, only the least + * significant data is read from the register. The most significant data + * will be read as 0. + * + * @param BaseAddress is the base address of the SPI_CON device. + * @param RegOffset is the register offset from the base to write to. + * + * @return Data is the data from the register. + * + * @note + * C-style signature: + * u32 SPI_CON_mReadReg(u32 BaseAddress, unsigned RegOffset) + * + */ +#define SPI_CON_mReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (RegOffset)) + +/************************** Function Prototypes ****************************/ +/** + * + * Run a self-test on the driver/device. Note this may be a destructive test if + * resets of the device are performed. + * + * If the hardware system is not built correctly, this function may never + * return to the caller. + * + * @param baseaddr_p is the base address of the SPI_CON instance to be worked on. + * + * @return + * + * - XST_SUCCESS if all self-test code passed + * - XST_FAILURE if any self-test code failed + * + * @note Caching must be turned off for this function to work. + * @note Self test may fail if data memory and device are not on the same bus. + * + */ +XStatus SPI_CON_Reg_SelfTest(void * baseaddr_p); + +#endif // SPI_CON_H diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/SPI_Con.mdd b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/SPI_Con.mdd new file mode 100755 index 0000000..4bd813f --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/SPI_Con.mdd @@ -0,0 +1,10 @@ + + +OPTION psf_version = 2.1; + +BEGIN DRIVER SPI_Con + OPTION supported_peripherals = (SPI_Con); + OPTION copyfiles = all; + OPTION VERSION = 1.0; + OPTION NAME = SPI_Con; +END DRIVER diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/SPI_Con.tcl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/SPI_Con.tcl new file mode 100755 index 0000000..7f913c9 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/SPI_Con.tcl @@ -0,0 +1,5 @@ + + +proc generate {drv_handle} { + xdefine_include_file $drv_handle "xparameters.h" "SPI_Con" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR" +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/file_info.txt b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/file_info.txt new file mode 100644 index 0000000..7320d80 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/file_info.txt @@ -0,0 +1,39 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" 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+NewExtInst_TOP.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/sim/NewExtInst_TOP.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/glbl.v b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/libps7.dll b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/libps7.dll new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/libps7.dll @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/libps7.so b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/libps7.so new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/libps7.so @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/libremoteport.dll b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/libremoteport.dll new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/libremoteport.dll @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/libremoteport.so b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/libremoteport.so new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/libremoteport.so @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/ps7_init.h b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/ps7_init.h new file mode 100755 index 0000000..224d7ea --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/ps7_init.h @@ -0,0 +1,117 @@ +/****************************************************************************** +* +* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + + + + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 142857132 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 25000000 +#define FPGA1_FREQ 50000000 +#define FPGA2_FREQ 100000000 +#define FPGA3_FREQ 200000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/ps7_init.html b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/ps7_init.html new file mode 100755 index 0000000..9ca53bd --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/ps7_init.html @@ -0,0 +1,125613 @@ + + + + +Zynq PS configuration detail + + + +

    +
    + +
  • +
    Zynq PS Register Summary Viewer +
    +
    • +     +
    +
    +
    + +
    Zynq PS7 Summary Report +
    +     +
    User Configurations +
    +
    + +
    MIO Configurations +
    +     +
    + +
    CLK Configurations +
    +     +
    + +
    DDR Configurations +
    +     +
    + +
    SMC Configurations +
    +     +
    +
    +
    Select Version: + +
    +
    +
    Zynq Register View +
    +
    + +
    MIO Registers +
    +     + +
    PLL Registers +
    +     + +
    Clock Registers +
    +     + +
    DDR Registers +
    +     + +
    Peripherals Registers +
    +     +
    +
    This design is targeted for xc7z035 board (part number: xc7z035ffg676-2) + +
    +

    Zynq Design Summary

    + + + + + + + + + + + + + + + + + + + + + +
    +Device + +xc7z035 +
    +SpeedGrade + +-2 +
    +Part + +xc7z035ffg676-2 +
    +Description + +Zynq PS Configuration Report with register details +
    +Vendor + +Xilinx +
    +

    MIO Table View

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +MIO Pin + +Peripheral + +Signal + +IO Type + +Speed + +Pullup + +Direction +
    +MIO 0 + +SD 1 + +wp + +LVCMOS 3.3V + +slow + +enabled + +in +
    +MIO 1 + +Quad SPI Flash + +qspi0_ss_b + +LVCMOS 3.3V + +slow + +enabled + +out +
    +MIO 2 + +Quad SPI Flash + +qspi0_io[0] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 3 + +Quad SPI Flash + +qspi0_io[1] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 4 + +Quad SPI Flash + +qspi0_io[2] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 5 + +Quad SPI Flash + +qspi0_io[3]/HOLD_B + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 6 + +Quad SPI Flash + +qspi0_sclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 7 + + + + + + + + + + + + +
    +MIO 8 + +Quad SPI Flash + +qspi_fbclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 9 + +SD 1 + +cd + +LVCMOS 3.3V + +slow + +enabled + +in +
    +MIO 10 + +SD 1 + +data[0] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 11 + +SD 1 + +cmd + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 12 + +SD 1 + +clk + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 13 + +SD 1 + +data[1] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 14 + +SD 1 + +data[2] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 15 + +SD 1 + +data[3] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 16 + +Enet 0 + +tx_clk + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 17 + +Enet 0 + +txd[0] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 18 + +Enet 0 + +txd[1] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 19 + +Enet 0 + +txd[2] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 20 + +Enet 0 + +txd[3] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 21 + +Enet 0 + +tx_ctl + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 22 + +Enet 0 + +rx_clk + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 23 + +Enet 0 + +rxd[0] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 24 + +Enet 0 + +rxd[1] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 25 + +Enet 0 + +rxd[2] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 26 + +Enet 0 + +rxd[3] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 27 + +Enet 0 + +rx_ctl + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 28 + + + + + + + + + + + + +
    +MIO 29 + + + + + + + + + + + + +
    +MIO 30 + + + + + + + + + + + + +
    +MIO 31 + + + + + + + + + + + + +
    +MIO 32 + + + + + + + + + + + + +
    +MIO 33 + + + + + + + + + + + + +
    +MIO 34 + + + + + + + + + + + + +
    +MIO 35 + + + + + + + + + + + + +
    +MIO 36 + + + + + + + + + + + + +
    +MIO 37 + + + + + + + + + + + + +
    +MIO 38 + + + + + + + + + + + + +
    +MIO 39 + + + + + + + + + + + + +
    +MIO 40 + +SD 0 + +clk + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 41 + +SD 0 + +cmd + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 42 + +SD 0 + +data[0] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 43 + +SD 0 + +data[1] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 44 + +SD 0 + +data[2] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 45 + +SD 0 + +data[3] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 46 + +SD 0 + +wp + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 47 + +SD 0 + +cd + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 48 + +UART 1 + +tx + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 49 + +UART 1 + +rx + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 50 + + + + + + + + + + + + +
    +MIO 51 + + + + + + + + + + + + +
    +MIO 52 + +Enet 0 + +mdc + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 53 + +Enet 0 + +mdio + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +

    DDR Memory information

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Parameter name + +Value + +Description +
    +Enable DDR + +1 + +Enable DDR Controller of Zynq PS +
    +Memory Part + +MT41J256M16 RE-125 + + +
    +DRAM bus width + +32 Bit + +Select the desired data width. Refer to the Thechnical Reference Manual(TRM) for a detailed list of supported DDR data widths +
    +ECC + +Disabled + +ECC is supported only for data width of 16-bit +
    +BURST Length (lppdr only) + +8 + +Select the burst Length. It refers to the amount of data read/written after a read/write command is presented to the controller +
    +Internal Vref + +0 + + +
    +Operating Frequency (MHz) + +533.333333 + +Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade +
    +HIGH temperature + +Normal (0-85) + +Select the operating temparature +
    +DRAM IC bus width + +16 Bits + +Provide the width of the DRAM chip +
    +DRAM Device Capacity + +4096 MBits + + +
    +Speed Bin + +DDR3_1066F + +Provide the Speed Bin +
    +BANK Address Count + +3 + +Defines the bank to which an active an ACTIVE, READ, WRITE, or Precharge Command is being applied +
    +ROW Address Count + +15 + +Provide the Row address for ACTIVE commands +
    +COLUMN Address Count + +10 + +Provide the Row address for READ/WRITE commands +
    +CAS Latency + +7 + +Select the Column Access Strobe (CAS) Latency. It refers to the amount of time it takes for data to appear on the pins of the memory module +
    +CAS Write Latency + +6 + +Select the CAS Write Latency +
    +RAS to CAS Delay + +7 + +Provide the row address to column address delay time. tRCD is t he time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS) +
    +RECHARGE Time + +7 + +Precharge Time (tRP) is the number of clock cycles needed o terminate acces s to an open row of memory, and open access to the next row +
    +tRC (ns ) + +48.91 + +Provide the Row cycle time tRC (ns) +
    +tRASmin ( ns ) + +35.0 + +tRASmin (ns) is the minimum number of clock cycles required between an Active command and issuing the Precharge command +
    +tFAW + +40.0 + +It restricts the number of activates that can be done within a certain window of time +
    +ADDITIVE Latency + +0 + +Provide the Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths +
    +Write levelling + +1 + + +
    +Read gate + +1 + + +
    +Read gate + +1 + + +
    +DQS to Clock delay [0] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [1] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [2] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [3] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +Board delay [0] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [1] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [2] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [3] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +

    PS Clocks information

    +

    PS Reference Clock : 33.333333

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Peripheral + +PLL source + +Frequency (MHz) +
    +CPU 6x Freq (MHz) + +ARM PLL + +666.666687 +
    +QSPI Flash Freq (MHz) + +IO PLL + +142.857132 +
    +ENET0 Freq (MHz) + +IO PLL + +125.000000 +
    +SDIO Freq (MHz) + +IO PLL + +100.000000 +
    +SDIO Freq (MHz) + +IO PLL + +100.000000 +
    +UART Freq (MHz) + +IO PLL + +100.000000 +
    +FPGA0 Freq (MHz) + +IO PLL + +25.000000 +
    +FPGA1 Freq (MHz) + +IO PLL + +50.000000 +
    +FPGA2 Freq (MHz) + +IO PLL + +100.000000 +
    +FPGA3 Freq (MHz) + +IO PLL + +200.000000 +
    +

    ps7_pll_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: ARM PLL 10: DDR PLL 11: IO PLL This field is reset by POR only. +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for programming the PLL. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock and Rx Signals Select +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +FPGA1_CLK_CTRL + + +0XF8000180 + +32 + +RW + +0x000000 + +PL Clock 1 Output control +
    + +FPGA2_CLK_CTRL + + +0XF8000190 + +32 + +RW + +0x000000 + +PL Clock 2 output control +
    + +FPGA3_CLK_CTRL + + +0XF80001A0 + +32 + +RW + +0x000000 + +PL Clock 3 output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source of the Rx clock, control and data signals: 0: MIO 1: EMIO +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock and Rx Signals Select +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +7 + +700 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +701 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a03 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +5 + +500000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +500800 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )FPGA1_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA1_CLK_CTRL + +0XF8000180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA1_CLK_CTRL@0XF8000180 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 1 Output control +
    +

    +

    Register ( slcr )FPGA2_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA2_CLK_CTRL + +0XF8000190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +2 + +200000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA2_CLK_CTRL@0XF8000190 + +31:0 + +3f03f30 + + + +200500 + +PL Clock 2 output control +
    +

    +

    Register ( slcr )FPGA3_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA3_CLK_CTRL + +0XF80001A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA3_CLK_CTRL@0XF80001A0 + +31:0 + +3f03f30 + + + +100500 + +PL Clock 3 output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ratio: (When this register changes, no access are allowed to OCM.) 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +1 + +800 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec0c4d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +82 + +82 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reserved_reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Reserved. Do not modify. +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +Two_rank_cfg@0XF8006004 + +31:0 + +7ffff + + + +1082 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a1 + +2840 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4285b + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +13 + +13 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d3 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. In non-LPDDR mode, the minimum DRAM Write Latency (DDR2) supported is 3. In LPDDR mode, the required DRAM Write Latency of 1 is supported. Since write latency (CWL) min is 3, and DDR2 CWL is CL-1, the min (DDR2) CL supported is 4 +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +f + +3c00 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +5 + +28000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +5 + +2800000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +7282bce5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_en_dfi_dram_clk_disable + +23:23 + +800000 + +0 + +0 + +Enables the assertion of ddrc_dfi_dram_clk_disable. In DDR2/DDR3, only asserted in Self Refresh. In mDDR/LPDDR2, can be asserted in following: - during normal operation (Clock Stop), - in Power Down - in Self Refresh - In Deep Power Down +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +7fdffffc + + + +270872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffc3 + + + +0 + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2: Value loaded into EMR2 register DDR3: Value loaded into MR2 register LPDDR2: Value loaded into MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2: Value loaded into EMR3 register DDR3: Value loaded into MR3 register. Set Bit[2:0] to 3'b000. These bits are set appropriately by the Controller during Read Data eye training and Read DQS gate leveling. LPDDR2: Unused +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +b30 + +b30 + +DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2: Value loaded into EMR1register. (Bits[9:7] are for OCD and the setting in this reg is ignored. Controller sets this bits appropriately during initialization DDR3: Value loaded into MR1 register. Set Bit[7] to 0. This bit is set appropriately by the Controller during Write Leveling LPDDR2: Value loaded into MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40b30 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 8, Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 7, Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 6, Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 5, Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reserved_reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +Reserved. Do not modify. +
    +reserved_reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Reserved. Do not modify. +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3f03f + + + +3c008 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +10000 + + + +0 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum d'128) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_2d@0XF80060B4 + +31:0 + +200 + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of uncorrectable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on board topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +0: Use reg_phy_ctrl_slave_ratio for address/command timing slave DLL 1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_64@0XF8006190 + +31:0 + +6ffffefe + + + +40080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. This feature should only be enabled after LPDDR2 initialization is completed +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff5 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Powerdown mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQ pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQS pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +Drive and Slew controls for Clock pins of the DDR Interface +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SD1_WP_CD_SEL + + +0XF8000834 + +32 + +RW + +0x000000 + +SDIO 1 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQ pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQS pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for Clock pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1x: Enable External VREF for upper 16 bits +
    +reserved_VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Reserved. Do not modify. +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +reserved_REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +1 + + + +1 + +DDR IOB DCI Config +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialize flops in DCI system +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDR IOB DCI Config +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +DCI System Enable. Set to 1 if any IOs in DDR IO Bank use DCI Termination. DDR2, DDR3 and LPDDR2 (Silicon Revision 2.0+) configurations require this bit set to 1 +
    +reserved_VRP_TRI + +2:2 + +4 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_TRI + +3:3 + +8 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRP_OUT + +4:4 + +10 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT1 + +15:14 + +c000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update Mode. Use the values in the Calibration Table. +
    +reserved_INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_CLK + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLN + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLP + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_RST + +25:25 + +2000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7feffff + + + +823 + +DDR IOB DCI Config +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. 0: disable 1: enable +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables Pullup on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3f01 + + + +1601 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3f01 + + + +1601 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1680 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1680 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait, Input 10: NAND Flash IO Bit 7, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 12 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1680 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5, Input/Output 10: NAND Flash IO Bit 3, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 13 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1680 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1680 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1680 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1, Output 10: NAND Flash IO Bit 8, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2, Output 10: NAND Flash IO Bit 9, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110 TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3, Output 10: NAND Flash IO Bit 10, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6, Output 10: NAND Flash IO Bit 13, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3f01 + + + +1201 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +2e + +2e + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f002e + +SDIO 0 WP CD select +
    +

    +

    Register ( slcr )SD1_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD1_WP_CD_SEL + +0XF8000834 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO1_WP_SEL + +5:0 + +3f + +0 + +0 + +SDIO 1 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO1_CD_SEL + +21:16 + +3f0000 + +9 + +90000 + +SDIO 1 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD1_WP_CD_SEL@0XF8000834 + +31:0 + +3f003f + + + +90000 + +SDIO 1 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +Baud Rate Divider Register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud Rate Generator Register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control Register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode Register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +Baud Rate Divider Register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud Rate Generator Register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter 1: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: enable 1: disable, regardless of the value of RXEN +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed. +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed. +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control Register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +3ff + + + +20 + +UART Mode Register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes . If not set, then external pull up is required on HOLDb and WPn pins . Note that this bit doesn't affect the quad(4-bit) mode as Controller always drives these pins in quad mode. It is highly recommended to set this bit always(irrespective of mode of operation) while using QSPI +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This register controls which POR timer the PL will use for power-up. 0 - Use 64k timer 1 - Use 4k timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    ENET RESET

    +

    I2C RESET

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_LVL_INP_EN_0 + +3:3 + +8 + +1 + +8 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_0 + +2:2 + +4 + +1 + +4 + +Level shifter enable to drive signals from PS to PL +
    +USER_LVL_INP_EN_1 + +1:1 + +2 + +1 + +2 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_1 + +0:0 + +1 + +1 + +1 + +Level shifter enable to drive signals from PS to PL +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +Reserved. Do not modify. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +PL Reset 3 (FCLKRESETN3 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN3 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +PL Reset 2 (FCLKRESETN2 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN2 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +PL Reset 1 (FCLKRESETN1 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN1 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +PL Reset 0 (FCLKRESETN0 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN0 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    AFI2 SECURE REGISTER

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_3_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: CPU PLL 10: divided DDR PLL 11: IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +FPGA1_CLK_CTRL + + +0XF8000180 + +32 + +RW + +0x000000 + +PL Clock 1 Output control +
    + +FPGA2_CLK_CTRL + + +0XF8000190 + +32 + +RW + +0x000000 + +PL Clock 2 output control +
    + +FPGA3_CLK_CTRL + + +0XF80001A0 + +32 + +RW + +0x000000 + +PL Clock 3 output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source to generate the Rx clock: 0: MIO Rx clock, 1: EMIO Rx clock +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +7 + +700 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +701 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a03 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +5 + +500000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +500800 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )FPGA1_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA1_CLK_CTRL + +0XF8000180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA1_CLK_CTRL@0XF8000180 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 1 Output control +
    +

    +

    Register ( slcr )FPGA2_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA2_CLK_CTRL + +0XF8000190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +2 + +200000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA2_CLK_CTRL@0XF8000190 + +31:0 + +3f03f30 + + + +200500 + +PL Clock 2 output control +
    +

    +

    Register ( slcr )FPGA3_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA3_CLK_CTRL + +0XF80001A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA3_CLK_CTRL@0XF80001A0 + +31:0 + +3f03f30 + + + +100500 + +PL Clock 3 output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ration: 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +1 + +800 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec0c4d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config0 + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config1 + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 1. +
    + +PHY_Config2 + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 2. +
    + +PHY_Config3 + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 3. +
    + +phy_init_ratio0 + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio1 + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 1. +
    + +phy_init_ratio2 + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 2. +
    + +phy_init_ratio3 + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 3. +
    + +phy_rd_dqs_cfg0 + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg1 + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 1. +
    + +phy_rd_dqs_cfg2 + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 2. +
    + +phy_rd_dqs_cfg3 + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 3. +
    + +phy_wr_dqs_cfg0 + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg1 + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 1. +
    + +phy_wr_dqs_cfg2 + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 2. +
    + +phy_wr_dqs_cfg3 + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 3. +
    + +phy_we_cfg0 + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg1 + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 1. +
    + +phy_we_cfg2 + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 2. +
    + +phy_we_cfg3 + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 3. +
    + +wr_data_slv0 + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv1 + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 1. +
    + +wr_data_slv2 + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 2. +
    + +wr_data_slv3 + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 3. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port0 + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port1 + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 1. +
    + +axi_priority_wr_port2 + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 2. +
    + +axi_priority_wr_port3 + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 3. +
    + +axi_priority_rd_port0 + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port1 + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 1. +
    + +axi_priority_rd_port2 + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 2. +
    + +axi_priority_rd_port3 + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 3. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +82 + +82 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Rank configuration: 01: One Rank of DDR 11: Two Ranks of DDR Others: reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +Block read/write scheduling cycle count when Write requires changing ODT settings 00: 1 cycle 01: 2 cycles 10: 3 cycles others: reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0: schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1: schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81082 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a1 + +2840 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4285b + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +13 + +13 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d3 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +f + +3c00 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +5 + +28000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +5 + +2800000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +7282bce5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1: sdram device 0: non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: stop_clk will never be asserted. 1: enable the assertion of stop_clk to the PHY whenever a clock is not required +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2 and DDR3: Value written into the DRAM EMR2 register. LPDDR2: Value written into the DRAM MR3 register. +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2 and DDR3: Value written into the DRAM EMR3 register. LPDDR2: not used. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +b30 + +b30 + +DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2 and DDR3: Value written into the DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. LPDDR2: Value written into the DRAM MR2 register. +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40b30 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODTs must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config0 + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config0@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config1 + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config1@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 1. +
    +

    +

    Register ( slcr )PHY_Config2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config2 + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config2@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 2. +
    +

    +

    Register ( slcr )PHY_Config3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config3 + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config3@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_init_ratio0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio0 + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio0@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio1 + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio1@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 1. +
    +

    +

    Register ( slcr )phy_init_ratio2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio2 + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio2@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 2. +
    +

    +

    Register ( slcr )phy_init_ratio3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio3 + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio3@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 3. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg0 + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg0@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg1 + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg1@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg2 + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg2@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg3 + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg3@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg0 + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg0@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg1 + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg1@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg2 + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg2@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg3 + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg3@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_we_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg0 + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg0@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg1 + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg1@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 1. +
    +

    +

    Register ( slcr )phy_we_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg2 + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg2@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 2. +
    +

    +

    Register ( slcr )phy_we_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg3 + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg3@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 3. +
    +

    +

    Register ( slcr )wr_data_slv0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv0 + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv0@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv1 + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv1@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 1. +
    +

    +

    Register ( slcr )wr_data_slv2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv2 + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv2@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 2. +
    +

    +

    Register ( slcr )wr_data_slv3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv3 + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv3@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 3. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +0: (default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) 1: assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 0: Each Rank uses its own delay 1: Rank 0 delays are used for all ranks +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1: enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port0 + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port0@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port1 + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port1@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 1. +
    +

    +

    Register ( slcr )axi_priority_wr_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port2 + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port2@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 2. +
    +

    +

    Register ( slcr )axi_priority_wr_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port3 + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port3@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 3. +
    +

    +

    Register ( slcr )axi_priority_rd_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port0 + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port0@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port1 + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port1@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 1. +
    +

    +

    Register ( slcr )axi_priority_rd_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port2 + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port2@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 2. +
    +

    +

    Register ( slcr )axi_priority_rd_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port3 + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port3@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 3. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +0:All bank refresh Per bank refresh allows traffic to flow to other banks. 1:Per bank refresh Per bank refresh is not supported on all LPDDR2 devices. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Power-down mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 0 +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 1 +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDR IOB Slew for Address +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDR IOB Slew for Data +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDR IOB Slew for Diff +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDR IOB Slew for Clock +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SD1_WP_CD_SEL + + +0XF8000834 + +32 + +RW + +0x000000 + +SDIO 1 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 0 +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 1 +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDR IOB Slew for Address +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Data +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Diff +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Clock +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1X: Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors x0: Disable VREF pull-up for lower 16 bits x1: Enable VREF pull-up for lower 16 bits 0x: Disable VREF pull-up for upper 16 bits 1x: Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Enable test mode for VRP and VRN: 00: VRP/VRN test mode not used 11: VRP/VRN test mode enabled using vref based receiver. VRP/VRN control is set using the VRN_OUT, VRP_OUT, VRN_TRI, VRP_TRI fields in the DDRIOB_DCI_CTRL register +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0: no pull-up 1: enable pull-up +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. 0: disable 1: enable +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables pull-up on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3f01 + + + +1601 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3f01 + + + +1601 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1680 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1680 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait 10: NAND Flash IO Bit 7 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 12 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1680 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5 10: NAND Flash IO Bit 3 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 13 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1680 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1680 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1680 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1 10: NAND Flash IO Bit 8 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Output 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2 10: NAND Flash IO Bit 9 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110 TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3 10: NAND Flash IO Bit 10 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6 10: NAND Flash IO Bit 13 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3f01 + + + +1201 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +2e + +2e + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f002e + +SDIO 0 WP CD select +
    +

    +

    Register ( slcr )SD1_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD1_WP_CD_SEL + +0XF8000834 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO1_WP_SEL + +5:0 + +3f + +0 + +0 + +SDIO 1 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO1_CD_SEL + +21:16 + +3f0000 + +9 + +90000 + +SDIO 1 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD1_WP_CD_SEL@0XF8000834 + +31:0 + +3f003f + + + +90000 + +SDIO 1 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass 2 - 65535: baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: start break transmission, 1: stop break transmission. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: 1: start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 0: receiver timeout counter disabled, 1: receiver timeout counter is restarted. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter, 0: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter, 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: disable, 1: enable +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable, 1: enable. When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: 1: transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: 1: receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode: 0: Default UART mode 1: Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select: 0: APB clock, pclk 1: a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: 00: normal 01: automatic cho 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: 0: clock source is uart_clk 1: clock source is uart_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    ENET RESET

    +

    I2C RESET

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset: 0: No reset 1: ACP AXI interface reset output asserted +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0: No reset 1: AXDS3AXI interface reset output asserted +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0: No reset 1: AXDS2 AXI interface reset output asserted +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0: No reset 1: AXDS1 AXI interface reset output asserted +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0: No reset 1: AXDS0 AXI interface reset output asserted +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0: No reset 1: FPGA slave interface 1 reset is asserted +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0: No reset 1: FPGA slave interface 0 reset is asserted +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface: 1: soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0: No reset 1: FPGA master interface 1 reset is asserted +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0: No reset 1: FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 3 peripheral request reset output asserted +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 2 peripheral request reset output asserted +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 1 peripheral request reset output asserted +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 0 peripheral request reset output asserted +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0: No reset 1: FPGA 3 top level reset output asserted +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0: No reset 1: FPGA 2 top level reset output asserted +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0: No reset 1: FPGA 1 top level reset output asserted +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0: No reset 1: FPGA 0 top level reset output asserted +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_2_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CORTEX A9 Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status. 0 - ARM PLL out of lock. 1 - ARM PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is CPU PLL. 10 - Source for generated clock is DDR divided clock. 11 - Source for generated clock is IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CORTEX A9 Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status. 0 - DDR PLL out of lock. 1 - DDR PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Divisor value for the ddr_3xclk +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk) +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status. 0 - IO PLL out of lock. 1 - IO PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 RX Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Linear Quad-SPI Reference Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Reference Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Reference Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP 2X Clock Contol +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +FPGA 0 Output Clock Control +
    + +FPGA1_CLK_CTRL + + +0XF8000180 + +32 + +RW + +0x000000 + +FPGA 1 Output Clock Control +
    + +FPGA2_CLK_CTRL + + +0XF8000190 + +32 + +RW + +0x000000 + +FPGA 2 Output Clock Control +
    + +FPGA3_CLK_CTRL + + +0XF80001A0 + +32 + +RW + +0x000000 + +FPGA 3 Output Clock Control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +6:2:1 ratio clock, if set +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Selects the source used to generate the clock. 0 - Source for generated clock is GEM 0 MIO RX clock. 1 - Source for generated clock is GEM 0 FMIO RX clock. +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +Gigabit Ethernet MAC 0 RX Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source used to generate the clock. 1xx - Source for generated clock is Ethernet 0 FMIO clock. 00x - Source for generated clock is IO PLL. 010 - Source for generated clock is ARM PLL. 011 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +7 + +700 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +701 + +Linear Quad-SPI Reference Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO 0 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +SDIO 1 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a03 + +SDIO Reference Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Reference Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active 0 - Clock is disabled 1 - Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP 2X Clock Contol +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +5 + +500000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +500800 + +FPGA 0 Output Clock Control +
    +

    +

    Register ( slcr )FPGA1_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA1_CLK_CTRL + +0XF8000180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA1_CLK_CTRL@0XF8000180 + +31:0 + +3f03f30 + + + +400500 + +FPGA 1 Output Clock Control +
    +

    +

    Register ( slcr )FPGA2_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA2_CLK_CTRL + +0XF8000190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +2 + +200000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA2_CLK_CTRL@0XF8000190 + +31:0 + +3f03f30 + + + +200500 + +FPGA 2 Output Clock Control +
    +

    +

    Register ( slcr )FPGA3_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA3_CLK_CTRL + +0XF80001A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA3_CLK_CTRL@0XF80001A0 + +31:0 + +3f03f30 + + + +100500 + +FPGA 3 Output Clock Control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Enable the 6:2:1 mode. 1 for 6:3:2:1. 0 for 4:2:2:1. +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +6:2:1 ratio clock, if set +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet MAC 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet MAC 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +1 + +800 + +SDIO 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +LQSPI AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec0c4d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two rank configuration register +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control register +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control register +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control register +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters register 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters register 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters register 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters register 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters register 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM initialization parameters register +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access register +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access register +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM burst 8 read/write register +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ register +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM bank address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT register +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO register +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration register +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold register +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller register 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller register 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller register 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller register 4 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters register +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters register +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown register +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control register +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug register +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing register +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear register +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction register +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status register +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count register +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub register +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control register (2) +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control register (3) +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask register +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 Register +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 Register +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 Register +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 Register +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control Register +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +82 + +82 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Only present for multi-rank configurations. Each bit represents one rank. 1=populated; 0=unpopulated 01 = One Rank 11 = Two Ranks Others = Reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +00 = block read/write scheduling for 1-cycle when Write requires changing ODT settings 01 = block read/write scheduling for 2 cycles when Write requires changing ODT settings 10 = block read/write scheduling for 3 cycles when Write requires changing ODT settings 11 = Reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0 = schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1 = schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81082 + +Two rank configuration register +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of clocks that the HPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control register +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control register +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control register +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a1 + +2840 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks DRAM RELATED +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4285b + +DRAM Parameters register 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +13 + +13 + +Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. LPDDR2 mode: Set this to the larger of tCKE or tCKESR. Non-LPDDR2 designs: Set this to tCKE value. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d3 + +DRAM Parameters register 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2/3 -> WL -1 LPDDR -> 1 LPDDR2 ->WL Where WL = Write Latency of DRAM DRAM RELATED. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. non-LPDDR2 -> RL + BL/2 + 2 - WL LPDDR2 -> RL + BL/2 + RU(tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +f + +3c00 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +5 + +28000 + +tXP: Minimum time after power down exit to any operation. DRAM RELATED. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +5 + +2800000 + +Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency DRAM RELATED +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +7282bce5 + +DRAM Parameters register 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1 DRAM RELATED +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1 = sdram device 0 = non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-mobile DRAM device in use. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +1=enable the assertion of stop_clk to the PHY whenever a clock is not required by LPDDR/ LPDDR2. 0=stop_clk will never be asserted. Note: This is only present for implementations supporting LPDDR/LPDDR2 devices. +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Set to RL. Time from Read command to Read data on DRAM interface. Unit: clocks This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. RL = Read Latency of DRAM Note: This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1 = disable the pad power down feature 0 = Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters register 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1 = DDRC will use 2T timing 0 = DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1 = Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and 'ddrc_reg_mr_wr_busy' is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +Mode register address - for non-LPDDR2 modes. This register is don't care in LPDDR2 mode 00 = MR0 01 = MR1 10 = MR2 11 = MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +Mode register write data - for non-LPDDR2 modes. For LPDDR2, these 16-bits are interpreted as Writes: \'7bMR Addr[7:0], MR Data[7:0]\'7d. Reads: \'7bMR Addr[7:0], Don't Care[7:0]\'7d +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 1 = Indicates that mode register write / read operation is in progress. 0 = Indicates that the core can initiate a mode register write / read operation. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 1 = read 0 = write +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 1'b0 by default. This bit will be cleared (1'b0), whenever a Mode Register Read command is issued. This bit will be set to 1'b1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters register 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands DRAM RELATED Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM initialization parameters register +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +Non LPDDR2- Value to be loaded into DRAM EMR2 registers. For LPDDR2 - Value to Write to the MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +Non LPDDR2- Value to be loaded into DRAM EMR3 registers. Used in non-LPDDR2 designs only. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access register +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +b30 + +b30 + +Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +Non LPDDR2-Value to be loaded into DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. For LPDDR2 - Value to Write to the MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40b30 + +DRAM EMR, MR access register +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +This controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. In LPDDR and LPDDR2, Burst length of 16 is supported only in Half Bus Width mode. Every input read/write command has 4 cycles of data associated with it and that is not enough data for doing Burst Length16 in Full Bus Width mode. 0010 - Burst length of 4 0100 - Burst length of 8 1000 - Burst length of 16 (only supported for LPDDR AND LPDDR2) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM burst 8 read/write register +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Active Low signal. When asserted (0), all incoming transactions will be forced to low priority. Forcing the incoming transactions to low priority implicitly turns OFF Bypass. Otherwise, HPR is allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. This bit is intended to be switched on-the-fly +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ register +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14 Internal Base: 5 The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Selects the address bits used as DRAM bank address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Selects the address bits used as DRAM column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Selects the address bits used as DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODT's must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT register +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1 = stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO register +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration register +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable for LPDDR and LPDDR2 modes. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold register +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +When 1, disable Write Combine +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to '0', auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller register 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +1 - Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on 'urgent' input coming from AXI master. 0 - Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 1'b0. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller register 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) Only present in designs that support DDR3 and LPDDR2 devices. +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Only present in designs that support DDR3 devices +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. Only present in designs that support DDR3 devices. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller register 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller register 4 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters register +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters register +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +1 - Controller puts the DRAM into Deep Powerdown mode when the transaction store is empty. 0 - Brings Controller out of Deep Powerdown mode Present only in designs configured to support LPDDR or LPDDR2 FOR PERFORMANCE ONLY. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown register +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +1 = Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0 = Write leveling disabled. +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +1 = Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0= Read DQS gate leveling is disabled. +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +1 = Read Data Eye training mode has been enabled as part of init sequence. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control register +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1 - Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0 - Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug register +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. Non-LPDDR -> RL-1 LPDDR -> RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing register +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear register +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when a correctable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction register +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when an uncorrectable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status register +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count register +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 3'b000 (No ECC) and 3'b100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 3'b100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 - No ECC, 001 - Reserved 010 - Parity 011 - Reserved 100 - SEC/DED over 1-beat 101 - SEC/DED over multiple beats 110 - Device Correction 111 - Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +This feature is NOT supported. Only default value works. 1 - Disable ECC scrubs 0 - Enable ECC scrubs Valid only when reg_ddrc_ecc_mode = 3'b100. +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub register +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +1 = run scan test at full clock speed but with less coverage 0 = run scan test at slow clock speed but with high coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 2'b00: constant pattern (0 repeated on each DQ bit) 2'b01: low freq pattern (00001111 repeated on each DQ bit) 2'b10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +1=assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) 0=(default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0 = Select algorithm # 1'b1 = Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 1- Rank 0 delays are used for all ranks 0- Each Rank uses its own delay +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-LPDDR DRAM device in use. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1=enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control register (2) +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control register (3) +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +This register must be set based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask register +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +1=LPDDR2 DRAM device in Use. 0=non-LPDDR2 device in use Present only in designs configured to support LPDDR2. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +1:Per bank refresh 0:All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported on all LPDDR2 devices. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 Register +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. Present only in designs configured to support LPDDR2. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 Register +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 Register +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 Register +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control Register +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0 = DDRC Init 1 = Normal operation 2 = Power-down mode 3 = Self-refresh mode 4 and above = deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDRIOB Address 0 Configuartion Register +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDRIOB Address 1 Configuration Register +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDRIOB Differential Clock Configuration Register +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Address Register +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Data Register +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Differential Strobe Register +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Clcok Register +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDRIOB DDR Control Register +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Control for Pin 0 +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Control for Pin 1 +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Control for Pin 2 +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Control for Pin 3 +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Control for Pin 4 +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Control for Pin 5 +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Control for Pin 6 +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Control for Pin 8 +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Control for Pin 9 +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Control for Pin 10 +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Control for Pin 11 +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Control for Pin 12 +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Control for Pin 13 +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Control for Pin 14 +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Control for Pin 15 +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Control for Pin 16 +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Control for Pin 17 +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Control for Pin 18 +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Control for Pin 19 +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Control for Pin 20 +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Control for Pin 21 +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Control for Pin 22 +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Control for Pin 23 +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Control for Pin 24 +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Control for Pin 25 +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Control for Pin 26 +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Control for Pin 27 +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Control for Pin 40 +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Control for Pin 41 +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Control for Pin 42 +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Control for Pin 43 +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Control for Pin 44 +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Control for Pin 45 +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Control for Pin 46 +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Control for Pin 47 +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Control for Pin 48 +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Control for Pin 49 +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Control for Pin 52 +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Control for Pin 53 +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select register +
    + +SD1_WP_CD_SEL + + +0XF8000834 + +32 + +RW + +0x000000 + +SDIO 1 WP CD select register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDRIOB Address 0 Configuartion Register +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDRIOB Address 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDRIOB Differential Clock Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDRIOB Drive Slew Address Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Data Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Differential Strobe Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Clcok Register +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output 0001 - VREF = 0.6V for LPDDR2 with 1.2V IO 0010 - VREF = 0.675V for LPDDR3 1.35 V IO 0100 - VREF = 0.75V for DDR3 with 1.5V IO 1000 - VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input X0 - Disable External VREF for lower 16 bits X1 - Enable External VREF for lower 16 bits 0X - Disable External VREF for upper 16 bits 1X - Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors X0 - Disable VREF pull-up for lower 16 bits X1 - Enable VREF pull-up for lower 16 bits 0X - Disable VREF pull-up for upper 16 bits 1X - Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0 - VRP/VRN not used 1 - VRP/VRN used as refio +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +73ff + + + +260 + +DDRIOB DDR Control Register +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3f01 + + + +1601 + +MIO Control for Pin 0 +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Control for Pin 1 +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 2 +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Control for Pin 3 +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 4 +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 5 +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 6 +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 8 +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3f01 + + + +1601 + +MIO Control for Pin 9 +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 10 +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 11 +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_wait- (SRAM Wait State indicator) 2= nand, Input, smc_nand_data_in[7]- (NAND Data Bus) = nand, Output, smc_nand_data_out[7]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 12 +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[5]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[5]- (SRAM Data) 2= nand, Input, smc_nand_data_in[3]- (NAND Data Bus) = nand, Output, smc_nand_data_out[3]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 13 +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 14 +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 15 +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[4]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[1]- (SRAM Address) 2= nand, Input, smc_nand_data_in[8]- (NAND Data Bus) = nand, Output, smc_nand_data_out[8]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 16 +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[5]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[2]- (SRAM Address) 2= nand, Input, smc_nand_data_in[9]- (NAND Data Bus) = nand, Output, smc_nand_data_out[9]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 17 +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[6]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[3]- (SRAM Address) 2= nand, Input, smc_nand_data_in[10]- (NAND Data Bus) = nand, Output, smc_nand_data_out[10]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 18 +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 19 +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 20 +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[6]- (SRAM Address) 2= nand, Input, smc_nand_data_in[13]- (NAND Data Bus) = nand, Output, smc_nand_data_out[13]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 21 +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 22 +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 23 +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 24 +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 25 +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 26 +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 27 +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 40 +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 41 +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 42 +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 43 +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 44 +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 45 +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3f01 + + + +1201 + +MIO Control for Pin 46 +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Control for Pin 47 +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Control for Pin 48 +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Control for Pin 49 +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 52 +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 53 +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +2e + +2e + +SDIO0 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO0 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f002e + +SDIO 0 WP CD select register +
    +

    +

    Register ( slcr )SD1_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD1_WP_CD_SEL + +0XF8000834 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO1_WP_SEL + +5:0 + +3f + +0 + +0 + +SDIO1 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SDIO1_CD_SEL + +21:16 + +3f0000 + +9 + +90000 + +SDIO1 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SD1_WP_CD_SEL@0XF8000834 + +31:0 + +3f003f + + + +90000 + +SDIO 1 WP CD select register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value 0 = Disables baud_sample 1 = Clock divisor bypass 2 - 65535 = baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break. 1 = stop transmission of the break. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break 1 = start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter 1 = receiver timeout counter is restarted +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable. 1, the transmitter is disabled +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable. 1, the transmitter is enabled, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable. 1= receiver is enabled +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable. 1=the receiver logic is enabled, provided RXDIS field is set to 0 +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for TX data path. 1=the transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for RX data path 1=receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode 0 : Default UART mode 1 : Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select 0 : APB clock, pclk 1 : a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode 00 = normal 01 = automatic cho 10 = local loopback 11 = remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits 00 = 1 stop bit 01 = 1.5 stop bits 10 = 2 stop bits 11 = reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select. 000 = even parity 001 = odd parity 010 = forced to 0 parity (space) 011 = forced to 1 parity (mark) 1xx = no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select 11 = 6 bits 10 = 7 bits 01 / 00 = 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +clock source select 1 = clock source is uart_clk/8 0 = clock source is uart_clk +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    ENET RESET

    +

    I2C RESET

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset. 0 - No reset. 1 - ACP AXI interface reset output asserted. +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS3AXI interface reset output asserted. +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS2 AXI interface reset output asserted. +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS1 AXI interface reset output asserted. +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS0 AXI interface reset output asserted. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 1 reset is asserted. +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 0 reset is asserted. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface 1 soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0 - No reset. 1 - FPGA master interface 1 reset is asserted. +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0 - No reset. 1 - FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 3 peripheral request reset output asserted. +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 2 peripheral request reset output asserted. +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 1 peripheral request reset output asserted. +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 0 peripheral request reset output asserted. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0 - No reset. 1 - FPGA 3 top level reset output asserted. +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0 - No reset. 1 - FPGA 2 top level reset output asserted. +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0 - No reset. 1 - FPGA 1 top level reset output asserted. +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0 - No reset. 1 - FPGA 0 top level reset output asserted. +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_1_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/ps7_init.tcl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/ps7_init.tcl new file mode 100755 index 0000000..85a6f34 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/ps7_init.tcl @@ -0,0 +1,781 @@ +proc ps7_pll_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000701 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00500800 + mask_write 0XF8000180 0x03F03F30 0x00400500 + mask_write 0XF8000190 0x03F03F30 0x00200500 + mask_write 0XF80001A0 0x03F03F30 0x00100500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_3_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x0007FFFF 0x00001082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006024 0x0FFFFFC3 0x00000000 + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00000003 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x0003F03F 0x0003C008 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x00010000 0x00000000 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x00000200 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFCF 0x40000001 + mask_write 0XF800611C 0x7FFFFFCF 0x40000001 + mask_write 0XF8006120 0x7FFFFFCF 0x40000001 + mask_write 0XF8006124 0x7FFFFFCF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0x6FFFFEFE 0x00040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000703FF 0x000003FF + mask_write 0XF800620C 0x000703FF 0x000003FF + mask_write 0XF8006210 0x000703FF 0x000003FF + mask_write 0XF8006214 0x000703FF 0x000003FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF5 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000001 0x00000001 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001601 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003F01 0x00001601 + mask_write 0XF8000728 0x00003FFF 0x00001680 + mask_write 0XF800072C 0x00003FFF 0x00001680 + mask_write 0XF8000730 0x00003FFF 0x00001680 + mask_write 0XF8000734 0x00003FFF 0x00001680 + mask_write 0XF8000738 0x00003FFF 0x00001680 + mask_write 0XF800073C 0x00003FFF 0x00001680 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003F01 0x00001201 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F002E + mask_write 0XF8000834 0x003F003F 0x00090000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x000003FF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 +} +proc ps7_post_config_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_3_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000701 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00500800 + mask_write 0XF8000180 0x03F03F30 0x00400500 + mask_write 0XF8000190 0x03F03F30 0x00200500 + mask_write 0XF80001A0 0x03F03F30 0x00100500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_2_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001601 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003F01 0x00001601 + mask_write 0XF8000728 0x00003FFF 0x00001680 + mask_write 0XF800072C 0x00003FFF 0x00001680 + mask_write 0XF8000730 0x00003FFF 0x00001680 + mask_write 0XF8000734 0x00003FFF 0x00001680 + mask_write 0XF8000738 0x00003FFF 0x00001680 + mask_write 0XF800073C 0x00003FFF 0x00001680 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003F01 0x00001201 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F002E + mask_write 0XF8000834 0x003F003F 0x00090000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 +} +proc ps7_post_config_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_2_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000701 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00500800 + mask_write 0XF8000180 0x03F03F30 0x00400500 + mask_write 0XF8000190 0x03F03F30 0x00200500 + mask_write 0XF80001A0 0x03F03F30 0x00100500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_1_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x000073FF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001601 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003F01 0x00001601 + mask_write 0XF8000728 0x00003FFF 0x00001680 + mask_write 0XF800072C 0x00003FFF 0x00001680 + mask_write 0XF8000730 0x00003FFF 0x00001680 + mask_write 0XF8000734 0x00003FFF 0x00001680 + mask_write 0XF8000738 0x00003FFF 0x00001680 + mask_write 0XF800073C 0x00003FFF 0x00001680 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003F01 0x00001201 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F002E + mask_write 0XF8000834 0x003F003F 0x00090000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 +} +proc ps7_post_config_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_1_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +set PCW_SILICON_VER_1_0 "0x0" +set PCW_SILICON_VER_2_0 "0x1" +set PCW_SILICON_VER_3_0 "0x2" +set APU_FREQ 666666666 + + + +proc mask_poll { addr mask } { + set count 1 + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + while { $maskedval == 0 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + set count [ expr { $count + 1 } ] + if { $count == 100000000 } { + puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask" + break + } + } +} + + + +proc mask_delay { addr val } { + set delay [ get_number_of_cycles_for_delay $val ] + perf_reset_and_start_timer + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + while { $maskedval == 1 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + } + perf_reset_clock +} + +proc ps_version { } { + set si_ver "0x[string range [mrd 0xF8007080] end-8 end]" + set mask_sil_ver "0x[expr {$si_ver >> 28}]" + return $mask_sil_ver; +} + +proc ps7_post_config {} { + set saved_mode [configparams force-mem-accesses] + configparams force-mem-accesses 1 + + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_post_config_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_post_config_2_0 + } else { + ps7_post_config_3_0 + } + configparams force-mem-accesses $saved_mode +} + +proc ps7_debug {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_debug_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_debug_2_0 + } else { + ps7_debug_3_0 + } +} +proc ps7_init {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_mio_init_data_1_0 + ps7_pll_init_data_1_0 + ps7_clock_init_data_1_0 + ps7_ddr_init_data_1_0 + ps7_peripherals_init_data_1_0 + #puts "PCW Silicon Version : 1.0" + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_mio_init_data_2_0 + ps7_pll_init_data_2_0 + ps7_clock_init_data_2_0 + ps7_ddr_init_data_2_0 + ps7_peripherals_init_data_2_0 + #puts "PCW Silicon Version : 2.0" + } else { + ps7_mio_init_data_3_0 + ps7_pll_init_data_3_0 + ps7_clock_init_data_3_0 + ps7_ddr_init_data_3_0 + ps7_peripherals_init_data_3_0 + #puts "PCW Silicon Version : 3.0" + } +} + + +# For delay calculation using global timer + +# start timer + proc perf_start_clock { } { + + #writing SCU_GLOBAL_TIMER_CONTROL register + + mask_write 0xF8F00208 0x00000109 0x00000009 +} + +# stop timer and reset timer count regs + proc perf_reset_clock { } { + perf_disable_clock + mask_write 0xF8F00200 0xFFFFFFFF 0x00000000 + mask_write 0xF8F00204 0xFFFFFFFF 0x00000000 +} + +# Compute mask for given delay in miliseconds +proc get_number_of_cycles_for_delay { delay } { + + # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + variable APU_FREQ + return [ expr ($delay * $APU_FREQ /(2 * 1000))] +} + + +# stop timer +proc perf_disable_clock {} { + mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 +} + +proc perf_reset_and_start_timer {} { + perf_reset_clock + perf_start_clock +} + + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/ps7_init_gpl.h b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/ps7_init_gpl.h new file mode 100755 index 0000000..45a7839 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/ps7_init_gpl.h @@ -0,0 +1,131 @@ +/****************************************************************************** +* +* Copyright (C) 2010-2020 +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, see +* +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init_gpl.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + + + + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 142857132 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 25000000 +#define FPGA1_FREQ 50000000 +#define FPGA2_FREQ 100000000 +#define FPGA3_FREQ 200000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/xilinx-zynq.cc b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/xilinx-zynq.cc new file mode 100755 index 0000000..14e40f9 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/xilinx-zynq.cc @@ -0,0 +1,106 @@ +/* + * Xilinx SystemC/TLM-2.0 Zynq Wrapper. + * + * Written by Edgar E. Iglesias + * + * Copyright (c) 2016, Xilinx Inc. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#define SC_INCLUDE_DYNAMIC_PROCESSES + +#include + +#include "tlm_utils/simple_initiator_socket.h" +#include "tlm_utils/simple_target_socket.h" + +using namespace sc_core; +using namespace std; + +#include "xilinx-zynq.h" +#include + +//xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr, +// Iremoteport_tlm_sync *sync) +// : remoteport_tlm(name, -1, sk_descr, sync), +xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr) + : remoteport_tlm(name, -1, sk_descr), + rp_m_axi_gp0("rp_m_axi_gp0"), + rp_m_axi_gp1("rp_m_axi_gp1"), + rp_s_axi_gp0("rp_s_axi_gp0"), + rp_s_axi_gp1("rp_s_axi_gp1"), + rp_s_axi_hp0("rp_s_axi_hp0"), + rp_s_axi_hp1("rp_s_axi_hp1"), + rp_s_axi_hp2("rp_s_axi_hp2"), + rp_s_axi_hp3("rp_s_axi_hp3"), + rp_s_axi_acp("rp_s_axi_acp"), + rp_wires_in("wires_in", 20, 0), + rp_wires_out("wires_out", 0, 17), + rp_irq_out("irq_out", 0, 28), + pl2ps_irq("pl2ps_irq", 20), + ps2pl_irq("ps2pl_irq", 28), + ps2pl_rst("ps2pl_rst", 17) +{ + int i; + + m_axi_gp[0] = &rp_m_axi_gp0.sk; + m_axi_gp[1] = &rp_m_axi_gp1.sk; + + s_axi_gp[0] = &rp_s_axi_gp0.sk; + s_axi_gp[1] = &rp_s_axi_gp1.sk; + + s_axi_hp[0] = &rp_s_axi_hp0.sk; + s_axi_hp[1] = &rp_s_axi_hp1.sk; + s_axi_hp[2] = &rp_s_axi_hp2.sk; + s_axi_hp[3] = &rp_s_axi_hp3.sk; + s_axi_acp = &rp_s_axi_acp.sk; + + /* PL to PS Interrupt signals. */ + for (i = 0; i < 20; i++) { + rp_wires_in.wires_in[i](pl2ps_irq[i]); + } + + /* PS to PL Interrupt signals. */ + for (i = 0; i < 28; i++) { + rp_irq_out.wires_out[i](ps2pl_irq[i]); + } + + /* PS to PL resets. */ + for (i = 0; i < 17; i++) { + rp_wires_out.wires_out[i](ps2pl_rst[i]); + } + + register_dev(0, &rp_s_axi_gp0); + register_dev(1, &rp_s_axi_gp1); + + register_dev(2, &rp_s_axi_hp0); + register_dev(3, &rp_s_axi_hp1); + register_dev(4, &rp_s_axi_hp2); + register_dev(5, &rp_s_axi_hp3); + + register_dev(6, &rp_s_axi_acp); + + register_dev(7, &rp_m_axi_gp0); + register_dev(8, &rp_m_axi_gp1); + register_dev(9, &rp_wires_in); + register_dev(10, &rp_wires_out); + register_dev(11, &rp_irq_out); +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/Makefile b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/Makefile new file mode 100755 index 0000000..33394b3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/Makefile @@ -0,0 +1,26 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +INCLUDEFILES=*.h +LIBSOURCES=*.c +OUTS = *.o + +libs: + echo "Compiling SPI_Con..." + $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} + make clean + +include: + ${CP} $(INCLUDEFILES) $(INCLUDEDIR) + +clean: + rm -rf ${OUTS} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/NewExtInst_TOP.bda b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/NewExtInst_TOP.bda new file mode 100755 index 0000000..ab7b1f9 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/NewExtInst_TOP.bda @@ -0,0 +1,272 @@ +{ + "graphjs": { + "version": "1.0", + "keys": [ + { + "abrv": "VH", + "name": "vert_hid", + "type": "int", + "for": "node" + }, + { + "abrv": "VM", + "name": "vert_name", + "type": "string", + "for": "node" + }, + { + "abrv": "VT", + "name": "vert_type", + "type": "string", + "for": "node" + }, + { + "abrv": "BA", + "name": "base_addr", + "type": "string", + "for": "node" + }, + { + "abrv": "HA", + "name": "high_addr", + "type": "string", + "for": "node" + }, + { + "abrv": "BP", + "name": "base_param", + "type": "string", + "for": "node" + }, + { + "abrv": "HP", + "name": "high_param", + "type": "string", + "for": "node" + }, + { + "abrv": "MA", + "name": "master_addrspace", + "type": "string", + "for": "node" + }, + { + "abrv": "MX", + "name": "master_instance", + "type": "string", + "for": "node" + }, + { + "abrv": "MI", + "name": "master_interface", + "type": "string", + "for": "node" + }, + { + "abrv": "MS", + "name": "master_segment", + "type": "string", + "for": "node" + }, + { + "abrv": "MV", + "name": "master_vlnv", + "type": "string", + "for": "node" + }, + { + "abrv": "SX", + "name": "slave_instance", + "type": "string", + "for": "node" + }, + { + "abrv": "SI", + "name": "slave_interface", + "type": "string", + "for": "node" + }, + { + "abrv": "MM", + "name": "slave_memmap", + "type": "string", + "for": "node" + }, + { + "abrv": "SS", + "name": "slave_segment", + "type": "string", + "for": "node" + }, + { + "abrv": "SV", + "name": "slave_vlnv", + "type": "string", + "for": "node" + }, + { + "abrv": "TM", + "name": "memory_type", + "type": "string", + "for": "node" + }, + { + "abrv": "TU", + "name": "usage_type", + "type": "string", + "for": "node" + }, + { + "abrv": "LT", + "name": "lock_type", + "type": "string", + "for": "node" + }, + { + "abrv": "BT", + "name": "boot_type", + "type": "string", + "for": "node" + }, + { + "abrv": "EH", + "name": "edge_hid", + "type": "int", + "for": "edge" + } + ], + "vertice_type_order": [ + { + "abrv": "BC", + "desc": "Block Container" + }, + { + "abrv": "PR", + "desc": "Parital Reference" + }, + { + "abrv": "VR", + "desc": "Variant" + }, + { + "abrv": "PM", + "desc": "Variant Permutations" + }, + { + "abrv": "CX", + "desc": "Boundary Connection" + }, + { + "abrv": "AC", + "desc": "Assignment Coordinate" + }, + { + "abrv": "ACE", + "desc": "Excluded Assign Coordinate" + }, + { + "abrv": "APX", + "desc": "Boundary Aperture" + }, + { + "abrv": "CIP", + "desc": "High level Processing System" + } + ], + "vertices": { + "V0": { + "VM": "NewExtInst_TOP", + "VT": "BC" + }, + "V1": { + "VH": "2", + "VM": "NewExtInst_TOP", + "VT": "VR" + }, + "V2": { + "VH": "2", + "VT": "PM", + "TU": "active" + }, + "V3": { + "VT": "AC", + "BA": "0x43C00000", + "HA": "0x43C0FFFF", + "BP": "C_S00_AXI_BASEADDR", + "HP": "C_S00_AXI_HIGHADDR", + "MA": "Data", + "MX": "/processing_system7_0", + "MI": "M_AXI_GP0", + "MS": "SEG_SPI_Con_0_S00_AXI_reg", + "MV": "xilinx.com:ip:processing_system7:5.5", + "SX": "/SPI_Con_0", + "SI": "S00_AXI", + "SS": "S00_AXI_reg", + "SV": "xilinx.com:user:SPI_Con:1.0", + "TM": "both", + "TU": "register" + }, + "V4": { + "VT": "AC", + "BA": "0x43C10000", + "HA": "0x43C1FFFF", + "BP": "C_S00_AXI_BASEADDR", + "HP": "C_S00_AXI_HIGHADDR", + "MA": "Data", + "MX": "/processing_system7_0", + "MI": "M_AXI_GP0", + "MS": "SEG_SPI_Con_1_S00_AXI_reg", + "MV": "xilinx.com:ip:processing_system7:5.5", + "SX": "/SPI_Con_1", + "SI": "S00_AXI", + "SS": "S00_AXI_reg", + "SV": "xilinx.com:user:SPI_Con:1.0", + "TM": "both", + "TU": "register" + }, + "V5": { + "VT": "AC", + "BA": "0x43C20000", + "HA": "0x43C2FFFF", + "BP": "C_S00_AXI_BASEADDR", + "HP": "C_S00_AXI_HIGHADDR", + "MA": "Data", + "MX": "/processing_system7_0", + "MI": "M_AXI_GP0", + "MS": "SEG_SPI_Con_2_S00_AXI_reg", + "MV": "xilinx.com:ip:processing_system7:5.5", + "SX": "/SPI_Con_2", + "SI": "S00_AXI", + "SS": "S00_AXI_reg", + "SV": "xilinx.com:user:SPI_Con:1.0", + "TM": "both", + "TU": "register" + } + }, + "edges": [ + { + "src": "V0", + "trg": "V1" + }, + { + "src": "V1", + "trg": "V2" + }, + { + "src": "V3", + "trg": "V2", + "EH": "2" + }, + { + "src": "V4", + "trg": "V2", + "EH": "2" + }, + { + "src": "V5", + "trg": "V2", + "EH": "2" + } + ] + } +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/NewExtInst_TOP.sh b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/NewExtInst_TOP.sh new file mode 100755 index 0000000..265ff55 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/NewExtInst_TOP.sh @@ -0,0 +1,297 @@ +#!/usr/bin/env bash +#********************************************************************************************************** +# Vivado (TM) v2023.2 (64-bit) +# +# Script generated by Vivado on Fri May 15 15:32:22 CST 2026 +# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 +# +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# +# Filename : NewExtInst_TOP.sh +# Simulator : Siemens Questa Advanced Simulator +# Description : Simulation script generated by export_simulation Tcl command +# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the +# design. The script will copy the library mapping file from the compiled library directory, +# create design library directories and library mappings in the mapping file. +# +# Usage : NewExtInst_TOP.sh +# NewExtInst_TOP.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]* +# NewExtInst_TOP.sh [-reset_run] +# NewExtInst_TOP.sh [-reset_log] +# NewExtInst_TOP.sh [-help] +# +# * The -noclean_files switch is deprecated and will not peform any function (by default, the +# simulator generated files will not be removed unless -reset_run switch is used) +# +# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library +# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help' +# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path +# switch with the directory path where the library is created while generating the script +# with export_simulation. +# +# Alternatively, you can set the library path by setting the following project property:- +# +# set_property compxlib._compiled_library_dir [current_project] +# +# You can also point to the simulation library by either setting the 'lib_map_path' global +# variable in this script or specify it with the '-lib_map_path' switch while executing this +# script (type 'NewExtInst_TOP.sh -help' for more information). +# +# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the +# generated script, but if design is targetted for system simulation containing SystemC/C++/C +# sources, then the library path MUST be specified upfront when calling export_simulation. +# +# For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************** + +# catch pipeline exit status +set -Eeuo pipefail + +# script info +echo -e "NewExtInst_TOP.sh - Script generated by export_simulation (Vivado v2023.2 (64-bit)-id)\n" + +# main steps +run() +{ + check_args $* + setup + if [[ ($b_step == 1) ]]; then + case $step in + "compile" ) + init_lib + compile + ;; + "elaborate" ) + elaborate + ;; + "simulate" ) + simulate + ;; + * ) + echo -e "ERROR: Invalid or missing step '$step' (type \"./NewExtInst_TOP.sh -help\" for more information)\n" + exit 1 + esac + else + init_lib + compile + elaborate + simulate + fi +} + +# RUN_STEP: +compile() +{ + source compile.do 2>&1 | tee -a compile.log +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + # delete previous files for a clean rerun + if [[ ($b_reset_run == 1) ]]; then + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + fi + + # delete previous log files + if [[ ($b_reset_log == 1) ]]; then + reset_log + echo -e "INFO: Simulation run log files deleted.\n" + exit 0 + fi + + # add any setup/initialization commands here:- + + # + +} + +# simulator index file/library directory processing +init_lib() +{ + if [[ ($b_keep_index == 1) ]]; then + # keep previous simulator index file + true + else + # copy simulator index file to current directory + copy_setup_file + fi + + if [[ ($lib_map_path != "") ]]; then + ref_lib_dir=$lib_map_path + fi + + if [[ ($b_keep_index == 1) ]]; then + # do not recreate design library directories + true + else + # create design library directories + create_lib_dir + fi +} + +# copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($lib_map_path == "") ]]; then + lib_map_path="/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/compile_simlib/questa" + fi + + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + fi +} + +# create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + mkdir $lib_dir +} + +# delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# delete generated log files from the previous run +reset_log() +{ + files_to_remove=(compile.log elaborate.log simulate.log) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# check switch argument value +check_arg_value() +{ + if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "elaborate") && ($2 != "simulate")) ]];then + echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then + echo -e "ERROR: Simulation library directory path not specified (type \"./NewExtInst_TOP.sh -help\" for more information)\n" + exit 1 + fi +} + +# check command line arguments +check_args() +{ + arg_count=$# + if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then + usage + fi + while [[ "$#" -gt 0 ]]; do + case $1 in + -step) check_arg_value $1 $2;step=$2; b_step=1; shift;; + -lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;; + -gen_bypass) b_gen_bypass=1 ;; + -reset_run) b_reset_run=1 ;; + -reset_log) b_reset_log=1 ;; + -keep_index) b_keep_index=1 ;; + -noclean_files) b_noclean_files=1 ;; + -help|-h) ;; + *) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;; + esac + shift + done + + # -reset_run is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then + echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -reset_log is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then + echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -keep_index is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then + echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -noclean_files is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then + echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi +} + +# script usage +usage() +{ + msg="Usage: NewExtInst_TOP.sh [-help]\n\ +Usage: NewExtInst_TOP.sh [-step]\n\ +Usage: NewExtInst_TOP.sh [-lib_map_path]\n\ +Usage: NewExtInst_TOP.sh [-reset_run]\n\ +Usage: NewExtInst_TOP.sh [-reset_log]\n\ +Usage: NewExtInst_TOP.sh [-keep_index]\n\ +Usage: NewExtInst_TOP.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-step ] -- Execute specified step (compile, elaborate, simulate)\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\ +file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\ +NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\ +NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\ +[-reset_log] -- Delete simulator generated log files from the previous run\n\n\ +[-keep_index] -- Keep simulator index file settings from the previous run\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n" + echo -e $msg + exit 0 +} + +# initialize globals +step="" +lib_map_path="" +b_step=0 +b_lib_map_path=0 +b_gen_bypass=0 +b_reset_run=0 +b_reset_log=0 +b_keep_index=0 +b_noclean_files=0 + +# launch script +run $* diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/NewExtInst_TOP.udo b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/NewExtInst_TOP.udo new file mode 100644 index 0000000..e69de29 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/README.txt b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/README.txt new file mode 100644 index 0000000..1d27b8b --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/README.txt @@ -0,0 +1,50 @@ +################################################################################ +# Vivado (TM) v2023.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and how to fetch design source file details +# from the file_info.txt file. +# +# Generated by export_simulation on Fri May 15 15:32:22 CST 2026 +# +################################################################################ + +1. Steps to run the generated simulation script + +From the shell prompt in the current directory, issue the following command:- + +./NewExtInst_TOP.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first calls the 'check_args' function, the purpose of which +is to verify the generated script arguments and print error if incorrect switch +is specified. The 'run' function then calls the 'setup' function, the purpose of +which is to specify custom or initialization commands. The function also executes +following sub-functions:- +'reset_run' if -reset_run switch is specified. +'reset_log' if -reset_log switch is specified. + +The purpose of 'reset_run' function' is to delete the simulator generated design +data from the previous run and the purpose of 'reset_log' function' is to delete +the simulator generated log files. + +The 'run' function then calls the 'init_lib' function, the purpose of which is to +create design library mappings and directories. This function is called before the +'compile' step. By default, if '-step' switch is specified with the script then the +script will execute that specfic step, else it will execute all steps applicable +for the target simulator. + +For more information on the script, please type './NewExtInst_TOP.sh -help' + +2. Design source file information + +export_simulation generates a 'file_info.txt' file that contains design file information +based on the compile order when export_simulation was executed from Vivado. The file +contains information about the file name, type, library it is compiled into, whether +it is part of the IP, associated library, file path information in a comma separated +format. This file can be parsed to extract the required information for generating a +custom script or can be read from verification test infra. + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/SPI_Con.h b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/SPI_Con.h new file mode 100755 index 0000000..5278bdd --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/SPI_Con.h @@ -0,0 +1,107 @@ + +#ifndef SPI_CON_H +#define SPI_CON_H + + +/****************** Include Files ********************/ +#include "xil_types.h" +#include "xstatus.h" + +#define SPI_CON_S00_AXI_SLV_REG0_OFFSET 0 +#define SPI_CON_S00_AXI_SLV_REG1_OFFSET 4 +#define SPI_CON_S00_AXI_SLV_REG2_OFFSET 8 +#define SPI_CON_S00_AXI_SLV_REG3_OFFSET 12 +#define SPI_CON_S00_AXI_SLV_REG4_OFFSET 16 +#define SPI_CON_S00_AXI_SLV_REG5_OFFSET 20 +#define SPI_CON_S00_AXI_SLV_REG6_OFFSET 24 +#define SPI_CON_S00_AXI_SLV_REG7_OFFSET 28 +#define SPI_CON_S00_AXI_SLV_REG8_OFFSET 32 +#define SPI_CON_S00_AXI_SLV_REG9_OFFSET 36 +#define SPI_CON_S00_AXI_SLV_REG10_OFFSET 40 +#define SPI_CON_S00_AXI_SLV_REG11_OFFSET 44 +#define SPI_CON_S00_AXI_SLV_REG12_OFFSET 48 +#define SPI_CON_S00_AXI_SLV_REG13_OFFSET 52 +#define SPI_CON_S00_AXI_SLV_REG14_OFFSET 56 +#define SPI_CON_S00_AXI_SLV_REG15_OFFSET 60 +#define SPI_CON_S00_AXI_SLV_REG16_OFFSET 64 +#define SPI_CON_S00_AXI_SLV_REG17_OFFSET 68 +#define SPI_CON_S00_AXI_SLV_REG18_OFFSET 72 +#define SPI_CON_S00_AXI_SLV_REG19_OFFSET 76 +#define SPI_CON_S00_AXI_SLV_REG20_OFFSET 80 +#define SPI_CON_S00_AXI_SLV_REG21_OFFSET 84 +#define SPI_CON_S00_AXI_SLV_REG22_OFFSET 88 +#define SPI_CON_S00_AXI_SLV_REG23_OFFSET 92 +#define SPI_CON_S00_AXI_SLV_REG24_OFFSET 96 +#define SPI_CON_S00_AXI_SLV_REG25_OFFSET 100 +#define SPI_CON_S00_AXI_SLV_REG26_OFFSET 104 +#define SPI_CON_S00_AXI_SLV_REG27_OFFSET 108 +#define SPI_CON_S00_AXI_SLV_REG28_OFFSET 112 +#define SPI_CON_S00_AXI_SLV_REG29_OFFSET 116 +#define SPI_CON_S00_AXI_SLV_REG30_OFFSET 120 +#define SPI_CON_S00_AXI_SLV_REG31_OFFSET 124 + + +/**************************** Type Definitions *****************************/ +/** + * + * Write a value to a SPI_CON register. A 32 bit write is performed. + * If the component is implemented in a smaller width, only the least + * significant data is written. + * + * @param BaseAddress is the base address of the SPI_CONdevice. + * @param RegOffset is the register offset from the base to write to. + * @param Data is the data written to the register. + * + * @return None. + * + * @note + * C-style signature: + * void SPI_CON_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data) + * + */ +#define SPI_CON_mWriteReg(BaseAddress, RegOffset, Data) \ + Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data)) + +/** + * + * Read a value from a SPI_CON register. A 32 bit read is performed. + * If the component is implemented in a smaller width, only the least + * significant data is read from the register. The most significant data + * will be read as 0. + * + * @param BaseAddress is the base address of the SPI_CON device. + * @param RegOffset is the register offset from the base to write to. + * + * @return Data is the data from the register. + * + * @note + * C-style signature: + * u32 SPI_CON_mReadReg(u32 BaseAddress, unsigned RegOffset) + * + */ +#define SPI_CON_mReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (RegOffset)) + +/************************** Function Prototypes ****************************/ +/** + * + * Run a self-test on the driver/device. Note this may be a destructive test if + * resets of the device are performed. + * + * If the hardware system is not built correctly, this function may never + * return to the caller. + * + * @param baseaddr_p is the base address of the SPI_CON instance to be worked on. + * + * @return + * + * - XST_SUCCESS if all self-test code passed + * - XST_FAILURE if any self-test code failed + * + * @note Caching must be turned off for this function to work. + * @note Self test may fail if data memory and device are not on the same bus. + * + */ +XStatus SPI_CON_Reg_SelfTest(void * baseaddr_p); + +#endif // SPI_CON_H diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/SPI_Con.mdd b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/SPI_Con.mdd new file mode 100755 index 0000000..4bd813f --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/SPI_Con.mdd @@ -0,0 +1,10 @@ + + +OPTION psf_version = 2.1; + +BEGIN DRIVER SPI_Con + OPTION supported_peripherals = (SPI_Con); + OPTION copyfiles = all; + OPTION VERSION = 1.0; + OPTION NAME = SPI_Con; +END DRIVER diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/SPI_Con.tcl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/SPI_Con.tcl new file mode 100755 index 0000000..7f913c9 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/SPI_Con.tcl @@ -0,0 +1,5 @@ + + +proc generate {drv_handle} { + xdefine_include_file $drv_handle "xparameters.h" "SPI_Con" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR" +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/file_info.txt b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/file_info.txt new file mode 100644 index 0000000..7320d80 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/file_info.txt @@ -0,0 +1,39 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" 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+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" 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+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" 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+axi_protocol_converter_v2_1_vl_rfs.v,verilog,axi_protocol_converter_v2_1_29,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +NewExtInst_TOP_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_auto_pc_0/sim/NewExtInst_TOP_auto_pc_0.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +NewExtInst_TOP.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/sim/NewExtInst_TOP.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/glbl.v b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/libps7.dll b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/libps7.dll new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/libps7.dll @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/libps7.so b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/libps7.so new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/libps7.so @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/libremoteport.dll b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/libremoteport.dll new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/libremoteport.dll @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/libremoteport.so b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/libremoteport.so new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/libremoteport.so @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/ps7_init.h b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/ps7_init.h new file mode 100755 index 0000000..224d7ea --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/ps7_init.h @@ -0,0 +1,117 @@ +/****************************************************************************** +* +* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + + + + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 142857132 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 25000000 +#define FPGA1_FREQ 50000000 +#define FPGA2_FREQ 100000000 +#define FPGA3_FREQ 200000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/ps7_init.html b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/ps7_init.html new file mode 100755 index 0000000..9ca53bd --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/ps7_init.html @@ -0,0 +1,125613 @@ + + + + +Zynq PS configuration detail + + + +

    +
    + +
  • +
    Zynq PS Register Summary Viewer +
    +
    • +     +
    +
    +
    + +
    Zynq PS7 Summary Report +
    +     +
    User Configurations +
    +
    + +
    MIO Configurations +
    +     +
    + +
    CLK Configurations +
    +     +
    + +
    DDR Configurations +
    +     +
    + +
    SMC Configurations +
    +     +
    +
    +
    Select Version: + +
    +
    +
    Zynq Register View +
    +
    + +
    MIO Registers +
    +     + +
    PLL Registers +
    +     + +
    Clock Registers +
    +     + +
    DDR Registers +
    +     + +
    Peripherals Registers +
    +     +
    +
    This design is targeted for xc7z035 board (part number: xc7z035ffg676-2) + +
    +

    Zynq Design Summary

    + + + + + + + + + + + + + + + + + + + + + +
    +Device + +xc7z035 +
    +SpeedGrade + +-2 +
    +Part + +xc7z035ffg676-2 +
    +Description + +Zynq PS Configuration Report with register details +
    +Vendor + +Xilinx +
    +

    MIO Table View

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +MIO Pin + +Peripheral + +Signal + +IO Type + +Speed + +Pullup + +Direction +
    +MIO 0 + +SD 1 + +wp + +LVCMOS 3.3V + +slow + +enabled + +in +
    +MIO 1 + +Quad SPI Flash + +qspi0_ss_b + +LVCMOS 3.3V + +slow + +enabled + +out +
    +MIO 2 + +Quad SPI Flash + +qspi0_io[0] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 3 + +Quad SPI Flash + +qspi0_io[1] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 4 + +Quad SPI Flash + +qspi0_io[2] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 5 + +Quad SPI Flash + +qspi0_io[3]/HOLD_B + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 6 + +Quad SPI Flash + +qspi0_sclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 7 + + + + + + + + + + + + +
    +MIO 8 + +Quad SPI Flash + +qspi_fbclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 9 + +SD 1 + +cd + +LVCMOS 3.3V + +slow + +enabled + +in +
    +MIO 10 + +SD 1 + +data[0] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 11 + +SD 1 + +cmd + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 12 + +SD 1 + +clk + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 13 + +SD 1 + +data[1] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 14 + +SD 1 + +data[2] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 15 + +SD 1 + +data[3] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 16 + +Enet 0 + +tx_clk + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 17 + +Enet 0 + +txd[0] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 18 + +Enet 0 + +txd[1] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 19 + +Enet 0 + +txd[2] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 20 + +Enet 0 + +txd[3] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 21 + +Enet 0 + +tx_ctl + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 22 + +Enet 0 + +rx_clk + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 23 + +Enet 0 + +rxd[0] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 24 + +Enet 0 + +rxd[1] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 25 + +Enet 0 + +rxd[2] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 26 + +Enet 0 + +rxd[3] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 27 + +Enet 0 + +rx_ctl + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 28 + + + + + + + + + + + + +
    +MIO 29 + + + + + + + + + + + + +
    +MIO 30 + + + + + + + + + + + + +
    +MIO 31 + + + + + + + + + + + + +
    +MIO 32 + + + + + + + + + + + + +
    +MIO 33 + + + + + + + + + + + + +
    +MIO 34 + + + + + + + + + + + + +
    +MIO 35 + + + + + + + + + + + + +
    +MIO 36 + + + + + + + + + + + + +
    +MIO 37 + + + + + + + + + + + + +
    +MIO 38 + + + + + + + + + + + + +
    +MIO 39 + + + + + + + + + + + + +
    +MIO 40 + +SD 0 + +clk + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 41 + +SD 0 + +cmd + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 42 + +SD 0 + +data[0] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 43 + +SD 0 + +data[1] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 44 + +SD 0 + +data[2] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 45 + +SD 0 + +data[3] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 46 + +SD 0 + +wp + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 47 + +SD 0 + +cd + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 48 + +UART 1 + +tx + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 49 + +UART 1 + +rx + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 50 + + + + + + + + + + + + +
    +MIO 51 + + + + + + + + + + + + +
    +MIO 52 + +Enet 0 + +mdc + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 53 + +Enet 0 + +mdio + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +

    DDR Memory information

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Parameter name + +Value + +Description +
    +Enable DDR + +1 + +Enable DDR Controller of Zynq PS +
    +Memory Part + +MT41J256M16 RE-125 + + +
    +DRAM bus width + +32 Bit + +Select the desired data width. Refer to the Thechnical Reference Manual(TRM) for a detailed list of supported DDR data widths +
    +ECC + +Disabled + +ECC is supported only for data width of 16-bit +
    +BURST Length (lppdr only) + +8 + +Select the burst Length. It refers to the amount of data read/written after a read/write command is presented to the controller +
    +Internal Vref + +0 + + +
    +Operating Frequency (MHz) + +533.333333 + +Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade +
    +HIGH temperature + +Normal (0-85) + +Select the operating temparature +
    +DRAM IC bus width + +16 Bits + +Provide the width of the DRAM chip +
    +DRAM Device Capacity + +4096 MBits + + +
    +Speed Bin + +DDR3_1066F + +Provide the Speed Bin +
    +BANK Address Count + +3 + +Defines the bank to which an active an ACTIVE, READ, WRITE, or Precharge Command is being applied +
    +ROW Address Count + +15 + +Provide the Row address for ACTIVE commands +
    +COLUMN Address Count + +10 + +Provide the Row address for READ/WRITE commands +
    +CAS Latency + +7 + +Select the Column Access Strobe (CAS) Latency. It refers to the amount of time it takes for data to appear on the pins of the memory module +
    +CAS Write Latency + +6 + +Select the CAS Write Latency +
    +RAS to CAS Delay + +7 + +Provide the row address to column address delay time. tRCD is t he time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS) +
    +RECHARGE Time + +7 + +Precharge Time (tRP) is the number of clock cycles needed o terminate acces s to an open row of memory, and open access to the next row +
    +tRC (ns ) + +48.91 + +Provide the Row cycle time tRC (ns) +
    +tRASmin ( ns ) + +35.0 + +tRASmin (ns) is the minimum number of clock cycles required between an Active command and issuing the Precharge command +
    +tFAW + +40.0 + +It restricts the number of activates that can be done within a certain window of time +
    +ADDITIVE Latency + +0 + +Provide the Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths +
    +Write levelling + +1 + + +
    +Read gate + +1 + + +
    +Read gate + +1 + + +
    +DQS to Clock delay [0] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [1] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [2] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [3] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +Board delay [0] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [1] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [2] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [3] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +

    PS Clocks information

    +

    PS Reference Clock : 33.333333

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Peripheral + +PLL source + +Frequency (MHz) +
    +CPU 6x Freq (MHz) + +ARM PLL + +666.666687 +
    +QSPI Flash Freq (MHz) + +IO PLL + +142.857132 +
    +ENET0 Freq (MHz) + +IO PLL + +125.000000 +
    +SDIO Freq (MHz) + +IO PLL + +100.000000 +
    +SDIO Freq (MHz) + +IO PLL + +100.000000 +
    +UART Freq (MHz) + +IO PLL + +100.000000 +
    +FPGA0 Freq (MHz) + +IO PLL + +25.000000 +
    +FPGA1 Freq (MHz) + +IO PLL + +50.000000 +
    +FPGA2 Freq (MHz) + +IO PLL + +100.000000 +
    +FPGA3 Freq (MHz) + +IO PLL + +200.000000 +
    +

    ps7_pll_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: ARM PLL 10: DDR PLL 11: IO PLL This field is reset by POR only. +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for programming the PLL. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock and Rx Signals Select +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +FPGA1_CLK_CTRL + + +0XF8000180 + +32 + +RW + +0x000000 + +PL Clock 1 Output control +
    + +FPGA2_CLK_CTRL + + +0XF8000190 + +32 + +RW + +0x000000 + +PL Clock 2 output control +
    + +FPGA3_CLK_CTRL + + +0XF80001A0 + +32 + +RW + +0x000000 + +PL Clock 3 output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source of the Rx clock, control and data signals: 0: MIO 1: EMIO +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock and Rx Signals Select +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +7 + +700 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +701 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a03 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +5 + +500000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +500800 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )FPGA1_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA1_CLK_CTRL + +0XF8000180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA1_CLK_CTRL@0XF8000180 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 1 Output control +
    +

    +

    Register ( slcr )FPGA2_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA2_CLK_CTRL + +0XF8000190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +2 + +200000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA2_CLK_CTRL@0XF8000190 + +31:0 + +3f03f30 + + + +200500 + +PL Clock 2 output control +
    +

    +

    Register ( slcr )FPGA3_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA3_CLK_CTRL + +0XF80001A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA3_CLK_CTRL@0XF80001A0 + +31:0 + +3f03f30 + + + +100500 + +PL Clock 3 output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ratio: (When this register changes, no access are allowed to OCM.) 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +1 + +800 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec0c4d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +82 + +82 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reserved_reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Reserved. Do not modify. +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +Two_rank_cfg@0XF8006004 + +31:0 + +7ffff + + + +1082 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a1 + +2840 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4285b + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +13 + +13 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d3 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. In non-LPDDR mode, the minimum DRAM Write Latency (DDR2) supported is 3. In LPDDR mode, the required DRAM Write Latency of 1 is supported. Since write latency (CWL) min is 3, and DDR2 CWL is CL-1, the min (DDR2) CL supported is 4 +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +f + +3c00 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +5 + +28000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +5 + +2800000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +7282bce5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_en_dfi_dram_clk_disable + +23:23 + +800000 + +0 + +0 + +Enables the assertion of ddrc_dfi_dram_clk_disable. In DDR2/DDR3, only asserted in Self Refresh. In mDDR/LPDDR2, can be asserted in following: - during normal operation (Clock Stop), - in Power Down - in Self Refresh - In Deep Power Down +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +7fdffffc + + + +270872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffc3 + + + +0 + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2: Value loaded into EMR2 register DDR3: Value loaded into MR2 register LPDDR2: Value loaded into MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2: Value loaded into EMR3 register DDR3: Value loaded into MR3 register. Set Bit[2:0] to 3'b000. These bits are set appropriately by the Controller during Read Data eye training and Read DQS gate leveling. LPDDR2: Unused +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +b30 + +b30 + +DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2: Value loaded into EMR1register. (Bits[9:7] are for OCD and the setting in this reg is ignored. Controller sets this bits appropriately during initialization DDR3: Value loaded into MR1 register. Set Bit[7] to 0. This bit is set appropriately by the Controller during Write Leveling LPDDR2: Value loaded into MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40b30 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 8, Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 7, Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 6, Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 5, Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reserved_reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +Reserved. Do not modify. +
    +reserved_reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Reserved. Do not modify. +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3f03f + + + +3c008 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +10000 + + + +0 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum d'128) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_2d@0XF80060B4 + +31:0 + +200 + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of uncorrectable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on board topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +0: Use reg_phy_ctrl_slave_ratio for address/command timing slave DLL 1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_64@0XF8006190 + +31:0 + +6ffffefe + + + +40080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. This feature should only be enabled after LPDDR2 initialization is completed +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff5 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Powerdown mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQ pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQS pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +Drive and Slew controls for Clock pins of the DDR Interface +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SD1_WP_CD_SEL + + +0XF8000834 + +32 + +RW + +0x000000 + +SDIO 1 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQ pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQS pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for Clock pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1x: Enable External VREF for upper 16 bits +
    +reserved_VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Reserved. Do not modify. +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +reserved_REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +1 + + + +1 + +DDR IOB DCI Config +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialize flops in DCI system +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDR IOB DCI Config +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +DCI System Enable. Set to 1 if any IOs in DDR IO Bank use DCI Termination. DDR2, DDR3 and LPDDR2 (Silicon Revision 2.0+) configurations require this bit set to 1 +
    +reserved_VRP_TRI + +2:2 + +4 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_TRI + +3:3 + +8 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRP_OUT + +4:4 + +10 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT1 + +15:14 + +c000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update Mode. Use the values in the Calibration Table. +
    +reserved_INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_CLK + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLN + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLP + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_RST + +25:25 + +2000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7feffff + + + +823 + +DDR IOB DCI Config +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. 0: disable 1: enable +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables Pullup on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3f01 + + + +1601 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3f01 + + + +1601 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1680 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1680 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait, Input 10: NAND Flash IO Bit 7, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 12 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1680 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5, Input/Output 10: NAND Flash IO Bit 3, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 13 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1680 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1680 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1680 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1, Output 10: NAND Flash IO Bit 8, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2, Output 10: NAND Flash IO Bit 9, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110 TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3, Output 10: NAND Flash IO Bit 10, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6, Output 10: NAND Flash IO Bit 13, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3f01 + + + +1201 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +2e + +2e + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f002e + +SDIO 0 WP CD select +
    +

    +

    Register ( slcr )SD1_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD1_WP_CD_SEL + +0XF8000834 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO1_WP_SEL + +5:0 + +3f + +0 + +0 + +SDIO 1 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO1_CD_SEL + +21:16 + +3f0000 + +9 + +90000 + +SDIO 1 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD1_WP_CD_SEL@0XF8000834 + +31:0 + +3f003f + + + +90000 + +SDIO 1 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +Baud Rate Divider Register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud Rate Generator Register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control Register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode Register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +Baud Rate Divider Register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud Rate Generator Register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter 1: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: enable 1: disable, regardless of the value of RXEN +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed. +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed. +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control Register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +3ff + + + +20 + +UART Mode Register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes . If not set, then external pull up is required on HOLDb and WPn pins . Note that this bit doesn't affect the quad(4-bit) mode as Controller always drives these pins in quad mode. It is highly recommended to set this bit always(irrespective of mode of operation) while using QSPI +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This register controls which POR timer the PL will use for power-up. 0 - Use 64k timer 1 - Use 4k timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    ENET RESET

    +

    I2C RESET

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_LVL_INP_EN_0 + +3:3 + +8 + +1 + +8 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_0 + +2:2 + +4 + +1 + +4 + +Level shifter enable to drive signals from PS to PL +
    +USER_LVL_INP_EN_1 + +1:1 + +2 + +1 + +2 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_1 + +0:0 + +1 + +1 + +1 + +Level shifter enable to drive signals from PS to PL +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +Reserved. Do not modify. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +PL Reset 3 (FCLKRESETN3 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN3 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +PL Reset 2 (FCLKRESETN2 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN2 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +PL Reset 1 (FCLKRESETN1 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN1 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +PL Reset 0 (FCLKRESETN0 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN0 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    AFI2 SECURE REGISTER

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_3_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: CPU PLL 10: divided DDR PLL 11: IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +FPGA1_CLK_CTRL + + +0XF8000180 + +32 + +RW + +0x000000 + +PL Clock 1 Output control +
    + +FPGA2_CLK_CTRL + + +0XF8000190 + +32 + +RW + +0x000000 + +PL Clock 2 output control +
    + +FPGA3_CLK_CTRL + + +0XF80001A0 + +32 + +RW + +0x000000 + +PL Clock 3 output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source to generate the Rx clock: 0: MIO Rx clock, 1: EMIO Rx clock +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +7 + +700 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +701 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a03 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +5 + +500000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +500800 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )FPGA1_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA1_CLK_CTRL + +0XF8000180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA1_CLK_CTRL@0XF8000180 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 1 Output control +
    +

    +

    Register ( slcr )FPGA2_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA2_CLK_CTRL + +0XF8000190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +2 + +200000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA2_CLK_CTRL@0XF8000190 + +31:0 + +3f03f30 + + + +200500 + +PL Clock 2 output control +
    +

    +

    Register ( slcr )FPGA3_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA3_CLK_CTRL + +0XF80001A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA3_CLK_CTRL@0XF80001A0 + +31:0 + +3f03f30 + + + +100500 + +PL Clock 3 output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ration: 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +1 + +800 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec0c4d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config0 + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config1 + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 1. +
    + +PHY_Config2 + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 2. +
    + +PHY_Config3 + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 3. +
    + +phy_init_ratio0 + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio1 + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 1. +
    + +phy_init_ratio2 + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 2. +
    + +phy_init_ratio3 + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 3. +
    + +phy_rd_dqs_cfg0 + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg1 + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 1. +
    + +phy_rd_dqs_cfg2 + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 2. +
    + +phy_rd_dqs_cfg3 + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 3. +
    + +phy_wr_dqs_cfg0 + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg1 + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 1. +
    + +phy_wr_dqs_cfg2 + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 2. +
    + +phy_wr_dqs_cfg3 + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 3. +
    + +phy_we_cfg0 + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg1 + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 1. +
    + +phy_we_cfg2 + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 2. +
    + +phy_we_cfg3 + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 3. +
    + +wr_data_slv0 + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv1 + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 1. +
    + +wr_data_slv2 + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 2. +
    + +wr_data_slv3 + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 3. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port0 + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port1 + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 1. +
    + +axi_priority_wr_port2 + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 2. +
    + +axi_priority_wr_port3 + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 3. +
    + +axi_priority_rd_port0 + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port1 + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 1. +
    + +axi_priority_rd_port2 + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 2. +
    + +axi_priority_rd_port3 + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 3. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +82 + +82 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Rank configuration: 01: One Rank of DDR 11: Two Ranks of DDR Others: reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +Block read/write scheduling cycle count when Write requires changing ODT settings 00: 1 cycle 01: 2 cycles 10: 3 cycles others: reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0: schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1: schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81082 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a1 + +2840 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4285b + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +13 + +13 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d3 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +f + +3c00 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +5 + +28000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +5 + +2800000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +7282bce5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1: sdram device 0: non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: stop_clk will never be asserted. 1: enable the assertion of stop_clk to the PHY whenever a clock is not required +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2 and DDR3: Value written into the DRAM EMR2 register. LPDDR2: Value written into the DRAM MR3 register. +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2 and DDR3: Value written into the DRAM EMR3 register. LPDDR2: not used. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +b30 + +b30 + +DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2 and DDR3: Value written into the DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. LPDDR2: Value written into the DRAM MR2 register. +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40b30 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODTs must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config0 + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config0@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config1 + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config1@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 1. +
    +

    +

    Register ( slcr )PHY_Config2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config2 + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config2@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 2. +
    +

    +

    Register ( slcr )PHY_Config3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config3 + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config3@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_init_ratio0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio0 + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio0@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio1 + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio1@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 1. +
    +

    +

    Register ( slcr )phy_init_ratio2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio2 + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio2@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 2. +
    +

    +

    Register ( slcr )phy_init_ratio3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio3 + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio3@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 3. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg0 + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg0@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg1 + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg1@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg2 + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg2@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg3 + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg3@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg0 + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg0@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg1 + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg1@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg2 + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg2@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg3 + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg3@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_we_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg0 + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg0@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg1 + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg1@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 1. +
    +

    +

    Register ( slcr )phy_we_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg2 + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg2@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 2. +
    +

    +

    Register ( slcr )phy_we_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg3 + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg3@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 3. +
    +

    +

    Register ( slcr )wr_data_slv0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv0 + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv0@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv1 + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv1@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 1. +
    +

    +

    Register ( slcr )wr_data_slv2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv2 + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv2@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 2. +
    +

    +

    Register ( slcr )wr_data_slv3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv3 + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv3@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 3. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +0: (default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) 1: assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 0: Each Rank uses its own delay 1: Rank 0 delays are used for all ranks +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1: enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port0 + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port0@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port1 + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port1@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 1. +
    +

    +

    Register ( slcr )axi_priority_wr_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port2 + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port2@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 2. +
    +

    +

    Register ( slcr )axi_priority_wr_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port3 + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port3@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 3. +
    +

    +

    Register ( slcr )axi_priority_rd_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port0 + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port0@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port1 + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port1@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 1. +
    +

    +

    Register ( slcr )axi_priority_rd_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port2 + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port2@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 2. +
    +

    +

    Register ( slcr )axi_priority_rd_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port3 + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port3@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 3. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +0:All bank refresh Per bank refresh allows traffic to flow to other banks. 1:Per bank refresh Per bank refresh is not supported on all LPDDR2 devices. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Power-down mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 0 +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 1 +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDR IOB Slew for Address +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDR IOB Slew for Data +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDR IOB Slew for Diff +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDR IOB Slew for Clock +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SD1_WP_CD_SEL + + +0XF8000834 + +32 + +RW + +0x000000 + +SDIO 1 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 0 +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 1 +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDR IOB Slew for Address +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Data +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Diff +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Clock +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1X: Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors x0: Disable VREF pull-up for lower 16 bits x1: Enable VREF pull-up for lower 16 bits 0x: Disable VREF pull-up for upper 16 bits 1x: Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Enable test mode for VRP and VRN: 00: VRP/VRN test mode not used 11: VRP/VRN test mode enabled using vref based receiver. VRP/VRN control is set using the VRN_OUT, VRP_OUT, VRN_TRI, VRP_TRI fields in the DDRIOB_DCI_CTRL register +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0: no pull-up 1: enable pull-up +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. 0: disable 1: enable +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables pull-up on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3f01 + + + +1601 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3f01 + + + +1601 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1680 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1680 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait 10: NAND Flash IO Bit 7 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 12 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1680 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5 10: NAND Flash IO Bit 3 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 13 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1680 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1680 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1680 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1 10: NAND Flash IO Bit 8 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Output 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2 10: NAND Flash IO Bit 9 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110 TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3 10: NAND Flash IO Bit 10 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6 10: NAND Flash IO Bit 13 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3f01 + + + +1201 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +2e + +2e + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f002e + +SDIO 0 WP CD select +
    +

    +

    Register ( slcr )SD1_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD1_WP_CD_SEL + +0XF8000834 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO1_WP_SEL + +5:0 + +3f + +0 + +0 + +SDIO 1 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO1_CD_SEL + +21:16 + +3f0000 + +9 + +90000 + +SDIO 1 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD1_WP_CD_SEL@0XF8000834 + +31:0 + +3f003f + + + +90000 + +SDIO 1 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass 2 - 65535: baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: start break transmission, 1: stop break transmission. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: 1: start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 0: receiver timeout counter disabled, 1: receiver timeout counter is restarted. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter, 0: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter, 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: disable, 1: enable +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable, 1: enable. When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: 1: transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: 1: receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode: 0: Default UART mode 1: Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select: 0: APB clock, pclk 1: a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: 00: normal 01: automatic cho 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: 0: clock source is uart_clk 1: clock source is uart_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    ENET RESET

    +

    I2C RESET

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset: 0: No reset 1: ACP AXI interface reset output asserted +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0: No reset 1: AXDS3AXI interface reset output asserted +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0: No reset 1: AXDS2 AXI interface reset output asserted +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0: No reset 1: AXDS1 AXI interface reset output asserted +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0: No reset 1: AXDS0 AXI interface reset output asserted +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0: No reset 1: FPGA slave interface 1 reset is asserted +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0: No reset 1: FPGA slave interface 0 reset is asserted +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface: 1: soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0: No reset 1: FPGA master interface 1 reset is asserted +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0: No reset 1: FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 3 peripheral request reset output asserted +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 2 peripheral request reset output asserted +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 1 peripheral request reset output asserted +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 0 peripheral request reset output asserted +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0: No reset 1: FPGA 3 top level reset output asserted +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0: No reset 1: FPGA 2 top level reset output asserted +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0: No reset 1: FPGA 1 top level reset output asserted +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0: No reset 1: FPGA 0 top level reset output asserted +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_2_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CORTEX A9 Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status. 0 - ARM PLL out of lock. 1 - ARM PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is CPU PLL. 10 - Source for generated clock is DDR divided clock. 11 - Source for generated clock is IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CORTEX A9 Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status. 0 - DDR PLL out of lock. 1 - DDR PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Divisor value for the ddr_3xclk +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk) +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status. 0 - IO PLL out of lock. 1 - IO PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 RX Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Linear Quad-SPI Reference Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Reference Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Reference Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP 2X Clock Contol +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +FPGA 0 Output Clock Control +
    + +FPGA1_CLK_CTRL + + +0XF8000180 + +32 + +RW + +0x000000 + +FPGA 1 Output Clock Control +
    + +FPGA2_CLK_CTRL + + +0XF8000190 + +32 + +RW + +0x000000 + +FPGA 2 Output Clock Control +
    + +FPGA3_CLK_CTRL + + +0XF80001A0 + +32 + +RW + +0x000000 + +FPGA 3 Output Clock Control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +6:2:1 ratio clock, if set +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Selects the source used to generate the clock. 0 - Source for generated clock is GEM 0 MIO RX clock. 1 - Source for generated clock is GEM 0 FMIO RX clock. +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +Gigabit Ethernet MAC 0 RX Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source used to generate the clock. 1xx - Source for generated clock is Ethernet 0 FMIO clock. 00x - Source for generated clock is IO PLL. 010 - Source for generated clock is ARM PLL. 011 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +7 + +700 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +701 + +Linear Quad-SPI Reference Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO 0 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +SDIO 1 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a03 + +SDIO Reference Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Reference Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active 0 - Clock is disabled 1 - Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP 2X Clock Contol +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +5 + +500000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +500800 + +FPGA 0 Output Clock Control +
    +

    +

    Register ( slcr )FPGA1_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA1_CLK_CTRL + +0XF8000180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA1_CLK_CTRL@0XF8000180 + +31:0 + +3f03f30 + + + +400500 + +FPGA 1 Output Clock Control +
    +

    +

    Register ( slcr )FPGA2_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA2_CLK_CTRL + +0XF8000190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +2 + +200000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA2_CLK_CTRL@0XF8000190 + +31:0 + +3f03f30 + + + +200500 + +FPGA 2 Output Clock Control +
    +

    +

    Register ( slcr )FPGA3_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA3_CLK_CTRL + +0XF80001A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA3_CLK_CTRL@0XF80001A0 + +31:0 + +3f03f30 + + + +100500 + +FPGA 3 Output Clock Control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Enable the 6:2:1 mode. 1 for 6:3:2:1. 0 for 4:2:2:1. +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +6:2:1 ratio clock, if set +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet MAC 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet MAC 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +1 + +800 + +SDIO 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +LQSPI AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec0c4d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two rank configuration register +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control register +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control register +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control register +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters register 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters register 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters register 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters register 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters register 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM initialization parameters register +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access register +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access register +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM burst 8 read/write register +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ register +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM bank address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT register +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO register +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration register +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold register +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller register 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller register 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller register 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller register 4 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters register +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters register +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown register +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control register +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug register +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing register +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear register +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction register +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status register +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count register +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub register +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control register (2) +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control register (3) +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask register +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 Register +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 Register +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 Register +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 Register +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control Register +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +82 + +82 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Only present for multi-rank configurations. Each bit represents one rank. 1=populated; 0=unpopulated 01 = One Rank 11 = Two Ranks Others = Reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +00 = block read/write scheduling for 1-cycle when Write requires changing ODT settings 01 = block read/write scheduling for 2 cycles when Write requires changing ODT settings 10 = block read/write scheduling for 3 cycles when Write requires changing ODT settings 11 = Reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0 = schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1 = schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81082 + +Two rank configuration register +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of clocks that the HPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control register +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control register +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control register +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a1 + +2840 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks DRAM RELATED +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4285b + +DRAM Parameters register 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +13 + +13 + +Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. LPDDR2 mode: Set this to the larger of tCKE or tCKESR. Non-LPDDR2 designs: Set this to tCKE value. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d3 + +DRAM Parameters register 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2/3 -> WL -1 LPDDR -> 1 LPDDR2 ->WL Where WL = Write Latency of DRAM DRAM RELATED. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. non-LPDDR2 -> RL + BL/2 + 2 - WL LPDDR2 -> RL + BL/2 + RU(tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +f + +3c00 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +5 + +28000 + +tXP: Minimum time after power down exit to any operation. DRAM RELATED. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +5 + +2800000 + +Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency DRAM RELATED +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +7282bce5 + +DRAM Parameters register 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1 DRAM RELATED +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1 = sdram device 0 = non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-mobile DRAM device in use. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +1=enable the assertion of stop_clk to the PHY whenever a clock is not required by LPDDR/ LPDDR2. 0=stop_clk will never be asserted. Note: This is only present for implementations supporting LPDDR/LPDDR2 devices. +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Set to RL. Time from Read command to Read data on DRAM interface. Unit: clocks This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. RL = Read Latency of DRAM Note: This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1 = disable the pad power down feature 0 = Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters register 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1 = DDRC will use 2T timing 0 = DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1 = Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and 'ddrc_reg_mr_wr_busy' is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +Mode register address - for non-LPDDR2 modes. This register is don't care in LPDDR2 mode 00 = MR0 01 = MR1 10 = MR2 11 = MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +Mode register write data - for non-LPDDR2 modes. For LPDDR2, these 16-bits are interpreted as Writes: \'7bMR Addr[7:0], MR Data[7:0]\'7d. Reads: \'7bMR Addr[7:0], Don't Care[7:0]\'7d +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 1 = Indicates that mode register write / read operation is in progress. 0 = Indicates that the core can initiate a mode register write / read operation. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 1 = read 0 = write +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 1'b0 by default. This bit will be cleared (1'b0), whenever a Mode Register Read command is issued. This bit will be set to 1'b1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters register 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands DRAM RELATED Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM initialization parameters register +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +Non LPDDR2- Value to be loaded into DRAM EMR2 registers. For LPDDR2 - Value to Write to the MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +Non LPDDR2- Value to be loaded into DRAM EMR3 registers. Used in non-LPDDR2 designs only. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access register +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +b30 + +b30 + +Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +Non LPDDR2-Value to be loaded into DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. For LPDDR2 - Value to Write to the MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40b30 + +DRAM EMR, MR access register +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +This controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. In LPDDR and LPDDR2, Burst length of 16 is supported only in Half Bus Width mode. Every input read/write command has 4 cycles of data associated with it and that is not enough data for doing Burst Length16 in Full Bus Width mode. 0010 - Burst length of 4 0100 - Burst length of 8 1000 - Burst length of 16 (only supported for LPDDR AND LPDDR2) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM burst 8 read/write register +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Active Low signal. When asserted (0), all incoming transactions will be forced to low priority. Forcing the incoming transactions to low priority implicitly turns OFF Bypass. Otherwise, HPR is allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. This bit is intended to be switched on-the-fly +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ register +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14 Internal Base: 5 The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Selects the address bits used as DRAM bank address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Selects the address bits used as DRAM column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Selects the address bits used as DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODT's must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT register +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1 = stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO register +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration register +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable for LPDDR and LPDDR2 modes. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold register +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +When 1, disable Write Combine +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to '0', auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller register 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +1 - Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on 'urgent' input coming from AXI master. 0 - Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 1'b0. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller register 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) Only present in designs that support DDR3 and LPDDR2 devices. +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Only present in designs that support DDR3 devices +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. Only present in designs that support DDR3 devices. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller register 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller register 4 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters register +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters register +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +1 - Controller puts the DRAM into Deep Powerdown mode when the transaction store is empty. 0 - Brings Controller out of Deep Powerdown mode Present only in designs configured to support LPDDR or LPDDR2 FOR PERFORMANCE ONLY. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown register +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +1 = Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0 = Write leveling disabled. +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +1 = Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0= Read DQS gate leveling is disabled. +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +1 = Read Data Eye training mode has been enabled as part of init sequence. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control register +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1 - Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0 - Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug register +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. Non-LPDDR -> RL-1 LPDDR -> RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing register +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear register +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when a correctable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction register +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when an uncorrectable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status register +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count register +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 3'b000 (No ECC) and 3'b100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 3'b100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 - No ECC, 001 - Reserved 010 - Parity 011 - Reserved 100 - SEC/DED over 1-beat 101 - SEC/DED over multiple beats 110 - Device Correction 111 - Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +This feature is NOT supported. Only default value works. 1 - Disable ECC scrubs 0 - Enable ECC scrubs Valid only when reg_ddrc_ecc_mode = 3'b100. +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub register +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +1 = run scan test at full clock speed but with less coverage 0 = run scan test at slow clock speed but with high coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 2'b00: constant pattern (0 repeated on each DQ bit) 2'b01: low freq pattern (00001111 repeated on each DQ bit) 2'b10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +1=assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) 0=(default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0 = Select algorithm # 1'b1 = Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 1- Rank 0 delays are used for all ranks 0- Each Rank uses its own delay +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-LPDDR DRAM device in use. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1=enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control register (2) +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control register (3) +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +This register must be set based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask register +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +1=LPDDR2 DRAM device in Use. 0=non-LPDDR2 device in use Present only in designs configured to support LPDDR2. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +1:Per bank refresh 0:All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported on all LPDDR2 devices. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 Register +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. Present only in designs configured to support LPDDR2. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 Register +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 Register +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 Register +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control Register +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0 = DDRC Init 1 = Normal operation 2 = Power-down mode 3 = Self-refresh mode 4 and above = deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDRIOB Address 0 Configuartion Register +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDRIOB Address 1 Configuration Register +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDRIOB Differential Clock Configuration Register +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Address Register +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Data Register +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Differential Strobe Register +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Clcok Register +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDRIOB DDR Control Register +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Control for Pin 0 +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Control for Pin 1 +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Control for Pin 2 +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Control for Pin 3 +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Control for Pin 4 +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Control for Pin 5 +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Control for Pin 6 +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Control for Pin 8 +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Control for Pin 9 +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Control for Pin 10 +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Control for Pin 11 +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Control for Pin 12 +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Control for Pin 13 +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Control for Pin 14 +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Control for Pin 15 +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Control for Pin 16 +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Control for Pin 17 +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Control for Pin 18 +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Control for Pin 19 +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Control for Pin 20 +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Control for Pin 21 +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Control for Pin 22 +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Control for Pin 23 +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Control for Pin 24 +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Control for Pin 25 +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Control for Pin 26 +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Control for Pin 27 +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Control for Pin 40 +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Control for Pin 41 +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Control for Pin 42 +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Control for Pin 43 +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Control for Pin 44 +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Control for Pin 45 +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Control for Pin 46 +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Control for Pin 47 +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Control for Pin 48 +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Control for Pin 49 +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Control for Pin 52 +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Control for Pin 53 +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select register +
    + +SD1_WP_CD_SEL + + +0XF8000834 + +32 + +RW + +0x000000 + +SDIO 1 WP CD select register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDRIOB Address 0 Configuartion Register +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDRIOB Address 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDRIOB Differential Clock Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDRIOB Drive Slew Address Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Data Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Differential Strobe Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Clcok Register +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output 0001 - VREF = 0.6V for LPDDR2 with 1.2V IO 0010 - VREF = 0.675V for LPDDR3 1.35 V IO 0100 - VREF = 0.75V for DDR3 with 1.5V IO 1000 - VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input X0 - Disable External VREF for lower 16 bits X1 - Enable External VREF for lower 16 bits 0X - Disable External VREF for upper 16 bits 1X - Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors X0 - Disable VREF pull-up for lower 16 bits X1 - Enable VREF pull-up for lower 16 bits 0X - Disable VREF pull-up for upper 16 bits 1X - Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0 - VRP/VRN not used 1 - VRP/VRN used as refio +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +73ff + + + +260 + +DDRIOB DDR Control Register +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3f01 + + + +1601 + +MIO Control for Pin 0 +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Control for Pin 1 +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 2 +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Control for Pin 3 +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 4 +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 5 +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 6 +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 8 +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3f01 + + + +1601 + +MIO Control for Pin 9 +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 10 +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 11 +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_wait- (SRAM Wait State indicator) 2= nand, Input, smc_nand_data_in[7]- (NAND Data Bus) = nand, Output, smc_nand_data_out[7]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 12 +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[5]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[5]- (SRAM Data) 2= nand, Input, smc_nand_data_in[3]- (NAND Data Bus) = nand, Output, smc_nand_data_out[3]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 13 +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 14 +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 15 +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[4]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[1]- (SRAM Address) 2= nand, Input, smc_nand_data_in[8]- (NAND Data Bus) = nand, Output, smc_nand_data_out[8]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 16 +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[5]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[2]- (SRAM Address) 2= nand, Input, smc_nand_data_in[9]- (NAND Data Bus) = nand, Output, smc_nand_data_out[9]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 17 +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[6]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[3]- (SRAM Address) 2= nand, Input, smc_nand_data_in[10]- (NAND Data Bus) = nand, Output, smc_nand_data_out[10]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 18 +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 19 +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 20 +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[6]- (SRAM Address) 2= nand, Input, smc_nand_data_in[13]- (NAND Data Bus) = nand, Output, smc_nand_data_out[13]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 21 +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 22 +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 23 +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 24 +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 25 +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 26 +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 27 +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 40 +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 41 +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 42 +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 43 +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 44 +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 45 +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3f01 + + + +1201 + +MIO Control for Pin 46 +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Control for Pin 47 +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Control for Pin 48 +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Control for Pin 49 +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 52 +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 53 +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +2e + +2e + +SDIO0 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO0 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f002e + +SDIO 0 WP CD select register +
    +

    +

    Register ( slcr )SD1_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD1_WP_CD_SEL + +0XF8000834 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO1_WP_SEL + +5:0 + +3f + +0 + +0 + +SDIO1 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SDIO1_CD_SEL + +21:16 + +3f0000 + +9 + +90000 + +SDIO1 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SD1_WP_CD_SEL@0XF8000834 + +31:0 + +3f003f + + + +90000 + +SDIO 1 WP CD select register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value 0 = Disables baud_sample 1 = Clock divisor bypass 2 - 65535 = baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break. 1 = stop transmission of the break. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break 1 = start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter 1 = receiver timeout counter is restarted +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable. 1, the transmitter is disabled +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable. 1, the transmitter is enabled, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable. 1= receiver is enabled +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable. 1=the receiver logic is enabled, provided RXDIS field is set to 0 +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for TX data path. 1=the transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for RX data path 1=receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode 0 : Default UART mode 1 : Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select 0 : APB clock, pclk 1 : a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode 00 = normal 01 = automatic cho 10 = local loopback 11 = remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits 00 = 1 stop bit 01 = 1.5 stop bits 10 = 2 stop bits 11 = reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select. 000 = even parity 001 = odd parity 010 = forced to 0 parity (space) 011 = forced to 1 parity (mark) 1xx = no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select 11 = 6 bits 10 = 7 bits 01 / 00 = 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +clock source select 1 = clock source is uart_clk/8 0 = clock source is uart_clk +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    ENET RESET

    +

    I2C RESET

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset. 0 - No reset. 1 - ACP AXI interface reset output asserted. +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS3AXI interface reset output asserted. +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS2 AXI interface reset output asserted. +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS1 AXI interface reset output asserted. +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS0 AXI interface reset output asserted. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 1 reset is asserted. +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 0 reset is asserted. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface 1 soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0 - No reset. 1 - FPGA master interface 1 reset is asserted. +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0 - No reset. 1 - FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 3 peripheral request reset output asserted. +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 2 peripheral request reset output asserted. +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 1 peripheral request reset output asserted. +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 0 peripheral request reset output asserted. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0 - No reset. 1 - FPGA 3 top level reset output asserted. +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0 - No reset. 1 - FPGA 2 top level reset output asserted. +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0 - No reset. 1 - FPGA 1 top level reset output asserted. +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0 - No reset. 1 - FPGA 0 top level reset output asserted. +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_1_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/ps7_init.tcl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/ps7_init.tcl new file mode 100755 index 0000000..85a6f34 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/ps7_init.tcl @@ -0,0 +1,781 @@ +proc ps7_pll_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000701 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00500800 + mask_write 0XF8000180 0x03F03F30 0x00400500 + mask_write 0XF8000190 0x03F03F30 0x00200500 + mask_write 0XF80001A0 0x03F03F30 0x00100500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_3_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x0007FFFF 0x00001082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006024 0x0FFFFFC3 0x00000000 + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00000003 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x0003F03F 0x0003C008 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x00010000 0x00000000 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x00000200 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFCF 0x40000001 + mask_write 0XF800611C 0x7FFFFFCF 0x40000001 + mask_write 0XF8006120 0x7FFFFFCF 0x40000001 + mask_write 0XF8006124 0x7FFFFFCF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0x6FFFFEFE 0x00040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000703FF 0x000003FF + mask_write 0XF800620C 0x000703FF 0x000003FF + mask_write 0XF8006210 0x000703FF 0x000003FF + mask_write 0XF8006214 0x000703FF 0x000003FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF5 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000001 0x00000001 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001601 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003F01 0x00001601 + mask_write 0XF8000728 0x00003FFF 0x00001680 + mask_write 0XF800072C 0x00003FFF 0x00001680 + mask_write 0XF8000730 0x00003FFF 0x00001680 + mask_write 0XF8000734 0x00003FFF 0x00001680 + mask_write 0XF8000738 0x00003FFF 0x00001680 + mask_write 0XF800073C 0x00003FFF 0x00001680 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003F01 0x00001201 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F002E + mask_write 0XF8000834 0x003F003F 0x00090000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x000003FF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 +} +proc ps7_post_config_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_3_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000701 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00500800 + mask_write 0XF8000180 0x03F03F30 0x00400500 + mask_write 0XF8000190 0x03F03F30 0x00200500 + mask_write 0XF80001A0 0x03F03F30 0x00100500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_2_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001601 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003F01 0x00001601 + mask_write 0XF8000728 0x00003FFF 0x00001680 + mask_write 0XF800072C 0x00003FFF 0x00001680 + mask_write 0XF8000730 0x00003FFF 0x00001680 + mask_write 0XF8000734 0x00003FFF 0x00001680 + mask_write 0XF8000738 0x00003FFF 0x00001680 + mask_write 0XF800073C 0x00003FFF 0x00001680 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003F01 0x00001201 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F002E + mask_write 0XF8000834 0x003F003F 0x00090000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 +} +proc ps7_post_config_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_2_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000701 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00500800 + mask_write 0XF8000180 0x03F03F30 0x00400500 + mask_write 0XF8000190 0x03F03F30 0x00200500 + mask_write 0XF80001A0 0x03F03F30 0x00100500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_1_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x000073FF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001601 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003F01 0x00001601 + mask_write 0XF8000728 0x00003FFF 0x00001680 + mask_write 0XF800072C 0x00003FFF 0x00001680 + mask_write 0XF8000730 0x00003FFF 0x00001680 + mask_write 0XF8000734 0x00003FFF 0x00001680 + mask_write 0XF8000738 0x00003FFF 0x00001680 + mask_write 0XF800073C 0x00003FFF 0x00001680 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003F01 0x00001201 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F002E + mask_write 0XF8000834 0x003F003F 0x00090000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 +} +proc ps7_post_config_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_1_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +set PCW_SILICON_VER_1_0 "0x0" +set PCW_SILICON_VER_2_0 "0x1" +set PCW_SILICON_VER_3_0 "0x2" +set APU_FREQ 666666666 + + + +proc mask_poll { addr mask } { + set count 1 + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + while { $maskedval == 0 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + set count [ expr { $count + 1 } ] + if { $count == 100000000 } { + puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask" + break + } + } +} + + + +proc mask_delay { addr val } { + set delay [ get_number_of_cycles_for_delay $val ] + perf_reset_and_start_timer + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + while { $maskedval == 1 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + } + perf_reset_clock +} + +proc ps_version { } { + set si_ver "0x[string range [mrd 0xF8007080] end-8 end]" + set mask_sil_ver "0x[expr {$si_ver >> 28}]" + return $mask_sil_ver; +} + +proc ps7_post_config {} { + set saved_mode [configparams force-mem-accesses] + configparams force-mem-accesses 1 + + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_post_config_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_post_config_2_0 + } else { + ps7_post_config_3_0 + } + configparams force-mem-accesses $saved_mode +} + +proc ps7_debug {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_debug_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_debug_2_0 + } else { + ps7_debug_3_0 + } +} +proc ps7_init {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_mio_init_data_1_0 + ps7_pll_init_data_1_0 + ps7_clock_init_data_1_0 + ps7_ddr_init_data_1_0 + ps7_peripherals_init_data_1_0 + #puts "PCW Silicon Version : 1.0" + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_mio_init_data_2_0 + ps7_pll_init_data_2_0 + ps7_clock_init_data_2_0 + ps7_ddr_init_data_2_0 + ps7_peripherals_init_data_2_0 + #puts "PCW Silicon Version : 2.0" + } else { + ps7_mio_init_data_3_0 + ps7_pll_init_data_3_0 + ps7_clock_init_data_3_0 + ps7_ddr_init_data_3_0 + ps7_peripherals_init_data_3_0 + #puts "PCW Silicon Version : 3.0" + } +} + + +# For delay calculation using global timer + +# start timer + proc perf_start_clock { } { + + #writing SCU_GLOBAL_TIMER_CONTROL register + + mask_write 0xF8F00208 0x00000109 0x00000009 +} + +# stop timer and reset timer count regs + proc perf_reset_clock { } { + perf_disable_clock + mask_write 0xF8F00200 0xFFFFFFFF 0x00000000 + mask_write 0xF8F00204 0xFFFFFFFF 0x00000000 +} + +# Compute mask for given delay in miliseconds +proc get_number_of_cycles_for_delay { delay } { + + # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + variable APU_FREQ + return [ expr ($delay * $APU_FREQ /(2 * 1000))] +} + + +# stop timer +proc perf_disable_clock {} { + mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 +} + +proc perf_reset_and_start_timer {} { + perf_reset_clock + perf_start_clock +} + + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/ps7_init_gpl.h b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/ps7_init_gpl.h new file mode 100755 index 0000000..45a7839 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/ps7_init_gpl.h @@ -0,0 +1,131 @@ +/****************************************************************************** +* +* Copyright (C) 2010-2020 +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, see +* +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init_gpl.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + + + + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 142857132 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 25000000 +#define FPGA1_FREQ 50000000 +#define FPGA2_FREQ 100000000 +#define FPGA3_FREQ 200000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/xilinx-zynq.cc b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/xilinx-zynq.cc new file mode 100755 index 0000000..14e40f9 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/questa/xilinx-zynq.cc @@ -0,0 +1,106 @@ +/* + * Xilinx SystemC/TLM-2.0 Zynq Wrapper. + * + * Written by Edgar E. Iglesias + * + * Copyright (c) 2016, Xilinx Inc. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#define SC_INCLUDE_DYNAMIC_PROCESSES + +#include + +#include "tlm_utils/simple_initiator_socket.h" +#include "tlm_utils/simple_target_socket.h" + +using namespace sc_core; +using namespace std; + +#include "xilinx-zynq.h" +#include + +//xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr, +// Iremoteport_tlm_sync *sync) +// : remoteport_tlm(name, -1, sk_descr, sync), +xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr) + : remoteport_tlm(name, -1, sk_descr), + rp_m_axi_gp0("rp_m_axi_gp0"), + rp_m_axi_gp1("rp_m_axi_gp1"), + rp_s_axi_gp0("rp_s_axi_gp0"), + rp_s_axi_gp1("rp_s_axi_gp1"), + rp_s_axi_hp0("rp_s_axi_hp0"), + rp_s_axi_hp1("rp_s_axi_hp1"), + rp_s_axi_hp2("rp_s_axi_hp2"), + rp_s_axi_hp3("rp_s_axi_hp3"), + rp_s_axi_acp("rp_s_axi_acp"), + rp_wires_in("wires_in", 20, 0), + rp_wires_out("wires_out", 0, 17), + rp_irq_out("irq_out", 0, 28), + pl2ps_irq("pl2ps_irq", 20), + ps2pl_irq("ps2pl_irq", 28), + ps2pl_rst("ps2pl_rst", 17) +{ + int i; + + m_axi_gp[0] = &rp_m_axi_gp0.sk; + m_axi_gp[1] = &rp_m_axi_gp1.sk; + + s_axi_gp[0] = &rp_s_axi_gp0.sk; + s_axi_gp[1] = &rp_s_axi_gp1.sk; + + s_axi_hp[0] = &rp_s_axi_hp0.sk; + s_axi_hp[1] = &rp_s_axi_hp1.sk; + s_axi_hp[2] = &rp_s_axi_hp2.sk; + s_axi_hp[3] = &rp_s_axi_hp3.sk; + s_axi_acp = &rp_s_axi_acp.sk; + + /* PL to PS Interrupt signals. */ + for (i = 0; i < 20; i++) { + rp_wires_in.wires_in[i](pl2ps_irq[i]); + } + + /* PS to PL Interrupt signals. */ + for (i = 0; i < 28; i++) { + rp_irq_out.wires_out[i](ps2pl_irq[i]); + } + + /* PS to PL resets. */ + for (i = 0; i < 17; i++) { + rp_wires_out.wires_out[i](ps2pl_rst[i]); + } + + register_dev(0, &rp_s_axi_gp0); + register_dev(1, &rp_s_axi_gp1); + + register_dev(2, &rp_s_axi_hp0); + register_dev(3, &rp_s_axi_hp1); + register_dev(4, &rp_s_axi_hp2); + register_dev(5, &rp_s_axi_hp3); + + register_dev(6, &rp_s_axi_acp); + + register_dev(7, &rp_m_axi_gp0); + register_dev(8, &rp_m_axi_gp1); + register_dev(9, &rp_wires_in); + register_dev(10, &rp_wires_out); + register_dev(11, &rp_irq_out); +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/Makefile b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/Makefile new file mode 100755 index 0000000..33394b3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/Makefile @@ -0,0 +1,26 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +INCLUDEFILES=*.h +LIBSOURCES=*.c +OUTS = *.o + +libs: + echo "Compiling SPI_Con..." + $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} + make clean + +include: + ${CP} $(INCLUDEFILES) $(INCLUDEDIR) + +clean: + rm -rf ${OUTS} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/NewExtInst_TOP.bda b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/NewExtInst_TOP.bda new file mode 100755 index 0000000..ab7b1f9 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/NewExtInst_TOP.bda @@ -0,0 +1,272 @@ +{ + "graphjs": { + "version": "1.0", + "keys": [ + { + "abrv": "VH", + "name": "vert_hid", + "type": "int", + "for": "node" + }, + { + "abrv": "VM", + "name": "vert_name", + "type": "string", + "for": "node" + }, + { + "abrv": "VT", + "name": "vert_type", + "type": "string", + "for": "node" + }, + { + "abrv": "BA", + "name": "base_addr", + "type": "string", + "for": "node" + }, + { + "abrv": "HA", + "name": "high_addr", + "type": "string", + "for": "node" + }, + { + "abrv": "BP", + "name": "base_param", + "type": "string", + "for": "node" + }, + { + "abrv": "HP", + "name": "high_param", + "type": "string", + "for": "node" + }, + { + "abrv": "MA", + "name": "master_addrspace", + "type": "string", + "for": "node" + }, + { + "abrv": "MX", + "name": "master_instance", + "type": "string", + "for": "node" + }, + { + "abrv": "MI", + "name": "master_interface", + "type": "string", + "for": "node" + }, + { + "abrv": "MS", + "name": "master_segment", + "type": "string", + "for": "node" + }, + { + "abrv": "MV", + "name": "master_vlnv", + "type": "string", + "for": "node" + }, + { + "abrv": "SX", + "name": "slave_instance", + "type": "string", + "for": "node" + }, + { + "abrv": "SI", + "name": "slave_interface", + "type": "string", + "for": "node" + }, + { + "abrv": "MM", + "name": "slave_memmap", + "type": "string", + "for": "node" + }, + { + "abrv": "SS", + "name": "slave_segment", + "type": "string", + "for": "node" + }, + { + "abrv": "SV", + "name": "slave_vlnv", + "type": "string", + "for": "node" + }, + { + "abrv": "TM", + "name": "memory_type", + "type": "string", + "for": "node" + }, + { + "abrv": "TU", + "name": "usage_type", + "type": "string", + "for": "node" + }, + { + "abrv": "LT", + "name": "lock_type", + "type": "string", + "for": "node" + }, + { + "abrv": "BT", + "name": "boot_type", + "type": "string", + "for": "node" + }, + { + "abrv": "EH", + "name": "edge_hid", + "type": "int", + "for": "edge" + } + ], + "vertice_type_order": [ + { + "abrv": "BC", + "desc": "Block Container" + }, + { + "abrv": "PR", + "desc": "Parital Reference" + }, + { + "abrv": "VR", + "desc": "Variant" + }, + { + "abrv": "PM", + "desc": "Variant Permutations" + }, + { + "abrv": "CX", + "desc": "Boundary Connection" + }, + { + "abrv": "AC", + "desc": "Assignment Coordinate" + }, + { + "abrv": "ACE", + "desc": "Excluded Assign Coordinate" + }, + { + "abrv": "APX", + "desc": "Boundary Aperture" + }, + { + "abrv": "CIP", + "desc": "High level Processing System" + } + ], + "vertices": { + "V0": { + "VM": "NewExtInst_TOP", + "VT": "BC" + }, + "V1": { + "VH": "2", + "VM": "NewExtInst_TOP", + "VT": "VR" + }, + "V2": { + "VH": "2", + "VT": "PM", + "TU": "active" + }, + "V3": { + "VT": "AC", + "BA": "0x43C00000", + "HA": "0x43C0FFFF", + "BP": "C_S00_AXI_BASEADDR", + "HP": "C_S00_AXI_HIGHADDR", + "MA": "Data", + "MX": "/processing_system7_0", + "MI": "M_AXI_GP0", + "MS": "SEG_SPI_Con_0_S00_AXI_reg", + "MV": "xilinx.com:ip:processing_system7:5.5", + "SX": "/SPI_Con_0", + "SI": "S00_AXI", + "SS": "S00_AXI_reg", + "SV": "xilinx.com:user:SPI_Con:1.0", + "TM": "both", + "TU": "register" + }, + "V4": { + "VT": "AC", + "BA": "0x43C10000", + "HA": "0x43C1FFFF", + "BP": "C_S00_AXI_BASEADDR", + "HP": "C_S00_AXI_HIGHADDR", + "MA": "Data", + "MX": "/processing_system7_0", + "MI": "M_AXI_GP0", + "MS": "SEG_SPI_Con_1_S00_AXI_reg", + "MV": "xilinx.com:ip:processing_system7:5.5", + "SX": "/SPI_Con_1", + "SI": "S00_AXI", + "SS": "S00_AXI_reg", + "SV": "xilinx.com:user:SPI_Con:1.0", + "TM": "both", + "TU": "register" + }, + "V5": { + "VT": "AC", + "BA": "0x43C20000", + "HA": "0x43C2FFFF", + "BP": "C_S00_AXI_BASEADDR", + "HP": "C_S00_AXI_HIGHADDR", + "MA": "Data", + "MX": "/processing_system7_0", + "MI": "M_AXI_GP0", + "MS": "SEG_SPI_Con_2_S00_AXI_reg", + "MV": "xilinx.com:ip:processing_system7:5.5", + "SX": "/SPI_Con_2", + "SI": "S00_AXI", + "SS": "S00_AXI_reg", + "SV": "xilinx.com:user:SPI_Con:1.0", + "TM": "both", + "TU": "register" + } + }, + "edges": [ + { + "src": "V0", + "trg": "V1" + }, + { + "src": "V1", + "trg": "V2" + }, + { + "src": "V3", + "trg": "V2", + "EH": "2" + }, + { + "src": "V4", + "trg": "V2", + "EH": "2" + }, + { + "src": "V5", + "trg": "V2", + "EH": "2" + } + ] + } +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/NewExtInst_TOP.sh b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/NewExtInst_TOP.sh new file mode 100755 index 0000000..d49e8fa --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/NewExtInst_TOP.sh @@ -0,0 +1,264 @@ +#!/usr/bin/env bash +#********************************************************************************************************** +# Vivado (TM) v2023.2 (64-bit) +# +# Script generated by Vivado on Fri May 15 15:32:22 CST 2026 +# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 +# +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# +# Filename : NewExtInst_TOP.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script generated by export_simulation Tcl command +# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the +# design. The script will copy the library mapping file from the compiled library directory, +# create design library directories and library mappings in the mapping file. +# +# Usage : NewExtInst_TOP.sh +# NewExtInst_TOP.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]* +# NewExtInst_TOP.sh [-reset_run] +# NewExtInst_TOP.sh [-reset_log] +# NewExtInst_TOP.sh [-help] +# +# * The -noclean_files switch is deprecated and will not peform any function (by default, the +# simulator generated files will not be removed unless -reset_run switch is used) +# +# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library +# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help' +# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path +# switch with the directory path where the library is created while generating the script +# with export_simulation. +# +# Alternatively, you can set the library path by setting the following project property:- +# +# set_property compxlib._compiled_library_dir [current_project] +# +# You can also point to the simulation library by either setting the 'lib_map_path' global +# variable in this script or specify it with the '-lib_map_path' switch while executing this +# script (type 'NewExtInst_TOP.sh -help' for more information). +# +# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the +# generated script, but if design is targetted for system simulation containing SystemC/C++/C +# sources, then the library path MUST be specified upfront when calling export_simulation. +# +# For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************** + +# catch pipeline exit status +set -Eeuo pipefail + +# script info +echo -e "NewExtInst_TOP.sh - Script generated by export_simulation (Vivado v2023.2 (64-bit)-id)\n" + +# main steps +run() +{ + check_args $* + setup + if [[ ($b_step == 1) ]]; then + case $step in + "compile" ) + init_lib + compile + ;; + "simulate" ) + simulate + ;; + * ) + echo -e "ERROR: Invalid or missing step '$step' (type \"./NewExtInst_TOP.sh -help\" for more information)\n" + exit 1 + esac + else + init_lib + compile + simulate + fi +} + +# RUN_STEP: +compile() +{ + runvsimsa -do "do {compile.do}" 2>&1 | tee -a compile.log +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + # delete previous files for a clean rerun + if [[ ($b_reset_run == 1) ]]; then + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + fi + + # delete previous log files + if [[ ($b_reset_log == 1) ]]; then + reset_log + echo -e "INFO: Simulation run log files deleted.\n" + exit 0 + fi + + # add any setup/initialization commands here:- + + # + +} + +# simulator index file/library directory processing +init_lib() +{ + if [[ ($b_keep_index == 1) ]]; then + # keep previous design library mappings + true + else + # map simulator index file + map_setup_file + fi +} + +# map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($lib_map_path == "") ]]; then + lib_map_path="/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# delete generated log files from the previous run +reset_log() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# check switch argument value +check_arg_value() +{ + if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "simulate")) ]];then + echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then + echo -e "ERROR: Simulation library directory path not specified (type \"./NewExtInst_TOP.sh -help\" for more information)\n" + exit 1 + fi +} + +# check command line arguments +check_args() +{ + arg_count=$# + if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then + usage + fi + while [[ "$#" -gt 0 ]]; do + case $1 in + -step) check_arg_value $1 $2;step=$2; b_step=1; shift;; + -lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;; + -gen_bypass) b_gen_bypass=1 ;; + -reset_run) b_reset_run=1 ;; + -reset_log) b_reset_log=1 ;; + -keep_index) b_keep_index=1 ;; + -noclean_files) b_noclean_files=1 ;; + -help|-h) ;; + *) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;; + esac + shift + done + + # -reset_run is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then + echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -reset_log is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then + echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -keep_index is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then + echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -noclean_files is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then + echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi +} + +# script usage +usage() +{ + msg="Usage: NewExtInst_TOP.sh [-help]\n\ +Usage: NewExtInst_TOP.sh [-step]\n\ +Usage: NewExtInst_TOP.sh [-lib_map_path]\n\ +Usage: NewExtInst_TOP.sh [-reset_run]\n\ +Usage: NewExtInst_TOP.sh [-reset_log]\n\ +Usage: NewExtInst_TOP.sh [-keep_index]\n\ +Usage: NewExtInst_TOP.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-step ] -- Execute specified step (compile, simulate)\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\ +file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\ +NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\ +NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\ +[-reset_log] -- Delete simulator generated log files from the previous run\n\n\ +[-keep_index] -- Keep simulator index file settings from the previous run\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n" + echo -e $msg + exit 0 +} + +# initialize globals +step="" +lib_map_path="" +b_step=0 +b_lib_map_path=0 +b_gen_bypass=0 +b_reset_run=0 +b_reset_log=0 +b_keep_index=0 +b_noclean_files=0 + +# launch script +run $* diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/NewExtInst_TOP.udo b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/NewExtInst_TOP.udo new file mode 100644 index 0000000..e69de29 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/README.txt b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/README.txt new file mode 100644 index 0000000..1d27b8b --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/README.txt @@ -0,0 +1,50 @@ +################################################################################ +# Vivado (TM) v2023.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and how to fetch design source file details +# from the file_info.txt file. +# +# Generated by export_simulation on Fri May 15 15:32:22 CST 2026 +# +################################################################################ + +1. Steps to run the generated simulation script + +From the shell prompt in the current directory, issue the following command:- + +./NewExtInst_TOP.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first calls the 'check_args' function, the purpose of which +is to verify the generated script arguments and print error if incorrect switch +is specified. The 'run' function then calls the 'setup' function, the purpose of +which is to specify custom or initialization commands. The function also executes +following sub-functions:- +'reset_run' if -reset_run switch is specified. +'reset_log' if -reset_log switch is specified. + +The purpose of 'reset_run' function' is to delete the simulator generated design +data from the previous run and the purpose of 'reset_log' function' is to delete +the simulator generated log files. + +The 'run' function then calls the 'init_lib' function, the purpose of which is to +create design library mappings and directories. This function is called before the +'compile' step. By default, if '-step' switch is specified with the script then the +script will execute that specfic step, else it will execute all steps applicable +for the target simulator. + +For more information on the script, please type './NewExtInst_TOP.sh -help' + +2. Design source file information + +export_simulation generates a 'file_info.txt' file that contains design file information +based on the compile order when export_simulation was executed from Vivado. The file +contains information about the file name, type, library it is compiled into, whether +it is part of the IP, associated library, file path information in a comma separated +format. This file can be parsed to extract the required information for generating a +custom script or can be read from verification test infra. + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/SPI_Con.h b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/SPI_Con.h new file mode 100755 index 0000000..5278bdd --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/SPI_Con.h @@ -0,0 +1,107 @@ + +#ifndef SPI_CON_H +#define SPI_CON_H + + +/****************** Include Files ********************/ +#include "xil_types.h" +#include "xstatus.h" + +#define SPI_CON_S00_AXI_SLV_REG0_OFFSET 0 +#define SPI_CON_S00_AXI_SLV_REG1_OFFSET 4 +#define SPI_CON_S00_AXI_SLV_REG2_OFFSET 8 +#define SPI_CON_S00_AXI_SLV_REG3_OFFSET 12 +#define SPI_CON_S00_AXI_SLV_REG4_OFFSET 16 +#define SPI_CON_S00_AXI_SLV_REG5_OFFSET 20 +#define SPI_CON_S00_AXI_SLV_REG6_OFFSET 24 +#define SPI_CON_S00_AXI_SLV_REG7_OFFSET 28 +#define SPI_CON_S00_AXI_SLV_REG8_OFFSET 32 +#define SPI_CON_S00_AXI_SLV_REG9_OFFSET 36 +#define SPI_CON_S00_AXI_SLV_REG10_OFFSET 40 +#define SPI_CON_S00_AXI_SLV_REG11_OFFSET 44 +#define SPI_CON_S00_AXI_SLV_REG12_OFFSET 48 +#define SPI_CON_S00_AXI_SLV_REG13_OFFSET 52 +#define SPI_CON_S00_AXI_SLV_REG14_OFFSET 56 +#define SPI_CON_S00_AXI_SLV_REG15_OFFSET 60 +#define SPI_CON_S00_AXI_SLV_REG16_OFFSET 64 +#define SPI_CON_S00_AXI_SLV_REG17_OFFSET 68 +#define SPI_CON_S00_AXI_SLV_REG18_OFFSET 72 +#define SPI_CON_S00_AXI_SLV_REG19_OFFSET 76 +#define SPI_CON_S00_AXI_SLV_REG20_OFFSET 80 +#define SPI_CON_S00_AXI_SLV_REG21_OFFSET 84 +#define SPI_CON_S00_AXI_SLV_REG22_OFFSET 88 +#define SPI_CON_S00_AXI_SLV_REG23_OFFSET 92 +#define SPI_CON_S00_AXI_SLV_REG24_OFFSET 96 +#define SPI_CON_S00_AXI_SLV_REG25_OFFSET 100 +#define SPI_CON_S00_AXI_SLV_REG26_OFFSET 104 +#define SPI_CON_S00_AXI_SLV_REG27_OFFSET 108 +#define SPI_CON_S00_AXI_SLV_REG28_OFFSET 112 +#define SPI_CON_S00_AXI_SLV_REG29_OFFSET 116 +#define SPI_CON_S00_AXI_SLV_REG30_OFFSET 120 +#define SPI_CON_S00_AXI_SLV_REG31_OFFSET 124 + + +/**************************** Type Definitions *****************************/ +/** + * + * Write a value to a SPI_CON register. A 32 bit write is performed. + * If the component is implemented in a smaller width, only the least + * significant data is written. + * + * @param BaseAddress is the base address of the SPI_CONdevice. + * @param RegOffset is the register offset from the base to write to. + * @param Data is the data written to the register. + * + * @return None. + * + * @note + * C-style signature: + * void SPI_CON_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data) + * + */ +#define SPI_CON_mWriteReg(BaseAddress, RegOffset, Data) \ + Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data)) + +/** + * + * Read a value from a SPI_CON register. A 32 bit read is performed. + * If the component is implemented in a smaller width, only the least + * significant data is read from the register. The most significant data + * will be read as 0. + * + * @param BaseAddress is the base address of the SPI_CON device. + * @param RegOffset is the register offset from the base to write to. + * + * @return Data is the data from the register. + * + * @note + * C-style signature: + * u32 SPI_CON_mReadReg(u32 BaseAddress, unsigned RegOffset) + * + */ +#define SPI_CON_mReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (RegOffset)) + +/************************** Function Prototypes ****************************/ +/** + * + * Run a self-test on the driver/device. Note this may be a destructive test if + * resets of the device are performed. + * + * If the hardware system is not built correctly, this function may never + * return to the caller. + * + * @param baseaddr_p is the base address of the SPI_CON instance to be worked on. + * + * @return + * + * - XST_SUCCESS if all self-test code passed + * - XST_FAILURE if any self-test code failed + * + * @note Caching must be turned off for this function to work. + * @note Self test may fail if data memory and device are not on the same bus. + * + */ +XStatus SPI_CON_Reg_SelfTest(void * baseaddr_p); + +#endif // SPI_CON_H diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/SPI_Con.mdd b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/SPI_Con.mdd new file mode 100755 index 0000000..4bd813f --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/SPI_Con.mdd @@ -0,0 +1,10 @@ + + +OPTION psf_version = 2.1; + +BEGIN DRIVER SPI_Con + OPTION supported_peripherals = (SPI_Con); + OPTION copyfiles = all; + OPTION VERSION = 1.0; + OPTION NAME = SPI_Con; +END DRIVER diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/SPI_Con.tcl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/SPI_Con.tcl new file mode 100755 index 0000000..7f913c9 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/SPI_Con.tcl @@ -0,0 +1,5 @@ + + +proc generate {drv_handle} { + xdefine_include_file $drv_handle "xparameters.h" "SPI_Con" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR" +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/file_info.txt b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/file_info.txt new file mode 100644 index 0000000..7320d80 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/file_info.txt @@ -0,0 +1,39 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" 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+fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_9,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.vhd,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_9,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi_data_fifo_v2_1_vl_rfs.v,verilog,axi_data_fifo_v2_1_28,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi_crossbar_v2_1_vl_rfs.v,verilog,axi_crossbar_v2_1_30,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +NewExtInst_TOP_xbar_0.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/sim/NewExtInst_TOP_xbar_0.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +NewExtInst_TOP_rst_clk_wiz_0_100M_0.vhd,vhdl,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/sim/NewExtInst_TOP_rst_clk_wiz_0_100M_0.vhd,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi_protocol_converter_v2_1_vl_rfs.v,verilog,axi_protocol_converter_v2_1_29,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +NewExtInst_TOP_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_auto_pc_0/sim/NewExtInst_TOP_auto_pc_0.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +NewExtInst_TOP.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/sim/NewExtInst_TOP.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/glbl.v b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/libps7.dll b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/libps7.dll new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/libps7.dll @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/libps7.so b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/libps7.so new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/libps7.so @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/libremoteport.dll b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/libremoteport.dll new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/libremoteport.dll @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/libremoteport.so b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/libremoteport.so new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/libremoteport.so @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/ps7_init.h b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/ps7_init.h new file mode 100755 index 0000000..224d7ea --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/ps7_init.h @@ -0,0 +1,117 @@ +/****************************************************************************** +* +* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + + + + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 142857132 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 25000000 +#define FPGA1_FREQ 50000000 +#define FPGA2_FREQ 100000000 +#define FPGA3_FREQ 200000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/ps7_init.html b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/ps7_init.html new file mode 100755 index 0000000..9ca53bd --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/ps7_init.html @@ -0,0 +1,125613 @@ + + + + +Zynq PS configuration detail + + + +

    +
    + +
  • +
    Zynq PS Register Summary Viewer +
    +
    • +     +
    +
    +
    + +
    Zynq PS7 Summary Report +
    +     +
    User Configurations +
    +
    + +
    MIO Configurations +
    +     +
    + +
    CLK Configurations +
    +     +
    + +
    DDR Configurations +
    +     +
    + +
    SMC Configurations +
    +     +
    +
    +
    Select Version: + +
    +
    +
    Zynq Register View +
    +
    + +
    MIO Registers +
    +     + +
    PLL Registers +
    +     + +
    Clock Registers +
    +     + +
    DDR Registers +
    +     + +
    Peripherals Registers +
    +     +
    +
    This design is targeted for xc7z035 board (part number: xc7z035ffg676-2) + +
    +

    Zynq Design Summary

    + + + + + + + + + + + + + + + + + + + + + +
    +Device + +xc7z035 +
    +SpeedGrade + +-2 +
    +Part + +xc7z035ffg676-2 +
    +Description + +Zynq PS Configuration Report with register details +
    +Vendor + +Xilinx +
    +

    MIO Table View

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +MIO Pin + +Peripheral + +Signal + +IO Type + +Speed + +Pullup + +Direction +
    +MIO 0 + +SD 1 + +wp + +LVCMOS 3.3V + +slow + +enabled + +in +
    +MIO 1 + +Quad SPI Flash + +qspi0_ss_b + +LVCMOS 3.3V + +slow + +enabled + +out +
    +MIO 2 + +Quad SPI Flash + +qspi0_io[0] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 3 + +Quad SPI Flash + +qspi0_io[1] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 4 + +Quad SPI Flash + +qspi0_io[2] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 5 + +Quad SPI Flash + +qspi0_io[3]/HOLD_B + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 6 + +Quad SPI Flash + +qspi0_sclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 7 + + + + + + + + + + + + +
    +MIO 8 + +Quad SPI Flash + +qspi_fbclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 9 + +SD 1 + +cd + +LVCMOS 3.3V + +slow + +enabled + +in +
    +MIO 10 + +SD 1 + +data[0] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 11 + +SD 1 + +cmd + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 12 + +SD 1 + +clk + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 13 + +SD 1 + +data[1] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 14 + +SD 1 + +data[2] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 15 + +SD 1 + +data[3] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 16 + +Enet 0 + +tx_clk + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 17 + +Enet 0 + +txd[0] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 18 + +Enet 0 + +txd[1] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 19 + +Enet 0 + +txd[2] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 20 + +Enet 0 + +txd[3] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 21 + +Enet 0 + +tx_ctl + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 22 + +Enet 0 + +rx_clk + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 23 + +Enet 0 + +rxd[0] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 24 + +Enet 0 + +rxd[1] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 25 + +Enet 0 + +rxd[2] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 26 + +Enet 0 + +rxd[3] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 27 + +Enet 0 + +rx_ctl + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 28 + + + + + + + + + + + + +
    +MIO 29 + + + + + + + + + + + + +
    +MIO 30 + + + + + + + + + + + + +
    +MIO 31 + + + + + + + + + + + + +
    +MIO 32 + + + + + + + + + + + + +
    +MIO 33 + + + + + + + + + + + + +
    +MIO 34 + + + + + + + + + + + + +
    +MIO 35 + + + + + + + + + + + + +
    +MIO 36 + + + + + + + + + + + + +
    +MIO 37 + + + + + + + + + + + + +
    +MIO 38 + + + + + + + + + + + + +
    +MIO 39 + + + + + + + + + + + + +
    +MIO 40 + +SD 0 + +clk + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 41 + +SD 0 + +cmd + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 42 + +SD 0 + +data[0] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 43 + +SD 0 + +data[1] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 44 + +SD 0 + +data[2] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 45 + +SD 0 + +data[3] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 46 + +SD 0 + +wp + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 47 + +SD 0 + +cd + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 48 + +UART 1 + +tx + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 49 + +UART 1 + +rx + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 50 + + + + + + + + + + + + +
    +MIO 51 + + + + + + + + + + + + +
    +MIO 52 + +Enet 0 + +mdc + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 53 + +Enet 0 + +mdio + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +

    DDR Memory information

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Parameter name + +Value + +Description +
    +Enable DDR + +1 + +Enable DDR Controller of Zynq PS +
    +Memory Part + +MT41J256M16 RE-125 + + +
    +DRAM bus width + +32 Bit + +Select the desired data width. Refer to the Thechnical Reference Manual(TRM) for a detailed list of supported DDR data widths +
    +ECC + +Disabled + +ECC is supported only for data width of 16-bit +
    +BURST Length (lppdr only) + +8 + +Select the burst Length. It refers to the amount of data read/written after a read/write command is presented to the controller +
    +Internal Vref + +0 + + +
    +Operating Frequency (MHz) + +533.333333 + +Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade +
    +HIGH temperature + +Normal (0-85) + +Select the operating temparature +
    +DRAM IC bus width + +16 Bits + +Provide the width of the DRAM chip +
    +DRAM Device Capacity + +4096 MBits + + +
    +Speed Bin + +DDR3_1066F + +Provide the Speed Bin +
    +BANK Address Count + +3 + +Defines the bank to which an active an ACTIVE, READ, WRITE, or Precharge Command is being applied +
    +ROW Address Count + +15 + +Provide the Row address for ACTIVE commands +
    +COLUMN Address Count + +10 + +Provide the Row address for READ/WRITE commands +
    +CAS Latency + +7 + +Select the Column Access Strobe (CAS) Latency. It refers to the amount of time it takes for data to appear on the pins of the memory module +
    +CAS Write Latency + +6 + +Select the CAS Write Latency +
    +RAS to CAS Delay + +7 + +Provide the row address to column address delay time. tRCD is t he time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS) +
    +RECHARGE Time + +7 + +Precharge Time (tRP) is the number of clock cycles needed o terminate acces s to an open row of memory, and open access to the next row +
    +tRC (ns ) + +48.91 + +Provide the Row cycle time tRC (ns) +
    +tRASmin ( ns ) + +35.0 + +tRASmin (ns) is the minimum number of clock cycles required between an Active command and issuing the Precharge command +
    +tFAW + +40.0 + +It restricts the number of activates that can be done within a certain window of time +
    +ADDITIVE Latency + +0 + +Provide the Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths +
    +Write levelling + +1 + + +
    +Read gate + +1 + + +
    +Read gate + +1 + + +
    +DQS to Clock delay [0] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [1] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [2] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [3] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +Board delay [0] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [1] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [2] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [3] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +

    PS Clocks information

    +

    PS Reference Clock : 33.333333

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Peripheral + +PLL source + +Frequency (MHz) +
    +CPU 6x Freq (MHz) + +ARM PLL + +666.666687 +
    +QSPI Flash Freq (MHz) + +IO PLL + +142.857132 +
    +ENET0 Freq (MHz) + +IO PLL + +125.000000 +
    +SDIO Freq (MHz) + +IO PLL + +100.000000 +
    +SDIO Freq (MHz) + +IO PLL + +100.000000 +
    +UART Freq (MHz) + +IO PLL + +100.000000 +
    +FPGA0 Freq (MHz) + +IO PLL + +25.000000 +
    +FPGA1 Freq (MHz) + +IO PLL + +50.000000 +
    +FPGA2 Freq (MHz) + +IO PLL + +100.000000 +
    +FPGA3 Freq (MHz) + +IO PLL + +200.000000 +
    +

    ps7_pll_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: ARM PLL 10: DDR PLL 11: IO PLL This field is reset by POR only. +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for programming the PLL. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock and Rx Signals Select +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +FPGA1_CLK_CTRL + + +0XF8000180 + +32 + +RW + +0x000000 + +PL Clock 1 Output control +
    + +FPGA2_CLK_CTRL + + +0XF8000190 + +32 + +RW + +0x000000 + +PL Clock 2 output control +
    + +FPGA3_CLK_CTRL + + +0XF80001A0 + +32 + +RW + +0x000000 + +PL Clock 3 output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source of the Rx clock, control and data signals: 0: MIO 1: EMIO +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock and Rx Signals Select +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +7 + +700 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +701 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a03 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +5 + +500000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +500800 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )FPGA1_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA1_CLK_CTRL + +0XF8000180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA1_CLK_CTRL@0XF8000180 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 1 Output control +
    +

    +

    Register ( slcr )FPGA2_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA2_CLK_CTRL + +0XF8000190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +2 + +200000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA2_CLK_CTRL@0XF8000190 + +31:0 + +3f03f30 + + + +200500 + +PL Clock 2 output control +
    +

    +

    Register ( slcr )FPGA3_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA3_CLK_CTRL + +0XF80001A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA3_CLK_CTRL@0XF80001A0 + +31:0 + +3f03f30 + + + +100500 + +PL Clock 3 output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ratio: (When this register changes, no access are allowed to OCM.) 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +1 + +800 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec0c4d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +82 + +82 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reserved_reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Reserved. Do not modify. +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +Two_rank_cfg@0XF8006004 + +31:0 + +7ffff + + + +1082 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a1 + +2840 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4285b + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +13 + +13 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d3 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. In non-LPDDR mode, the minimum DRAM Write Latency (DDR2) supported is 3. In LPDDR mode, the required DRAM Write Latency of 1 is supported. Since write latency (CWL) min is 3, and DDR2 CWL is CL-1, the min (DDR2) CL supported is 4 +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +f + +3c00 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +5 + +28000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +5 + +2800000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +7282bce5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_en_dfi_dram_clk_disable + +23:23 + +800000 + +0 + +0 + +Enables the assertion of ddrc_dfi_dram_clk_disable. In DDR2/DDR3, only asserted in Self Refresh. In mDDR/LPDDR2, can be asserted in following: - during normal operation (Clock Stop), - in Power Down - in Self Refresh - In Deep Power Down +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +7fdffffc + + + +270872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffc3 + + + +0 + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2: Value loaded into EMR2 register DDR3: Value loaded into MR2 register LPDDR2: Value loaded into MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2: Value loaded into EMR3 register DDR3: Value loaded into MR3 register. Set Bit[2:0] to 3'b000. These bits are set appropriately by the Controller during Read Data eye training and Read DQS gate leveling. LPDDR2: Unused +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +b30 + +b30 + +DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2: Value loaded into EMR1register. (Bits[9:7] are for OCD and the setting in this reg is ignored. Controller sets this bits appropriately during initialization DDR3: Value loaded into MR1 register. Set Bit[7] to 0. This bit is set appropriately by the Controller during Write Leveling LPDDR2: Value loaded into MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40b30 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 8, Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 7, Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 6, Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 5, Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reserved_reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +Reserved. Do not modify. +
    +reserved_reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Reserved. Do not modify. +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3f03f + + + +3c008 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +10000 + + + +0 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum d'128) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_2d@0XF80060B4 + +31:0 + +200 + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of uncorrectable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on board topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +0: Use reg_phy_ctrl_slave_ratio for address/command timing slave DLL 1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_64@0XF8006190 + +31:0 + +6ffffefe + + + +40080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. This feature should only be enabled after LPDDR2 initialization is completed +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff5 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Powerdown mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQ pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQS pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +Drive and Slew controls for Clock pins of the DDR Interface +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SD1_WP_CD_SEL + + +0XF8000834 + +32 + +RW + +0x000000 + +SDIO 1 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQ pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQS pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for Clock pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1x: Enable External VREF for upper 16 bits +
    +reserved_VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Reserved. Do not modify. +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +reserved_REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +1 + + + +1 + +DDR IOB DCI Config +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialize flops in DCI system +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDR IOB DCI Config +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +DCI System Enable. Set to 1 if any IOs in DDR IO Bank use DCI Termination. DDR2, DDR3 and LPDDR2 (Silicon Revision 2.0+) configurations require this bit set to 1 +
    +reserved_VRP_TRI + +2:2 + +4 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_TRI + +3:3 + +8 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRP_OUT + +4:4 + +10 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT1 + +15:14 + +c000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update Mode. Use the values in the Calibration Table. +
    +reserved_INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_CLK + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLN + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLP + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_RST + +25:25 + +2000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7feffff + + + +823 + +DDR IOB DCI Config +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. 0: disable 1: enable +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables Pullup on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3f01 + + + +1601 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3f01 + + + +1601 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1680 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1680 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait, Input 10: NAND Flash IO Bit 7, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 12 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1680 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5, Input/Output 10: NAND Flash IO Bit 3, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 13 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1680 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1680 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1680 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1, Output 10: NAND Flash IO Bit 8, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2, Output 10: NAND Flash IO Bit 9, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110 TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3, Output 10: NAND Flash IO Bit 10, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6, Output 10: NAND Flash IO Bit 13, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3f01 + + + +1201 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +2e + +2e + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f002e + +SDIO 0 WP CD select +
    +

    +

    Register ( slcr )SD1_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD1_WP_CD_SEL + +0XF8000834 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO1_WP_SEL + +5:0 + +3f + +0 + +0 + +SDIO 1 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO1_CD_SEL + +21:16 + +3f0000 + +9 + +90000 + +SDIO 1 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD1_WP_CD_SEL@0XF8000834 + +31:0 + +3f003f + + + +90000 + +SDIO 1 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +Baud Rate Divider Register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud Rate Generator Register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control Register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode Register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +Baud Rate Divider Register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud Rate Generator Register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter 1: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: enable 1: disable, regardless of the value of RXEN +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed. +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed. +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control Register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +3ff + + + +20 + +UART Mode Register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes . If not set, then external pull up is required on HOLDb and WPn pins . Note that this bit doesn't affect the quad(4-bit) mode as Controller always drives these pins in quad mode. It is highly recommended to set this bit always(irrespective of mode of operation) while using QSPI +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This register controls which POR timer the PL will use for power-up. 0 - Use 64k timer 1 - Use 4k timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    ENET RESET

    +

    I2C RESET

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_LVL_INP_EN_0 + +3:3 + +8 + +1 + +8 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_0 + +2:2 + +4 + +1 + +4 + +Level shifter enable to drive signals from PS to PL +
    +USER_LVL_INP_EN_1 + +1:1 + +2 + +1 + +2 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_1 + +0:0 + +1 + +1 + +1 + +Level shifter enable to drive signals from PS to PL +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +Reserved. Do not modify. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +PL Reset 3 (FCLKRESETN3 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN3 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +PL Reset 2 (FCLKRESETN2 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN2 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +PL Reset 1 (FCLKRESETN1 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN1 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +PL Reset 0 (FCLKRESETN0 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN0 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    AFI2 SECURE REGISTER

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_3_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: CPU PLL 10: divided DDR PLL 11: IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +FPGA1_CLK_CTRL + + +0XF8000180 + +32 + +RW + +0x000000 + +PL Clock 1 Output control +
    + +FPGA2_CLK_CTRL + + +0XF8000190 + +32 + +RW + +0x000000 + +PL Clock 2 output control +
    + +FPGA3_CLK_CTRL + + +0XF80001A0 + +32 + +RW + +0x000000 + +PL Clock 3 output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source to generate the Rx clock: 0: MIO Rx clock, 1: EMIO Rx clock +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +7 + +700 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +701 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a03 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +5 + +500000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +500800 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )FPGA1_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA1_CLK_CTRL + +0XF8000180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA1_CLK_CTRL@0XF8000180 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 1 Output control +
    +

    +

    Register ( slcr )FPGA2_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA2_CLK_CTRL + +0XF8000190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +2 + +200000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA2_CLK_CTRL@0XF8000190 + +31:0 + +3f03f30 + + + +200500 + +PL Clock 2 output control +
    +

    +

    Register ( slcr )FPGA3_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA3_CLK_CTRL + +0XF80001A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA3_CLK_CTRL@0XF80001A0 + +31:0 + +3f03f30 + + + +100500 + +PL Clock 3 output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ration: 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +1 + +800 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec0c4d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config0 + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config1 + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 1. +
    + +PHY_Config2 + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 2. +
    + +PHY_Config3 + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 3. +
    + +phy_init_ratio0 + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio1 + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 1. +
    + +phy_init_ratio2 + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 2. +
    + +phy_init_ratio3 + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 3. +
    + +phy_rd_dqs_cfg0 + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg1 + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 1. +
    + +phy_rd_dqs_cfg2 + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 2. +
    + +phy_rd_dqs_cfg3 + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 3. +
    + +phy_wr_dqs_cfg0 + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg1 + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 1. +
    + +phy_wr_dqs_cfg2 + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 2. +
    + +phy_wr_dqs_cfg3 + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 3. +
    + +phy_we_cfg0 + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg1 + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 1. +
    + +phy_we_cfg2 + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 2. +
    + +phy_we_cfg3 + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 3. +
    + +wr_data_slv0 + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv1 + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 1. +
    + +wr_data_slv2 + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 2. +
    + +wr_data_slv3 + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 3. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port0 + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port1 + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 1. +
    + +axi_priority_wr_port2 + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 2. +
    + +axi_priority_wr_port3 + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 3. +
    + +axi_priority_rd_port0 + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port1 + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 1. +
    + +axi_priority_rd_port2 + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 2. +
    + +axi_priority_rd_port3 + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 3. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +82 + +82 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Rank configuration: 01: One Rank of DDR 11: Two Ranks of DDR Others: reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +Block read/write scheduling cycle count when Write requires changing ODT settings 00: 1 cycle 01: 2 cycles 10: 3 cycles others: reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0: schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1: schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81082 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a1 + +2840 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4285b + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +13 + +13 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d3 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +f + +3c00 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +5 + +28000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +5 + +2800000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +7282bce5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1: sdram device 0: non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: stop_clk will never be asserted. 1: enable the assertion of stop_clk to the PHY whenever a clock is not required +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2 and DDR3: Value written into the DRAM EMR2 register. LPDDR2: Value written into the DRAM MR3 register. +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2 and DDR3: Value written into the DRAM EMR3 register. LPDDR2: not used. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +b30 + +b30 + +DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2 and DDR3: Value written into the DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. LPDDR2: Value written into the DRAM MR2 register. +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40b30 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODTs must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config0 + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config0@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config1 + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config1@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 1. +
    +

    +

    Register ( slcr )PHY_Config2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config2 + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config2@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 2. +
    +

    +

    Register ( slcr )PHY_Config3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config3 + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config3@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_init_ratio0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio0 + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio0@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio1 + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio1@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 1. +
    +

    +

    Register ( slcr )phy_init_ratio2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio2 + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio2@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 2. +
    +

    +

    Register ( slcr )phy_init_ratio3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio3 + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio3@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 3. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg0 + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg0@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg1 + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg1@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg2 + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg2@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg3 + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg3@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg0 + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg0@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg1 + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg1@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg2 + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg2@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg3 + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg3@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_we_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg0 + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg0@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg1 + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg1@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 1. +
    +

    +

    Register ( slcr )phy_we_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg2 + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg2@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 2. +
    +

    +

    Register ( slcr )phy_we_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg3 + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg3@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 3. +
    +

    +

    Register ( slcr )wr_data_slv0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv0 + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv0@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv1 + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv1@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 1. +
    +

    +

    Register ( slcr )wr_data_slv2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv2 + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv2@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 2. +
    +

    +

    Register ( slcr )wr_data_slv3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv3 + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv3@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 3. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +0: (default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) 1: assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 0: Each Rank uses its own delay 1: Rank 0 delays are used for all ranks +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1: enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port0 + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port0@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port1 + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port1@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 1. +
    +

    +

    Register ( slcr )axi_priority_wr_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port2 + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port2@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 2. +
    +

    +

    Register ( slcr )axi_priority_wr_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port3 + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port3@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 3. +
    +

    +

    Register ( slcr )axi_priority_rd_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port0 + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port0@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port1 + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port1@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 1. +
    +

    +

    Register ( slcr )axi_priority_rd_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port2 + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port2@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 2. +
    +

    +

    Register ( slcr )axi_priority_rd_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port3 + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port3@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 3. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +0:All bank refresh Per bank refresh allows traffic to flow to other banks. 1:Per bank refresh Per bank refresh is not supported on all LPDDR2 devices. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Power-down mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 0 +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 1 +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDR IOB Slew for Address +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDR IOB Slew for Data +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDR IOB Slew for Diff +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDR IOB Slew for Clock +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SD1_WP_CD_SEL + + +0XF8000834 + +32 + +RW + +0x000000 + +SDIO 1 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 0 +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 1 +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDR IOB Slew for Address +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Data +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Diff +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Clock +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1X: Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors x0: Disable VREF pull-up for lower 16 bits x1: Enable VREF pull-up for lower 16 bits 0x: Disable VREF pull-up for upper 16 bits 1x: Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Enable test mode for VRP and VRN: 00: VRP/VRN test mode not used 11: VRP/VRN test mode enabled using vref based receiver. VRP/VRN control is set using the VRN_OUT, VRP_OUT, VRN_TRI, VRP_TRI fields in the DDRIOB_DCI_CTRL register +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0: no pull-up 1: enable pull-up +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. 0: disable 1: enable +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables pull-up on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3f01 + + + +1601 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3f01 + + + +1601 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1680 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1680 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait 10: NAND Flash IO Bit 7 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 12 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1680 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5 10: NAND Flash IO Bit 3 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 13 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1680 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1680 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1680 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1 10: NAND Flash IO Bit 8 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Output 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2 10: NAND Flash IO Bit 9 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110 TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3 10: NAND Flash IO Bit 10 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6 10: NAND Flash IO Bit 13 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3f01 + + + +1201 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +2e + +2e + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f002e + +SDIO 0 WP CD select +
    +

    +

    Register ( slcr )SD1_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD1_WP_CD_SEL + +0XF8000834 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO1_WP_SEL + +5:0 + +3f + +0 + +0 + +SDIO 1 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO1_CD_SEL + +21:16 + +3f0000 + +9 + +90000 + +SDIO 1 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD1_WP_CD_SEL@0XF8000834 + +31:0 + +3f003f + + + +90000 + +SDIO 1 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass 2 - 65535: baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: start break transmission, 1: stop break transmission. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: 1: start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 0: receiver timeout counter disabled, 1: receiver timeout counter is restarted. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter, 0: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter, 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: disable, 1: enable +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable, 1: enable. When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: 1: transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: 1: receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode: 0: Default UART mode 1: Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select: 0: APB clock, pclk 1: a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: 00: normal 01: automatic cho 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: 0: clock source is uart_clk 1: clock source is uart_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    ENET RESET

    +

    I2C RESET

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset: 0: No reset 1: ACP AXI interface reset output asserted +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0: No reset 1: AXDS3AXI interface reset output asserted +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0: No reset 1: AXDS2 AXI interface reset output asserted +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0: No reset 1: AXDS1 AXI interface reset output asserted +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0: No reset 1: AXDS0 AXI interface reset output asserted +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0: No reset 1: FPGA slave interface 1 reset is asserted +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0: No reset 1: FPGA slave interface 0 reset is asserted +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface: 1: soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0: No reset 1: FPGA master interface 1 reset is asserted +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0: No reset 1: FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 3 peripheral request reset output asserted +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 2 peripheral request reset output asserted +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 1 peripheral request reset output asserted +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 0 peripheral request reset output asserted +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0: No reset 1: FPGA 3 top level reset output asserted +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0: No reset 1: FPGA 2 top level reset output asserted +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0: No reset 1: FPGA 1 top level reset output asserted +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0: No reset 1: FPGA 0 top level reset output asserted +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_2_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CORTEX A9 Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status. 0 - ARM PLL out of lock. 1 - ARM PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is CPU PLL. 10 - Source for generated clock is DDR divided clock. 11 - Source for generated clock is IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CORTEX A9 Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status. 0 - DDR PLL out of lock. 1 - DDR PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Divisor value for the ddr_3xclk +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk) +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status. 0 - IO PLL out of lock. 1 - IO PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 RX Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Linear Quad-SPI Reference Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Reference Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Reference Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP 2X Clock Contol +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +FPGA 0 Output Clock Control +
    + +FPGA1_CLK_CTRL + + +0XF8000180 + +32 + +RW + +0x000000 + +FPGA 1 Output Clock Control +
    + +FPGA2_CLK_CTRL + + +0XF8000190 + +32 + +RW + +0x000000 + +FPGA 2 Output Clock Control +
    + +FPGA3_CLK_CTRL + + +0XF80001A0 + +32 + +RW + +0x000000 + +FPGA 3 Output Clock Control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +6:2:1 ratio clock, if set +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Selects the source used to generate the clock. 0 - Source for generated clock is GEM 0 MIO RX clock. 1 - Source for generated clock is GEM 0 FMIO RX clock. +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +Gigabit Ethernet MAC 0 RX Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source used to generate the clock. 1xx - Source for generated clock is Ethernet 0 FMIO clock. 00x - Source for generated clock is IO PLL. 010 - Source for generated clock is ARM PLL. 011 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +7 + +700 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +701 + +Linear Quad-SPI Reference Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO 0 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +SDIO 1 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a03 + +SDIO Reference Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Reference Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active 0 - Clock is disabled 1 - Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP 2X Clock Contol +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +5 + +500000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +500800 + +FPGA 0 Output Clock Control +
    +

    +

    Register ( slcr )FPGA1_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA1_CLK_CTRL + +0XF8000180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA1_CLK_CTRL@0XF8000180 + +31:0 + +3f03f30 + + + +400500 + +FPGA 1 Output Clock Control +
    +

    +

    Register ( slcr )FPGA2_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA2_CLK_CTRL + +0XF8000190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +2 + +200000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA2_CLK_CTRL@0XF8000190 + +31:0 + +3f03f30 + + + +200500 + +FPGA 2 Output Clock Control +
    +

    +

    Register ( slcr )FPGA3_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA3_CLK_CTRL + +0XF80001A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA3_CLK_CTRL@0XF80001A0 + +31:0 + +3f03f30 + + + +100500 + +FPGA 3 Output Clock Control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Enable the 6:2:1 mode. 1 for 6:3:2:1. 0 for 4:2:2:1. +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +6:2:1 ratio clock, if set +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet MAC 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet MAC 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +1 + +800 + +SDIO 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +LQSPI AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec0c4d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two rank configuration register +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control register +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control register +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control register +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters register 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters register 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters register 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters register 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters register 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM initialization parameters register +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access register +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access register +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM burst 8 read/write register +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ register +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM bank address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT register +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO register +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration register +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold register +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller register 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller register 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller register 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller register 4 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters register +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters register +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown register +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control register +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug register +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing register +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear register +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction register +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status register +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count register +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub register +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control register (2) +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control register (3) +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask register +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 Register +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 Register +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 Register +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 Register +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control Register +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +82 + +82 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Only present for multi-rank configurations. Each bit represents one rank. 1=populated; 0=unpopulated 01 = One Rank 11 = Two Ranks Others = Reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +00 = block read/write scheduling for 1-cycle when Write requires changing ODT settings 01 = block read/write scheduling for 2 cycles when Write requires changing ODT settings 10 = block read/write scheduling for 3 cycles when Write requires changing ODT settings 11 = Reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0 = schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1 = schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81082 + +Two rank configuration register +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of clocks that the HPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control register +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control register +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control register +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a1 + +2840 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks DRAM RELATED +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4285b + +DRAM Parameters register 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +13 + +13 + +Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. LPDDR2 mode: Set this to the larger of tCKE or tCKESR. Non-LPDDR2 designs: Set this to tCKE value. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d3 + +DRAM Parameters register 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2/3 -> WL -1 LPDDR -> 1 LPDDR2 ->WL Where WL = Write Latency of DRAM DRAM RELATED. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. non-LPDDR2 -> RL + BL/2 + 2 - WL LPDDR2 -> RL + BL/2 + RU(tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +f + +3c00 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +5 + +28000 + +tXP: Minimum time after power down exit to any operation. DRAM RELATED. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +5 + +2800000 + +Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency DRAM RELATED +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +7282bce5 + +DRAM Parameters register 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1 DRAM RELATED +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1 = sdram device 0 = non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-mobile DRAM device in use. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +1=enable the assertion of stop_clk to the PHY whenever a clock is not required by LPDDR/ LPDDR2. 0=stop_clk will never be asserted. Note: This is only present for implementations supporting LPDDR/LPDDR2 devices. +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Set to RL. Time from Read command to Read data on DRAM interface. Unit: clocks This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. RL = Read Latency of DRAM Note: This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1 = disable the pad power down feature 0 = Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters register 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1 = DDRC will use 2T timing 0 = DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1 = Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and 'ddrc_reg_mr_wr_busy' is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +Mode register address - for non-LPDDR2 modes. This register is don't care in LPDDR2 mode 00 = MR0 01 = MR1 10 = MR2 11 = MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +Mode register write data - for non-LPDDR2 modes. For LPDDR2, these 16-bits are interpreted as Writes: \'7bMR Addr[7:0], MR Data[7:0]\'7d. Reads: \'7bMR Addr[7:0], Don't Care[7:0]\'7d +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 1 = Indicates that mode register write / read operation is in progress. 0 = Indicates that the core can initiate a mode register write / read operation. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 1 = read 0 = write +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 1'b0 by default. This bit will be cleared (1'b0), whenever a Mode Register Read command is issued. This bit will be set to 1'b1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters register 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands DRAM RELATED Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM initialization parameters register +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +Non LPDDR2- Value to be loaded into DRAM EMR2 registers. For LPDDR2 - Value to Write to the MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +Non LPDDR2- Value to be loaded into DRAM EMR3 registers. Used in non-LPDDR2 designs only. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access register +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +b30 + +b30 + +Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +Non LPDDR2-Value to be loaded into DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. For LPDDR2 - Value to Write to the MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40b30 + +DRAM EMR, MR access register +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +This controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. In LPDDR and LPDDR2, Burst length of 16 is supported only in Half Bus Width mode. Every input read/write command has 4 cycles of data associated with it and that is not enough data for doing Burst Length16 in Full Bus Width mode. 0010 - Burst length of 4 0100 - Burst length of 8 1000 - Burst length of 16 (only supported for LPDDR AND LPDDR2) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM burst 8 read/write register +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Active Low signal. When asserted (0), all incoming transactions will be forced to low priority. Forcing the incoming transactions to low priority implicitly turns OFF Bypass. Otherwise, HPR is allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. This bit is intended to be switched on-the-fly +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ register +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14 Internal Base: 5 The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Selects the address bits used as DRAM bank address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Selects the address bits used as DRAM column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Selects the address bits used as DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODT's must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT register +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1 = stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO register +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration register +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable for LPDDR and LPDDR2 modes. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold register +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +When 1, disable Write Combine +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to '0', auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller register 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +1 - Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on 'urgent' input coming from AXI master. 0 - Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 1'b0. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller register 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) Only present in designs that support DDR3 and LPDDR2 devices. +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Only present in designs that support DDR3 devices +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. Only present in designs that support DDR3 devices. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller register 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller register 4 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters register +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters register +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +1 - Controller puts the DRAM into Deep Powerdown mode when the transaction store is empty. 0 - Brings Controller out of Deep Powerdown mode Present only in designs configured to support LPDDR or LPDDR2 FOR PERFORMANCE ONLY. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown register +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +1 = Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0 = Write leveling disabled. +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +1 = Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0= Read DQS gate leveling is disabled. +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +1 = Read Data Eye training mode has been enabled as part of init sequence. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control register +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1 - Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0 - Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug register +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. Non-LPDDR -> RL-1 LPDDR -> RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing register +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear register +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when a correctable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction register +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when an uncorrectable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status register +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count register +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 3'b000 (No ECC) and 3'b100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 3'b100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 - No ECC, 001 - Reserved 010 - Parity 011 - Reserved 100 - SEC/DED over 1-beat 101 - SEC/DED over multiple beats 110 - Device Correction 111 - Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +This feature is NOT supported. Only default value works. 1 - Disable ECC scrubs 0 - Enable ECC scrubs Valid only when reg_ddrc_ecc_mode = 3'b100. +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub register +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +1 = run scan test at full clock speed but with less coverage 0 = run scan test at slow clock speed but with high coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 2'b00: constant pattern (0 repeated on each DQ bit) 2'b01: low freq pattern (00001111 repeated on each DQ bit) 2'b10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +1=assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) 0=(default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0 = Select algorithm # 1'b1 = Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 1- Rank 0 delays are used for all ranks 0- Each Rank uses its own delay +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-LPDDR DRAM device in use. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1=enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control register (2) +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control register (3) +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +This register must be set based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask register +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +1=LPDDR2 DRAM device in Use. 0=non-LPDDR2 device in use Present only in designs configured to support LPDDR2. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +1:Per bank refresh 0:All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported on all LPDDR2 devices. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 Register +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. Present only in designs configured to support LPDDR2. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 Register +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 Register +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 Register +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control Register +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0 = DDRC Init 1 = Normal operation 2 = Power-down mode 3 = Self-refresh mode 4 and above = deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDRIOB Address 0 Configuartion Register +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDRIOB Address 1 Configuration Register +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDRIOB Differential Clock Configuration Register +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Address Register +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Data Register +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Differential Strobe Register +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Clcok Register +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDRIOB DDR Control Register +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Control for Pin 0 +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Control for Pin 1 +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Control for Pin 2 +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Control for Pin 3 +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Control for Pin 4 +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Control for Pin 5 +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Control for Pin 6 +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Control for Pin 8 +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Control for Pin 9 +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Control for Pin 10 +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Control for Pin 11 +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Control for Pin 12 +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Control for Pin 13 +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Control for Pin 14 +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Control for Pin 15 +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Control for Pin 16 +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Control for Pin 17 +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Control for Pin 18 +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Control for Pin 19 +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Control for Pin 20 +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Control for Pin 21 +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Control for Pin 22 +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Control for Pin 23 +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Control for Pin 24 +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Control for Pin 25 +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Control for Pin 26 +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Control for Pin 27 +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Control for Pin 40 +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Control for Pin 41 +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Control for Pin 42 +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Control for Pin 43 +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Control for Pin 44 +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Control for Pin 45 +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Control for Pin 46 +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Control for Pin 47 +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Control for Pin 48 +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Control for Pin 49 +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Control for Pin 52 +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Control for Pin 53 +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select register +
    + +SD1_WP_CD_SEL + + +0XF8000834 + +32 + +RW + +0x000000 + +SDIO 1 WP CD select register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDRIOB Address 0 Configuartion Register +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDRIOB Address 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDRIOB Differential Clock Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDRIOB Drive Slew Address Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Data Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Differential Strobe Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Clcok Register +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output 0001 - VREF = 0.6V for LPDDR2 with 1.2V IO 0010 - VREF = 0.675V for LPDDR3 1.35 V IO 0100 - VREF = 0.75V for DDR3 with 1.5V IO 1000 - VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input X0 - Disable External VREF for lower 16 bits X1 - Enable External VREF for lower 16 bits 0X - Disable External VREF for upper 16 bits 1X - Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors X0 - Disable VREF pull-up for lower 16 bits X1 - Enable VREF pull-up for lower 16 bits 0X - Disable VREF pull-up for upper 16 bits 1X - Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0 - VRP/VRN not used 1 - VRP/VRN used as refio +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +73ff + + + +260 + +DDRIOB DDR Control Register +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3f01 + + + +1601 + +MIO Control for Pin 0 +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Control for Pin 1 +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 2 +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Control for Pin 3 +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 4 +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 5 +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 6 +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 8 +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3f01 + + + +1601 + +MIO Control for Pin 9 +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 10 +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 11 +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_wait- (SRAM Wait State indicator) 2= nand, Input, smc_nand_data_in[7]- (NAND Data Bus) = nand, Output, smc_nand_data_out[7]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 12 +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[5]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[5]- (SRAM Data) 2= nand, Input, smc_nand_data_in[3]- (NAND Data Bus) = nand, Output, smc_nand_data_out[3]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 13 +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 14 +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 15 +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[4]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[1]- (SRAM Address) 2= nand, Input, smc_nand_data_in[8]- (NAND Data Bus) = nand, Output, smc_nand_data_out[8]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 16 +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[5]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[2]- (SRAM Address) 2= nand, Input, smc_nand_data_in[9]- (NAND Data Bus) = nand, Output, smc_nand_data_out[9]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 17 +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[6]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[3]- (SRAM Address) 2= nand, Input, smc_nand_data_in[10]- (NAND Data Bus) = nand, Output, smc_nand_data_out[10]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 18 +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 19 +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 20 +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[6]- (SRAM Address) 2= nand, Input, smc_nand_data_in[13]- (NAND Data Bus) = nand, Output, smc_nand_data_out[13]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 21 +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 22 +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 23 +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 24 +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 25 +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 26 +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 27 +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 40 +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 41 +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 42 +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 43 +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 44 +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 45 +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3f01 + + + +1201 + +MIO Control for Pin 46 +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Control for Pin 47 +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Control for Pin 48 +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Control for Pin 49 +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 52 +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 53 +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +2e + +2e + +SDIO0 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO0 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f002e + +SDIO 0 WP CD select register +
    +

    +

    Register ( slcr )SD1_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD1_WP_CD_SEL + +0XF8000834 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO1_WP_SEL + +5:0 + +3f + +0 + +0 + +SDIO1 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SDIO1_CD_SEL + +21:16 + +3f0000 + +9 + +90000 + +SDIO1 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SD1_WP_CD_SEL@0XF8000834 + +31:0 + +3f003f + + + +90000 + +SDIO 1 WP CD select register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value 0 = Disables baud_sample 1 = Clock divisor bypass 2 - 65535 = baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break. 1 = stop transmission of the break. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break 1 = start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter 1 = receiver timeout counter is restarted +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable. 1, the transmitter is disabled +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable. 1, the transmitter is enabled, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable. 1= receiver is enabled +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable. 1=the receiver logic is enabled, provided RXDIS field is set to 0 +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for TX data path. 1=the transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for RX data path 1=receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode 0 : Default UART mode 1 : Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select 0 : APB clock, pclk 1 : a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode 00 = normal 01 = automatic cho 10 = local loopback 11 = remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits 00 = 1 stop bit 01 = 1.5 stop bits 10 = 2 stop bits 11 = reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select. 000 = even parity 001 = odd parity 010 = forced to 0 parity (space) 011 = forced to 1 parity (mark) 1xx = no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select 11 = 6 bits 10 = 7 bits 01 / 00 = 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +clock source select 1 = clock source is uart_clk/8 0 = clock source is uart_clk +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    ENET RESET

    +

    I2C RESET

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset. 0 - No reset. 1 - ACP AXI interface reset output asserted. +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS3AXI interface reset output asserted. +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS2 AXI interface reset output asserted. +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS1 AXI interface reset output asserted. +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS0 AXI interface reset output asserted. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 1 reset is asserted. +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 0 reset is asserted. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface 1 soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0 - No reset. 1 - FPGA master interface 1 reset is asserted. +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0 - No reset. 1 - FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 3 peripheral request reset output asserted. +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 2 peripheral request reset output asserted. +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 1 peripheral request reset output asserted. +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 0 peripheral request reset output asserted. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0 - No reset. 1 - FPGA 3 top level reset output asserted. +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0 - No reset. 1 - FPGA 2 top level reset output asserted. +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0 - No reset. 1 - FPGA 1 top level reset output asserted. +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0 - No reset. 1 - FPGA 0 top level reset output asserted. +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_1_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/ps7_init.tcl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/ps7_init.tcl new file mode 100755 index 0000000..85a6f34 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/ps7_init.tcl @@ -0,0 +1,781 @@ +proc ps7_pll_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000701 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00500800 + mask_write 0XF8000180 0x03F03F30 0x00400500 + mask_write 0XF8000190 0x03F03F30 0x00200500 + mask_write 0XF80001A0 0x03F03F30 0x00100500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_3_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x0007FFFF 0x00001082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006024 0x0FFFFFC3 0x00000000 + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00000003 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x0003F03F 0x0003C008 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x00010000 0x00000000 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x00000200 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFCF 0x40000001 + mask_write 0XF800611C 0x7FFFFFCF 0x40000001 + mask_write 0XF8006120 0x7FFFFFCF 0x40000001 + mask_write 0XF8006124 0x7FFFFFCF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0x6FFFFEFE 0x00040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000703FF 0x000003FF + mask_write 0XF800620C 0x000703FF 0x000003FF + mask_write 0XF8006210 0x000703FF 0x000003FF + mask_write 0XF8006214 0x000703FF 0x000003FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF5 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000001 0x00000001 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001601 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003F01 0x00001601 + mask_write 0XF8000728 0x00003FFF 0x00001680 + mask_write 0XF800072C 0x00003FFF 0x00001680 + mask_write 0XF8000730 0x00003FFF 0x00001680 + mask_write 0XF8000734 0x00003FFF 0x00001680 + mask_write 0XF8000738 0x00003FFF 0x00001680 + mask_write 0XF800073C 0x00003FFF 0x00001680 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003F01 0x00001201 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F002E + mask_write 0XF8000834 0x003F003F 0x00090000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x000003FF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 +} +proc ps7_post_config_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_3_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000701 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00500800 + mask_write 0XF8000180 0x03F03F30 0x00400500 + mask_write 0XF8000190 0x03F03F30 0x00200500 + mask_write 0XF80001A0 0x03F03F30 0x00100500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_2_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001601 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003F01 0x00001601 + mask_write 0XF8000728 0x00003FFF 0x00001680 + mask_write 0XF800072C 0x00003FFF 0x00001680 + mask_write 0XF8000730 0x00003FFF 0x00001680 + mask_write 0XF8000734 0x00003FFF 0x00001680 + mask_write 0XF8000738 0x00003FFF 0x00001680 + mask_write 0XF800073C 0x00003FFF 0x00001680 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003F01 0x00001201 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F002E + mask_write 0XF8000834 0x003F003F 0x00090000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 +} +proc ps7_post_config_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_2_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000701 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00500800 + mask_write 0XF8000180 0x03F03F30 0x00400500 + mask_write 0XF8000190 0x03F03F30 0x00200500 + mask_write 0XF80001A0 0x03F03F30 0x00100500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_1_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x000073FF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001601 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003F01 0x00001601 + mask_write 0XF8000728 0x00003FFF 0x00001680 + mask_write 0XF800072C 0x00003FFF 0x00001680 + mask_write 0XF8000730 0x00003FFF 0x00001680 + mask_write 0XF8000734 0x00003FFF 0x00001680 + mask_write 0XF8000738 0x00003FFF 0x00001680 + mask_write 0XF800073C 0x00003FFF 0x00001680 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003F01 0x00001201 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F002E + mask_write 0XF8000834 0x003F003F 0x00090000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 +} +proc ps7_post_config_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_1_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +set PCW_SILICON_VER_1_0 "0x0" +set PCW_SILICON_VER_2_0 "0x1" +set PCW_SILICON_VER_3_0 "0x2" +set APU_FREQ 666666666 + + + +proc mask_poll { addr mask } { + set count 1 + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + while { $maskedval == 0 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + set count [ expr { $count + 1 } ] + if { $count == 100000000 } { + puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask" + break + } + } +} + + + +proc mask_delay { addr val } { + set delay [ get_number_of_cycles_for_delay $val ] + perf_reset_and_start_timer + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + while { $maskedval == 1 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + } + perf_reset_clock +} + +proc ps_version { } { + set si_ver "0x[string range [mrd 0xF8007080] end-8 end]" + set mask_sil_ver "0x[expr {$si_ver >> 28}]" + return $mask_sil_ver; +} + +proc ps7_post_config {} { + set saved_mode [configparams force-mem-accesses] + configparams force-mem-accesses 1 + + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_post_config_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_post_config_2_0 + } else { + ps7_post_config_3_0 + } + configparams force-mem-accesses $saved_mode +} + +proc ps7_debug {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_debug_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_debug_2_0 + } else { + ps7_debug_3_0 + } +} +proc ps7_init {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_mio_init_data_1_0 + ps7_pll_init_data_1_0 + ps7_clock_init_data_1_0 + ps7_ddr_init_data_1_0 + ps7_peripherals_init_data_1_0 + #puts "PCW Silicon Version : 1.0" + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_mio_init_data_2_0 + ps7_pll_init_data_2_0 + ps7_clock_init_data_2_0 + ps7_ddr_init_data_2_0 + ps7_peripherals_init_data_2_0 + #puts "PCW Silicon Version : 2.0" + } else { + ps7_mio_init_data_3_0 + ps7_pll_init_data_3_0 + ps7_clock_init_data_3_0 + ps7_ddr_init_data_3_0 + ps7_peripherals_init_data_3_0 + #puts "PCW Silicon Version : 3.0" + } +} + + +# For delay calculation using global timer + +# start timer + proc perf_start_clock { } { + + #writing SCU_GLOBAL_TIMER_CONTROL register + + mask_write 0xF8F00208 0x00000109 0x00000009 +} + +# stop timer and reset timer count regs + proc perf_reset_clock { } { + perf_disable_clock + mask_write 0xF8F00200 0xFFFFFFFF 0x00000000 + mask_write 0xF8F00204 0xFFFFFFFF 0x00000000 +} + +# Compute mask for given delay in miliseconds +proc get_number_of_cycles_for_delay { delay } { + + # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + variable APU_FREQ + return [ expr ($delay * $APU_FREQ /(2 * 1000))] +} + + +# stop timer +proc perf_disable_clock {} { + mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 +} + +proc perf_reset_and_start_timer {} { + perf_reset_clock + perf_start_clock +} + + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/ps7_init_gpl.h b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/ps7_init_gpl.h new file mode 100755 index 0000000..45a7839 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/ps7_init_gpl.h @@ -0,0 +1,131 @@ +/****************************************************************************** +* +* Copyright (C) 2010-2020 +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, see +* +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init_gpl.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + + + + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 142857132 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 25000000 +#define FPGA1_FREQ 50000000 +#define FPGA2_FREQ 100000000 +#define FPGA3_FREQ 200000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/xilinx-zynq.cc b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/xilinx-zynq.cc new file mode 100755 index 0000000..14e40f9 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/riviera/xilinx-zynq.cc @@ -0,0 +1,106 @@ +/* + * Xilinx SystemC/TLM-2.0 Zynq Wrapper. + * + * Written by Edgar E. Iglesias + * + * Copyright (c) 2016, Xilinx Inc. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#define SC_INCLUDE_DYNAMIC_PROCESSES + +#include + +#include "tlm_utils/simple_initiator_socket.h" +#include "tlm_utils/simple_target_socket.h" + +using namespace sc_core; +using namespace std; + +#include "xilinx-zynq.h" +#include + +//xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr, +// Iremoteport_tlm_sync *sync) +// : remoteport_tlm(name, -1, sk_descr, sync), +xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr) + : remoteport_tlm(name, -1, sk_descr), + rp_m_axi_gp0("rp_m_axi_gp0"), + rp_m_axi_gp1("rp_m_axi_gp1"), + rp_s_axi_gp0("rp_s_axi_gp0"), + rp_s_axi_gp1("rp_s_axi_gp1"), + rp_s_axi_hp0("rp_s_axi_hp0"), + rp_s_axi_hp1("rp_s_axi_hp1"), + rp_s_axi_hp2("rp_s_axi_hp2"), + rp_s_axi_hp3("rp_s_axi_hp3"), + rp_s_axi_acp("rp_s_axi_acp"), + rp_wires_in("wires_in", 20, 0), + rp_wires_out("wires_out", 0, 17), + rp_irq_out("irq_out", 0, 28), + pl2ps_irq("pl2ps_irq", 20), + ps2pl_irq("ps2pl_irq", 28), + ps2pl_rst("ps2pl_rst", 17) +{ + int i; + + m_axi_gp[0] = &rp_m_axi_gp0.sk; + m_axi_gp[1] = &rp_m_axi_gp1.sk; + + s_axi_gp[0] = &rp_s_axi_gp0.sk; + s_axi_gp[1] = &rp_s_axi_gp1.sk; + + s_axi_hp[0] = &rp_s_axi_hp0.sk; + s_axi_hp[1] = &rp_s_axi_hp1.sk; + s_axi_hp[2] = &rp_s_axi_hp2.sk; + s_axi_hp[3] = &rp_s_axi_hp3.sk; + s_axi_acp = &rp_s_axi_acp.sk; + + /* PL to PS Interrupt signals. */ + for (i = 0; i < 20; i++) { + rp_wires_in.wires_in[i](pl2ps_irq[i]); + } + + /* PS to PL Interrupt signals. */ + for (i = 0; i < 28; i++) { + rp_irq_out.wires_out[i](ps2pl_irq[i]); + } + + /* PS to PL resets. */ + for (i = 0; i < 17; i++) { + rp_wires_out.wires_out[i](ps2pl_rst[i]); + } + + register_dev(0, &rp_s_axi_gp0); + register_dev(1, &rp_s_axi_gp1); + + register_dev(2, &rp_s_axi_hp0); + register_dev(3, &rp_s_axi_hp1); + register_dev(4, &rp_s_axi_hp2); + register_dev(5, &rp_s_axi_hp3); + + register_dev(6, &rp_s_axi_acp); + + register_dev(7, &rp_m_axi_gp0); + register_dev(8, &rp_m_axi_gp1); + register_dev(9, &rp_wires_in); + register_dev(10, &rp_wires_out); + register_dev(11, &rp_irq_out); +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/Makefile b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/Makefile new file mode 100755 index 0000000..33394b3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/Makefile @@ -0,0 +1,26 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +INCLUDEFILES=*.h +LIBSOURCES=*.c +OUTS = *.o + +libs: + echo "Compiling SPI_Con..." + $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} + make clean + +include: + ${CP} $(INCLUDEFILES) $(INCLUDEDIR) + +clean: + rm -rf ${OUTS} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/NewExtInst_TOP.bda b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/NewExtInst_TOP.bda new file mode 100755 index 0000000..ab7b1f9 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/NewExtInst_TOP.bda @@ -0,0 +1,272 @@ +{ + "graphjs": { + "version": "1.0", + "keys": [ + { + "abrv": "VH", + "name": "vert_hid", + "type": "int", + "for": "node" + }, + { + "abrv": "VM", + "name": "vert_name", + "type": "string", + "for": "node" + }, + { + "abrv": "VT", + "name": "vert_type", + "type": "string", + "for": "node" + }, + { + "abrv": "BA", + "name": "base_addr", + "type": "string", + "for": "node" + }, + { + "abrv": "HA", + "name": "high_addr", + "type": "string", + "for": "node" + }, + { + "abrv": "BP", + "name": "base_param", + "type": "string", + "for": "node" + }, + { + "abrv": "HP", + "name": "high_param", + "type": "string", + "for": "node" + }, + { + "abrv": "MA", + "name": "master_addrspace", + "type": "string", + "for": "node" + }, + { + "abrv": "MX", + "name": "master_instance", + "type": "string", + "for": "node" + }, + { + "abrv": "MI", + "name": "master_interface", + "type": "string", + "for": "node" + }, + { + "abrv": "MS", + "name": "master_segment", + "type": "string", + "for": "node" + }, + { + "abrv": "MV", + "name": "master_vlnv", + "type": "string", + "for": "node" + }, + { + "abrv": "SX", + "name": "slave_instance", + "type": "string", + "for": "node" + }, + { + "abrv": "SI", + "name": "slave_interface", + "type": "string", + "for": "node" + }, + { + "abrv": "MM", + "name": "slave_memmap", + "type": "string", + "for": "node" + }, + { + "abrv": "SS", + "name": "slave_segment", + "type": "string", + "for": "node" + }, + { + "abrv": "SV", + "name": "slave_vlnv", + "type": "string", + "for": "node" + }, + { + "abrv": "TM", + "name": "memory_type", + "type": "string", + "for": "node" + }, + { + "abrv": "TU", + "name": "usage_type", + "type": "string", + "for": "node" + }, + { + "abrv": "LT", + "name": "lock_type", + "type": "string", + "for": "node" + }, + { + "abrv": "BT", + "name": "boot_type", + "type": "string", + "for": "node" + }, + { + "abrv": "EH", + "name": "edge_hid", + "type": "int", + "for": "edge" + } + ], + "vertice_type_order": [ + { + "abrv": "BC", + "desc": "Block Container" + }, + { + "abrv": "PR", + "desc": "Parital Reference" + }, + { + "abrv": "VR", + "desc": "Variant" + }, + { + "abrv": "PM", + "desc": "Variant Permutations" + }, + { + "abrv": "CX", + "desc": "Boundary Connection" + }, + { + "abrv": "AC", + "desc": "Assignment Coordinate" + }, + { + "abrv": "ACE", + "desc": "Excluded Assign Coordinate" + }, + { + "abrv": "APX", + "desc": "Boundary Aperture" + }, + { + "abrv": "CIP", + "desc": "High level Processing System" + } + ], + "vertices": { + "V0": { + "VM": "NewExtInst_TOP", + "VT": "BC" + }, + "V1": { + "VH": "2", + "VM": "NewExtInst_TOP", + "VT": "VR" + }, + "V2": { + "VH": "2", + "VT": "PM", + "TU": "active" + }, + "V3": { + "VT": "AC", + "BA": "0x43C00000", + "HA": "0x43C0FFFF", + "BP": "C_S00_AXI_BASEADDR", + "HP": "C_S00_AXI_HIGHADDR", + "MA": "Data", + "MX": "/processing_system7_0", + "MI": "M_AXI_GP0", + "MS": "SEG_SPI_Con_0_S00_AXI_reg", + "MV": "xilinx.com:ip:processing_system7:5.5", + "SX": "/SPI_Con_0", + "SI": "S00_AXI", + "SS": "S00_AXI_reg", + "SV": "xilinx.com:user:SPI_Con:1.0", + "TM": "both", + "TU": "register" + }, + "V4": { + "VT": "AC", + "BA": "0x43C10000", + "HA": "0x43C1FFFF", + "BP": "C_S00_AXI_BASEADDR", + "HP": "C_S00_AXI_HIGHADDR", + "MA": "Data", + "MX": "/processing_system7_0", + "MI": "M_AXI_GP0", + "MS": "SEG_SPI_Con_1_S00_AXI_reg", + "MV": "xilinx.com:ip:processing_system7:5.5", + "SX": "/SPI_Con_1", + "SI": "S00_AXI", + "SS": "S00_AXI_reg", + "SV": "xilinx.com:user:SPI_Con:1.0", + "TM": "both", + "TU": "register" + }, + "V5": { + "VT": "AC", + "BA": "0x43C20000", + "HA": "0x43C2FFFF", + "BP": "C_S00_AXI_BASEADDR", + "HP": "C_S00_AXI_HIGHADDR", + "MA": "Data", + "MX": "/processing_system7_0", + "MI": "M_AXI_GP0", + "MS": "SEG_SPI_Con_2_S00_AXI_reg", + "MV": "xilinx.com:ip:processing_system7:5.5", + "SX": "/SPI_Con_2", + "SI": "S00_AXI", + "SS": "S00_AXI_reg", + "SV": "xilinx.com:user:SPI_Con:1.0", + "TM": "both", + "TU": "register" + } + }, + "edges": [ + { + "src": "V0", + "trg": "V1" + }, + { + "src": "V1", + "trg": "V2" + }, + { + "src": "V3", + "trg": "V2", + "EH": "2" + }, + { + "src": "V4", + "trg": "V2", + "EH": "2" + }, + { + "src": "V5", + "trg": "V2", + "EH": "2" + } + ] + } +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/NewExtInst_TOP.sh b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/NewExtInst_TOP.sh new file mode 100755 index 0000000..c12ab34 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/NewExtInst_TOP.sh @@ -0,0 +1,436 @@ +#!/usr/bin/env bash +#********************************************************************************************************** +# Vivado (TM) v2023.2 (64-bit) +# +# Script generated by Vivado on Fri May 15 15:32:22 CST 2026 +# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 +# +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# +# Filename : NewExtInst_TOP.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script generated by export_simulation Tcl command +# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the +# design. The script will copy the library mapping file from the compiled library directory, +# create design library directories and library mappings in the mapping file. +# +# Usage : NewExtInst_TOP.sh +# NewExtInst_TOP.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]* +# NewExtInst_TOP.sh [-reset_run] +# NewExtInst_TOP.sh [-reset_log] +# NewExtInst_TOP.sh [-help] +# +# * The -noclean_files switch is deprecated and will not peform any function (by default, the +# simulator generated files will not be removed unless -reset_run switch is used) +# +# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library +# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help' +# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path +# switch with the directory path where the library is created while generating the script +# with export_simulation. +# +# Alternatively, you can set the library path by setting the following project property:- +# +# set_property compxlib._compiled_library_dir [current_project] +# +# You can also point to the simulation library by either setting the 'lib_map_path' global +# variable in this script or specify it with the '-lib_map_path' switch while executing this +# script (type 'NewExtInst_TOP.sh -help' for more information). +# +# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the +# generated script, but if design is targetted for system simulation containing SystemC/C++/C +# sources, then the library path MUST be specified upfront when calling export_simulation. +# +# For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************** + +# catch pipeline exit status +set -Eeuo pipefail + +# set vhdlan compile options +vhdlan_opts="-full64 -l .tmp_log" + +# set vlogan compile options +vlogan_opts="-full64 -l .tmp_log" + +# set vcs elaboration options +vcs_elab_opts="-full64 -debug_acc+pp+dmptf -t ps -licqueue -l elaborate.log" + +# set vcs simulation options +vcs_sim_opts="-ucli -licqueue -l simulate.log " + +# set design libraries +design_libs=(xilinx_vip xpm axi_infrastructure_v1_1_0 axi_vip_v1_1_15 processing_system7_vip_v1_0_17 xil_defaultlib lib_cdc_v1_0_2 proc_sys_reset_v5_0_14 generic_baseblocks_v2_1_1 axi_register_slice_v2_1_29 fifo_generator_v13_2_9 axi_data_fifo_v2_1_28 axi_crossbar_v2_1_30 axi_protocol_converter_v2_1_29) + +# simulation root library directory +sim_lib_dir="vcs_lib" + +# script info +echo -e "NewExtInst_TOP.sh - Script generated by export_simulation (Vivado v2023.2 (64-bit)-id)\n" + +# main steps +run() +{ + check_args $* + setup + if [[ ($b_step == 1) ]]; then + case $step in + "compile" ) + init_lib + compile + ;; + "elaborate" ) + elaborate + ;; + "simulate" ) + simulate + ;; + * ) + echo -e "ERROR: Invalid or missing step '$step' (type \"./NewExtInst_TOP.sh -help\" for more information)\n" + exit 1 + esac + else + init_lib + compile + elaborate + simulate + fi +} + +# RUN_STEP: +compile() +{ + vlogan -work xilinx_vip $vlogan_opts -sverilog +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + 2>&1 | tee compile.log; cat .tmp_log > vlogan.log 2>/dev/null + + vlogan -work xpm $vlogan_opts -sverilog +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "/data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null + + vhdlan -work xpm $vhdlan_opts \ + "/data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a compile.log; cat .tmp_log > vhdlan.log 2>/dev/null + + vlogan -work axi_infrastructure_v1_1_0 $vlogan_opts +v2k +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null + + vlogan -work axi_vip_v1_1_15 $vlogan_opts -sverilog +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/5753/hdl/axi_vip_v1_1_vl_rfs.sv" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null + + vlogan -work processing_system7_vip_v1_0_17 $vlogan_opts -sverilog +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl/processing_system7_vip_v1_0_vl_rfs.sv" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/sim/NewExtInst_TOP_processing_system7_0_0.v" \ + "../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_clk_wiz.v" \ + "../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.v" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null + + vhdlan -work lib_cdc_v1_0_2 $vhdlan_opts \ + "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> vhdlan.log 2>/dev/null + + vhdlan -work proc_sys_reset_v5_0_14 $vhdlan_opts \ + "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> vhdlan.log 2>/dev/null + + vhdlan -work xil_defaultlib $vhdlan_opts \ + "../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/sim/NewExtInst_TOP_proc_sys_reset_0_0.vhd" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> vhdlan.log 2>/dev/null + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "../../../bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v" \ + "../../../bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v" \ + "../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/sim/NewExtInst_TOP_SPI_Con_0_0.v" \ + "../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/sim/NewExtInst_TOP_SPI_Con_0_1.v" \ + "../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/sim/NewExtInst_TOP_SPI_Con_0_2.v" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null + + vlogan -work generic_baseblocks_v2_1_1 $vlogan_opts +v2k +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null + + vlogan -work axi_register_slice_v2_1_29 $vlogan_opts +v2k +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null + + vlogan -work fifo_generator_v13_2_9 $vlogan_opts +v2k +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ac72/simulation/fifo_generator_vlog_beh.v" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null + + vhdlan -work fifo_generator_v13_2_9 $vhdlan_opts \ + "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.vhd" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> vhdlan.log 2>/dev/null + + vlogan -work fifo_generator_v13_2_9 $vlogan_opts +v2k +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.v" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null + + vlogan -work axi_data_fifo_v2_1_28 $vlogan_opts +v2k +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null + + vlogan -work axi_crossbar_v2_1_30 $vlogan_opts +v2k +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/sim/NewExtInst_TOP_xbar_0.v" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null + + vhdlan -work xil_defaultlib $vhdlan_opts \ + "../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/sim/NewExtInst_TOP_rst_clk_wiz_0_100M_0.vhd" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> vhdlan.log 2>/dev/null + + vlogan -work axi_protocol_converter_v2_1_29 $vlogan_opts +v2k +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_auto_pc_0/sim/NewExtInst_TOP_auto_pc_0.v" \ + "../../../bd/NewExtInst_TOP/sim/NewExtInst_TOP.v" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.NewExtInst_TOP xil_defaultlib.glbl -o NewExtInst_TOP_simv +} + +# RUN_STEP: +simulate() +{ + ./NewExtInst_TOP_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + # delete previous files for a clean rerun + if [[ ($b_reset_run == 1) ]]; then + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + fi + + # delete previous log files + if [[ ($b_reset_log == 1) ]]; then + reset_log + echo -e "INFO: Simulation run log files deleted.\n" + exit 0 + fi + + # add any setup/initialization commands here:- + + # + +} + +# simulator index file/library directory processing +init_lib() +{ + if [[ ($b_keep_index == 1) ]]; then + # keep previous design library mappings + true + else + # define design library mappings + create_lib_mappings + fi + + if [[ ($b_keep_index == 1) ]]; then + # do not recreate design library directories + true + else + # create design library directories + create_lib_dir + fi +} + +# define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($lib_map_path == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($lib_map_path == "") ]]; then + lib_map_path="/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/compile_simlib/vcs" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# create design library directory +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key NewExtInst_TOP_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .tmp_log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log lib_sc.so 64 AN.DB csrc NewExtInst_TOP_simv.daidir vcs_lib c.obj) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# delete generated log files from the previous run +reset_log() +{ + files_to_remove=(vlogan.log vhdlan.log compile.log elaborate.log simulate.log .tmp_log) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# check switch argument value +check_arg_value() +{ + if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "elaborate") && ($2 != "simulate")) ]];then + echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then + echo -e "ERROR: Simulation library directory path not specified (type \"./NewExtInst_TOP.sh -help\" for more information)\n" + exit 1 + fi +} + +# check command line arguments +check_args() +{ + arg_count=$# + if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then + usage + fi + while [[ "$#" -gt 0 ]]; do + case $1 in + -step) check_arg_value $1 $2;step=$2; b_step=1; shift;; + -lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;; + -gen_bypass) b_gen_bypass=1 ;; + -reset_run) b_reset_run=1 ;; + -reset_log) b_reset_log=1 ;; + -keep_index) b_keep_index=1 ;; + -noclean_files) b_noclean_files=1 ;; + -help|-h) ;; + *) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;; + esac + shift + done + + # -reset_run is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then + echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -reset_log is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then + echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -keep_index is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then + echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -noclean_files is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then + echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi +} + +# script usage +usage() +{ + msg="Usage: NewExtInst_TOP.sh [-help]\n\ +Usage: NewExtInst_TOP.sh [-step]\n\ +Usage: NewExtInst_TOP.sh [-lib_map_path]\n\ +Usage: NewExtInst_TOP.sh [-reset_run]\n\ +Usage: NewExtInst_TOP.sh [-reset_log]\n\ +Usage: NewExtInst_TOP.sh [-keep_index]\n\ +Usage: NewExtInst_TOP.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-step ] -- Execute specified step (compile, elaborate, simulate)\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\ +file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\ +NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\ +NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\ +[-reset_log] -- Delete simulator generated log files from the previous run\n\n\ +[-keep_index] -- Keep simulator index file settings from the previous run\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n" + echo -e $msg + exit 0 +} + +# initialize globals +step="" +lib_map_path="" +b_step=0 +b_lib_map_path=0 +b_gen_bypass=0 +b_reset_run=0 +b_reset_log=0 +b_keep_index=0 +b_noclean_files=0 + +# launch script +run $* diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/README.txt b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/README.txt new file mode 100644 index 0000000..1d27b8b --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/README.txt @@ -0,0 +1,50 @@ +################################################################################ +# Vivado (TM) v2023.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and how to fetch design source file details +# from the file_info.txt file. +# +# Generated by export_simulation on Fri May 15 15:32:22 CST 2026 +# +################################################################################ + +1. Steps to run the generated simulation script + +From the shell prompt in the current directory, issue the following command:- + +./NewExtInst_TOP.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first calls the 'check_args' function, the purpose of which +is to verify the generated script arguments and print error if incorrect switch +is specified. The 'run' function then calls the 'setup' function, the purpose of +which is to specify custom or initialization commands. The function also executes +following sub-functions:- +'reset_run' if -reset_run switch is specified. +'reset_log' if -reset_log switch is specified. + +The purpose of 'reset_run' function' is to delete the simulator generated design +data from the previous run and the purpose of 'reset_log' function' is to delete +the simulator generated log files. + +The 'run' function then calls the 'init_lib' function, the purpose of which is to +create design library mappings and directories. This function is called before the +'compile' step. By default, if '-step' switch is specified with the script then the +script will execute that specfic step, else it will execute all steps applicable +for the target simulator. + +For more information on the script, please type './NewExtInst_TOP.sh -help' + +2. Design source file information + +export_simulation generates a 'file_info.txt' file that contains design file information +based on the compile order when export_simulation was executed from Vivado. The file +contains information about the file name, type, library it is compiled into, whether +it is part of the IP, associated library, file path information in a comma separated +format. This file can be parsed to extract the required information for generating a +custom script or can be read from verification test infra. + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/SPI_Con.h b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/SPI_Con.h new file mode 100755 index 0000000..5278bdd --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/SPI_Con.h @@ -0,0 +1,107 @@ + +#ifndef SPI_CON_H +#define SPI_CON_H + + +/****************** Include Files ********************/ +#include "xil_types.h" +#include "xstatus.h" + +#define SPI_CON_S00_AXI_SLV_REG0_OFFSET 0 +#define SPI_CON_S00_AXI_SLV_REG1_OFFSET 4 +#define SPI_CON_S00_AXI_SLV_REG2_OFFSET 8 +#define SPI_CON_S00_AXI_SLV_REG3_OFFSET 12 +#define SPI_CON_S00_AXI_SLV_REG4_OFFSET 16 +#define SPI_CON_S00_AXI_SLV_REG5_OFFSET 20 +#define SPI_CON_S00_AXI_SLV_REG6_OFFSET 24 +#define SPI_CON_S00_AXI_SLV_REG7_OFFSET 28 +#define SPI_CON_S00_AXI_SLV_REG8_OFFSET 32 +#define SPI_CON_S00_AXI_SLV_REG9_OFFSET 36 +#define SPI_CON_S00_AXI_SLV_REG10_OFFSET 40 +#define SPI_CON_S00_AXI_SLV_REG11_OFFSET 44 +#define SPI_CON_S00_AXI_SLV_REG12_OFFSET 48 +#define SPI_CON_S00_AXI_SLV_REG13_OFFSET 52 +#define SPI_CON_S00_AXI_SLV_REG14_OFFSET 56 +#define SPI_CON_S00_AXI_SLV_REG15_OFFSET 60 +#define SPI_CON_S00_AXI_SLV_REG16_OFFSET 64 +#define SPI_CON_S00_AXI_SLV_REG17_OFFSET 68 +#define SPI_CON_S00_AXI_SLV_REG18_OFFSET 72 +#define SPI_CON_S00_AXI_SLV_REG19_OFFSET 76 +#define SPI_CON_S00_AXI_SLV_REG20_OFFSET 80 +#define SPI_CON_S00_AXI_SLV_REG21_OFFSET 84 +#define SPI_CON_S00_AXI_SLV_REG22_OFFSET 88 +#define SPI_CON_S00_AXI_SLV_REG23_OFFSET 92 +#define SPI_CON_S00_AXI_SLV_REG24_OFFSET 96 +#define SPI_CON_S00_AXI_SLV_REG25_OFFSET 100 +#define SPI_CON_S00_AXI_SLV_REG26_OFFSET 104 +#define SPI_CON_S00_AXI_SLV_REG27_OFFSET 108 +#define SPI_CON_S00_AXI_SLV_REG28_OFFSET 112 +#define SPI_CON_S00_AXI_SLV_REG29_OFFSET 116 +#define SPI_CON_S00_AXI_SLV_REG30_OFFSET 120 +#define SPI_CON_S00_AXI_SLV_REG31_OFFSET 124 + + +/**************************** Type Definitions *****************************/ +/** + * + * Write a value to a SPI_CON register. A 32 bit write is performed. + * If the component is implemented in a smaller width, only the least + * significant data is written. + * + * @param BaseAddress is the base address of the SPI_CONdevice. + * @param RegOffset is the register offset from the base to write to. + * @param Data is the data written to the register. + * + * @return None. + * + * @note + * C-style signature: + * void SPI_CON_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data) + * + */ +#define SPI_CON_mWriteReg(BaseAddress, RegOffset, Data) \ + Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data)) + +/** + * + * Read a value from a SPI_CON register. A 32 bit read is performed. + * If the component is implemented in a smaller width, only the least + * significant data is read from the register. The most significant data + * will be read as 0. + * + * @param BaseAddress is the base address of the SPI_CON device. + * @param RegOffset is the register offset from the base to write to. + * + * @return Data is the data from the register. + * + * @note + * C-style signature: + * u32 SPI_CON_mReadReg(u32 BaseAddress, unsigned RegOffset) + * + */ +#define SPI_CON_mReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (RegOffset)) + +/************************** Function Prototypes ****************************/ +/** + * + * Run a self-test on the driver/device. Note this may be a destructive test if + * resets of the device are performed. + * + * If the hardware system is not built correctly, this function may never + * return to the caller. + * + * @param baseaddr_p is the base address of the SPI_CON instance to be worked on. + * + * @return + * + * - XST_SUCCESS if all self-test code passed + * - XST_FAILURE if any self-test code failed + * + * @note Caching must be turned off for this function to work. + * @note Self test may fail if data memory and device are not on the same bus. + * + */ +XStatus SPI_CON_Reg_SelfTest(void * baseaddr_p); + +#endif // SPI_CON_H diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/SPI_Con.mdd b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/SPI_Con.mdd new file mode 100755 index 0000000..4bd813f --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/SPI_Con.mdd @@ -0,0 +1,10 @@ + + +OPTION psf_version = 2.1; + +BEGIN DRIVER SPI_Con + OPTION supported_peripherals = (SPI_Con); + OPTION copyfiles = all; + OPTION VERSION = 1.0; + OPTION NAME = SPI_Con; +END DRIVER diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/SPI_Con.tcl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/SPI_Con.tcl new file mode 100755 index 0000000..7f913c9 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/SPI_Con.tcl @@ -0,0 +1,5 @@ + + +proc generate {drv_handle} { + xdefine_include_file $drv_handle "xparameters.h" "SPI_Con" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR" +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/file_info.txt b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/file_info.txt new file mode 100644 index 0000000..7320d80 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/file_info.txt @@ -0,0 +1,39 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" 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+axi_register_slice_v2_1_vl_rfs.v,verilog,axi_register_slice_v2_1_29,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_9,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ac72/simulation/fifo_generator_vlog_beh.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_9,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.vhd,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_9,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi_data_fifo_v2_1_vl_rfs.v,verilog,axi_data_fifo_v2_1_28,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi_crossbar_v2_1_vl_rfs.v,verilog,axi_crossbar_v2_1_30,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +NewExtInst_TOP_xbar_0.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/sim/NewExtInst_TOP_xbar_0.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +NewExtInst_TOP_rst_clk_wiz_0_100M_0.vhd,vhdl,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/sim/NewExtInst_TOP_rst_clk_wiz_0_100M_0.vhd,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi_protocol_converter_v2_1_vl_rfs.v,verilog,axi_protocol_converter_v2_1_29,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +NewExtInst_TOP_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_auto_pc_0/sim/NewExtInst_TOP_auto_pc_0.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +NewExtInst_TOP.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/sim/NewExtInst_TOP.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/glbl.v b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/libps7.dll b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/libps7.dll new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/libps7.dll @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/libps7.so b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/libps7.so new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/libps7.so @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/libremoteport.dll b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/libremoteport.dll new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/libremoteport.dll @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/libremoteport.so b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/libremoteport.so new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/libremoteport.so @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/ps7_init.h b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/ps7_init.h new file mode 100755 index 0000000..224d7ea --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/ps7_init.h @@ -0,0 +1,117 @@ +/****************************************************************************** +* +* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + + + + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 142857132 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 25000000 +#define FPGA1_FREQ 50000000 +#define FPGA2_FREQ 100000000 +#define FPGA3_FREQ 200000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/ps7_init.html b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/ps7_init.html new file mode 100755 index 0000000..9ca53bd --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/ps7_init.html @@ -0,0 +1,125613 @@ + + + + +Zynq PS configuration detail + + + +

    +
    + +
  • +
    Zynq PS Register Summary Viewer +
    +
    • +     +
    +
    +
    + +
    Zynq PS7 Summary Report +
    +     +
    User Configurations +
    +
    + +
    MIO Configurations +
    +     +
    + +
    CLK Configurations +
    +     +
    + +
    DDR Configurations +
    +     +
    + +
    SMC Configurations +
    +     +
    +
    +
    Select Version: + +
    +
    +
    Zynq Register View +
    +
    + +
    MIO Registers +
    +     + +
    PLL Registers +
    +     + +
    Clock Registers +
    +     + +
    DDR Registers +
    +     + +
    Peripherals Registers +
    +     +
    +
    This design is targeted for xc7z035 board (part number: xc7z035ffg676-2) + +
    +

    Zynq Design Summary

    + + + + + + + + + + + + + + + + + + + + + +
    +Device + +xc7z035 +
    +SpeedGrade + +-2 +
    +Part + +xc7z035ffg676-2 +
    +Description + +Zynq PS Configuration Report with register details +
    +Vendor + +Xilinx +
    +

    MIO Table View

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +MIO Pin + +Peripheral + +Signal + +IO Type + +Speed + +Pullup + +Direction +
    +MIO 0 + +SD 1 + +wp + +LVCMOS 3.3V + +slow + +enabled + +in +
    +MIO 1 + +Quad SPI Flash + +qspi0_ss_b + +LVCMOS 3.3V + +slow + +enabled + +out +
    +MIO 2 + +Quad SPI Flash + +qspi0_io[0] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 3 + +Quad SPI Flash + +qspi0_io[1] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 4 + +Quad SPI Flash + +qspi0_io[2] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 5 + +Quad SPI Flash + +qspi0_io[3]/HOLD_B + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 6 + +Quad SPI Flash + +qspi0_sclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 7 + + + + + + + + + + + + +
    +MIO 8 + +Quad SPI Flash + +qspi_fbclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 9 + +SD 1 + +cd + +LVCMOS 3.3V + +slow + +enabled + +in +
    +MIO 10 + +SD 1 + +data[0] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 11 + +SD 1 + +cmd + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 12 + +SD 1 + +clk + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 13 + +SD 1 + +data[1] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 14 + +SD 1 + +data[2] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 15 + +SD 1 + +data[3] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 16 + +Enet 0 + +tx_clk + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 17 + +Enet 0 + +txd[0] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 18 + +Enet 0 + +txd[1] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 19 + +Enet 0 + +txd[2] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 20 + +Enet 0 + +txd[3] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 21 + +Enet 0 + +tx_ctl + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 22 + +Enet 0 + +rx_clk + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 23 + +Enet 0 + +rxd[0] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 24 + +Enet 0 + +rxd[1] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 25 + +Enet 0 + +rxd[2] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 26 + +Enet 0 + +rxd[3] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 27 + +Enet 0 + +rx_ctl + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 28 + + + + + + + + + + + + +
    +MIO 29 + + + + + + + + + + + + +
    +MIO 30 + + + + + + + + + + + + +
    +MIO 31 + + + + + + + + + + + + +
    +MIO 32 + + + + + + + + + + + + +
    +MIO 33 + + + + + + + + + + + + +
    +MIO 34 + + + + + + + + + + + + +
    +MIO 35 + + + + + + + + + + + + +
    +MIO 36 + + + + + + + + + + + + +
    +MIO 37 + + + + + + + + + + + + +
    +MIO 38 + + + + + + + + + + + + +
    +MIO 39 + + + + + + + + + + + + +
    +MIO 40 + +SD 0 + +clk + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 41 + +SD 0 + +cmd + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 42 + +SD 0 + +data[0] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 43 + +SD 0 + +data[1] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 44 + +SD 0 + +data[2] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 45 + +SD 0 + +data[3] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 46 + +SD 0 + +wp + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 47 + +SD 0 + +cd + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 48 + +UART 1 + +tx + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 49 + +UART 1 + +rx + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 50 + + + + + + + + + + + + +
    +MIO 51 + + + + + + + + + + + + +
    +MIO 52 + +Enet 0 + +mdc + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 53 + +Enet 0 + +mdio + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +

    DDR Memory information

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Parameter name + +Value + +Description +
    +Enable DDR + +1 + +Enable DDR Controller of Zynq PS +
    +Memory Part + +MT41J256M16 RE-125 + + +
    +DRAM bus width + +32 Bit + +Select the desired data width. Refer to the Thechnical Reference Manual(TRM) for a detailed list of supported DDR data widths +
    +ECC + +Disabled + +ECC is supported only for data width of 16-bit +
    +BURST Length (lppdr only) + +8 + +Select the burst Length. It refers to the amount of data read/written after a read/write command is presented to the controller +
    +Internal Vref + +0 + + +
    +Operating Frequency (MHz) + +533.333333 + +Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade +
    +HIGH temperature + +Normal (0-85) + +Select the operating temparature +
    +DRAM IC bus width + +16 Bits + +Provide the width of the DRAM chip +
    +DRAM Device Capacity + +4096 MBits + + +
    +Speed Bin + +DDR3_1066F + +Provide the Speed Bin +
    +BANK Address Count + +3 + +Defines the bank to which an active an ACTIVE, READ, WRITE, or Precharge Command is being applied +
    +ROW Address Count + +15 + +Provide the Row address for ACTIVE commands +
    +COLUMN Address Count + +10 + +Provide the Row address for READ/WRITE commands +
    +CAS Latency + +7 + +Select the Column Access Strobe (CAS) Latency. It refers to the amount of time it takes for data to appear on the pins of the memory module +
    +CAS Write Latency + +6 + +Select the CAS Write Latency +
    +RAS to CAS Delay + +7 + +Provide the row address to column address delay time. tRCD is t he time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS) +
    +RECHARGE Time + +7 + +Precharge Time (tRP) is the number of clock cycles needed o terminate acces s to an open row of memory, and open access to the next row +
    +tRC (ns ) + +48.91 + +Provide the Row cycle time tRC (ns) +
    +tRASmin ( ns ) + +35.0 + +tRASmin (ns) is the minimum number of clock cycles required between an Active command and issuing the Precharge command +
    +tFAW + +40.0 + +It restricts the number of activates that can be done within a certain window of time +
    +ADDITIVE Latency + +0 + +Provide the Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths +
    +Write levelling + +1 + + +
    +Read gate + +1 + + +
    +Read gate + +1 + + +
    +DQS to Clock delay [0] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [1] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [2] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [3] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +Board delay [0] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [1] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [2] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [3] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +

    PS Clocks information

    +

    PS Reference Clock : 33.333333

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Peripheral + +PLL source + +Frequency (MHz) +
    +CPU 6x Freq (MHz) + +ARM PLL + +666.666687 +
    +QSPI Flash Freq (MHz) + +IO PLL + +142.857132 +
    +ENET0 Freq (MHz) + +IO PLL + +125.000000 +
    +SDIO Freq (MHz) + +IO PLL + +100.000000 +
    +SDIO Freq (MHz) + +IO PLL + +100.000000 +
    +UART Freq (MHz) + +IO PLL + +100.000000 +
    +FPGA0 Freq (MHz) + +IO PLL + +25.000000 +
    +FPGA1 Freq (MHz) + +IO PLL + +50.000000 +
    +FPGA2 Freq (MHz) + +IO PLL + +100.000000 +
    +FPGA3 Freq (MHz) + +IO PLL + +200.000000 +
    +

    ps7_pll_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: ARM PLL 10: DDR PLL 11: IO PLL This field is reset by POR only. +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for programming the PLL. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock and Rx Signals Select +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +FPGA1_CLK_CTRL + + +0XF8000180 + +32 + +RW + +0x000000 + +PL Clock 1 Output control +
    + +FPGA2_CLK_CTRL + + +0XF8000190 + +32 + +RW + +0x000000 + +PL Clock 2 output control +
    + +FPGA3_CLK_CTRL + + +0XF80001A0 + +32 + +RW + +0x000000 + +PL Clock 3 output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source of the Rx clock, control and data signals: 0: MIO 1: EMIO +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock and Rx Signals Select +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +7 + +700 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +701 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a03 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +5 + +500000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +500800 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )FPGA1_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA1_CLK_CTRL + +0XF8000180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA1_CLK_CTRL@0XF8000180 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 1 Output control +
    +

    +

    Register ( slcr )FPGA2_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA2_CLK_CTRL + +0XF8000190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +2 + +200000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA2_CLK_CTRL@0XF8000190 + +31:0 + +3f03f30 + + + +200500 + +PL Clock 2 output control +
    +

    +

    Register ( slcr )FPGA3_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA3_CLK_CTRL + +0XF80001A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA3_CLK_CTRL@0XF80001A0 + +31:0 + +3f03f30 + + + +100500 + +PL Clock 3 output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ratio: (When this register changes, no access are allowed to OCM.) 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +1 + +800 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec0c4d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +82 + +82 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reserved_reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Reserved. Do not modify. +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +Two_rank_cfg@0XF8006004 + +31:0 + +7ffff + + + +1082 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a1 + +2840 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4285b + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +13 + +13 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d3 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. In non-LPDDR mode, the minimum DRAM Write Latency (DDR2) supported is 3. In LPDDR mode, the required DRAM Write Latency of 1 is supported. Since write latency (CWL) min is 3, and DDR2 CWL is CL-1, the min (DDR2) CL supported is 4 +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +f + +3c00 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +5 + +28000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +5 + +2800000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +7282bce5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_en_dfi_dram_clk_disable + +23:23 + +800000 + +0 + +0 + +Enables the assertion of ddrc_dfi_dram_clk_disable. In DDR2/DDR3, only asserted in Self Refresh. In mDDR/LPDDR2, can be asserted in following: - during normal operation (Clock Stop), - in Power Down - in Self Refresh - In Deep Power Down +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +7fdffffc + + + +270872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffc3 + + + +0 + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2: Value loaded into EMR2 register DDR3: Value loaded into MR2 register LPDDR2: Value loaded into MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2: Value loaded into EMR3 register DDR3: Value loaded into MR3 register. Set Bit[2:0] to 3'b000. These bits are set appropriately by the Controller during Read Data eye training and Read DQS gate leveling. LPDDR2: Unused +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +b30 + +b30 + +DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2: Value loaded into EMR1register. (Bits[9:7] are for OCD and the setting in this reg is ignored. Controller sets this bits appropriately during initialization DDR3: Value loaded into MR1 register. Set Bit[7] to 0. This bit is set appropriately by the Controller during Write Leveling LPDDR2: Value loaded into MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40b30 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 8, Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 7, Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 6, Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 5, Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reserved_reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +Reserved. Do not modify. +
    +reserved_reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Reserved. Do not modify. +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3f03f + + + +3c008 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +10000 + + + +0 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum d'128) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_2d@0XF80060B4 + +31:0 + +200 + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of uncorrectable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on board topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +0: Use reg_phy_ctrl_slave_ratio for address/command timing slave DLL 1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_64@0XF8006190 + +31:0 + +6ffffefe + + + +40080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. This feature should only be enabled after LPDDR2 initialization is completed +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff5 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Powerdown mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQ pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQS pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +Drive and Slew controls for Clock pins of the DDR Interface +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SD1_WP_CD_SEL + + +0XF8000834 + +32 + +RW + +0x000000 + +SDIO 1 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQ pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQS pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for Clock pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1x: Enable External VREF for upper 16 bits +
    +reserved_VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Reserved. Do not modify. +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +reserved_REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +1 + + + +1 + +DDR IOB DCI Config +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialize flops in DCI system +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDR IOB DCI Config +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +DCI System Enable. Set to 1 if any IOs in DDR IO Bank use DCI Termination. DDR2, DDR3 and LPDDR2 (Silicon Revision 2.0+) configurations require this bit set to 1 +
    +reserved_VRP_TRI + +2:2 + +4 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_TRI + +3:3 + +8 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRP_OUT + +4:4 + +10 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT1 + +15:14 + +c000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update Mode. Use the values in the Calibration Table. +
    +reserved_INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_CLK + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLN + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLP + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_RST + +25:25 + +2000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7feffff + + + +823 + +DDR IOB DCI Config +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. 0: disable 1: enable +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables Pullup on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3f01 + + + +1601 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3f01 + + + +1601 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1680 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1680 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait, Input 10: NAND Flash IO Bit 7, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 12 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1680 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5, Input/Output 10: NAND Flash IO Bit 3, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 13 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1680 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1680 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1680 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1, Output 10: NAND Flash IO Bit 8, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2, Output 10: NAND Flash IO Bit 9, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110 TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3, Output 10: NAND Flash IO Bit 10, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6, Output 10: NAND Flash IO Bit 13, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3f01 + + + +1201 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +2e + +2e + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f002e + +SDIO 0 WP CD select +
    +

    +

    Register ( slcr )SD1_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD1_WP_CD_SEL + +0XF8000834 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO1_WP_SEL + +5:0 + +3f + +0 + +0 + +SDIO 1 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO1_CD_SEL + +21:16 + +3f0000 + +9 + +90000 + +SDIO 1 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD1_WP_CD_SEL@0XF8000834 + +31:0 + +3f003f + + + +90000 + +SDIO 1 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +Baud Rate Divider Register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud Rate Generator Register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control Register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode Register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +Baud Rate Divider Register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud Rate Generator Register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter 1: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: enable 1: disable, regardless of the value of RXEN +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed. +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed. +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control Register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +3ff + + + +20 + +UART Mode Register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes . If not set, then external pull up is required on HOLDb and WPn pins . Note that this bit doesn't affect the quad(4-bit) mode as Controller always drives these pins in quad mode. It is highly recommended to set this bit always(irrespective of mode of operation) while using QSPI +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This register controls which POR timer the PL will use for power-up. 0 - Use 64k timer 1 - Use 4k timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    ENET RESET

    +

    I2C RESET

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_LVL_INP_EN_0 + +3:3 + +8 + +1 + +8 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_0 + +2:2 + +4 + +1 + +4 + +Level shifter enable to drive signals from PS to PL +
    +USER_LVL_INP_EN_1 + +1:1 + +2 + +1 + +2 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_1 + +0:0 + +1 + +1 + +1 + +Level shifter enable to drive signals from PS to PL +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +Reserved. Do not modify. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +PL Reset 3 (FCLKRESETN3 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN3 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +PL Reset 2 (FCLKRESETN2 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN2 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +PL Reset 1 (FCLKRESETN1 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN1 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +PL Reset 0 (FCLKRESETN0 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN0 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    AFI2 SECURE REGISTER

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_3_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: CPU PLL 10: divided DDR PLL 11: IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +FPGA1_CLK_CTRL + + +0XF8000180 + +32 + +RW + +0x000000 + +PL Clock 1 Output control +
    + +FPGA2_CLK_CTRL + + +0XF8000190 + +32 + +RW + +0x000000 + +PL Clock 2 output control +
    + +FPGA3_CLK_CTRL + + +0XF80001A0 + +32 + +RW + +0x000000 + +PL Clock 3 output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source to generate the Rx clock: 0: MIO Rx clock, 1: EMIO Rx clock +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +7 + +700 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +701 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a03 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +5 + +500000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +500800 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )FPGA1_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA1_CLK_CTRL + +0XF8000180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA1_CLK_CTRL@0XF8000180 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 1 Output control +
    +

    +

    Register ( slcr )FPGA2_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA2_CLK_CTRL + +0XF8000190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +2 + +200000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA2_CLK_CTRL@0XF8000190 + +31:0 + +3f03f30 + + + +200500 + +PL Clock 2 output control +
    +

    +

    Register ( slcr )FPGA3_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA3_CLK_CTRL + +0XF80001A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA3_CLK_CTRL@0XF80001A0 + +31:0 + +3f03f30 + + + +100500 + +PL Clock 3 output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ration: 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +1 + +800 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec0c4d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config0 + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config1 + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 1. +
    + +PHY_Config2 + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 2. +
    + +PHY_Config3 + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 3. +
    + +phy_init_ratio0 + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio1 + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 1. +
    + +phy_init_ratio2 + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 2. +
    + +phy_init_ratio3 + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 3. +
    + +phy_rd_dqs_cfg0 + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg1 + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 1. +
    + +phy_rd_dqs_cfg2 + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 2. +
    + +phy_rd_dqs_cfg3 + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 3. +
    + +phy_wr_dqs_cfg0 + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg1 + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 1. +
    + +phy_wr_dqs_cfg2 + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 2. +
    + +phy_wr_dqs_cfg3 + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 3. +
    + +phy_we_cfg0 + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg1 + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 1. +
    + +phy_we_cfg2 + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 2. +
    + +phy_we_cfg3 + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 3. +
    + +wr_data_slv0 + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv1 + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 1. +
    + +wr_data_slv2 + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 2. +
    + +wr_data_slv3 + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 3. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port0 + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port1 + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 1. +
    + +axi_priority_wr_port2 + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 2. +
    + +axi_priority_wr_port3 + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 3. +
    + +axi_priority_rd_port0 + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port1 + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 1. +
    + +axi_priority_rd_port2 + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 2. +
    + +axi_priority_rd_port3 + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 3. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +82 + +82 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Rank configuration: 01: One Rank of DDR 11: Two Ranks of DDR Others: reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +Block read/write scheduling cycle count when Write requires changing ODT settings 00: 1 cycle 01: 2 cycles 10: 3 cycles others: reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0: schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1: schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81082 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a1 + +2840 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4285b + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +13 + +13 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d3 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +f + +3c00 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +5 + +28000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +5 + +2800000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +7282bce5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1: sdram device 0: non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: stop_clk will never be asserted. 1: enable the assertion of stop_clk to the PHY whenever a clock is not required +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2 and DDR3: Value written into the DRAM EMR2 register. LPDDR2: Value written into the DRAM MR3 register. +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2 and DDR3: Value written into the DRAM EMR3 register. LPDDR2: not used. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +b30 + +b30 + +DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2 and DDR3: Value written into the DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. LPDDR2: Value written into the DRAM MR2 register. +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40b30 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODTs must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config0 + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config0@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config1 + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config1@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 1. +
    +

    +

    Register ( slcr )PHY_Config2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config2 + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config2@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 2. +
    +

    +

    Register ( slcr )PHY_Config3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config3 + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config3@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_init_ratio0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio0 + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio0@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio1 + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio1@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 1. +
    +

    +

    Register ( slcr )phy_init_ratio2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio2 + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio2@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 2. +
    +

    +

    Register ( slcr )phy_init_ratio3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio3 + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio3@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 3. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg0 + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg0@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg1 + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg1@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg2 + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg2@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg3 + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg3@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg0 + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg0@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg1 + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg1@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg2 + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg2@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg3 + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg3@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_we_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg0 + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg0@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg1 + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg1@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 1. +
    +

    +

    Register ( slcr )phy_we_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg2 + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg2@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 2. +
    +

    +

    Register ( slcr )phy_we_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg3 + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg3@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 3. +
    +

    +

    Register ( slcr )wr_data_slv0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv0 + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv0@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv1 + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv1@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 1. +
    +

    +

    Register ( slcr )wr_data_slv2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv2 + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv2@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 2. +
    +

    +

    Register ( slcr )wr_data_slv3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv3 + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv3@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 3. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +0: (default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) 1: assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 0: Each Rank uses its own delay 1: Rank 0 delays are used for all ranks +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1: enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port0 + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port0@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port1 + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port1@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 1. +
    +

    +

    Register ( slcr )axi_priority_wr_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port2 + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port2@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 2. +
    +

    +

    Register ( slcr )axi_priority_wr_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port3 + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port3@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 3. +
    +

    +

    Register ( slcr )axi_priority_rd_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port0 + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port0@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port1 + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port1@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 1. +
    +

    +

    Register ( slcr )axi_priority_rd_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port2 + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port2@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 2. +
    +

    +

    Register ( slcr )axi_priority_rd_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port3 + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port3@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 3. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +0:All bank refresh Per bank refresh allows traffic to flow to other banks. 1:Per bank refresh Per bank refresh is not supported on all LPDDR2 devices. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Power-down mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 0 +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 1 +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDR IOB Slew for Address +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDR IOB Slew for Data +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDR IOB Slew for Diff +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDR IOB Slew for Clock +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SD1_WP_CD_SEL + + +0XF8000834 + +32 + +RW + +0x000000 + +SDIO 1 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 0 +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 1 +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDR IOB Slew for Address +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Data +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Diff +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Clock +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1X: Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors x0: Disable VREF pull-up for lower 16 bits x1: Enable VREF pull-up for lower 16 bits 0x: Disable VREF pull-up for upper 16 bits 1x: Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Enable test mode for VRP and VRN: 00: VRP/VRN test mode not used 11: VRP/VRN test mode enabled using vref based receiver. VRP/VRN control is set using the VRN_OUT, VRP_OUT, VRN_TRI, VRP_TRI fields in the DDRIOB_DCI_CTRL register +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0: no pull-up 1: enable pull-up +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. 0: disable 1: enable +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables pull-up on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3f01 + + + +1601 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3f01 + + + +1601 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1680 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1680 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait 10: NAND Flash IO Bit 7 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 12 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1680 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5 10: NAND Flash IO Bit 3 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 13 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1680 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1680 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1680 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1 10: NAND Flash IO Bit 8 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Output 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2 10: NAND Flash IO Bit 9 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110 TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3 10: NAND Flash IO Bit 10 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6 10: NAND Flash IO Bit 13 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3f01 + + + +1201 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +2e + +2e + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f002e + +SDIO 0 WP CD select +
    +

    +

    Register ( slcr )SD1_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD1_WP_CD_SEL + +0XF8000834 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO1_WP_SEL + +5:0 + +3f + +0 + +0 + +SDIO 1 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO1_CD_SEL + +21:16 + +3f0000 + +9 + +90000 + +SDIO 1 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD1_WP_CD_SEL@0XF8000834 + +31:0 + +3f003f + + + +90000 + +SDIO 1 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass 2 - 65535: baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: start break transmission, 1: stop break transmission. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: 1: start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 0: receiver timeout counter disabled, 1: receiver timeout counter is restarted. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter, 0: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter, 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: disable, 1: enable +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable, 1: enable. When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: 1: transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: 1: receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode: 0: Default UART mode 1: Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select: 0: APB clock, pclk 1: a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: 00: normal 01: automatic cho 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: 0: clock source is uart_clk 1: clock source is uart_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    ENET RESET

    +

    I2C RESET

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset: 0: No reset 1: ACP AXI interface reset output asserted +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0: No reset 1: AXDS3AXI interface reset output asserted +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0: No reset 1: AXDS2 AXI interface reset output asserted +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0: No reset 1: AXDS1 AXI interface reset output asserted +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0: No reset 1: AXDS0 AXI interface reset output asserted +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0: No reset 1: FPGA slave interface 1 reset is asserted +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0: No reset 1: FPGA slave interface 0 reset is asserted +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface: 1: soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0: No reset 1: FPGA master interface 1 reset is asserted +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0: No reset 1: FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 3 peripheral request reset output asserted +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 2 peripheral request reset output asserted +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 1 peripheral request reset output asserted +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 0 peripheral request reset output asserted +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0: No reset 1: FPGA 3 top level reset output asserted +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0: No reset 1: FPGA 2 top level reset output asserted +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0: No reset 1: FPGA 1 top level reset output asserted +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0: No reset 1: FPGA 0 top level reset output asserted +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_2_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CORTEX A9 Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status. 0 - ARM PLL out of lock. 1 - ARM PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is CPU PLL. 10 - Source for generated clock is DDR divided clock. 11 - Source for generated clock is IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CORTEX A9 Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status. 0 - DDR PLL out of lock. 1 - DDR PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Divisor value for the ddr_3xclk +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk) +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status. 0 - IO PLL out of lock. 1 - IO PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 RX Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Linear Quad-SPI Reference Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Reference Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Reference Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP 2X Clock Contol +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +FPGA 0 Output Clock Control +
    + +FPGA1_CLK_CTRL + + +0XF8000180 + +32 + +RW + +0x000000 + +FPGA 1 Output Clock Control +
    + +FPGA2_CLK_CTRL + + +0XF8000190 + +32 + +RW + +0x000000 + +FPGA 2 Output Clock Control +
    + +FPGA3_CLK_CTRL + + +0XF80001A0 + +32 + +RW + +0x000000 + +FPGA 3 Output Clock Control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +6:2:1 ratio clock, if set +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Selects the source used to generate the clock. 0 - Source for generated clock is GEM 0 MIO RX clock. 1 - Source for generated clock is GEM 0 FMIO RX clock. +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +Gigabit Ethernet MAC 0 RX Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source used to generate the clock. 1xx - Source for generated clock is Ethernet 0 FMIO clock. 00x - Source for generated clock is IO PLL. 010 - Source for generated clock is ARM PLL. 011 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +7 + +700 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +701 + +Linear Quad-SPI Reference Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO 0 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +SDIO 1 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a03 + +SDIO Reference Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Reference Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active 0 - Clock is disabled 1 - Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP 2X Clock Contol +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +5 + +500000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +500800 + +FPGA 0 Output Clock Control +
    +

    +

    Register ( slcr )FPGA1_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA1_CLK_CTRL + +0XF8000180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA1_CLK_CTRL@0XF8000180 + +31:0 + +3f03f30 + + + +400500 + +FPGA 1 Output Clock Control +
    +

    +

    Register ( slcr )FPGA2_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA2_CLK_CTRL + +0XF8000190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +2 + +200000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA2_CLK_CTRL@0XF8000190 + +31:0 + +3f03f30 + + + +200500 + +FPGA 2 Output Clock Control +
    +

    +

    Register ( slcr )FPGA3_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA3_CLK_CTRL + +0XF80001A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA3_CLK_CTRL@0XF80001A0 + +31:0 + +3f03f30 + + + +100500 + +FPGA 3 Output Clock Control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Enable the 6:2:1 mode. 1 for 6:3:2:1. 0 for 4:2:2:1. +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +6:2:1 ratio clock, if set +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet MAC 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet MAC 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +1 + +800 + +SDIO 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +LQSPI AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec0c4d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two rank configuration register +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control register +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control register +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control register +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters register 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters register 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters register 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters register 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters register 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM initialization parameters register +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access register +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access register +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM burst 8 read/write register +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ register +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM bank address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT register +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO register +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration register +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold register +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller register 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller register 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller register 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller register 4 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters register +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters register +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown register +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control register +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug register +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing register +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear register +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction register +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status register +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count register +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub register +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control register (2) +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control register (3) +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask register +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 Register +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 Register +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 Register +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 Register +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control Register +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +82 + +82 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Only present for multi-rank configurations. Each bit represents one rank. 1=populated; 0=unpopulated 01 = One Rank 11 = Two Ranks Others = Reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +00 = block read/write scheduling for 1-cycle when Write requires changing ODT settings 01 = block read/write scheduling for 2 cycles when Write requires changing ODT settings 10 = block read/write scheduling for 3 cycles when Write requires changing ODT settings 11 = Reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0 = schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1 = schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81082 + +Two rank configuration register +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of clocks that the HPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control register +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control register +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control register +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a1 + +2840 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks DRAM RELATED +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4285b + +DRAM Parameters register 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +13 + +13 + +Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. LPDDR2 mode: Set this to the larger of tCKE or tCKESR. Non-LPDDR2 designs: Set this to tCKE value. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d3 + +DRAM Parameters register 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2/3 -> WL -1 LPDDR -> 1 LPDDR2 ->WL Where WL = Write Latency of DRAM DRAM RELATED. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. non-LPDDR2 -> RL + BL/2 + 2 - WL LPDDR2 -> RL + BL/2 + RU(tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +f + +3c00 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +5 + +28000 + +tXP: Minimum time after power down exit to any operation. DRAM RELATED. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +5 + +2800000 + +Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency DRAM RELATED +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +7282bce5 + +DRAM Parameters register 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1 DRAM RELATED +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1 = sdram device 0 = non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-mobile DRAM device in use. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +1=enable the assertion of stop_clk to the PHY whenever a clock is not required by LPDDR/ LPDDR2. 0=stop_clk will never be asserted. Note: This is only present for implementations supporting LPDDR/LPDDR2 devices. +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Set to RL. Time from Read command to Read data on DRAM interface. Unit: clocks This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. RL = Read Latency of DRAM Note: This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1 = disable the pad power down feature 0 = Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters register 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1 = DDRC will use 2T timing 0 = DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1 = Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and 'ddrc_reg_mr_wr_busy' is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +Mode register address - for non-LPDDR2 modes. This register is don't care in LPDDR2 mode 00 = MR0 01 = MR1 10 = MR2 11 = MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +Mode register write data - for non-LPDDR2 modes. For LPDDR2, these 16-bits are interpreted as Writes: \'7bMR Addr[7:0], MR Data[7:0]\'7d. Reads: \'7bMR Addr[7:0], Don't Care[7:0]\'7d +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 1 = Indicates that mode register write / read operation is in progress. 0 = Indicates that the core can initiate a mode register write / read operation. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 1 = read 0 = write +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 1'b0 by default. This bit will be cleared (1'b0), whenever a Mode Register Read command is issued. This bit will be set to 1'b1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters register 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands DRAM RELATED Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM initialization parameters register +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +Non LPDDR2- Value to be loaded into DRAM EMR2 registers. For LPDDR2 - Value to Write to the MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +Non LPDDR2- Value to be loaded into DRAM EMR3 registers. Used in non-LPDDR2 designs only. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access register +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +b30 + +b30 + +Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +Non LPDDR2-Value to be loaded into DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. For LPDDR2 - Value to Write to the MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40b30 + +DRAM EMR, MR access register +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +This controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. In LPDDR and LPDDR2, Burst length of 16 is supported only in Half Bus Width mode. Every input read/write command has 4 cycles of data associated with it and that is not enough data for doing Burst Length16 in Full Bus Width mode. 0010 - Burst length of 4 0100 - Burst length of 8 1000 - Burst length of 16 (only supported for LPDDR AND LPDDR2) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM burst 8 read/write register +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Active Low signal. When asserted (0), all incoming transactions will be forced to low priority. Forcing the incoming transactions to low priority implicitly turns OFF Bypass. Otherwise, HPR is allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. This bit is intended to be switched on-the-fly +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ register +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14 Internal Base: 5 The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Selects the address bits used as DRAM bank address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Selects the address bits used as DRAM column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Selects the address bits used as DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODT's must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT register +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1 = stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO register +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration register +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable for LPDDR and LPDDR2 modes. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold register +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +When 1, disable Write Combine +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to '0', auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller register 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +1 - Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on 'urgent' input coming from AXI master. 0 - Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 1'b0. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller register 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) Only present in designs that support DDR3 and LPDDR2 devices. +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Only present in designs that support DDR3 devices +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. Only present in designs that support DDR3 devices. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller register 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller register 4 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters register +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters register +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +1 - Controller puts the DRAM into Deep Powerdown mode when the transaction store is empty. 0 - Brings Controller out of Deep Powerdown mode Present only in designs configured to support LPDDR or LPDDR2 FOR PERFORMANCE ONLY. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown register +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +1 = Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0 = Write leveling disabled. +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +1 = Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0= Read DQS gate leveling is disabled. +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +1 = Read Data Eye training mode has been enabled as part of init sequence. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control register +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1 - Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0 - Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug register +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. Non-LPDDR -> RL-1 LPDDR -> RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing register +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear register +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when a correctable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction register +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when an uncorrectable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status register +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count register +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 3'b000 (No ECC) and 3'b100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 3'b100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 - No ECC, 001 - Reserved 010 - Parity 011 - Reserved 100 - SEC/DED over 1-beat 101 - SEC/DED over multiple beats 110 - Device Correction 111 - Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +This feature is NOT supported. Only default value works. 1 - Disable ECC scrubs 0 - Enable ECC scrubs Valid only when reg_ddrc_ecc_mode = 3'b100. +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub register +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +1 = run scan test at full clock speed but with less coverage 0 = run scan test at slow clock speed but with high coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 2'b00: constant pattern (0 repeated on each DQ bit) 2'b01: low freq pattern (00001111 repeated on each DQ bit) 2'b10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +1=assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) 0=(default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0 = Select algorithm # 1'b1 = Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 1- Rank 0 delays are used for all ranks 0- Each Rank uses its own delay +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-LPDDR DRAM device in use. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1=enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control register (2) +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control register (3) +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +This register must be set based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask register +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +1=LPDDR2 DRAM device in Use. 0=non-LPDDR2 device in use Present only in designs configured to support LPDDR2. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +1:Per bank refresh 0:All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported on all LPDDR2 devices. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 Register +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. Present only in designs configured to support LPDDR2. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 Register +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 Register +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 Register +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control Register +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0 = DDRC Init 1 = Normal operation 2 = Power-down mode 3 = Self-refresh mode 4 and above = deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDRIOB Address 0 Configuartion Register +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDRIOB Address 1 Configuration Register +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDRIOB Differential Clock Configuration Register +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Address Register +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Data Register +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Differential Strobe Register +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Clcok Register +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDRIOB DDR Control Register +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Control for Pin 0 +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Control for Pin 1 +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Control for Pin 2 +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Control for Pin 3 +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Control for Pin 4 +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Control for Pin 5 +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Control for Pin 6 +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Control for Pin 8 +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Control for Pin 9 +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Control for Pin 10 +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Control for Pin 11 +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Control for Pin 12 +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Control for Pin 13 +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Control for Pin 14 +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Control for Pin 15 +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Control for Pin 16 +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Control for Pin 17 +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Control for Pin 18 +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Control for Pin 19 +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Control for Pin 20 +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Control for Pin 21 +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Control for Pin 22 +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Control for Pin 23 +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Control for Pin 24 +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Control for Pin 25 +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Control for Pin 26 +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Control for Pin 27 +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Control for Pin 40 +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Control for Pin 41 +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Control for Pin 42 +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Control for Pin 43 +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Control for Pin 44 +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Control for Pin 45 +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Control for Pin 46 +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Control for Pin 47 +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Control for Pin 48 +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Control for Pin 49 +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Control for Pin 52 +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Control for Pin 53 +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select register +
    + +SD1_WP_CD_SEL + + +0XF8000834 + +32 + +RW + +0x000000 + +SDIO 1 WP CD select register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDRIOB Address 0 Configuartion Register +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDRIOB Address 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDRIOB Differential Clock Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDRIOB Drive Slew Address Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Data Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Differential Strobe Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Clcok Register +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output 0001 - VREF = 0.6V for LPDDR2 with 1.2V IO 0010 - VREF = 0.675V for LPDDR3 1.35 V IO 0100 - VREF = 0.75V for DDR3 with 1.5V IO 1000 - VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input X0 - Disable External VREF for lower 16 bits X1 - Enable External VREF for lower 16 bits 0X - Disable External VREF for upper 16 bits 1X - Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors X0 - Disable VREF pull-up for lower 16 bits X1 - Enable VREF pull-up for lower 16 bits 0X - Disable VREF pull-up for upper 16 bits 1X - Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0 - VRP/VRN not used 1 - VRP/VRN used as refio +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +73ff + + + +260 + +DDRIOB DDR Control Register +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3f01 + + + +1601 + +MIO Control for Pin 0 +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Control for Pin 1 +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 2 +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Control for Pin 3 +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 4 +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 5 +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 6 +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 8 +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3f01 + + + +1601 + +MIO Control for Pin 9 +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 10 +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 11 +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_wait- (SRAM Wait State indicator) 2= nand, Input, smc_nand_data_in[7]- (NAND Data Bus) = nand, Output, smc_nand_data_out[7]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 12 +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[5]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[5]- (SRAM Data) 2= nand, Input, smc_nand_data_in[3]- (NAND Data Bus) = nand, Output, smc_nand_data_out[3]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 13 +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 14 +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 15 +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[4]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[1]- (SRAM Address) 2= nand, Input, smc_nand_data_in[8]- (NAND Data Bus) = nand, Output, smc_nand_data_out[8]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 16 +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[5]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[2]- (SRAM Address) 2= nand, Input, smc_nand_data_in[9]- (NAND Data Bus) = nand, Output, smc_nand_data_out[9]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 17 +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[6]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[3]- (SRAM Address) 2= nand, Input, smc_nand_data_in[10]- (NAND Data Bus) = nand, Output, smc_nand_data_out[10]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 18 +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 19 +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 20 +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[6]- (SRAM Address) 2= nand, Input, smc_nand_data_in[13]- (NAND Data Bus) = nand, Output, smc_nand_data_out[13]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 21 +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 22 +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 23 +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 24 +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 25 +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 26 +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 27 +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 40 +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 41 +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 42 +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 43 +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 44 +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 45 +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3f01 + + + +1201 + +MIO Control for Pin 46 +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Control for Pin 47 +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Control for Pin 48 +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Control for Pin 49 +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 52 +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 53 +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +2e + +2e + +SDIO0 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO0 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f002e + +SDIO 0 WP CD select register +
    +

    +

    Register ( slcr )SD1_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD1_WP_CD_SEL + +0XF8000834 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO1_WP_SEL + +5:0 + +3f + +0 + +0 + +SDIO1 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SDIO1_CD_SEL + +21:16 + +3f0000 + +9 + +90000 + +SDIO1 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SD1_WP_CD_SEL@0XF8000834 + +31:0 + +3f003f + + + +90000 + +SDIO 1 WP CD select register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value 0 = Disables baud_sample 1 = Clock divisor bypass 2 - 65535 = baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break. 1 = stop transmission of the break. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break 1 = start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter 1 = receiver timeout counter is restarted +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable. 1, the transmitter is disabled +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable. 1, the transmitter is enabled, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable. 1= receiver is enabled +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable. 1=the receiver logic is enabled, provided RXDIS field is set to 0 +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for TX data path. 1=the transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for RX data path 1=receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode 0 : Default UART mode 1 : Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select 0 : APB clock, pclk 1 : a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode 00 = normal 01 = automatic cho 10 = local loopback 11 = remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits 00 = 1 stop bit 01 = 1.5 stop bits 10 = 2 stop bits 11 = reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select. 000 = even parity 001 = odd parity 010 = forced to 0 parity (space) 011 = forced to 1 parity (mark) 1xx = no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select 11 = 6 bits 10 = 7 bits 01 / 00 = 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +clock source select 1 = clock source is uart_clk/8 0 = clock source is uart_clk +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    ENET RESET

    +

    I2C RESET

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset. 0 - No reset. 1 - ACP AXI interface reset output asserted. +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS3AXI interface reset output asserted. +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS2 AXI interface reset output asserted. +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS1 AXI interface reset output asserted. +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS0 AXI interface reset output asserted. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 1 reset is asserted. +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 0 reset is asserted. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface 1 soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0 - No reset. 1 - FPGA master interface 1 reset is asserted. +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0 - No reset. 1 - FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 3 peripheral request reset output asserted. +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 2 peripheral request reset output asserted. +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 1 peripheral request reset output asserted. +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 0 peripheral request reset output asserted. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0 - No reset. 1 - FPGA 3 top level reset output asserted. +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0 - No reset. 1 - FPGA 2 top level reset output asserted. +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0 - No reset. 1 - FPGA 1 top level reset output asserted. +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0 - No reset. 1 - FPGA 0 top level reset output asserted. +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_1_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/ps7_init.tcl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/ps7_init.tcl new file mode 100755 index 0000000..85a6f34 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/ps7_init.tcl @@ -0,0 +1,781 @@ +proc ps7_pll_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000701 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00500800 + mask_write 0XF8000180 0x03F03F30 0x00400500 + mask_write 0XF8000190 0x03F03F30 0x00200500 + mask_write 0XF80001A0 0x03F03F30 0x00100500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_3_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x0007FFFF 0x00001082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006024 0x0FFFFFC3 0x00000000 + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00000003 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x0003F03F 0x0003C008 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x00010000 0x00000000 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x00000200 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFCF 0x40000001 + mask_write 0XF800611C 0x7FFFFFCF 0x40000001 + mask_write 0XF8006120 0x7FFFFFCF 0x40000001 + mask_write 0XF8006124 0x7FFFFFCF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0x6FFFFEFE 0x00040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000703FF 0x000003FF + mask_write 0XF800620C 0x000703FF 0x000003FF + mask_write 0XF8006210 0x000703FF 0x000003FF + mask_write 0XF8006214 0x000703FF 0x000003FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF5 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000001 0x00000001 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001601 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003F01 0x00001601 + mask_write 0XF8000728 0x00003FFF 0x00001680 + mask_write 0XF800072C 0x00003FFF 0x00001680 + mask_write 0XF8000730 0x00003FFF 0x00001680 + mask_write 0XF8000734 0x00003FFF 0x00001680 + mask_write 0XF8000738 0x00003FFF 0x00001680 + mask_write 0XF800073C 0x00003FFF 0x00001680 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003F01 0x00001201 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F002E + mask_write 0XF8000834 0x003F003F 0x00090000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x000003FF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 +} +proc ps7_post_config_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_3_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000701 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00500800 + mask_write 0XF8000180 0x03F03F30 0x00400500 + mask_write 0XF8000190 0x03F03F30 0x00200500 + mask_write 0XF80001A0 0x03F03F30 0x00100500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_2_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001601 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003F01 0x00001601 + mask_write 0XF8000728 0x00003FFF 0x00001680 + mask_write 0XF800072C 0x00003FFF 0x00001680 + mask_write 0XF8000730 0x00003FFF 0x00001680 + mask_write 0XF8000734 0x00003FFF 0x00001680 + mask_write 0XF8000738 0x00003FFF 0x00001680 + mask_write 0XF800073C 0x00003FFF 0x00001680 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003F01 0x00001201 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F002E + mask_write 0XF8000834 0x003F003F 0x00090000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 +} +proc ps7_post_config_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_2_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000701 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00500800 + mask_write 0XF8000180 0x03F03F30 0x00400500 + mask_write 0XF8000190 0x03F03F30 0x00200500 + mask_write 0XF80001A0 0x03F03F30 0x00100500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_1_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x000073FF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001601 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003F01 0x00001601 + mask_write 0XF8000728 0x00003FFF 0x00001680 + mask_write 0XF800072C 0x00003FFF 0x00001680 + mask_write 0XF8000730 0x00003FFF 0x00001680 + mask_write 0XF8000734 0x00003FFF 0x00001680 + mask_write 0XF8000738 0x00003FFF 0x00001680 + mask_write 0XF800073C 0x00003FFF 0x00001680 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003F01 0x00001201 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F002E + mask_write 0XF8000834 0x003F003F 0x00090000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 +} +proc ps7_post_config_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_1_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +set PCW_SILICON_VER_1_0 "0x0" +set PCW_SILICON_VER_2_0 "0x1" +set PCW_SILICON_VER_3_0 "0x2" +set APU_FREQ 666666666 + + + +proc mask_poll { addr mask } { + set count 1 + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + while { $maskedval == 0 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + set count [ expr { $count + 1 } ] + if { $count == 100000000 } { + puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask" + break + } + } +} + + + +proc mask_delay { addr val } { + set delay [ get_number_of_cycles_for_delay $val ] + perf_reset_and_start_timer + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + while { $maskedval == 1 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + } + perf_reset_clock +} + +proc ps_version { } { + set si_ver "0x[string range [mrd 0xF8007080] end-8 end]" + set mask_sil_ver "0x[expr {$si_ver >> 28}]" + return $mask_sil_ver; +} + +proc ps7_post_config {} { + set saved_mode [configparams force-mem-accesses] + configparams force-mem-accesses 1 + + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_post_config_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_post_config_2_0 + } else { + ps7_post_config_3_0 + } + configparams force-mem-accesses $saved_mode +} + +proc ps7_debug {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_debug_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_debug_2_0 + } else { + ps7_debug_3_0 + } +} +proc ps7_init {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_mio_init_data_1_0 + ps7_pll_init_data_1_0 + ps7_clock_init_data_1_0 + ps7_ddr_init_data_1_0 + ps7_peripherals_init_data_1_0 + #puts "PCW Silicon Version : 1.0" + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_mio_init_data_2_0 + ps7_pll_init_data_2_0 + ps7_clock_init_data_2_0 + ps7_ddr_init_data_2_0 + ps7_peripherals_init_data_2_0 + #puts "PCW Silicon Version : 2.0" + } else { + ps7_mio_init_data_3_0 + ps7_pll_init_data_3_0 + ps7_clock_init_data_3_0 + ps7_ddr_init_data_3_0 + ps7_peripherals_init_data_3_0 + #puts "PCW Silicon Version : 3.0" + } +} + + +# For delay calculation using global timer + +# start timer + proc perf_start_clock { } { + + #writing SCU_GLOBAL_TIMER_CONTROL register + + mask_write 0xF8F00208 0x00000109 0x00000009 +} + +# stop timer and reset timer count regs + proc perf_reset_clock { } { + perf_disable_clock + mask_write 0xF8F00200 0xFFFFFFFF 0x00000000 + mask_write 0xF8F00204 0xFFFFFFFF 0x00000000 +} + +# Compute mask for given delay in miliseconds +proc get_number_of_cycles_for_delay { delay } { + + # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + variable APU_FREQ + return [ expr ($delay * $APU_FREQ /(2 * 1000))] +} + + +# stop timer +proc perf_disable_clock {} { + mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 +} + +proc perf_reset_and_start_timer {} { + perf_reset_clock + perf_start_clock +} + + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/ps7_init_gpl.h b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/ps7_init_gpl.h new file mode 100755 index 0000000..45a7839 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/ps7_init_gpl.h @@ -0,0 +1,131 @@ +/****************************************************************************** +* +* Copyright (C) 2010-2020 +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, see +* +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init_gpl.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + + + + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 142857132 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 25000000 +#define FPGA1_FREQ 50000000 +#define FPGA2_FREQ 100000000 +#define FPGA3_FREQ 200000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/xilinx-zynq.cc b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/xilinx-zynq.cc new file mode 100755 index 0000000..14e40f9 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/vcs/xilinx-zynq.cc @@ -0,0 +1,106 @@ +/* + * Xilinx SystemC/TLM-2.0 Zynq Wrapper. + * + * Written by Edgar E. Iglesias + * + * Copyright (c) 2016, Xilinx Inc. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#define SC_INCLUDE_DYNAMIC_PROCESSES + +#include + +#include "tlm_utils/simple_initiator_socket.h" +#include "tlm_utils/simple_target_socket.h" + +using namespace sc_core; +using namespace std; + +#include "xilinx-zynq.h" +#include + +//xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr, +// Iremoteport_tlm_sync *sync) +// : remoteport_tlm(name, -1, sk_descr, sync), +xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr) + : remoteport_tlm(name, -1, sk_descr), + rp_m_axi_gp0("rp_m_axi_gp0"), + rp_m_axi_gp1("rp_m_axi_gp1"), + rp_s_axi_gp0("rp_s_axi_gp0"), + rp_s_axi_gp1("rp_s_axi_gp1"), + rp_s_axi_hp0("rp_s_axi_hp0"), + rp_s_axi_hp1("rp_s_axi_hp1"), + rp_s_axi_hp2("rp_s_axi_hp2"), + rp_s_axi_hp3("rp_s_axi_hp3"), + rp_s_axi_acp("rp_s_axi_acp"), + rp_wires_in("wires_in", 20, 0), + rp_wires_out("wires_out", 0, 17), + rp_irq_out("irq_out", 0, 28), + pl2ps_irq("pl2ps_irq", 20), + ps2pl_irq("ps2pl_irq", 28), + ps2pl_rst("ps2pl_rst", 17) +{ + int i; + + m_axi_gp[0] = &rp_m_axi_gp0.sk; + m_axi_gp[1] = &rp_m_axi_gp1.sk; + + s_axi_gp[0] = &rp_s_axi_gp0.sk; + s_axi_gp[1] = &rp_s_axi_gp1.sk; + + s_axi_hp[0] = &rp_s_axi_hp0.sk; + s_axi_hp[1] = &rp_s_axi_hp1.sk; + s_axi_hp[2] = &rp_s_axi_hp2.sk; + s_axi_hp[3] = &rp_s_axi_hp3.sk; + s_axi_acp = &rp_s_axi_acp.sk; + + /* PL to PS Interrupt signals. */ + for (i = 0; i < 20; i++) { + rp_wires_in.wires_in[i](pl2ps_irq[i]); + } + + /* PS to PL Interrupt signals. */ + for (i = 0; i < 28; i++) { + rp_irq_out.wires_out[i](ps2pl_irq[i]); + } + + /* PS to PL resets. */ + for (i = 0; i < 17; i++) { + rp_wires_out.wires_out[i](ps2pl_rst[i]); + } + + register_dev(0, &rp_s_axi_gp0); + register_dev(1, &rp_s_axi_gp1); + + register_dev(2, &rp_s_axi_hp0); + register_dev(3, &rp_s_axi_hp1); + register_dev(4, &rp_s_axi_hp2); + register_dev(5, &rp_s_axi_hp3); + + register_dev(6, &rp_s_axi_acp); + + register_dev(7, &rp_m_axi_gp0); + register_dev(8, &rp_m_axi_gp1); + register_dev(9, &rp_wires_in); + register_dev(10, &rp_wires_out); + register_dev(11, &rp_irq_out); +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/Makefile b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/Makefile new file mode 100755 index 0000000..33394b3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/Makefile @@ -0,0 +1,26 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +INCLUDEFILES=*.h +LIBSOURCES=*.c +OUTS = *.o + +libs: + echo "Compiling SPI_Con..." + $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} + make clean + +include: + ${CP} $(INCLUDEFILES) $(INCLUDEDIR) + +clean: + rm -rf ${OUTS} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/NewExtInst_TOP.bda b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/NewExtInst_TOP.bda new file mode 100755 index 0000000..ab7b1f9 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/NewExtInst_TOP.bda @@ -0,0 +1,272 @@ +{ + "graphjs": { + "version": "1.0", + "keys": [ + { + "abrv": "VH", + "name": "vert_hid", + "type": "int", + "for": "node" + }, + { + "abrv": "VM", + "name": "vert_name", + "type": "string", + "for": "node" + }, + { + "abrv": "VT", + "name": "vert_type", + "type": "string", + "for": "node" + }, + { + "abrv": "BA", + "name": "base_addr", + "type": "string", + "for": "node" + }, + { + "abrv": "HA", + "name": "high_addr", + "type": "string", + "for": "node" + }, + { + "abrv": "BP", + "name": "base_param", + "type": "string", + "for": "node" + }, + { + "abrv": "HP", + "name": "high_param", + "type": "string", + "for": "node" + }, + { + "abrv": "MA", + "name": "master_addrspace", + "type": "string", + "for": "node" + }, + { + "abrv": "MX", + "name": "master_instance", + "type": "string", + "for": "node" + }, + { + "abrv": "MI", + "name": "master_interface", + "type": "string", + "for": "node" + }, + { + "abrv": "MS", + "name": "master_segment", + "type": "string", + "for": "node" + }, + { + "abrv": "MV", + "name": "master_vlnv", + "type": "string", + "for": "node" + }, + { + "abrv": "SX", + "name": "slave_instance", + "type": "string", + "for": "node" + }, + { + "abrv": "SI", + "name": "slave_interface", + "type": "string", + "for": "node" + }, + { + "abrv": "MM", + "name": "slave_memmap", + "type": "string", + "for": "node" + }, + { + "abrv": "SS", + "name": "slave_segment", + "type": "string", + "for": "node" + }, + { + "abrv": "SV", + "name": "slave_vlnv", + "type": "string", + "for": "node" + }, + { + "abrv": "TM", + "name": "memory_type", + "type": "string", + "for": "node" + }, + { + "abrv": "TU", + "name": "usage_type", + "type": "string", + "for": "node" + }, + { + "abrv": "LT", + "name": "lock_type", + "type": "string", + "for": "node" + }, + { + "abrv": "BT", + "name": "boot_type", + "type": "string", + "for": "node" + }, + { + "abrv": "EH", + "name": "edge_hid", + "type": "int", + "for": "edge" + } + ], + "vertice_type_order": [ + { + "abrv": "BC", + "desc": "Block Container" + }, + { + "abrv": "PR", + "desc": "Parital Reference" + }, + { + "abrv": "VR", + "desc": "Variant" + }, + { + "abrv": "PM", + "desc": "Variant Permutations" + }, + { + "abrv": "CX", + "desc": "Boundary Connection" + }, + { + "abrv": "AC", + "desc": "Assignment Coordinate" + }, + { + "abrv": "ACE", + "desc": "Excluded Assign Coordinate" + }, + { + "abrv": "APX", + "desc": "Boundary Aperture" + }, + { + "abrv": "CIP", + "desc": "High level Processing System" + } + ], + "vertices": { + "V0": { + "VM": "NewExtInst_TOP", + "VT": "BC" + }, + "V1": { + "VH": "2", + "VM": "NewExtInst_TOP", + "VT": "VR" + }, + "V2": { + "VH": "2", + "VT": "PM", + "TU": "active" + }, + "V3": { + "VT": "AC", + "BA": "0x43C00000", + "HA": "0x43C0FFFF", + "BP": "C_S00_AXI_BASEADDR", + "HP": "C_S00_AXI_HIGHADDR", + "MA": "Data", + "MX": "/processing_system7_0", + "MI": "M_AXI_GP0", + "MS": "SEG_SPI_Con_0_S00_AXI_reg", + "MV": "xilinx.com:ip:processing_system7:5.5", + "SX": "/SPI_Con_0", + "SI": "S00_AXI", + "SS": "S00_AXI_reg", + "SV": "xilinx.com:user:SPI_Con:1.0", + "TM": "both", + "TU": "register" + }, + "V4": { + "VT": "AC", + "BA": "0x43C10000", + "HA": "0x43C1FFFF", + "BP": "C_S00_AXI_BASEADDR", + "HP": "C_S00_AXI_HIGHADDR", + "MA": "Data", + "MX": "/processing_system7_0", + "MI": "M_AXI_GP0", + "MS": "SEG_SPI_Con_1_S00_AXI_reg", + "MV": "xilinx.com:ip:processing_system7:5.5", + "SX": "/SPI_Con_1", + "SI": "S00_AXI", + "SS": "S00_AXI_reg", + "SV": "xilinx.com:user:SPI_Con:1.0", + "TM": "both", + "TU": "register" + }, + "V5": { + "VT": "AC", + "BA": "0x43C20000", + "HA": "0x43C2FFFF", + "BP": "C_S00_AXI_BASEADDR", + "HP": "C_S00_AXI_HIGHADDR", + "MA": "Data", + "MX": "/processing_system7_0", + "MI": "M_AXI_GP0", + "MS": "SEG_SPI_Con_2_S00_AXI_reg", + "MV": "xilinx.com:ip:processing_system7:5.5", + "SX": "/SPI_Con_2", + "SI": "S00_AXI", + "SS": "S00_AXI_reg", + "SV": "xilinx.com:user:SPI_Con:1.0", + "TM": "both", + "TU": "register" + } + }, + "edges": [ + { + "src": "V0", + "trg": "V1" + }, + { + "src": "V1", + "trg": "V2" + }, + { + "src": "V3", + "trg": "V2", + "EH": "2" + }, + { + "src": "V4", + "trg": "V2", + "EH": "2" + }, + { + "src": "V5", + "trg": "V2", + "EH": "2" + } + ] + } +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/NewExtInst_TOP.sh b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/NewExtInst_TOP.sh new file mode 100755 index 0000000..7817c57 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/NewExtInst_TOP.sh @@ -0,0 +1,442 @@ +#!/usr/bin/env bash +#********************************************************************************************************** +# Vivado (TM) v2023.2 (64-bit) +# +# Script generated by Vivado on Fri May 15 15:32:22 CST 2026 +# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 +# +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# +# Filename : NewExtInst_TOP.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script generated by export_simulation Tcl command +# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the +# design. The script will copy the library mapping file from the compiled library directory, +# create design library directories and library mappings in the mapping file. +# +# Usage : NewExtInst_TOP.sh +# NewExtInst_TOP.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]* +# NewExtInst_TOP.sh [-reset_run] +# NewExtInst_TOP.sh [-reset_log] +# NewExtInst_TOP.sh [-help] +# +# * The -noclean_files switch is deprecated and will not peform any function (by default, the +# simulator generated files will not be removed unless -reset_run switch is used) +# +# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library +# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help' +# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path +# switch with the directory path where the library is created while generating the script +# with export_simulation. +# +# Alternatively, you can set the library path by setting the following project property:- +# +# set_property compxlib._compiled_library_dir [current_project] +# +# You can also point to the simulation library by either setting the 'lib_map_path' global +# variable in this script or specify it with the '-lib_map_path' switch while executing this +# script (type 'NewExtInst_TOP.sh -help' for more information). +# +# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the +# generated script, but if design is targetted for system simulation containing SystemC/C++/C +# sources, then the library path MUST be specified upfront when calling export_simulation. +# +# For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************** + +# catch pipeline exit status +set -Eeuo pipefail + +# set xmvhdl compile options +xmvhdl_opts="-64bit -messages -relax -logfile .tmp_log -update" + +# set xmvlog compile options +xmvlog_opts="-64bit -messages -logfile .tmp_log -update" + +# set xmelab elaboration options +xmelab_opts="-64bit -relax -access +rwc -namemap_mixgen -messages -logfile elaborate.log" + +# set xmsim simulation options +xmsim_opts="-64bit -logfile simulate.log" + +# set design libraries for elaboration +design_libs_elab="-libname xilinx_vip -libname xpm -libname axi_infrastructure_v1_1_0 -libname axi_vip_v1_1_15 -libname processing_system7_vip_v1_0_17 -libname xil_defaultlib -libname lib_cdc_v1_0_2 -libname proc_sys_reset_v5_0_14 -libname generic_baseblocks_v2_1_1 -libname axi_register_slice_v2_1_29 -libname fifo_generator_v13_2_9 -libname axi_data_fifo_v2_1_28 -libname axi_crossbar_v2_1_30 -libname axi_protocol_converter_v2_1_29 -libname xilinx_vip -libname unisims_ver -libname unimacro_ver -libname secureip" + +# set design libraries +design_libs=(simprims_ver xilinx_vip xpm axi_infrastructure_v1_1_0 axi_vip_v1_1_15 processing_system7_vip_v1_0_17 xil_defaultlib lib_cdc_v1_0_2 proc_sys_reset_v5_0_14 generic_baseblocks_v2_1_1 axi_register_slice_v2_1_29 fifo_generator_v13_2_9 axi_data_fifo_v2_1_28 axi_crossbar_v2_1_30 axi_protocol_converter_v2_1_29) + +# simulation root library directory +sim_lib_dir="xcelium_lib" + +# script info +echo -e "NewExtInst_TOP.sh - Script generated by export_simulation (Vivado v2023.2 (64-bit)-id)\n" + +# main steps +run() +{ + check_args $* + setup + if [[ ($b_step == 1) ]]; then + case $step in + "compile" ) + init_lib + compile + ;; + "elaborate" ) + elaborate + ;; + "simulate" ) + simulate + ;; + * ) + echo -e "ERROR: Invalid or missing step '$step' (type \"./NewExtInst_TOP.sh -help\" for more information)\n" + exit 1 + esac + else + init_lib + compile + elaborate + simulate + fi +} + +# RUN_STEP: +compile() +{ + xmvlog -work xilinx_vip $xmvlog_opts -sv +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + 2>&1 | tee compile.log; cat .tmp_log > xmvlog.log 2>/dev/null + + xmvlog -work xpm $xmvlog_opts -sv +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "/data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> xmvlog.log 2>/dev/null + + xmvhdl -work xpm -V93 $xmvhdl_opts \ + "/data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a compile.log; cat .tmp_log > xmvhdl.log 2>/dev/null + + xmvlog -work axi_infrastructure_v1_1_0 $xmvlog_opts +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> xmvlog.log 2>/dev/null + + xmvlog -work axi_vip_v1_1_15 $xmvlog_opts -sv +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/5753/hdl/axi_vip_v1_1_vl_rfs.sv" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> xmvlog.log 2>/dev/null + + xmvlog -work processing_system7_vip_v1_0_17 $xmvlog_opts -sv +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl/processing_system7_vip_v1_0_vl_rfs.sv" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> xmvlog.log 2>/dev/null + + xmvlog -work xil_defaultlib $xmvlog_opts +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/sim/NewExtInst_TOP_processing_system7_0_0.v" \ + "../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_clk_wiz.v" \ + "../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.v" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> xmvlog.log 2>/dev/null + + xmvhdl -work lib_cdc_v1_0_2 -V93 $xmvhdl_opts \ + "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> xmvhdl.log 2>/dev/null + + xmvhdl -work proc_sys_reset_v5_0_14 -V93 $xmvhdl_opts \ + "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> xmvhdl.log 2>/dev/null + + xmvhdl -work xil_defaultlib -V93 $xmvhdl_opts \ + "../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/sim/NewExtInst_TOP_proc_sys_reset_0_0.vhd" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> xmvhdl.log 2>/dev/null + + xmvlog -work xil_defaultlib $xmvlog_opts +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "../../../bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v" \ + "../../../bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v" \ + "../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/sim/NewExtInst_TOP_SPI_Con_0_0.v" \ + "../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/sim/NewExtInst_TOP_SPI_Con_0_1.v" \ + "../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/sim/NewExtInst_TOP_SPI_Con_0_2.v" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> xmvlog.log 2>/dev/null + + xmvlog -work generic_baseblocks_v2_1_1 $xmvlog_opts +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> xmvlog.log 2>/dev/null + + xmvlog -work axi_register_slice_v2_1_29 $xmvlog_opts +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> xmvlog.log 2>/dev/null + + xmvlog -work fifo_generator_v13_2_9 $xmvlog_opts +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ac72/simulation/fifo_generator_vlog_beh.v" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> xmvlog.log 2>/dev/null + + xmvhdl -work fifo_generator_v13_2_9 -V93 $xmvhdl_opts \ + "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.vhd" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> xmvhdl.log 2>/dev/null + + xmvlog -work fifo_generator_v13_2_9 $xmvlog_opts +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.v" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> xmvlog.log 2>/dev/null + + xmvlog -work axi_data_fifo_v2_1_28 $xmvlog_opts +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> xmvlog.log 2>/dev/null + + xmvlog -work axi_crossbar_v2_1_30 $xmvlog_opts +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> xmvlog.log 2>/dev/null + + xmvlog -work xil_defaultlib $xmvlog_opts +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/sim/NewExtInst_TOP_xbar_0.v" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> xmvlog.log 2>/dev/null + + xmvhdl -work xil_defaultlib -V93 $xmvhdl_opts \ + "../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/sim/NewExtInst_TOP_rst_clk_wiz_0_100M_0.vhd" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> xmvhdl.log 2>/dev/null + + xmvlog -work axi_protocol_converter_v2_1_29 $xmvlog_opts +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> xmvlog.log 2>/dev/null + + xmvlog -work xil_defaultlib $xmvlog_opts +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" +incdir+"../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \ + "../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_auto_pc_0/sim/NewExtInst_TOP_auto_pc_0.v" \ + "../../../bd/NewExtInst_TOP/sim/NewExtInst_TOP.v" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> xmvlog.log 2>/dev/null + + xmvlog -work xil_defaultlib $xmvlog_opts \ + glbl.v \ + 2>&1 | tee -a compile.log; cat .tmp_log >> xmvlog.log 2>/dev/null +} + +# RUN_STEP: +elaborate() +{ + xmelab $xmelab_opts $design_libs_elab xil_defaultlib.NewExtInst_TOP xil_defaultlib.glbl +} + +# RUN_STEP: +simulate() +{ + xmsim $xmsim_opts xil_defaultlib.NewExtInst_TOP -input simulate.do +} + +# STEP: setup +setup() +{ + # delete previous files for a clean rerun + if [[ ($b_reset_run == 1) ]]; then + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + fi + + # delete previous log files + if [[ ($b_reset_log == 1) ]]; then + reset_log + echo -e "INFO: Simulation run log files deleted.\n" + exit 0 + fi + + # add any setup/initialization commands here:- + + # + +} + +# simulator index file/library directory processing +init_lib() +{ + if [[ ($b_keep_index == 1) ]]; then + # keep previous design library mappings + true + else + # define design library mappings + create_lib_mappings + fi + + if [[ ($b_keep_index == 1) ]]; then + # do not recreate design library directories + true + else + # create design library directories + create_lib_dir + fi +} + +# define design library mappings +create_lib_mappings() +{ + file="hdl.var" + touch $file + + file="cds.lib" + if [[ -e $file ]]; then + if [[ ($lib_map_path == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($lib_map_path == "") ]]; then + lib_map_path="/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/compile_simlib/xcelium" + fi + + if [[ ($lib_map_path != "") ]]; then + incl_ref="INCLUDE $lib_map_path/cds.lib" + echo $incl_ref >> $file + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="DEFINE $lib $sim_lib_dir/$lib" + echo $mapping >> $file + done +} + +# create design library directory +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmvlog.log xmvhdl.log xmsc.log compile.log elaborate.log simulate.log diag_report.log xsc_report.log NewExtInst_TOP_sc.so .tmp_log xcelium_lib waves.shm c.obj) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# delete generated log files from the previous run +reset_log() +{ + files_to_remove=(xmvlog.log xmvhdl.log xmsc.log compile.log elaborate.log simulate.log diag_report.log xsc_report.log .tmp_log) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# check switch argument value +check_arg_value() +{ + if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "elaborate") && ($2 != "simulate")) ]];then + echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then + echo -e "ERROR: Simulation library directory path not specified (type \"./NewExtInst_TOP.sh -help\" for more information)\n" + exit 1 + fi +} + +# check command line arguments +check_args() +{ + arg_count=$# + if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then + usage + fi + while [[ "$#" -gt 0 ]]; do + case $1 in + -step) check_arg_value $1 $2;step=$2; b_step=1; shift;; + -lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;; + -gen_bypass) b_gen_bypass=1 ;; + -reset_run) b_reset_run=1 ;; + -reset_log) b_reset_log=1 ;; + -keep_index) b_keep_index=1 ;; + -noclean_files) b_noclean_files=1 ;; + -help|-h) ;; + *) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;; + esac + shift + done + + # -reset_run is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then + echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -reset_log is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then + echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -keep_index is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then + echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -noclean_files is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then + echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi +} + +# script usage +usage() +{ + msg="Usage: NewExtInst_TOP.sh [-help]\n\ +Usage: NewExtInst_TOP.sh [-step]\n\ +Usage: NewExtInst_TOP.sh [-lib_map_path]\n\ +Usage: NewExtInst_TOP.sh [-reset_run]\n\ +Usage: NewExtInst_TOP.sh [-reset_log]\n\ +Usage: NewExtInst_TOP.sh [-keep_index]\n\ +Usage: NewExtInst_TOP.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-step ] -- Execute specified step (simulate)\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\ +file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\ +NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\ +NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\ +[-reset_log] -- Delete simulator generated log files from the previous run\n\n\ +[-keep_index] -- Keep simulator index file settings from the previous run\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n" + echo -e $msg + exit 0 +} + +# initialize globals +step="" +lib_map_path="" +b_step=0 +b_lib_map_path=0 +b_gen_bypass=0 +b_reset_run=0 +b_reset_log=0 +b_keep_index=0 +b_noclean_files=0 + +# launch script +run $* diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/README.txt b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/README.txt new file mode 100644 index 0000000..1d27b8b --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/README.txt @@ -0,0 +1,50 @@ +################################################################################ +# Vivado (TM) v2023.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and how to fetch design source file details +# from the file_info.txt file. +# +# Generated by export_simulation on Fri May 15 15:32:22 CST 2026 +# +################################################################################ + +1. Steps to run the generated simulation script + +From the shell prompt in the current directory, issue the following command:- + +./NewExtInst_TOP.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first calls the 'check_args' function, the purpose of which +is to verify the generated script arguments and print error if incorrect switch +is specified. The 'run' function then calls the 'setup' function, the purpose of +which is to specify custom or initialization commands. The function also executes +following sub-functions:- +'reset_run' if -reset_run switch is specified. +'reset_log' if -reset_log switch is specified. + +The purpose of 'reset_run' function' is to delete the simulator generated design +data from the previous run and the purpose of 'reset_log' function' is to delete +the simulator generated log files. + +The 'run' function then calls the 'init_lib' function, the purpose of which is to +create design library mappings and directories. This function is called before the +'compile' step. By default, if '-step' switch is specified with the script then the +script will execute that specfic step, else it will execute all steps applicable +for the target simulator. + +For more information on the script, please type './NewExtInst_TOP.sh -help' + +2. Design source file information + +export_simulation generates a 'file_info.txt' file that contains design file information +based on the compile order when export_simulation was executed from Vivado. The file +contains information about the file name, type, library it is compiled into, whether +it is part of the IP, associated library, file path information in a comma separated +format. This file can be parsed to extract the required information for generating a +custom script or can be read from verification test infra. + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/SPI_Con.h b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/SPI_Con.h new file mode 100755 index 0000000..5278bdd --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/SPI_Con.h @@ -0,0 +1,107 @@ + +#ifndef SPI_CON_H +#define SPI_CON_H + + +/****************** Include Files ********************/ +#include "xil_types.h" +#include "xstatus.h" + +#define SPI_CON_S00_AXI_SLV_REG0_OFFSET 0 +#define SPI_CON_S00_AXI_SLV_REG1_OFFSET 4 +#define SPI_CON_S00_AXI_SLV_REG2_OFFSET 8 +#define SPI_CON_S00_AXI_SLV_REG3_OFFSET 12 +#define SPI_CON_S00_AXI_SLV_REG4_OFFSET 16 +#define SPI_CON_S00_AXI_SLV_REG5_OFFSET 20 +#define SPI_CON_S00_AXI_SLV_REG6_OFFSET 24 +#define SPI_CON_S00_AXI_SLV_REG7_OFFSET 28 +#define SPI_CON_S00_AXI_SLV_REG8_OFFSET 32 +#define SPI_CON_S00_AXI_SLV_REG9_OFFSET 36 +#define SPI_CON_S00_AXI_SLV_REG10_OFFSET 40 +#define SPI_CON_S00_AXI_SLV_REG11_OFFSET 44 +#define SPI_CON_S00_AXI_SLV_REG12_OFFSET 48 +#define SPI_CON_S00_AXI_SLV_REG13_OFFSET 52 +#define SPI_CON_S00_AXI_SLV_REG14_OFFSET 56 +#define SPI_CON_S00_AXI_SLV_REG15_OFFSET 60 +#define SPI_CON_S00_AXI_SLV_REG16_OFFSET 64 +#define SPI_CON_S00_AXI_SLV_REG17_OFFSET 68 +#define SPI_CON_S00_AXI_SLV_REG18_OFFSET 72 +#define SPI_CON_S00_AXI_SLV_REG19_OFFSET 76 +#define SPI_CON_S00_AXI_SLV_REG20_OFFSET 80 +#define SPI_CON_S00_AXI_SLV_REG21_OFFSET 84 +#define SPI_CON_S00_AXI_SLV_REG22_OFFSET 88 +#define SPI_CON_S00_AXI_SLV_REG23_OFFSET 92 +#define SPI_CON_S00_AXI_SLV_REG24_OFFSET 96 +#define SPI_CON_S00_AXI_SLV_REG25_OFFSET 100 +#define SPI_CON_S00_AXI_SLV_REG26_OFFSET 104 +#define SPI_CON_S00_AXI_SLV_REG27_OFFSET 108 +#define SPI_CON_S00_AXI_SLV_REG28_OFFSET 112 +#define SPI_CON_S00_AXI_SLV_REG29_OFFSET 116 +#define SPI_CON_S00_AXI_SLV_REG30_OFFSET 120 +#define SPI_CON_S00_AXI_SLV_REG31_OFFSET 124 + + +/**************************** Type Definitions *****************************/ +/** + * + * Write a value to a SPI_CON register. A 32 bit write is performed. + * If the component is implemented in a smaller width, only the least + * significant data is written. + * + * @param BaseAddress is the base address of the SPI_CONdevice. + * @param RegOffset is the register offset from the base to write to. + * @param Data is the data written to the register. + * + * @return None. + * + * @note + * C-style signature: + * void SPI_CON_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data) + * + */ +#define SPI_CON_mWriteReg(BaseAddress, RegOffset, Data) \ + Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data)) + +/** + * + * Read a value from a SPI_CON register. A 32 bit read is performed. + * If the component is implemented in a smaller width, only the least + * significant data is read from the register. The most significant data + * will be read as 0. + * + * @param BaseAddress is the base address of the SPI_CON device. + * @param RegOffset is the register offset from the base to write to. + * + * @return Data is the data from the register. + * + * @note + * C-style signature: + * u32 SPI_CON_mReadReg(u32 BaseAddress, unsigned RegOffset) + * + */ +#define SPI_CON_mReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (RegOffset)) + +/************************** Function Prototypes ****************************/ +/** + * + * Run a self-test on the driver/device. Note this may be a destructive test if + * resets of the device are performed. + * + * If the hardware system is not built correctly, this function may never + * return to the caller. + * + * @param baseaddr_p is the base address of the SPI_CON instance to be worked on. + * + * @return + * + * - XST_SUCCESS if all self-test code passed + * - XST_FAILURE if any self-test code failed + * + * @note Caching must be turned off for this function to work. + * @note Self test may fail if data memory and device are not on the same bus. + * + */ +XStatus SPI_CON_Reg_SelfTest(void * baseaddr_p); + +#endif // SPI_CON_H diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/SPI_Con.mdd b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/SPI_Con.mdd new file mode 100755 index 0000000..4bd813f --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/SPI_Con.mdd @@ -0,0 +1,10 @@ + + +OPTION psf_version = 2.1; + +BEGIN DRIVER SPI_Con + OPTION supported_peripherals = (SPI_Con); + OPTION copyfiles = all; + OPTION VERSION = 1.0; + OPTION NAME = SPI_Con; +END DRIVER diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/SPI_Con.tcl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/SPI_Con.tcl new file mode 100755 index 0000000..7f913c9 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/SPI_Con.tcl @@ -0,0 +1,5 @@ + + +proc generate {drv_handle} { + xdefine_include_file $drv_handle "xparameters.h" "SPI_Con" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR" +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/file_info.txt b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/file_info.txt new file mode 100644 index 0000000..7320d80 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/file_info.txt @@ -0,0 +1,39 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +xpm_cdc.sv,systemverilog,xpm,../../../../../data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +xpm_memory.sv,systemverilog,xpm,../../../../../data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +xpm_VCOMP.vhd,vhdl,xpm,../../../../../data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi_infrastructure_v1_1_vl_rfs.v,verilog,axi_infrastructure_v1_1_0,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +axi_vip_v1_1_vl_rfs.sv,systemverilog,axi_vip_v1_1_15,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/5753/hdl/axi_vip_v1_1_vl_rfs.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +processing_system7_vip_v1_0_vl_rfs.sv,systemverilog,processing_system7_vip_v1_0_17,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl/processing_system7_vip_v1_0_vl_rfs.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" 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b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/hdl.var b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/hdl.var new file mode 100644 index 0000000..e69de29 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/libps7.dll b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/libps7.dll new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/libps7.dll @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/libps7.so b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/libps7.so new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/libps7.so @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/libremoteport.dll b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/libremoteport.dll new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/libremoteport.dll @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/libremoteport.so b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/libremoteport.so new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/libremoteport.so @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/ps7_init.h b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/ps7_init.h new file mode 100755 index 0000000..224d7ea --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/ps7_init.h @@ -0,0 +1,117 @@ +/****************************************************************************** +* +* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + + + + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 142857132 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 25000000 +#define FPGA1_FREQ 50000000 +#define FPGA2_FREQ 100000000 +#define FPGA3_FREQ 200000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/ps7_init.html b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/ps7_init.html new file mode 100755 index 0000000..9ca53bd --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/ps7_init.html @@ -0,0 +1,125613 @@ + + + + +Zynq PS configuration detail + + + +

    +
    + +
  • +
    Zynq PS Register Summary Viewer +
    +
    • +     +
    +
    +
    + +
    Zynq PS7 Summary Report +
    +     +
    User Configurations +
    +
    + +
    MIO Configurations +
    +     +
    + +
    CLK Configurations +
    +     +
    + +
    DDR Configurations +
    +     +
    + +
    SMC Configurations +
    +     +
    +
    +
    Select Version: + +
    +
    +
    Zynq Register View +
    +
    + +
    MIO Registers +
    +     + +
    PLL Registers +
    +     + +
    Clock Registers +
    +     + +
    DDR Registers +
    +     + +
    Peripherals Registers +
    +     +
    +
    This design is targeted for xc7z035 board (part number: xc7z035ffg676-2) + +
    +

    Zynq Design Summary

    + + + + + + + + + + + + + + + + + + + + + +
    +Device + +xc7z035 +
    +SpeedGrade + +-2 +
    +Part + +xc7z035ffg676-2 +
    +Description + +Zynq PS Configuration Report with register details +
    +Vendor + +Xilinx +
    +

    MIO Table View

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +MIO Pin + +Peripheral + +Signal + +IO Type + +Speed + +Pullup + +Direction +
    +MIO 0 + +SD 1 + +wp + +LVCMOS 3.3V + +slow + +enabled + +in +
    +MIO 1 + +Quad SPI Flash + +qspi0_ss_b + +LVCMOS 3.3V + +slow + +enabled + +out +
    +MIO 2 + +Quad SPI Flash + +qspi0_io[0] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 3 + +Quad SPI Flash + +qspi0_io[1] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 4 + +Quad SPI Flash + +qspi0_io[2] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 5 + +Quad SPI Flash + +qspi0_io[3]/HOLD_B + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 6 + +Quad SPI Flash + +qspi0_sclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 7 + + + + + + + + + + + + +
    +MIO 8 + +Quad SPI Flash + +qspi_fbclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 9 + +SD 1 + +cd + +LVCMOS 3.3V + +slow + +enabled + +in +
    +MIO 10 + +SD 1 + +data[0] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 11 + +SD 1 + +cmd + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 12 + +SD 1 + +clk + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 13 + +SD 1 + +data[1] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 14 + +SD 1 + +data[2] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 15 + +SD 1 + +data[3] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 16 + +Enet 0 + +tx_clk + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 17 + +Enet 0 + +txd[0] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 18 + +Enet 0 + +txd[1] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 19 + +Enet 0 + +txd[2] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 20 + +Enet 0 + +txd[3] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 21 + +Enet 0 + +tx_ctl + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 22 + +Enet 0 + +rx_clk + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 23 + +Enet 0 + +rxd[0] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 24 + +Enet 0 + +rxd[1] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 25 + +Enet 0 + +rxd[2] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 26 + +Enet 0 + +rxd[3] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 27 + +Enet 0 + +rx_ctl + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 28 + + + + + + + + + + + + +
    +MIO 29 + + + + + + + + + + + + +
    +MIO 30 + + + + + + + + + + + + +
    +MIO 31 + + + + + + + + + + + + +
    +MIO 32 + + + + + + + + + + + + +
    +MIO 33 + + + + + + + + + + + + +
    +MIO 34 + + + + + + + + + + + + +
    +MIO 35 + + + + + + + + + + + + +
    +MIO 36 + + + + + + + + + + + + +
    +MIO 37 + + + + + + + + + + + + +
    +MIO 38 + + + + + + + + + + + + +
    +MIO 39 + + + + + + + + + + + + +
    +MIO 40 + +SD 0 + +clk + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 41 + +SD 0 + +cmd + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 42 + +SD 0 + +data[0] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 43 + +SD 0 + +data[1] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 44 + +SD 0 + +data[2] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 45 + +SD 0 + +data[3] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 46 + +SD 0 + +wp + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 47 + +SD 0 + +cd + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 48 + +UART 1 + +tx + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 49 + +UART 1 + +rx + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 50 + + + + + + + + + + + + +
    +MIO 51 + + + + + + + + + + + + +
    +MIO 52 + +Enet 0 + +mdc + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 53 + +Enet 0 + +mdio + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +

    DDR Memory information

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Parameter name + +Value + +Description +
    +Enable DDR + +1 + +Enable DDR Controller of Zynq PS +
    +Memory Part + +MT41J256M16 RE-125 + + +
    +DRAM bus width + +32 Bit + +Select the desired data width. Refer to the Thechnical Reference Manual(TRM) for a detailed list of supported DDR data widths +
    +ECC + +Disabled + +ECC is supported only for data width of 16-bit +
    +BURST Length (lppdr only) + +8 + +Select the burst Length. It refers to the amount of data read/written after a read/write command is presented to the controller +
    +Internal Vref + +0 + + +
    +Operating Frequency (MHz) + +533.333333 + +Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade +
    +HIGH temperature + +Normal (0-85) + +Select the operating temparature +
    +DRAM IC bus width + +16 Bits + +Provide the width of the DRAM chip +
    +DRAM Device Capacity + +4096 MBits + + +
    +Speed Bin + +DDR3_1066F + +Provide the Speed Bin +
    +BANK Address Count + +3 + +Defines the bank to which an active an ACTIVE, READ, WRITE, or Precharge Command is being applied +
    +ROW Address Count + +15 + +Provide the Row address for ACTIVE commands +
    +COLUMN Address Count + +10 + +Provide the Row address for READ/WRITE commands +
    +CAS Latency + +7 + +Select the Column Access Strobe (CAS) Latency. It refers to the amount of time it takes for data to appear on the pins of the memory module +
    +CAS Write Latency + +6 + +Select the CAS Write Latency +
    +RAS to CAS Delay + +7 + +Provide the row address to column address delay time. tRCD is t he time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS) +
    +RECHARGE Time + +7 + +Precharge Time (tRP) is the number of clock cycles needed o terminate acces s to an open row of memory, and open access to the next row +
    +tRC (ns ) + +48.91 + +Provide the Row cycle time tRC (ns) +
    +tRASmin ( ns ) + +35.0 + +tRASmin (ns) is the minimum number of clock cycles required between an Active command and issuing the Precharge command +
    +tFAW + +40.0 + +It restricts the number of activates that can be done within a certain window of time +
    +ADDITIVE Latency + +0 + +Provide the Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths +
    +Write levelling + +1 + + +
    +Read gate + +1 + + +
    +Read gate + +1 + + +
    +DQS to Clock delay [0] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [1] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [2] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [3] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +Board delay [0] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [1] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [2] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [3] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +

    PS Clocks information

    +

    PS Reference Clock : 33.333333

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Peripheral + +PLL source + +Frequency (MHz) +
    +CPU 6x Freq (MHz) + +ARM PLL + +666.666687 +
    +QSPI Flash Freq (MHz) + +IO PLL + +142.857132 +
    +ENET0 Freq (MHz) + +IO PLL + +125.000000 +
    +SDIO Freq (MHz) + +IO PLL + +100.000000 +
    +SDIO Freq (MHz) + +IO PLL + +100.000000 +
    +UART Freq (MHz) + +IO PLL + +100.000000 +
    +FPGA0 Freq (MHz) + +IO PLL + +25.000000 +
    +FPGA1 Freq (MHz) + +IO PLL + +50.000000 +
    +FPGA2 Freq (MHz) + +IO PLL + +100.000000 +
    +FPGA3 Freq (MHz) + +IO PLL + +200.000000 +
    +

    ps7_pll_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: ARM PLL 10: DDR PLL 11: IO PLL This field is reset by POR only. +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for programming the PLL. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock and Rx Signals Select +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +FPGA1_CLK_CTRL + + +0XF8000180 + +32 + +RW + +0x000000 + +PL Clock 1 Output control +
    + +FPGA2_CLK_CTRL + + +0XF8000190 + +32 + +RW + +0x000000 + +PL Clock 2 output control +
    + +FPGA3_CLK_CTRL + + +0XF80001A0 + +32 + +RW + +0x000000 + +PL Clock 3 output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source of the Rx clock, control and data signals: 0: MIO 1: EMIO +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock and Rx Signals Select +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +7 + +700 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +701 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a03 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +5 + +500000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +500800 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )FPGA1_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA1_CLK_CTRL + +0XF8000180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA1_CLK_CTRL@0XF8000180 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 1 Output control +
    +

    +

    Register ( slcr )FPGA2_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA2_CLK_CTRL + +0XF8000190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +2 + +200000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA2_CLK_CTRL@0XF8000190 + +31:0 + +3f03f30 + + + +200500 + +PL Clock 2 output control +
    +

    +

    Register ( slcr )FPGA3_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA3_CLK_CTRL + +0XF80001A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA3_CLK_CTRL@0XF80001A0 + +31:0 + +3f03f30 + + + +100500 + +PL Clock 3 output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ratio: (When this register changes, no access are allowed to OCM.) 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +1 + +800 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec0c4d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +82 + +82 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reserved_reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Reserved. Do not modify. +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +Two_rank_cfg@0XF8006004 + +31:0 + +7ffff + + + +1082 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a1 + +2840 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4285b + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +13 + +13 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d3 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. In non-LPDDR mode, the minimum DRAM Write Latency (DDR2) supported is 3. In LPDDR mode, the required DRAM Write Latency of 1 is supported. Since write latency (CWL) min is 3, and DDR2 CWL is CL-1, the min (DDR2) CL supported is 4 +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +f + +3c00 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +5 + +28000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +5 + +2800000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +7282bce5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_en_dfi_dram_clk_disable + +23:23 + +800000 + +0 + +0 + +Enables the assertion of ddrc_dfi_dram_clk_disable. In DDR2/DDR3, only asserted in Self Refresh. In mDDR/LPDDR2, can be asserted in following: - during normal operation (Clock Stop), - in Power Down - in Self Refresh - In Deep Power Down +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +7fdffffc + + + +270872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffc3 + + + +0 + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2: Value loaded into EMR2 register DDR3: Value loaded into MR2 register LPDDR2: Value loaded into MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2: Value loaded into EMR3 register DDR3: Value loaded into MR3 register. Set Bit[2:0] to 3'b000. These bits are set appropriately by the Controller during Read Data eye training and Read DQS gate leveling. LPDDR2: Unused +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +b30 + +b30 + +DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2: Value loaded into EMR1register. (Bits[9:7] are for OCD and the setting in this reg is ignored. Controller sets this bits appropriately during initialization DDR3: Value loaded into MR1 register. Set Bit[7] to 0. This bit is set appropriately by the Controller during Write Leveling LPDDR2: Value loaded into MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40b30 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 8, Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 7, Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 6, Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 5, Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reserved_reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +Reserved. Do not modify. +
    +reserved_reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Reserved. Do not modify. +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3f03f + + + +3c008 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +10000 + + + +0 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum d'128) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_2d@0XF80060B4 + +31:0 + +200 + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of uncorrectable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on board topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +0: Use reg_phy_ctrl_slave_ratio for address/command timing slave DLL 1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_64@0XF8006190 + +31:0 + +6ffffefe + + + +40080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. This feature should only be enabled after LPDDR2 initialization is completed +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff5 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Powerdown mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQ pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQS pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +Drive and Slew controls for Clock pins of the DDR Interface +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SD1_WP_CD_SEL + + +0XF8000834 + +32 + +RW + +0x000000 + +SDIO 1 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQ pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQS pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for Clock pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1x: Enable External VREF for upper 16 bits +
    +reserved_VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Reserved. Do not modify. +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +reserved_REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +1 + + + +1 + +DDR IOB DCI Config +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialize flops in DCI system +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDR IOB DCI Config +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +DCI System Enable. Set to 1 if any IOs in DDR IO Bank use DCI Termination. DDR2, DDR3 and LPDDR2 (Silicon Revision 2.0+) configurations require this bit set to 1 +
    +reserved_VRP_TRI + +2:2 + +4 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_TRI + +3:3 + +8 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRP_OUT + +4:4 + +10 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT1 + +15:14 + +c000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update Mode. Use the values in the Calibration Table. +
    +reserved_INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_CLK + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLN + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLP + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_RST + +25:25 + +2000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7feffff + + + +823 + +DDR IOB DCI Config +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. 0: disable 1: enable +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables Pullup on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3f01 + + + +1601 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3f01 + + + +1601 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1680 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1680 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait, Input 10: NAND Flash IO Bit 7, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 12 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1680 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5, Input/Output 10: NAND Flash IO Bit 3, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 13 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1680 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1680 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1680 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1, Output 10: NAND Flash IO Bit 8, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2, Output 10: NAND Flash IO Bit 9, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110 TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3, Output 10: NAND Flash IO Bit 10, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6, Output 10: NAND Flash IO Bit 13, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3f01 + + + +1201 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +2e + +2e + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f002e + +SDIO 0 WP CD select +
    +

    +

    Register ( slcr )SD1_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD1_WP_CD_SEL + +0XF8000834 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO1_WP_SEL + +5:0 + +3f + +0 + +0 + +SDIO 1 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO1_CD_SEL + +21:16 + +3f0000 + +9 + +90000 + +SDIO 1 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD1_WP_CD_SEL@0XF8000834 + +31:0 + +3f003f + + + +90000 + +SDIO 1 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +Baud Rate Divider Register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud Rate Generator Register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control Register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode Register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +Baud Rate Divider Register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud Rate Generator Register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter 1: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: enable 1: disable, regardless of the value of RXEN +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed. +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed. +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control Register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +3ff + + + +20 + +UART Mode Register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes . If not set, then external pull up is required on HOLDb and WPn pins . Note that this bit doesn't affect the quad(4-bit) mode as Controller always drives these pins in quad mode. It is highly recommended to set this bit always(irrespective of mode of operation) while using QSPI +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This register controls which POR timer the PL will use for power-up. 0 - Use 64k timer 1 - Use 4k timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    ENET RESET

    +

    I2C RESET

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_LVL_INP_EN_0 + +3:3 + +8 + +1 + +8 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_0 + +2:2 + +4 + +1 + +4 + +Level shifter enable to drive signals from PS to PL +
    +USER_LVL_INP_EN_1 + +1:1 + +2 + +1 + +2 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_1 + +0:0 + +1 + +1 + +1 + +Level shifter enable to drive signals from PS to PL +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +Reserved. Do not modify. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +PL Reset 3 (FCLKRESETN3 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN3 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +PL Reset 2 (FCLKRESETN2 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN2 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +PL Reset 1 (FCLKRESETN1 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN1 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +PL Reset 0 (FCLKRESETN0 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN0 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    AFI2 SECURE REGISTER

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_3_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: CPU PLL 10: divided DDR PLL 11: IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +FPGA1_CLK_CTRL + + +0XF8000180 + +32 + +RW + +0x000000 + +PL Clock 1 Output control +
    + +FPGA2_CLK_CTRL + + +0XF8000190 + +32 + +RW + +0x000000 + +PL Clock 2 output control +
    + +FPGA3_CLK_CTRL + + +0XF80001A0 + +32 + +RW + +0x000000 + +PL Clock 3 output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source to generate the Rx clock: 0: MIO Rx clock, 1: EMIO Rx clock +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +7 + +700 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +701 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a03 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +5 + +500000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +500800 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )FPGA1_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA1_CLK_CTRL + +0XF8000180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA1_CLK_CTRL@0XF8000180 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 1 Output control +
    +

    +

    Register ( slcr )FPGA2_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA2_CLK_CTRL + +0XF8000190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +2 + +200000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA2_CLK_CTRL@0XF8000190 + +31:0 + +3f03f30 + + + +200500 + +PL Clock 2 output control +
    +

    +

    Register ( slcr )FPGA3_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA3_CLK_CTRL + +0XF80001A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA3_CLK_CTRL@0XF80001A0 + +31:0 + +3f03f30 + + + +100500 + +PL Clock 3 output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ration: 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +1 + +800 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec0c4d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config0 + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config1 + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 1. +
    + +PHY_Config2 + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 2. +
    + +PHY_Config3 + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 3. +
    + +phy_init_ratio0 + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio1 + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 1. +
    + +phy_init_ratio2 + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 2. +
    + +phy_init_ratio3 + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 3. +
    + +phy_rd_dqs_cfg0 + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg1 + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 1. +
    + +phy_rd_dqs_cfg2 + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 2. +
    + +phy_rd_dqs_cfg3 + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 3. +
    + +phy_wr_dqs_cfg0 + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg1 + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 1. +
    + +phy_wr_dqs_cfg2 + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 2. +
    + +phy_wr_dqs_cfg3 + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 3. +
    + +phy_we_cfg0 + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg1 + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 1. +
    + +phy_we_cfg2 + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 2. +
    + +phy_we_cfg3 + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 3. +
    + +wr_data_slv0 + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv1 + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 1. +
    + +wr_data_slv2 + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 2. +
    + +wr_data_slv3 + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 3. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port0 + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port1 + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 1. +
    + +axi_priority_wr_port2 + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 2. +
    + +axi_priority_wr_port3 + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 3. +
    + +axi_priority_rd_port0 + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port1 + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 1. +
    + +axi_priority_rd_port2 + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 2. +
    + +axi_priority_rd_port3 + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 3. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +82 + +82 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Rank configuration: 01: One Rank of DDR 11: Two Ranks of DDR Others: reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +Block read/write scheduling cycle count when Write requires changing ODT settings 00: 1 cycle 01: 2 cycles 10: 3 cycles others: reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0: schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1: schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81082 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a1 + +2840 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4285b + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +13 + +13 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d3 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +f + +3c00 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +5 + +28000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +5 + +2800000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +7282bce5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1: sdram device 0: non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: stop_clk will never be asserted. 1: enable the assertion of stop_clk to the PHY whenever a clock is not required +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2 and DDR3: Value written into the DRAM EMR2 register. LPDDR2: Value written into the DRAM MR3 register. +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2 and DDR3: Value written into the DRAM EMR3 register. LPDDR2: not used. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +b30 + +b30 + +DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2 and DDR3: Value written into the DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. LPDDR2: Value written into the DRAM MR2 register. +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40b30 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODTs must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config0 + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config0@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config1 + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config1@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 1. +
    +

    +

    Register ( slcr )PHY_Config2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config2 + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config2@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 2. +
    +

    +

    Register ( slcr )PHY_Config3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config3 + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config3@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_init_ratio0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio0 + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio0@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio1 + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio1@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 1. +
    +

    +

    Register ( slcr )phy_init_ratio2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio2 + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio2@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 2. +
    +

    +

    Register ( slcr )phy_init_ratio3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio3 + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio3@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 3. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg0 + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg0@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg1 + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg1@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg2 + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg2@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg3 + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg3@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg0 + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg0@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg1 + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg1@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg2 + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg2@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg3 + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg3@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_we_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg0 + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg0@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg1 + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg1@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 1. +
    +

    +

    Register ( slcr )phy_we_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg2 + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg2@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 2. +
    +

    +

    Register ( slcr )phy_we_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg3 + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg3@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 3. +
    +

    +

    Register ( slcr )wr_data_slv0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv0 + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv0@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv1 + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv1@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 1. +
    +

    +

    Register ( slcr )wr_data_slv2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv2 + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv2@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 2. +
    +

    +

    Register ( slcr )wr_data_slv3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv3 + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv3@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 3. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +0: (default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) 1: assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 0: Each Rank uses its own delay 1: Rank 0 delays are used for all ranks +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1: enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port0 + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port0@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port1 + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port1@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 1. +
    +

    +

    Register ( slcr )axi_priority_wr_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port2 + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port2@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 2. +
    +

    +

    Register ( slcr )axi_priority_wr_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port3 + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port3@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 3. +
    +

    +

    Register ( slcr )axi_priority_rd_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port0 + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port0@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port1 + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port1@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 1. +
    +

    +

    Register ( slcr )axi_priority_rd_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port2 + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port2@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 2. +
    +

    +

    Register ( slcr )axi_priority_rd_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port3 + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port3@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 3. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +0:All bank refresh Per bank refresh allows traffic to flow to other banks. 1:Per bank refresh Per bank refresh is not supported on all LPDDR2 devices. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Power-down mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 0 +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 1 +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDR IOB Slew for Address +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDR IOB Slew for Data +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDR IOB Slew for Diff +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDR IOB Slew for Clock +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SD1_WP_CD_SEL + + +0XF8000834 + +32 + +RW + +0x000000 + +SDIO 1 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 0 +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 1 +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDR IOB Slew for Address +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Data +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Diff +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Clock +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1X: Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors x0: Disable VREF pull-up for lower 16 bits x1: Enable VREF pull-up for lower 16 bits 0x: Disable VREF pull-up for upper 16 bits 1x: Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Enable test mode for VRP and VRN: 00: VRP/VRN test mode not used 11: VRP/VRN test mode enabled using vref based receiver. VRP/VRN control is set using the VRN_OUT, VRP_OUT, VRN_TRI, VRP_TRI fields in the DDRIOB_DCI_CTRL register +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0: no pull-up 1: enable pull-up +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. 0: disable 1: enable +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables pull-up on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3f01 + + + +1601 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3f01 + + + +1601 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1680 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1680 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait 10: NAND Flash IO Bit 7 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 12 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1680 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5 10: NAND Flash IO Bit 3 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 13 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1680 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1680 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1680 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1 10: NAND Flash IO Bit 8 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Output 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2 10: NAND Flash IO Bit 9 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110 TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3 10: NAND Flash IO Bit 10 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6 10: NAND Flash IO Bit 13 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3f01 + + + +1201 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +2e + +2e + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f002e + +SDIO 0 WP CD select +
    +

    +

    Register ( slcr )SD1_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD1_WP_CD_SEL + +0XF8000834 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO1_WP_SEL + +5:0 + +3f + +0 + +0 + +SDIO 1 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO1_CD_SEL + +21:16 + +3f0000 + +9 + +90000 + +SDIO 1 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD1_WP_CD_SEL@0XF8000834 + +31:0 + +3f003f + + + +90000 + +SDIO 1 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass 2 - 65535: baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: start break transmission, 1: stop break transmission. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: 1: start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 0: receiver timeout counter disabled, 1: receiver timeout counter is restarted. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter, 0: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter, 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: disable, 1: enable +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable, 1: enable. When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: 1: transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: 1: receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode: 0: Default UART mode 1: Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select: 0: APB clock, pclk 1: a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: 00: normal 01: automatic cho 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: 0: clock source is uart_clk 1: clock source is uart_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    ENET RESET

    +

    I2C RESET

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset: 0: No reset 1: ACP AXI interface reset output asserted +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0: No reset 1: AXDS3AXI interface reset output asserted +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0: No reset 1: AXDS2 AXI interface reset output asserted +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0: No reset 1: AXDS1 AXI interface reset output asserted +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0: No reset 1: AXDS0 AXI interface reset output asserted +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0: No reset 1: FPGA slave interface 1 reset is asserted +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0: No reset 1: FPGA slave interface 0 reset is asserted +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface: 1: soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0: No reset 1: FPGA master interface 1 reset is asserted +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0: No reset 1: FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 3 peripheral request reset output asserted +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 2 peripheral request reset output asserted +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 1 peripheral request reset output asserted +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 0 peripheral request reset output asserted +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0: No reset 1: FPGA 3 top level reset output asserted +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0: No reset 1: FPGA 2 top level reset output asserted +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0: No reset 1: FPGA 1 top level reset output asserted +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0: No reset 1: FPGA 0 top level reset output asserted +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_2_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CORTEX A9 Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status. 0 - ARM PLL out of lock. 1 - ARM PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is CPU PLL. 10 - Source for generated clock is DDR divided clock. 11 - Source for generated clock is IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CORTEX A9 Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status. 0 - DDR PLL out of lock. 1 - DDR PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Divisor value for the ddr_3xclk +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk) +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status. 0 - IO PLL out of lock. 1 - IO PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 RX Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Linear Quad-SPI Reference Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Reference Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Reference Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP 2X Clock Contol +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +FPGA 0 Output Clock Control +
    + +FPGA1_CLK_CTRL + + +0XF8000180 + +32 + +RW + +0x000000 + +FPGA 1 Output Clock Control +
    + +FPGA2_CLK_CTRL + + +0XF8000190 + +32 + +RW + +0x000000 + +FPGA 2 Output Clock Control +
    + +FPGA3_CLK_CTRL + + +0XF80001A0 + +32 + +RW + +0x000000 + +FPGA 3 Output Clock Control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +6:2:1 ratio clock, if set +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Selects the source used to generate the clock. 0 - Source for generated clock is GEM 0 MIO RX clock. 1 - Source for generated clock is GEM 0 FMIO RX clock. +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +Gigabit Ethernet MAC 0 RX Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source used to generate the clock. 1xx - Source for generated clock is Ethernet 0 FMIO clock. 00x - Source for generated clock is IO PLL. 010 - Source for generated clock is ARM PLL. 011 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +7 + +700 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +701 + +Linear Quad-SPI Reference Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO 0 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +SDIO 1 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a03 + +SDIO Reference Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Reference Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active 0 - Clock is disabled 1 - Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP 2X Clock Contol +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +5 + +500000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +500800 + +FPGA 0 Output Clock Control +
    +

    +

    Register ( slcr )FPGA1_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA1_CLK_CTRL + +0XF8000180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA1_CLK_CTRL@0XF8000180 + +31:0 + +3f03f30 + + + +400500 + +FPGA 1 Output Clock Control +
    +

    +

    Register ( slcr )FPGA2_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA2_CLK_CTRL + +0XF8000190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +2 + +200000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA2_CLK_CTRL@0XF8000190 + +31:0 + +3f03f30 + + + +200500 + +FPGA 2 Output Clock Control +
    +

    +

    Register ( slcr )FPGA3_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA3_CLK_CTRL + +0XF80001A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA3_CLK_CTRL@0XF80001A0 + +31:0 + +3f03f30 + + + +100500 + +FPGA 3 Output Clock Control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Enable the 6:2:1 mode. 1 for 6:3:2:1. 0 for 4:2:2:1. +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +6:2:1 ratio clock, if set +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet MAC 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet MAC 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +1 + +800 + +SDIO 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +LQSPI AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec0c4d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two rank configuration register +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control register +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control register +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control register +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters register 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters register 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters register 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters register 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters register 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM initialization parameters register +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access register +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access register +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM burst 8 read/write register +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ register +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM bank address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT register +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO register +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration register +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold register +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller register 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller register 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller register 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller register 4 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters register +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters register +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown register +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control register +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug register +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing register +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear register +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction register +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status register +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count register +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub register +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control register (2) +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control register (3) +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask register +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 Register +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 Register +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 Register +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 Register +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control Register +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +82 + +82 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Only present for multi-rank configurations. Each bit represents one rank. 1=populated; 0=unpopulated 01 = One Rank 11 = Two Ranks Others = Reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +00 = block read/write scheduling for 1-cycle when Write requires changing ODT settings 01 = block read/write scheduling for 2 cycles when Write requires changing ODT settings 10 = block read/write scheduling for 3 cycles when Write requires changing ODT settings 11 = Reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0 = schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1 = schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81082 + +Two rank configuration register +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of clocks that the HPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control register +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control register +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control register +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a1 + +2840 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks DRAM RELATED +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4285b + +DRAM Parameters register 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +13 + +13 + +Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. LPDDR2 mode: Set this to the larger of tCKE or tCKESR. Non-LPDDR2 designs: Set this to tCKE value. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d3 + +DRAM Parameters register 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2/3 -> WL -1 LPDDR -> 1 LPDDR2 ->WL Where WL = Write Latency of DRAM DRAM RELATED. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. non-LPDDR2 -> RL + BL/2 + 2 - WL LPDDR2 -> RL + BL/2 + RU(tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +f + +3c00 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +5 + +28000 + +tXP: Minimum time after power down exit to any operation. DRAM RELATED. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +5 + +2800000 + +Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency DRAM RELATED +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +7282bce5 + +DRAM Parameters register 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1 DRAM RELATED +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1 = sdram device 0 = non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-mobile DRAM device in use. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +1=enable the assertion of stop_clk to the PHY whenever a clock is not required by LPDDR/ LPDDR2. 0=stop_clk will never be asserted. Note: This is only present for implementations supporting LPDDR/LPDDR2 devices. +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Set to RL. Time from Read command to Read data on DRAM interface. Unit: clocks This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. RL = Read Latency of DRAM Note: This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1 = disable the pad power down feature 0 = Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters register 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1 = DDRC will use 2T timing 0 = DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1 = Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and 'ddrc_reg_mr_wr_busy' is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +Mode register address - for non-LPDDR2 modes. This register is don't care in LPDDR2 mode 00 = MR0 01 = MR1 10 = MR2 11 = MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +Mode register write data - for non-LPDDR2 modes. For LPDDR2, these 16-bits are interpreted as Writes: \'7bMR Addr[7:0], MR Data[7:0]\'7d. Reads: \'7bMR Addr[7:0], Don't Care[7:0]\'7d +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 1 = Indicates that mode register write / read operation is in progress. 0 = Indicates that the core can initiate a mode register write / read operation. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 1 = read 0 = write +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 1'b0 by default. This bit will be cleared (1'b0), whenever a Mode Register Read command is issued. This bit will be set to 1'b1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters register 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands DRAM RELATED Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM initialization parameters register +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +Non LPDDR2- Value to be loaded into DRAM EMR2 registers. For LPDDR2 - Value to Write to the MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +Non LPDDR2- Value to be loaded into DRAM EMR3 registers. Used in non-LPDDR2 designs only. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access register +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +b30 + +b30 + +Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +Non LPDDR2-Value to be loaded into DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. For LPDDR2 - Value to Write to the MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40b30 + +DRAM EMR, MR access register +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +This controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. In LPDDR and LPDDR2, Burst length of 16 is supported only in Half Bus Width mode. Every input read/write command has 4 cycles of data associated with it and that is not enough data for doing Burst Length16 in Full Bus Width mode. 0010 - Burst length of 4 0100 - Burst length of 8 1000 - Burst length of 16 (only supported for LPDDR AND LPDDR2) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM burst 8 read/write register +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Active Low signal. When asserted (0), all incoming transactions will be forced to low priority. Forcing the incoming transactions to low priority implicitly turns OFF Bypass. Otherwise, HPR is allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. This bit is intended to be switched on-the-fly +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ register +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14 Internal Base: 5 The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Selects the address bits used as DRAM bank address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Selects the address bits used as DRAM column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Selects the address bits used as DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODT's must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT register +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1 = stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO register +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration register +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable for LPDDR and LPDDR2 modes. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold register +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +When 1, disable Write Combine +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to '0', auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller register 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +1 - Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on 'urgent' input coming from AXI master. 0 - Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 1'b0. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller register 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) Only present in designs that support DDR3 and LPDDR2 devices. +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Only present in designs that support DDR3 devices +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. Only present in designs that support DDR3 devices. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller register 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller register 4 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters register +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters register +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +1 - Controller puts the DRAM into Deep Powerdown mode when the transaction store is empty. 0 - Brings Controller out of Deep Powerdown mode Present only in designs configured to support LPDDR or LPDDR2 FOR PERFORMANCE ONLY. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown register +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +1 = Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0 = Write leveling disabled. +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +1 = Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0= Read DQS gate leveling is disabled. +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +1 = Read Data Eye training mode has been enabled as part of init sequence. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control register +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1 - Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0 - Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug register +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. Non-LPDDR -> RL-1 LPDDR -> RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing register +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear register +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when a correctable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction register +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when an uncorrectable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status register +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count register +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 3'b000 (No ECC) and 3'b100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 3'b100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 - No ECC, 001 - Reserved 010 - Parity 011 - Reserved 100 - SEC/DED over 1-beat 101 - SEC/DED over multiple beats 110 - Device Correction 111 - Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +This feature is NOT supported. Only default value works. 1 - Disable ECC scrubs 0 - Enable ECC scrubs Valid only when reg_ddrc_ecc_mode = 3'b100. +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub register +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +1 = run scan test at full clock speed but with less coverage 0 = run scan test at slow clock speed but with high coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 2'b00: constant pattern (0 repeated on each DQ bit) 2'b01: low freq pattern (00001111 repeated on each DQ bit) 2'b10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +1=assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) 0=(default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0 = Select algorithm # 1'b1 = Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 1- Rank 0 delays are used for all ranks 0- Each Rank uses its own delay +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-LPDDR DRAM device in use. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1=enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control register (2) +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control register (3) +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +This register must be set based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask register +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +1=LPDDR2 DRAM device in Use. 0=non-LPDDR2 device in use Present only in designs configured to support LPDDR2. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +1:Per bank refresh 0:All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported on all LPDDR2 devices. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 Register +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. Present only in designs configured to support LPDDR2. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 Register +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 Register +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 Register +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control Register +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0 = DDRC Init 1 = Normal operation 2 = Power-down mode 3 = Self-refresh mode 4 and above = deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDRIOB Address 0 Configuartion Register +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDRIOB Address 1 Configuration Register +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDRIOB Differential Clock Configuration Register +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Address Register +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Data Register +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Differential Strobe Register +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Clcok Register +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDRIOB DDR Control Register +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Control for Pin 0 +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Control for Pin 1 +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Control for Pin 2 +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Control for Pin 3 +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Control for Pin 4 +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Control for Pin 5 +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Control for Pin 6 +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Control for Pin 8 +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Control for Pin 9 +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Control for Pin 10 +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Control for Pin 11 +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Control for Pin 12 +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Control for Pin 13 +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Control for Pin 14 +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Control for Pin 15 +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Control for Pin 16 +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Control for Pin 17 +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Control for Pin 18 +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Control for Pin 19 +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Control for Pin 20 +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Control for Pin 21 +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Control for Pin 22 +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Control for Pin 23 +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Control for Pin 24 +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Control for Pin 25 +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Control for Pin 26 +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Control for Pin 27 +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Control for Pin 40 +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Control for Pin 41 +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Control for Pin 42 +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Control for Pin 43 +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Control for Pin 44 +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Control for Pin 45 +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Control for Pin 46 +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Control for Pin 47 +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Control for Pin 48 +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Control for Pin 49 +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Control for Pin 52 +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Control for Pin 53 +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select register +
    + +SD1_WP_CD_SEL + + +0XF8000834 + +32 + +RW + +0x000000 + +SDIO 1 WP CD select register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDRIOB Address 0 Configuartion Register +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDRIOB Address 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDRIOB Differential Clock Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDRIOB Drive Slew Address Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Data Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Differential Strobe Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Clcok Register +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output 0001 - VREF = 0.6V for LPDDR2 with 1.2V IO 0010 - VREF = 0.675V for LPDDR3 1.35 V IO 0100 - VREF = 0.75V for DDR3 with 1.5V IO 1000 - VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input X0 - Disable External VREF for lower 16 bits X1 - Enable External VREF for lower 16 bits 0X - Disable External VREF for upper 16 bits 1X - Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors X0 - Disable VREF pull-up for lower 16 bits X1 - Enable VREF pull-up for lower 16 bits 0X - Disable VREF pull-up for upper 16 bits 1X - Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0 - VRP/VRN not used 1 - VRP/VRN used as refio +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +73ff + + + +260 + +DDRIOB DDR Control Register +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3f01 + + + +1601 + +MIO Control for Pin 0 +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Control for Pin 1 +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 2 +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Control for Pin 3 +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 4 +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 5 +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 6 +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 8 +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3f01 + + + +1601 + +MIO Control for Pin 9 +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 10 +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 11 +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_wait- (SRAM Wait State indicator) 2= nand, Input, smc_nand_data_in[7]- (NAND Data Bus) = nand, Output, smc_nand_data_out[7]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 12 +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[5]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[5]- (SRAM Data) 2= nand, Input, smc_nand_data_in[3]- (NAND Data Bus) = nand, Output, smc_nand_data_out[3]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 13 +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 14 +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 15 +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[4]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[1]- (SRAM Address) 2= nand, Input, smc_nand_data_in[8]- (NAND Data Bus) = nand, Output, smc_nand_data_out[8]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 16 +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[5]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[2]- (SRAM Address) 2= nand, Input, smc_nand_data_in[9]- (NAND Data Bus) = nand, Output, smc_nand_data_out[9]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 17 +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[6]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[3]- (SRAM Address) 2= nand, Input, smc_nand_data_in[10]- (NAND Data Bus) = nand, Output, smc_nand_data_out[10]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 18 +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 19 +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 20 +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[6]- (SRAM Address) 2= nand, Input, smc_nand_data_in[13]- (NAND Data Bus) = nand, Output, smc_nand_data_out[13]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 21 +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 22 +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 23 +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 24 +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 25 +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 26 +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 27 +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 40 +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 41 +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 42 +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 43 +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 44 +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 45 +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3f01 + + + +1201 + +MIO Control for Pin 46 +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Control for Pin 47 +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Control for Pin 48 +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Control for Pin 49 +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 52 +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 53 +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +2e + +2e + +SDIO0 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO0 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f002e + +SDIO 0 WP CD select register +
    +

    +

    Register ( slcr )SD1_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD1_WP_CD_SEL + +0XF8000834 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO1_WP_SEL + +5:0 + +3f + +0 + +0 + +SDIO1 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SDIO1_CD_SEL + +21:16 + +3f0000 + +9 + +90000 + +SDIO1 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SD1_WP_CD_SEL@0XF8000834 + +31:0 + +3f003f + + + +90000 + +SDIO 1 WP CD select register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value 0 = Disables baud_sample 1 = Clock divisor bypass 2 - 65535 = baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break. 1 = stop transmission of the break. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break 1 = start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter 1 = receiver timeout counter is restarted +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable. 1, the transmitter is disabled +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable. 1, the transmitter is enabled, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable. 1= receiver is enabled +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable. 1=the receiver logic is enabled, provided RXDIS field is set to 0 +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for TX data path. 1=the transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for RX data path 1=receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode 0 : Default UART mode 1 : Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select 0 : APB clock, pclk 1 : a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode 00 = normal 01 = automatic cho 10 = local loopback 11 = remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits 00 = 1 stop bit 01 = 1.5 stop bits 10 = 2 stop bits 11 = reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select. 000 = even parity 001 = odd parity 010 = forced to 0 parity (space) 011 = forced to 1 parity (mark) 1xx = no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select 11 = 6 bits 10 = 7 bits 01 / 00 = 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +clock source select 1 = clock source is uart_clk/8 0 = clock source is uart_clk +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    ENET RESET

    +

    I2C RESET

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset. 0 - No reset. 1 - ACP AXI interface reset output asserted. +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS3AXI interface reset output asserted. +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS2 AXI interface reset output asserted. +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS1 AXI interface reset output asserted. +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS0 AXI interface reset output asserted. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 1 reset is asserted. +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 0 reset is asserted. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface 1 soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0 - No reset. 1 - FPGA master interface 1 reset is asserted. +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0 - No reset. 1 - FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 3 peripheral request reset output asserted. +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 2 peripheral request reset output asserted. +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 1 peripheral request reset output asserted. +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 0 peripheral request reset output asserted. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0 - No reset. 1 - FPGA 3 top level reset output asserted. +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0 - No reset. 1 - FPGA 2 top level reset output asserted. +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0 - No reset. 1 - FPGA 1 top level reset output asserted. +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0 - No reset. 1 - FPGA 0 top level reset output asserted. +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_1_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/ps7_init.tcl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/ps7_init.tcl new file mode 100755 index 0000000..85a6f34 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/ps7_init.tcl @@ -0,0 +1,781 @@ +proc ps7_pll_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000701 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00500800 + mask_write 0XF8000180 0x03F03F30 0x00400500 + mask_write 0XF8000190 0x03F03F30 0x00200500 + mask_write 0XF80001A0 0x03F03F30 0x00100500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_3_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x0007FFFF 0x00001082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006024 0x0FFFFFC3 0x00000000 + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00000003 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x0003F03F 0x0003C008 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x00010000 0x00000000 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x00000200 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFCF 0x40000001 + mask_write 0XF800611C 0x7FFFFFCF 0x40000001 + mask_write 0XF8006120 0x7FFFFFCF 0x40000001 + mask_write 0XF8006124 0x7FFFFFCF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0x6FFFFEFE 0x00040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000703FF 0x000003FF + mask_write 0XF800620C 0x000703FF 0x000003FF + mask_write 0XF8006210 0x000703FF 0x000003FF + mask_write 0XF8006214 0x000703FF 0x000003FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF5 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000001 0x00000001 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001601 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003F01 0x00001601 + mask_write 0XF8000728 0x00003FFF 0x00001680 + mask_write 0XF800072C 0x00003FFF 0x00001680 + mask_write 0XF8000730 0x00003FFF 0x00001680 + mask_write 0XF8000734 0x00003FFF 0x00001680 + mask_write 0XF8000738 0x00003FFF 0x00001680 + mask_write 0XF800073C 0x00003FFF 0x00001680 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003F01 0x00001201 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F002E + mask_write 0XF8000834 0x003F003F 0x00090000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x000003FF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 +} +proc ps7_post_config_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_3_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000701 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00500800 + mask_write 0XF8000180 0x03F03F30 0x00400500 + mask_write 0XF8000190 0x03F03F30 0x00200500 + mask_write 0XF80001A0 0x03F03F30 0x00100500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_2_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001601 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003F01 0x00001601 + mask_write 0XF8000728 0x00003FFF 0x00001680 + mask_write 0XF800072C 0x00003FFF 0x00001680 + mask_write 0XF8000730 0x00003FFF 0x00001680 + mask_write 0XF8000734 0x00003FFF 0x00001680 + mask_write 0XF8000738 0x00003FFF 0x00001680 + mask_write 0XF800073C 0x00003FFF 0x00001680 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003F01 0x00001201 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F002E + mask_write 0XF8000834 0x003F003F 0x00090000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 +} +proc ps7_post_config_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_2_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000701 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00500800 + mask_write 0XF8000180 0x03F03F30 0x00400500 + mask_write 0XF8000190 0x03F03F30 0x00200500 + mask_write 0XF80001A0 0x03F03F30 0x00100500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_1_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x000073FF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001601 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003F01 0x00001601 + mask_write 0XF8000728 0x00003FFF 0x00001680 + mask_write 0XF800072C 0x00003FFF 0x00001680 + mask_write 0XF8000730 0x00003FFF 0x00001680 + mask_write 0XF8000734 0x00003FFF 0x00001680 + mask_write 0XF8000738 0x00003FFF 0x00001680 + mask_write 0XF800073C 0x00003FFF 0x00001680 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003F01 0x00001201 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F002E + mask_write 0XF8000834 0x003F003F 0x00090000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 +} +proc ps7_post_config_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_1_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +set PCW_SILICON_VER_1_0 "0x0" +set PCW_SILICON_VER_2_0 "0x1" +set PCW_SILICON_VER_3_0 "0x2" +set APU_FREQ 666666666 + + + +proc mask_poll { addr mask } { + set count 1 + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + while { $maskedval == 0 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + set count [ expr { $count + 1 } ] + if { $count == 100000000 } { + puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask" + break + } + } +} + + + +proc mask_delay { addr val } { + set delay [ get_number_of_cycles_for_delay $val ] + perf_reset_and_start_timer + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + while { $maskedval == 1 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + } + perf_reset_clock +} + +proc ps_version { } { + set si_ver "0x[string range [mrd 0xF8007080] end-8 end]" + set mask_sil_ver "0x[expr {$si_ver >> 28}]" + return $mask_sil_ver; +} + +proc ps7_post_config {} { + set saved_mode [configparams force-mem-accesses] + configparams force-mem-accesses 1 + + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_post_config_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_post_config_2_0 + } else { + ps7_post_config_3_0 + } + configparams force-mem-accesses $saved_mode +} + +proc ps7_debug {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_debug_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_debug_2_0 + } else { + ps7_debug_3_0 + } +} +proc ps7_init {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_mio_init_data_1_0 + ps7_pll_init_data_1_0 + ps7_clock_init_data_1_0 + ps7_ddr_init_data_1_0 + ps7_peripherals_init_data_1_0 + #puts "PCW Silicon Version : 1.0" + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_mio_init_data_2_0 + ps7_pll_init_data_2_0 + ps7_clock_init_data_2_0 + ps7_ddr_init_data_2_0 + ps7_peripherals_init_data_2_0 + #puts "PCW Silicon Version : 2.0" + } else { + ps7_mio_init_data_3_0 + ps7_pll_init_data_3_0 + ps7_clock_init_data_3_0 + ps7_ddr_init_data_3_0 + ps7_peripherals_init_data_3_0 + #puts "PCW Silicon Version : 3.0" + } +} + + +# For delay calculation using global timer + +# start timer + proc perf_start_clock { } { + + #writing SCU_GLOBAL_TIMER_CONTROL register + + mask_write 0xF8F00208 0x00000109 0x00000009 +} + +# stop timer and reset timer count regs + proc perf_reset_clock { } { + perf_disable_clock + mask_write 0xF8F00200 0xFFFFFFFF 0x00000000 + mask_write 0xF8F00204 0xFFFFFFFF 0x00000000 +} + +# Compute mask for given delay in miliseconds +proc get_number_of_cycles_for_delay { delay } { + + # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + variable APU_FREQ + return [ expr ($delay * $APU_FREQ /(2 * 1000))] +} + + +# stop timer +proc perf_disable_clock {} { + mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 +} + +proc perf_reset_and_start_timer {} { + perf_reset_clock + perf_start_clock +} + + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/ps7_init_gpl.h b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/ps7_init_gpl.h new file mode 100755 index 0000000..45a7839 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/ps7_init_gpl.h @@ -0,0 +1,131 @@ +/****************************************************************************** +* +* Copyright (C) 2010-2020 +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, see +* +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init_gpl.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + + + + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 142857132 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 25000000 +#define FPGA1_FREQ 50000000 +#define FPGA2_FREQ 100000000 +#define FPGA3_FREQ 200000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/xilinx-zynq.cc b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/xilinx-zynq.cc new file mode 100755 index 0000000..14e40f9 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xcelium/xilinx-zynq.cc @@ -0,0 +1,106 @@ +/* + * Xilinx SystemC/TLM-2.0 Zynq Wrapper. + * + * Written by Edgar E. Iglesias + * + * Copyright (c) 2016, Xilinx Inc. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#define SC_INCLUDE_DYNAMIC_PROCESSES + +#include + +#include "tlm_utils/simple_initiator_socket.h" +#include "tlm_utils/simple_target_socket.h" + +using namespace sc_core; +using namespace std; + +#include "xilinx-zynq.h" +#include + +//xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr, +// Iremoteport_tlm_sync *sync) +// : remoteport_tlm(name, -1, sk_descr, sync), +xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr) + : remoteport_tlm(name, -1, sk_descr), + rp_m_axi_gp0("rp_m_axi_gp0"), + rp_m_axi_gp1("rp_m_axi_gp1"), + rp_s_axi_gp0("rp_s_axi_gp0"), + rp_s_axi_gp1("rp_s_axi_gp1"), + rp_s_axi_hp0("rp_s_axi_hp0"), + rp_s_axi_hp1("rp_s_axi_hp1"), + rp_s_axi_hp2("rp_s_axi_hp2"), + rp_s_axi_hp3("rp_s_axi_hp3"), + rp_s_axi_acp("rp_s_axi_acp"), + rp_wires_in("wires_in", 20, 0), + rp_wires_out("wires_out", 0, 17), + rp_irq_out("irq_out", 0, 28), + pl2ps_irq("pl2ps_irq", 20), + ps2pl_irq("ps2pl_irq", 28), + ps2pl_rst("ps2pl_rst", 17) +{ + int i; + + m_axi_gp[0] = &rp_m_axi_gp0.sk; + m_axi_gp[1] = &rp_m_axi_gp1.sk; + + s_axi_gp[0] = &rp_s_axi_gp0.sk; + s_axi_gp[1] = &rp_s_axi_gp1.sk; + + s_axi_hp[0] = &rp_s_axi_hp0.sk; + s_axi_hp[1] = &rp_s_axi_hp1.sk; + s_axi_hp[2] = &rp_s_axi_hp2.sk; + s_axi_hp[3] = &rp_s_axi_hp3.sk; + s_axi_acp = &rp_s_axi_acp.sk; + + /* PL to PS Interrupt signals. */ + for (i = 0; i < 20; i++) { + rp_wires_in.wires_in[i](pl2ps_irq[i]); + } + + /* PS to PL Interrupt signals. */ + for (i = 0; i < 28; i++) { + rp_irq_out.wires_out[i](ps2pl_irq[i]); + } + + /* PS to PL resets. */ + for (i = 0; i < 17; i++) { + rp_wires_out.wires_out[i](ps2pl_rst[i]); + } + + register_dev(0, &rp_s_axi_gp0); + register_dev(1, &rp_s_axi_gp1); + + register_dev(2, &rp_s_axi_hp0); + register_dev(3, &rp_s_axi_hp1); + register_dev(4, &rp_s_axi_hp2); + register_dev(5, &rp_s_axi_hp3); + + register_dev(6, &rp_s_axi_acp); + + register_dev(7, &rp_m_axi_gp0); + register_dev(8, &rp_m_axi_gp1); + register_dev(9, &rp_wires_in); + register_dev(10, &rp_wires_out); + register_dev(11, &rp_irq_out); +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/Makefile b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/Makefile new file mode 100755 index 0000000..33394b3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/Makefile @@ -0,0 +1,26 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +INCLUDEFILES=*.h +LIBSOURCES=*.c +OUTS = *.o + +libs: + echo "Compiling SPI_Con..." + $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} + make clean + +include: + ${CP} $(INCLUDEFILES) $(INCLUDEDIR) + +clean: + rm -rf ${OUTS} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/NewExtInst_TOP.bda b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/NewExtInst_TOP.bda new file mode 100755 index 0000000..ab7b1f9 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/NewExtInst_TOP.bda @@ -0,0 +1,272 @@ +{ + "graphjs": { + "version": "1.0", + "keys": [ + { + "abrv": "VH", + "name": "vert_hid", + "type": "int", + "for": "node" + }, + { + "abrv": "VM", + "name": "vert_name", + "type": "string", + "for": "node" + }, + { + "abrv": "VT", + "name": "vert_type", + "type": "string", + "for": "node" + }, + { + "abrv": "BA", + "name": "base_addr", + "type": "string", + "for": "node" + }, + { + "abrv": "HA", + "name": "high_addr", + "type": "string", + "for": "node" + }, + { + "abrv": "BP", + "name": "base_param", + "type": "string", + "for": "node" + }, + { + "abrv": "HP", + "name": "high_param", + "type": "string", + "for": "node" + }, + { + "abrv": "MA", + "name": "master_addrspace", + "type": "string", + "for": "node" + }, + { + "abrv": "MX", + "name": "master_instance", + "type": "string", + "for": "node" + }, + { + "abrv": "MI", + "name": "master_interface", + "type": "string", + "for": "node" + }, + { + "abrv": "MS", + "name": "master_segment", + "type": "string", + "for": "node" + }, + { + "abrv": "MV", + "name": "master_vlnv", + "type": "string", + "for": "node" + }, + { + "abrv": "SX", + "name": "slave_instance", + "type": "string", + "for": "node" + }, + { + "abrv": "SI", + "name": "slave_interface", + "type": "string", + "for": "node" + }, + { + "abrv": "MM", + "name": "slave_memmap", + "type": "string", + "for": "node" + }, + { + "abrv": "SS", + "name": "slave_segment", + "type": "string", + "for": "node" + }, + { + "abrv": "SV", + "name": "slave_vlnv", + "type": "string", + "for": "node" + }, + { + "abrv": "TM", + "name": "memory_type", + "type": "string", + "for": "node" + }, + { + "abrv": "TU", + "name": "usage_type", + "type": "string", + "for": "node" + }, + { + "abrv": "LT", + "name": "lock_type", + "type": "string", + "for": "node" + }, + { + "abrv": "BT", + "name": "boot_type", + "type": "string", + "for": "node" + }, + { + "abrv": "EH", + "name": "edge_hid", + "type": "int", + "for": "edge" + } + ], + "vertice_type_order": [ + { + "abrv": "BC", + "desc": "Block Container" + }, + { + "abrv": "PR", + "desc": "Parital Reference" + }, + { + "abrv": "VR", + "desc": "Variant" + }, + { + "abrv": "PM", + "desc": "Variant Permutations" + }, + { + "abrv": "CX", + "desc": "Boundary Connection" + }, + { + "abrv": "AC", + "desc": "Assignment Coordinate" + }, + { + "abrv": "ACE", + "desc": "Excluded Assign Coordinate" + }, + { + "abrv": "APX", + "desc": "Boundary Aperture" + }, + { + "abrv": "CIP", + "desc": "High level Processing System" + } + ], + "vertices": { + "V0": { + "VM": "NewExtInst_TOP", + "VT": "BC" + }, + "V1": { + "VH": "2", + "VM": "NewExtInst_TOP", + "VT": "VR" + }, + "V2": { + "VH": "2", + "VT": "PM", + "TU": "active" + }, + "V3": { + "VT": "AC", + "BA": "0x43C00000", + "HA": "0x43C0FFFF", + "BP": "C_S00_AXI_BASEADDR", + "HP": "C_S00_AXI_HIGHADDR", + "MA": "Data", + "MX": "/processing_system7_0", + "MI": "M_AXI_GP0", + "MS": "SEG_SPI_Con_0_S00_AXI_reg", + "MV": "xilinx.com:ip:processing_system7:5.5", + "SX": "/SPI_Con_0", + "SI": "S00_AXI", + "SS": "S00_AXI_reg", + "SV": "xilinx.com:user:SPI_Con:1.0", + "TM": "both", + "TU": "register" + }, + "V4": { + "VT": "AC", + "BA": "0x43C10000", + "HA": "0x43C1FFFF", + "BP": "C_S00_AXI_BASEADDR", + "HP": "C_S00_AXI_HIGHADDR", + "MA": "Data", + "MX": "/processing_system7_0", + "MI": "M_AXI_GP0", + "MS": "SEG_SPI_Con_1_S00_AXI_reg", + "MV": "xilinx.com:ip:processing_system7:5.5", + "SX": "/SPI_Con_1", + "SI": "S00_AXI", + "SS": "S00_AXI_reg", + "SV": "xilinx.com:user:SPI_Con:1.0", + "TM": "both", + "TU": "register" + }, + "V5": { + "VT": "AC", + "BA": "0x43C20000", + "HA": "0x43C2FFFF", + "BP": "C_S00_AXI_BASEADDR", + "HP": "C_S00_AXI_HIGHADDR", + "MA": "Data", + "MX": "/processing_system7_0", + "MI": "M_AXI_GP0", + "MS": "SEG_SPI_Con_2_S00_AXI_reg", + "MV": "xilinx.com:ip:processing_system7:5.5", + "SX": "/SPI_Con_2", + "SI": "S00_AXI", + "SS": "S00_AXI_reg", + "SV": "xilinx.com:user:SPI_Con:1.0", + "TM": "both", + "TU": "register" + } + }, + "edges": [ + { + "src": "V0", + "trg": "V1" + }, + { + "src": "V1", + "trg": "V2" + }, + { + "src": "V3", + "trg": "V2", + "EH": "2" + }, + { + "src": "V4", + "trg": "V2", + "EH": "2" + }, + { + "src": "V5", + "trg": "V2", + "EH": "2" + } + ] + } +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/NewExtInst_TOP.sh b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/NewExtInst_TOP.sh new file mode 100755 index 0000000..9f23168 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/NewExtInst_TOP.sh @@ -0,0 +1,335 @@ +#!/usr/bin/env bash +#********************************************************************************************************** +# Vivado (TM) v2023.2 (64-bit) +# +# Script generated by Vivado on Fri May 15 15:32:22 CST 2026 +# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 +# +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# +# Filename : NewExtInst_TOP.sh +# Simulator : AMD Vivado Simulator +# Description : Simulation script generated by export_simulation Tcl command +# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the +# design. The script will copy the library mapping file from the compiled library directory, +# create design library directories and library mappings in the mapping file. +# +# Usage : NewExtInst_TOP.sh +# NewExtInst_TOP.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]* +# NewExtInst_TOP.sh [-reset_run] +# NewExtInst_TOP.sh [-reset_log] +# NewExtInst_TOP.sh [-help] +# +# * The -noclean_files switch is deprecated and will not peform any function (by default, the +# simulator generated files will not be removed unless -reset_run switch is used) +# +#********************************************************************************************************** + +# catch pipeline exit status +set -Eeuo pipefail + +# set xvlog options +xvlog_opts="--incr --relax -L uvm -L axi_vip_v1_1_15 -L processing_system7_vip_v1_0_17 -L xilinx_vip" + +# set xvhdl options +xvhdl_opts="--incr --relax " + +# script info +echo -e "NewExtInst_TOP.sh - Script generated by export_simulation (Vivado v2023.2 (64-bit)-id)\n" + +# main steps +run() +{ + check_args $* + setup + if [[ ($b_step == 1) ]]; then + case $step in + "compile" ) + init_lib + compile + ;; + "elaborate" ) + elaborate + ;; + "simulate" ) + simulate + ;; + * ) + echo -e "ERROR: Invalid or missing step '$step' (type \"./NewExtInst_TOP.sh -help\" for more information)\n" + exit 1 + esac + else + init_lib + compile + elaborate + simulate + fi +} + +# RUN_STEP: +compile() +{ + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + + xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log +} + +# RUN_STEP: +elaborate() +{ + xelab --incr --debug typical --relax --mt 8 -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_15 -L processing_system7_vip_v1_0_17 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_14 -L generic_baseblocks_v2_1_1 -L axi_register_slice_v2_1_29 -L fifo_generator_v13_2_9 -L axi_data_fifo_v2_1_28 -L axi_crossbar_v2_1_30 -L axi_protocol_converter_v2_1_29 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot NewExtInst_TOP xil_defaultlib.NewExtInst_TOP xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim NewExtInst_TOP -key {Behavioral:sim_1:Functional:NewExtInst_TOP} -tclbatch cmd.tcl -protoinst "protoinst_files/NewExtInst_TOP.protoinst" -log simulate.log +} + +# STEP: setup +setup() +{ + # delete previous files for a clean rerun + if [[ ($b_reset_run == 1) ]]; then + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + fi + + # delete previous log files + if [[ ($b_reset_log == 1) ]]; then + reset_log + echo -e "INFO: Simulation run log files deleted.\n" + exit 0 + fi + + # add any setup/initialization commands here:- + + # + +} + +# simulator index file/library directory processing +init_lib() +{ + if [[ ($b_keep_index == 1) ]]; then + # keep previous simulator index file + true + else + # copy simulator index file to current directory + copy_setup_file + fi + + if [[ ($lib_map_path != "") ]]; then + ref_lib_dir=$lib_map_path + fi +} + +# copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + + if [[ ($lib_map_path == "") ]]; then + lib_map_path="/data/xilinx/Vivado/2023.2/data/xsim" + fi + + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # map local design libraries to xsim.ini + map_local_libs + fi +} + +# map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # local design libraries + local_libs=(xil_defaultlib) + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + + # create a backup copy of the xsim.ini file + cp $file $file_backup + + # read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + + # split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + + # if local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + + # add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + + # append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + + # write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb NewExtInst_TOP.wdb xsim.dir libdpi.so) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# delete generated log files from the previous run +reset_log() +{ + files_to_remove=(xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# check switch argument value +check_arg_value() +{ + if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "elaborate") && ($2 != "simulate")) ]];then + echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then + echo -e "ERROR: Simulation library directory path not specified (type \"./NewExtInst_TOP.sh -help\" for more information)\n" + exit 1 + fi +} + +# check command line arguments +check_args() +{ + arg_count=$# + if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then + usage + fi + while [[ "$#" -gt 0 ]]; do + case $1 in + -step) check_arg_value $1 $2;step=$2; b_step=1; shift;; + -lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;; + -gen_bypass) b_gen_bypass=1 ;; + -reset_run) b_reset_run=1 ;; + -reset_log) b_reset_log=1 ;; + -keep_index) b_keep_index=1 ;; + -noclean_files) b_noclean_files=1 ;; + -help|-h) ;; + *) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;; + esac + shift + done + + # -reset_run is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then + echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -reset_log is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then + echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -keep_index is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then + echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -noclean_files is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then + echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi +} + +# script usage +usage() +{ + msg="Usage: NewExtInst_TOP.sh [-help]\n\ +Usage: NewExtInst_TOP.sh [-step]\n\ +Usage: NewExtInst_TOP.sh [-lib_map_path]\n\ +Usage: NewExtInst_TOP.sh [-reset_run]\n\ +Usage: NewExtInst_TOP.sh [-reset_log]\n\ +Usage: NewExtInst_TOP.sh [-keep_index]\n\ +Usage: NewExtInst_TOP.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-step ] -- Execute specified step (compile, elaborate, simulate)\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\ +file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\ +NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\ +NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\ +[-reset_log] -- Delete simulator generated log files from the previous run\n\n\ +[-keep_index] -- Keep simulator index file settings from the previous run\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n" + echo -e $msg + exit 0 +} + +# initialize globals +step="" +lib_map_path="" +b_step=0 +b_lib_map_path=0 +b_gen_bypass=0 +b_reset_run=0 +b_reset_log=0 +b_keep_index=0 +b_noclean_files=0 + +# launch script +run $* diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/README.txt b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/README.txt new file mode 100644 index 0000000..1d27b8b --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/README.txt @@ -0,0 +1,50 @@ +################################################################################ +# Vivado (TM) v2023.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and how to fetch design source file details +# from the file_info.txt file. +# +# Generated by export_simulation on Fri May 15 15:32:22 CST 2026 +# +################################################################################ + +1. Steps to run the generated simulation script + +From the shell prompt in the current directory, issue the following command:- + +./NewExtInst_TOP.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first calls the 'check_args' function, the purpose of which +is to verify the generated script arguments and print error if incorrect switch +is specified. The 'run' function then calls the 'setup' function, the purpose of +which is to specify custom or initialization commands. The function also executes +following sub-functions:- +'reset_run' if -reset_run switch is specified. +'reset_log' if -reset_log switch is specified. + +The purpose of 'reset_run' function' is to delete the simulator generated design +data from the previous run and the purpose of 'reset_log' function' is to delete +the simulator generated log files. + +The 'run' function then calls the 'init_lib' function, the purpose of which is to +create design library mappings and directories. This function is called before the +'compile' step. By default, if '-step' switch is specified with the script then the +script will execute that specfic step, else it will execute all steps applicable +for the target simulator. + +For more information on the script, please type './NewExtInst_TOP.sh -help' + +2. Design source file information + +export_simulation generates a 'file_info.txt' file that contains design file information +based on the compile order when export_simulation was executed from Vivado. The file +contains information about the file name, type, library it is compiled into, whether +it is part of the IP, associated library, file path information in a comma separated +format. This file can be parsed to extract the required information for generating a +custom script or can be read from verification test infra. + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/SPI_Con.h b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/SPI_Con.h new file mode 100755 index 0000000..5278bdd --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/SPI_Con.h @@ -0,0 +1,107 @@ + +#ifndef SPI_CON_H +#define SPI_CON_H + + +/****************** Include Files ********************/ +#include "xil_types.h" +#include "xstatus.h" + +#define SPI_CON_S00_AXI_SLV_REG0_OFFSET 0 +#define SPI_CON_S00_AXI_SLV_REG1_OFFSET 4 +#define SPI_CON_S00_AXI_SLV_REG2_OFFSET 8 +#define SPI_CON_S00_AXI_SLV_REG3_OFFSET 12 +#define SPI_CON_S00_AXI_SLV_REG4_OFFSET 16 +#define SPI_CON_S00_AXI_SLV_REG5_OFFSET 20 +#define SPI_CON_S00_AXI_SLV_REG6_OFFSET 24 +#define SPI_CON_S00_AXI_SLV_REG7_OFFSET 28 +#define SPI_CON_S00_AXI_SLV_REG8_OFFSET 32 +#define SPI_CON_S00_AXI_SLV_REG9_OFFSET 36 +#define SPI_CON_S00_AXI_SLV_REG10_OFFSET 40 +#define SPI_CON_S00_AXI_SLV_REG11_OFFSET 44 +#define SPI_CON_S00_AXI_SLV_REG12_OFFSET 48 +#define SPI_CON_S00_AXI_SLV_REG13_OFFSET 52 +#define SPI_CON_S00_AXI_SLV_REG14_OFFSET 56 +#define SPI_CON_S00_AXI_SLV_REG15_OFFSET 60 +#define SPI_CON_S00_AXI_SLV_REG16_OFFSET 64 +#define SPI_CON_S00_AXI_SLV_REG17_OFFSET 68 +#define SPI_CON_S00_AXI_SLV_REG18_OFFSET 72 +#define SPI_CON_S00_AXI_SLV_REG19_OFFSET 76 +#define SPI_CON_S00_AXI_SLV_REG20_OFFSET 80 +#define SPI_CON_S00_AXI_SLV_REG21_OFFSET 84 +#define SPI_CON_S00_AXI_SLV_REG22_OFFSET 88 +#define SPI_CON_S00_AXI_SLV_REG23_OFFSET 92 +#define SPI_CON_S00_AXI_SLV_REG24_OFFSET 96 +#define SPI_CON_S00_AXI_SLV_REG25_OFFSET 100 +#define SPI_CON_S00_AXI_SLV_REG26_OFFSET 104 +#define SPI_CON_S00_AXI_SLV_REG27_OFFSET 108 +#define SPI_CON_S00_AXI_SLV_REG28_OFFSET 112 +#define SPI_CON_S00_AXI_SLV_REG29_OFFSET 116 +#define SPI_CON_S00_AXI_SLV_REG30_OFFSET 120 +#define SPI_CON_S00_AXI_SLV_REG31_OFFSET 124 + + +/**************************** Type Definitions *****************************/ +/** + * + * Write a value to a SPI_CON register. A 32 bit write is performed. + * If the component is implemented in a smaller width, only the least + * significant data is written. + * + * @param BaseAddress is the base address of the SPI_CONdevice. + * @param RegOffset is the register offset from the base to write to. + * @param Data is the data written to the register. + * + * @return None. + * + * @note + * C-style signature: + * void SPI_CON_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data) + * + */ +#define SPI_CON_mWriteReg(BaseAddress, RegOffset, Data) \ + Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data)) + +/** + * + * Read a value from a SPI_CON register. A 32 bit read is performed. + * If the component is implemented in a smaller width, only the least + * significant data is read from the register. The most significant data + * will be read as 0. + * + * @param BaseAddress is the base address of the SPI_CON device. + * @param RegOffset is the register offset from the base to write to. + * + * @return Data is the data from the register. + * + * @note + * C-style signature: + * u32 SPI_CON_mReadReg(u32 BaseAddress, unsigned RegOffset) + * + */ +#define SPI_CON_mReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (RegOffset)) + +/************************** Function Prototypes ****************************/ +/** + * + * Run a self-test on the driver/device. Note this may be a destructive test if + * resets of the device are performed. + * + * If the hardware system is not built correctly, this function may never + * return to the caller. + * + * @param baseaddr_p is the base address of the SPI_CON instance to be worked on. + * + * @return + * + * - XST_SUCCESS if all self-test code passed + * - XST_FAILURE if any self-test code failed + * + * @note Caching must be turned off for this function to work. + * @note Self test may fail if data memory and device are not on the same bus. + * + */ +XStatus SPI_CON_Reg_SelfTest(void * baseaddr_p); + +#endif // SPI_CON_H diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/SPI_Con.mdd b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/SPI_Con.mdd new file mode 100755 index 0000000..4bd813f --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/SPI_Con.mdd @@ -0,0 +1,10 @@ + + +OPTION psf_version = 2.1; + +BEGIN DRIVER SPI_Con + OPTION supported_peripherals = (SPI_Con); + OPTION copyfiles = all; + OPTION VERSION = 1.0; + OPTION NAME = SPI_Con; +END DRIVER diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/SPI_Con.tcl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/SPI_Con.tcl new file mode 100755 index 0000000..7f913c9 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/SPI_Con.tcl @@ -0,0 +1,5 @@ + + +proc generate {drv_handle} { + xdefine_include_file $drv_handle "xparameters.h" "SPI_Con" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR" +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/cmd.tcl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/cmd.tcl new file mode 100644 index 0000000..6ac0dc8 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns +quit diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/file_info.txt b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/file_info.txt new file mode 100644 index 0000000..d0f246a --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/file_info.txt @@ -0,0 +1,14 @@ +NewExtInst_TOP_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/sim/NewExtInst_TOP_processing_system7_0_0.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +NewExtInst_TOP_clk_wiz_0_0_clk_wiz.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_clk_wiz.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +NewExtInst_TOP_clk_wiz_0_0.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +NewExtInst_TOP_proc_sys_reset_0_0.vhd,vhdl,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/sim/NewExtInst_TOP_proc_sys_reset_0_0.vhd,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" 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+NewExtInst_TOP_SPI_Con_0_2.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/sim/NewExtInst_TOP_SPI_Con_0_2.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" 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+NewExtInst_TOP_rst_clk_wiz_0_100M_0.vhd,vhdl,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/sim/NewExtInst_TOP_rst_clk_wiz_0_100M_0.vhd,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" 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+NewExtInst_TOP.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/sim/NewExtInst_TOP.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/glbl.v b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/libps7.dll b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/libps7.dll new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/libps7.dll @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/libps7.so b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/libps7.so new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/libps7.so @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/libremoteport.dll b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/libremoteport.dll new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/libremoteport.dll @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/libremoteport.so b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/libremoteport.so new file mode 100755 index 0000000..592f0f3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/libremoteport.so @@ -0,0 +1,47 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/protoinst_files/NewExtInst_TOP.protoinst b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/protoinst_files/NewExtInst_TOP.protoinst new file mode 100644 index 0000000..98e9271 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/protoinst_files/NewExtInst_TOP.protoinst @@ -0,0 +1,656 @@ +{ + "version": "1.0", + "modules": { + "NewExtInst_TOP": { + "proto_instances": { + "/SPI_Con_0/S00_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "s00_axi_aclk"}, + "ARADDR": { "actual": "s00_axi_araddr[6:0]"}, + "ARESETN": { "actual": "s00_axi_aresetn"}, + "ARPROT": { "actual": "s00_axi_arprot[2:0]"}, + "ARREADY": { "actual": "s00_axi_arready"}, + "ARVALID": { "actual": "s00_axi_arvalid"}, + "AWADDR": { "actual": "s00_axi_awaddr[6:0]"}, + "AWPROT": { "actual": "s00_axi_awprot[2:0]"}, + "AWREADY": { "actual": "s00_axi_awready"}, + "AWVALID": { "actual": "s00_axi_awvalid"}, + "BREADY": { "actual": "s00_axi_bready"}, + "BRESP": { "actual": "s00_axi_bresp[1:0]"}, + "BVALID": { "actual": "s00_axi_bvalid"}, + "RDATA": { "actual": "s00_axi_rdata[31:0]"}, + "RREADY": { "actual": "s00_axi_rready"}, + "RRESP": { "actual": "s00_axi_rresp[1:0]"}, + "RVALID": { "actual": "s00_axi_rvalid"}, + "WDATA": { "actual": "s00_axi_wdata[31:0]"}, + "WREADY": { "actual": "s00_axi_wready"}, + "WSTRB": { "actual": "s00_axi_wstrb[3:0]"}, + "WVALID": { "actual": "s00_axi_wvalid"} + } + }, + "/SPI_Con_1/S00_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "s00_axi_aclk"}, + "ARADDR": { "actual": "s00_axi_araddr[6:0]"}, + "ARESETN": { "actual": "s00_axi_aresetn"}, + "ARPROT": { "actual": "s00_axi_arprot[2:0]"}, + "ARREADY": { "actual": "s00_axi_arready"}, + "ARVALID": { "actual": "s00_axi_arvalid"}, + "AWADDR": { "actual": "s00_axi_awaddr[6:0]"}, + "AWPROT": { "actual": "s00_axi_awprot[2:0]"}, + "AWREADY": { "actual": "s00_axi_awready"}, + "AWVALID": { "actual": "s00_axi_awvalid"}, + "BREADY": { "actual": "s00_axi_bready"}, + "BRESP": { "actual": "s00_axi_bresp[1:0]"}, + "BVALID": { "actual": "s00_axi_bvalid"}, + "RDATA": { "actual": "s00_axi_rdata[31:0]"}, + "RREADY": { "actual": "s00_axi_rready"}, + "RRESP": { "actual": "s00_axi_rresp[1:0]"}, + "RVALID": { "actual": "s00_axi_rvalid"}, + "WDATA": { "actual": "s00_axi_wdata[31:0]"}, + "WREADY": { "actual": "s00_axi_wready"}, + "WSTRB": { "actual": "s00_axi_wstrb[3:0]"}, + "WVALID": { "actual": "s00_axi_wvalid"} + } + }, + "/SPI_Con_2/S00_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "s00_axi_aclk"}, + "ARADDR": { "actual": "s00_axi_araddr[6:0]"}, + "ARESETN": { "actual": "s00_axi_aresetn"}, + "ARPROT": { "actual": "s00_axi_arprot[2:0]"}, + "ARREADY": { "actual": "s00_axi_arready"}, + "ARVALID": { "actual": "s00_axi_arvalid"}, + "AWADDR": { "actual": "s00_axi_awaddr[6:0]"}, + "AWPROT": { "actual": "s00_axi_awprot[2:0]"}, + "AWREADY": { "actual": "s00_axi_awready"}, + "AWVALID": { "actual": "s00_axi_awvalid"}, + "BREADY": { "actual": "s00_axi_bready"}, + "BRESP": { "actual": "s00_axi_bresp[1:0]"}, + "BVALID": { "actual": "s00_axi_bvalid"}, + "RDATA": { "actual": "s00_axi_rdata[31:0]"}, + "RREADY": { "actual": "s00_axi_rready"}, + "RRESP": { "actual": "s00_axi_rresp[1:0]"}, + "RVALID": { "actual": "s00_axi_rvalid"}, + "WDATA": { "actual": "s00_axi_wdata[31:0]"}, + "WREADY": { "actual": "s00_axi_wready"}, + "WSTRB": { "actual": "s00_axi_wstrb[3:0]"}, + "WVALID": { "actual": "s00_axi_wvalid"} + } + }, + "/processing_system7_0/M_AXI_GP0": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "M_AXI_GP0_ACLK"}, + "ARADDR": { "actual": "M_AXI_GP0_ARADDR[31:0]"}, + "ARBURST": { "actual": "M_AXI_GP0_ARBURST[1:0]"}, + "ARCACHE": { "actual": "M_AXI_GP0_ARCACHE[3:0]"}, + "ARID": { "actual": "M_AXI_GP0_ARID[11:0]"}, + "ARLEN": { "actual": "M_AXI_GP0_ARLEN[3:0]"}, + "ARLOCK": { "actual": "M_AXI_GP0_ARLOCK[1:0]"}, + "ARPROT": { "actual": "M_AXI_GP0_ARPROT[2:0]"}, + "ARQOS": { "actual": "M_AXI_GP0_ARQOS[3:0]"}, + "ARREADY": { "actual": "M_AXI_GP0_ARREADY"}, + "ARSIZE": { "actual": "M_AXI_GP0_ARSIZE[2:0]"}, + "ARVALID": { "actual": "M_AXI_GP0_ARVALID"}, + "AWADDR": { "actual": "M_AXI_GP0_AWADDR[31:0]"}, + "AWBURST": { "actual": "M_AXI_GP0_AWBURST[1:0]"}, + "AWCACHE": { "actual": "M_AXI_GP0_AWCACHE[3:0]"}, + "AWID": { "actual": "M_AXI_GP0_AWID[11:0]"}, + "AWLEN": { "actual": "M_AXI_GP0_AWLEN[3:0]"}, + "AWLOCK": { "actual": "M_AXI_GP0_AWLOCK[1:0]"}, + "AWPROT": { "actual": "M_AXI_GP0_AWPROT[2:0]"}, + "AWQOS": { "actual": "M_AXI_GP0_AWQOS[3:0]"}, + "AWREADY": { "actual": "M_AXI_GP0_AWREADY"}, + "AWSIZE": { "actual": "M_AXI_GP0_AWSIZE[2:0]"}, + "AWVALID": { "actual": "M_AXI_GP0_AWVALID"}, + "BID": { "actual": "M_AXI_GP0_BID[11:0]"}, + "BREADY": { "actual": "M_AXI_GP0_BREADY"}, + "BRESP": { "actual": "M_AXI_GP0_BRESP[1:0]"}, + "BVALID": { "actual": "M_AXI_GP0_BVALID"}, + "RDATA": { "actual": "M_AXI_GP0_RDATA[31:0]"}, + "RID": { "actual": "M_AXI_GP0_RID[11:0]"}, + "RLAST": { "actual": "M_AXI_GP0_RLAST"}, + "RREADY": { "actual": "M_AXI_GP0_RREADY"}, + "RRESP": { "actual": "M_AXI_GP0_RRESP[1:0]"}, + "RVALID": { "actual": "M_AXI_GP0_RVALID"}, + "WDATA": { "actual": "M_AXI_GP0_WDATA[31:0]"}, + "WID": { "actual": "M_AXI_GP0_WID[11:0]"}, + "WLAST": { "actual": "M_AXI_GP0_WLAST"}, + "WREADY": { "actual": "M_AXI_GP0_WREADY"}, + "WSTRB": { "actual": "M_AXI_GP0_WSTRB[3:0]"}, + "WVALID": { "actual": "M_AXI_GP0_WVALID"} + } + }, + "/ps7_0_axi_periph/M00_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "M00_ACLK"}, + "ARADDR": { "actual": "M00_AXI_araddr[31:0]"}, + "ARESETN": { "actual": "ARESETN"}, + "ARPROT": { "actual": "M00_AXI_arprot[2:0]"}, + "ARREADY": { "actual": "M00_AXI_arready[0:0]"}, + "ARVALID": { "actual": "M00_AXI_arvalid[0:0]"}, + "AWADDR": { "actual": "M00_AXI_awaddr[31:0]"}, + "AWPROT": { "actual": "M00_AXI_awprot[2:0]"}, + "AWREADY": { "actual": "M00_AXI_awready[0:0]"}, + "AWVALID": { "actual": "M00_AXI_awvalid[0:0]"}, + "BREADY": { "actual": "M00_AXI_bready[0:0]"}, + "BRESP": { "actual": "M00_AXI_bresp[1:0]"}, + "BVALID": { "actual": "M00_AXI_bvalid[0:0]"}, + "RDATA": { "actual": "M00_AXI_rdata[31:0]"}, + "RREADY": { "actual": "M00_AXI_rready[0:0]"}, + "RRESP": { "actual": "M00_AXI_rresp[1:0]"}, + "RVALID": { "actual": "M00_AXI_rvalid[0:0]"}, + "WDATA": { "actual": "M00_AXI_wdata[31:0]"}, + "WREADY": { "actual": "M00_AXI_wready[0:0]"}, + "WSTRB": { "actual": "M00_AXI_wstrb[3:0]"}, + "WVALID": { "actual": "M00_AXI_wvalid[0:0]"} + } + }, + "/ps7_0_axi_periph/M01_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "M01_ACLK"}, + "ARADDR": { "actual": "M01_AXI_araddr[63:32]"}, + "ARESETN": { "actual": "ARESETN"}, + "ARPROT": { "actual": "M01_AXI_arprot[5:3]"}, + "ARREADY": { "actual": "M01_AXI_arready[1:1]"}, + "ARVALID": { "actual": "M01_AXI_arvalid[1:1]"}, + "AWADDR": { "actual": "M01_AXI_awaddr[63:32]"}, + "AWPROT": { "actual": "M01_AXI_awprot[5:3]"}, + "AWREADY": { "actual": "M01_AXI_awready[1:1]"}, + "AWVALID": { "actual": "M01_AXI_awvalid[1:1]"}, + "BREADY": { "actual": "M01_AXI_bready[1:1]"}, + "BRESP": { "actual": "M01_AXI_bresp[3:2]"}, + "BVALID": { "actual": "M01_AXI_bvalid[1:1]"}, + "RDATA": { "actual": "M01_AXI_rdata[63:32]"}, + "RREADY": { "actual": "M01_AXI_rready[1:1]"}, + "RRESP": { "actual": "M01_AXI_rresp[3:2]"}, + "RVALID": { "actual": "M01_AXI_rvalid[1:1]"}, + "WDATA": { "actual": "M01_AXI_wdata[63:32]"}, + "WREADY": { "actual": "M01_AXI_wready[1:1]"}, + "WSTRB": { "actual": "M01_AXI_wstrb[7:4]"}, + "WVALID": { "actual": "M01_AXI_wvalid[1:1]"} + } + }, + "/ps7_0_axi_periph/M02_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "M02_ACLK"}, + "ARADDR": { "actual": "M02_AXI_araddr[95:64]"}, + "ARESETN": { "actual": "ARESETN"}, + "ARPROT": { "actual": "M02_AXI_arprot[8:6]"}, + "ARREADY": { "actual": "M02_AXI_arready[2:2]"}, + "ARVALID": { "actual": "M02_AXI_arvalid[2:2]"}, + "AWADDR": { "actual": "M02_AXI_awaddr[95:64]"}, + "AWPROT": { "actual": "M02_AXI_awprot[8:6]"}, + "AWREADY": { "actual": "M02_AXI_awready[2:2]"}, + "AWVALID": { "actual": "M02_AXI_awvalid[2:2]"}, + "BREADY": { "actual": "M02_AXI_bready[2:2]"}, + "BRESP": { "actual": "M02_AXI_bresp[5:4]"}, + "BVALID": { "actual": "M02_AXI_bvalid[2:2]"}, + "RDATA": { "actual": "M02_AXI_rdata[95:64]"}, + "RREADY": { "actual": "M02_AXI_rready[2:2]"}, + "RRESP": { "actual": "M02_AXI_rresp[5:4]"}, + "RVALID": { "actual": "M02_AXI_rvalid[2:2]"}, + "WDATA": { "actual": "M02_AXI_wdata[95:64]"}, + "WREADY": { "actual": "M02_AXI_wready[2:2]"}, + "WSTRB": { "actual": "M02_AXI_wstrb[11:8]"}, + "WVALID": { "actual": "M02_AXI_wvalid[2:2]"} + } + }, + "/ps7_0_axi_periph/S00_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "S00_ACLK"}, + "ARADDR": { "actual": "S00_AXI_araddr[31:0]"}, + "ARBURST": { "actual": "S00_AXI_arburst[1:0]"}, + "ARCACHE": { "actual": "S00_AXI_arcache[3:0]"}, + "ARESETN": { "actual": "ARESETN"}, + "ARID": { "actual": "S00_AXI_arid[11:0]"}, + "ARLEN": { "actual": "S00_AXI_arlen[7:0]"}, + "ARLOCK": { "actual": "S00_AXI_arlock[0:0]"}, + "ARPROT": { "actual": "S00_AXI_arprot[2:0]"}, + "ARQOS": { "actual": "S00_AXI_arqos[3:0]"}, + "ARREADY": { "actual": "S00_AXI_arready"}, + "ARSIZE": { "actual": "S00_AXI_arsize[2:0]"}, + "ARVALID": { "actual": "S00_AXI_arvalid"}, + "AWADDR": { "actual": "S00_AXI_awaddr[31:0]"}, + "AWBURST": { "actual": "S00_AXI_awburst[1:0]"}, + "AWCACHE": { "actual": "S00_AXI_awcache[3:0]"}, + "AWID": { "actual": "S00_AXI_awid[11:0]"}, + "AWLEN": { "actual": "S00_AXI_awlen[7:0]"}, + "AWLOCK": { "actual": "S00_AXI_awlock[0:0]"}, + "AWPROT": { "actual": "S00_AXI_awprot[2:0]"}, + "AWQOS": { "actual": "S00_AXI_awqos[3:0]"}, + "AWREADY": { "actual": "S00_AXI_awready"}, + "AWSIZE": { "actual": "S00_AXI_awsize[2:0]"}, + "AWVALID": { "actual": "S00_AXI_awvalid"}, + "BID": { "actual": "S00_AXI_bid[11:0]"}, + "BREADY": { "actual": "S00_AXI_bready"}, + "BRESP": { "actual": "S00_AXI_bresp[1:0]"}, + "BVALID": { "actual": "S00_AXI_bvalid"}, + "RDATA": { "actual": "S00_AXI_rdata[31:0]"}, + "RID": { "actual": "S00_AXI_rid[11:0]"}, + "RLAST": { "actual": "S00_AXI_rlast"}, + "RREADY": { "actual": "S00_AXI_rready"}, + "RRESP": { "actual": "S00_AXI_rresp[1:0]"}, + "RVALID": { "actual": "S00_AXI_rvalid"}, + "WDATA": { "actual": "S00_AXI_wdata[31:0]"}, + "WID": { "actual": "S00_AXI_wid[11:0]"}, + "WLAST": { "actual": "S00_AXI_wlast"}, + "WREADY": { "actual": "S00_AXI_wready"}, + "WSTRB": { "actual": "S00_AXI_wstrb[3:0]"}, + "WVALID": { "actual": "S00_AXI_wvalid"} + } + }, + "/ps7_0_axi_periph/m00_couplers/M_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "M_ACLK"}, + "ARADDR": { "actual": "M_AXI_araddr[31:0]"}, + "ARESETN": { "actual": "M_ARESETN"}, + "ARPROT": { "actual": "M_AXI_arprot[2:0]"}, + "ARREADY": { "actual": "M_AXI_arready[0:0]"}, + "ARVALID": { "actual": "M_AXI_arvalid[0:0]"}, + "AWADDR": { "actual": "M_AXI_awaddr[31:0]"}, + "AWPROT": { "actual": "M_AXI_awprot[2:0]"}, + "AWREADY": { "actual": "M_AXI_awready[0:0]"}, + "AWVALID": { "actual": "M_AXI_awvalid[0:0]"}, + "BREADY": { "actual": "M_AXI_bready[0:0]"}, + "BRESP": { "actual": "M_AXI_bresp[1:0]"}, + "BVALID": { "actual": "M_AXI_bvalid[0:0]"}, + "RDATA": { "actual": "M_AXI_rdata[31:0]"}, + "RREADY": { "actual": "M_AXI_rready[0:0]"}, + "RRESP": { "actual": "M_AXI_rresp[1:0]"}, + "RVALID": { "actual": "M_AXI_rvalid[0:0]"}, + "WDATA": { "actual": "M_AXI_wdata[31:0]"}, + "WREADY": { "actual": "M_AXI_wready[0:0]"}, + "WSTRB": { "actual": "M_AXI_wstrb[3:0]"}, + "WVALID": { "actual": "M_AXI_wvalid[0:0]"} + } + }, + "/ps7_0_axi_periph/m00_couplers/S_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "S_ACLK"}, + "ARADDR": { "actual": "S_AXI_araddr[31:0]"}, + "ARESETN": { "actual": "S_ARESETN"}, + "ARPROT": { "actual": "S_AXI_arprot[2:0]"}, + "ARREADY": { "actual": "S_AXI_arready[0:0]"}, + "ARVALID": { "actual": "S_AXI_arvalid[0:0]"}, + "AWADDR": { "actual": "S_AXI_awaddr[31:0]"}, + "AWPROT": { "actual": "S_AXI_awprot[2:0]"}, + "AWREADY": { "actual": "S_AXI_awready[0:0]"}, + "AWVALID": { "actual": "S_AXI_awvalid[0:0]"}, + "BREADY": { "actual": "S_AXI_bready[0:0]"}, + "BRESP": { "actual": "S_AXI_bresp[1:0]"}, + "BVALID": { "actual": "S_AXI_bvalid[0:0]"}, + "RDATA": { "actual": "S_AXI_rdata[31:0]"}, + "RREADY": { "actual": "S_AXI_rready[0:0]"}, + "RRESP": { "actual": "S_AXI_rresp[1:0]"}, + "RVALID": { "actual": "S_AXI_rvalid[0:0]"}, + "WDATA": { "actual": "S_AXI_wdata[31:0]"}, + "WREADY": { "actual": "S_AXI_wready[0:0]"}, + "WSTRB": { "actual": "S_AXI_wstrb[3:0]"}, + "WVALID": { "actual": "S_AXI_wvalid[0:0]"} + } + }, + "/ps7_0_axi_periph/m01_couplers/M_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "M_ACLK"}, + "ARADDR": { "actual": "M_AXI_araddr[63:32]"}, + "ARESETN": { "actual": "M_ARESETN"}, + "ARPROT": { "actual": "M_AXI_arprot[5:3]"}, + "ARREADY": { "actual": "M_AXI_arready[1:1]"}, + "ARVALID": { "actual": "M_AXI_arvalid[1:1]"}, + "AWADDR": { "actual": "M_AXI_awaddr[63:32]"}, + "AWPROT": { "actual": "M_AXI_awprot[5:3]"}, + "AWREADY": { "actual": "M_AXI_awready[1:1]"}, + "AWVALID": { "actual": "M_AXI_awvalid[1:1]"}, + "BREADY": { "actual": "M_AXI_bready[1:1]"}, + "BRESP": { "actual": "M_AXI_bresp[3:2]"}, + "BVALID": { "actual": "M_AXI_bvalid[1:1]"}, + "RDATA": { "actual": "M_AXI_rdata[63:32]"}, + "RREADY": { "actual": "M_AXI_rready[1:1]"}, + "RRESP": { "actual": "M_AXI_rresp[3:2]"}, + "RVALID": { "actual": "M_AXI_rvalid[1:1]"}, + "WDATA": { "actual": "M_AXI_wdata[63:32]"}, + "WREADY": { "actual": "M_AXI_wready[1:1]"}, + "WSTRB": { "actual": "M_AXI_wstrb[7:4]"}, + "WVALID": { "actual": "M_AXI_wvalid[1:1]"} + } + }, + "/ps7_0_axi_periph/m01_couplers/S_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "S_ACLK"}, + "ARADDR": { "actual": "S_AXI_araddr[63:32]"}, + "ARESETN": { "actual": "S_ARESETN"}, + "ARPROT": { "actual": "S_AXI_arprot[5:3]"}, + "ARREADY": { "actual": "S_AXI_arready[1:1]"}, + "ARVALID": { "actual": "S_AXI_arvalid[1:1]"}, + "AWADDR": { "actual": "S_AXI_awaddr[63:32]"}, + "AWPROT": { "actual": "S_AXI_awprot[5:3]"}, + "AWREADY": { "actual": "S_AXI_awready[1:1]"}, + "AWVALID": { "actual": "S_AXI_awvalid[1:1]"}, + "BREADY": { "actual": "S_AXI_bready[1:1]"}, + "BRESP": { "actual": "S_AXI_bresp[3:2]"}, + "BVALID": { "actual": "S_AXI_bvalid[1:1]"}, + "RDATA": { "actual": "S_AXI_rdata[63:32]"}, + "RREADY": { "actual": "S_AXI_rready[1:1]"}, + "RRESP": { "actual": "S_AXI_rresp[3:2]"}, + "RVALID": { "actual": "S_AXI_rvalid[1:1]"}, + "WDATA": { "actual": "S_AXI_wdata[63:32]"}, + "WREADY": { "actual": "S_AXI_wready[1:1]"}, + "WSTRB": { "actual": "S_AXI_wstrb[7:4]"}, + "WVALID": { "actual": "S_AXI_wvalid[1:1]"} + } + }, + "/ps7_0_axi_periph/m02_couplers/M_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "M_ACLK"}, + "ARADDR": { "actual": "M_AXI_araddr[95:64]"}, + "ARESETN": { "actual": "M_ARESETN"}, + "ARPROT": { "actual": "M_AXI_arprot[8:6]"}, + "ARREADY": { "actual": "M_AXI_arready[2:2]"}, + "ARVALID": { "actual": "M_AXI_arvalid[2:2]"}, + "AWADDR": { "actual": "M_AXI_awaddr[95:64]"}, + "AWPROT": { "actual": "M_AXI_awprot[8:6]"}, + "AWREADY": { "actual": "M_AXI_awready[2:2]"}, + "AWVALID": { "actual": "M_AXI_awvalid[2:2]"}, + "BREADY": { "actual": "M_AXI_bready[2:2]"}, + "BRESP": { "actual": "M_AXI_bresp[5:4]"}, + "BVALID": { "actual": "M_AXI_bvalid[2:2]"}, + "RDATA": { "actual": "M_AXI_rdata[95:64]"}, + "RREADY": { "actual": "M_AXI_rready[2:2]"}, + "RRESP": { "actual": "M_AXI_rresp[5:4]"}, + "RVALID": { "actual": "M_AXI_rvalid[2:2]"}, + "WDATA": { "actual": "M_AXI_wdata[95:64]"}, + "WREADY": { "actual": "M_AXI_wready[2:2]"}, + "WSTRB": { "actual": "M_AXI_wstrb[11:8]"}, + "WVALID": { "actual": "M_AXI_wvalid[2:2]"} + } + }, + "/ps7_0_axi_periph/m02_couplers/S_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "S_ACLK"}, + "ARADDR": { "actual": "S_AXI_araddr[95:64]"}, + "ARESETN": { "actual": "S_ARESETN"}, + "ARPROT": { "actual": "S_AXI_arprot[8:6]"}, + "ARREADY": { "actual": "S_AXI_arready[2:2]"}, + "ARVALID": { "actual": "S_AXI_arvalid[2:2]"}, + "AWADDR": { "actual": "S_AXI_awaddr[95:64]"}, + "AWPROT": { "actual": "S_AXI_awprot[8:6]"}, + "AWREADY": { "actual": "S_AXI_awready[2:2]"}, + "AWVALID": { "actual": "S_AXI_awvalid[2:2]"}, + "BREADY": { "actual": "S_AXI_bready[2:2]"}, + "BRESP": { "actual": "S_AXI_bresp[5:4]"}, + "BVALID": { "actual": "S_AXI_bvalid[2:2]"}, + "RDATA": { "actual": "S_AXI_rdata[95:64]"}, + "RREADY": { "actual": "S_AXI_rready[2:2]"}, + "RRESP": { "actual": "S_AXI_rresp[5:4]"}, + "RVALID": { "actual": "S_AXI_rvalid[2:2]"}, + "WDATA": { "actual": "S_AXI_wdata[95:64]"}, + "WREADY": { "actual": "S_AXI_wready[2:2]"}, + "WSTRB": { "actual": "S_AXI_wstrb[11:8]"}, + "WVALID": { "actual": "S_AXI_wvalid[2:2]"} + } + }, + "/ps7_0_axi_periph/s00_couplers/M_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "M_ACLK"}, + "ARADDR": { "actual": "M_AXI_araddr[31:0]"}, + "ARESETN": { "actual": "M_ARESETN"}, + "ARPROT": { "actual": "M_AXI_arprot[2:0]"}, + "ARREADY": { "actual": "M_AXI_arready"}, + "ARVALID": { "actual": "M_AXI_arvalid"}, + "AWADDR": { "actual": "M_AXI_awaddr[31:0]"}, + "AWPROT": { "actual": "M_AXI_awprot[2:0]"}, + "AWREADY": { "actual": "M_AXI_awready"}, + "AWVALID": { "actual": "M_AXI_awvalid"}, + "BREADY": { "actual": "M_AXI_bready"}, + "BRESP": { "actual": "M_AXI_bresp[1:0]"}, + "BVALID": { "actual": "M_AXI_bvalid"}, + "RDATA": { "actual": "M_AXI_rdata[31:0]"}, + "RREADY": { "actual": "M_AXI_rready"}, + "RRESP": { "actual": "M_AXI_rresp[1:0]"}, + "RVALID": { "actual": "M_AXI_rvalid"}, + "WDATA": { "actual": "M_AXI_wdata[31:0]"}, + "WREADY": { "actual": "M_AXI_wready"}, + "WSTRB": { "actual": "M_AXI_wstrb[3:0]"}, + "WVALID": { "actual": "M_AXI_wvalid"} + } + }, + "/ps7_0_axi_periph/s00_couplers/S_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "S_ACLK"}, + "ARADDR": { "actual": "S_AXI_araddr[31:0]"}, + "ARBURST": { "actual": "S_AXI_arburst[1:0]"}, + "ARCACHE": { "actual": "S_AXI_arcache[3:0]"}, + "ARESETN": { "actual": "S_ARESETN"}, + "ARID": { "actual": "S_AXI_arid[11:0]"}, + "ARLEN": { "actual": "S_AXI_arlen[7:0]"}, + "ARLOCK": { "actual": "S_AXI_arlock[0:0]"}, + "ARPROT": { "actual": "S_AXI_arprot[2:0]"}, + "ARQOS": { "actual": "S_AXI_arqos[3:0]"}, + "ARREADY": { "actual": "S_AXI_arready"}, + "ARSIZE": { "actual": "S_AXI_arsize[2:0]"}, + "ARVALID": { "actual": "S_AXI_arvalid"}, + "AWADDR": { "actual": "S_AXI_awaddr[31:0]"}, + "AWBURST": { "actual": "S_AXI_awburst[1:0]"}, + "AWCACHE": { "actual": "S_AXI_awcache[3:0]"}, + "AWID": { "actual": "S_AXI_awid[11:0]"}, + "AWLEN": { "actual": "S_AXI_awlen[7:0]"}, + "AWLOCK": { "actual": "S_AXI_awlock[0:0]"}, + "AWPROT": { "actual": "S_AXI_awprot[2:0]"}, + "AWQOS": { "actual": "S_AXI_awqos[3:0]"}, + "AWREADY": { "actual": "S_AXI_awready"}, + "AWSIZE": { "actual": "S_AXI_awsize[2:0]"}, + "AWVALID": { "actual": "S_AXI_awvalid"}, + "BID": { "actual": "S_AXI_bid[11:0]"}, + "BREADY": { "actual": "S_AXI_bready"}, + "BRESP": { "actual": "S_AXI_bresp[1:0]"}, + "BVALID": { "actual": "S_AXI_bvalid"}, + "RDATA": { "actual": "S_AXI_rdata[31:0]"}, + "RID": { "actual": "S_AXI_rid[11:0]"}, + "RLAST": { "actual": "S_AXI_rlast"}, + "RREADY": { "actual": "S_AXI_rready"}, + "RRESP": { "actual": "S_AXI_rresp[1:0]"}, + "RVALID": { "actual": "S_AXI_rvalid"}, + "WDATA": { "actual": "S_AXI_wdata[31:0]"}, + "WID": { "actual": "S_AXI_wid[11:0]"}, + "WLAST": { "actual": "S_AXI_wlast"}, + "WREADY": { "actual": "S_AXI_wready"}, + "WSTRB": { "actual": "S_AXI_wstrb[3:0]"}, + "WVALID": { "actual": "S_AXI_wvalid"} + } + }, + "/ps7_0_axi_periph/s00_couplers/auto_pc/M_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "aclk"}, + "ARADDR": { "actual": "m_axi_araddr[31:0]"}, + "ARESETN": { "actual": "aresetn"}, + "ARPROT": { "actual": "m_axi_arprot[2:0]"}, + "ARREADY": { "actual": "m_axi_arready"}, + "ARVALID": { "actual": "m_axi_arvalid"}, + "AWADDR": { "actual": "m_axi_awaddr[31:0]"}, + "AWPROT": { "actual": "m_axi_awprot[2:0]"}, + "AWREADY": { "actual": "m_axi_awready"}, + "AWVALID": { "actual": "m_axi_awvalid"}, + "BREADY": { "actual": "m_axi_bready"}, + "BRESP": { "actual": "m_axi_bresp[1:0]"}, + "BVALID": { "actual": "m_axi_bvalid"}, + "RDATA": { "actual": "m_axi_rdata[31:0]"}, + "RREADY": { "actual": "m_axi_rready"}, + "RRESP": { "actual": "m_axi_rresp[1:0]"}, + "RVALID": { "actual": "m_axi_rvalid"}, + "WDATA": { "actual": "m_axi_wdata[31:0]"}, + "WREADY": { "actual": "m_axi_wready"}, + "WSTRB": { "actual": "m_axi_wstrb[3:0]"}, + "WVALID": { "actual": "m_axi_wvalid"} + } + }, + "/ps7_0_axi_periph/s00_couplers/auto_pc/S_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "aclk"}, + "ARADDR": { "actual": "s_axi_araddr[31:0]"}, + "ARBURST": { "actual": "s_axi_arburst[1:0]"}, + "ARCACHE": { "actual": "s_axi_arcache[3:0]"}, + "ARESETN": { "actual": "aresetn"}, + "ARID": { "actual": "s_axi_arid[11:0]"}, + "ARLEN": { "actual": "s_axi_arlen[3:0]"}, + "ARLOCK": { "actual": "s_axi_arlock[1:0]"}, + "ARPROT": { "actual": "s_axi_arprot[2:0]"}, + "ARQOS": { "actual": "s_axi_arqos[3:0]"}, + "ARREADY": { "actual": "s_axi_arready"}, + "ARSIZE": { "actual": "s_axi_arsize[2:0]"}, + "ARVALID": { "actual": "s_axi_arvalid"}, + "AWADDR": { "actual": "s_axi_awaddr[31:0]"}, + "AWBURST": { "actual": "s_axi_awburst[1:0]"}, + "AWCACHE": { "actual": "s_axi_awcache[3:0]"}, + "AWID": { "actual": "s_axi_awid[11:0]"}, + "AWLEN": { "actual": "s_axi_awlen[3:0]"}, + "AWLOCK": { "actual": "s_axi_awlock[1:0]"}, + "AWPROT": { "actual": "s_axi_awprot[2:0]"}, + "AWQOS": { "actual": "s_axi_awqos[3:0]"}, + "AWREADY": { "actual": "s_axi_awready"}, + "AWSIZE": { "actual": "s_axi_awsize[2:0]"}, + "AWVALID": { "actual": "s_axi_awvalid"}, + "BID": { "actual": "s_axi_bid[11:0]"}, + "BREADY": { "actual": "s_axi_bready"}, + "BRESP": { "actual": "s_axi_bresp[1:0]"}, + "BVALID": { "actual": "s_axi_bvalid"}, + "RDATA": { "actual": "s_axi_rdata[31:0]"}, + "RID": { "actual": "s_axi_rid[11:0]"}, + "RLAST": { "actual": "s_axi_rlast"}, + "RREADY": { "actual": "s_axi_rready"}, + "RRESP": { "actual": "s_axi_rresp[1:0]"}, + "RVALID": { "actual": "s_axi_rvalid"}, + "WDATA": { "actual": "s_axi_wdata[31:0]"}, + "WID": { "actual": "s_axi_wid[11:0]"}, + "WLAST": { "actual": "s_axi_wlast"}, + "WREADY": { "actual": "s_axi_wready"}, + "WSTRB": { "actual": "s_axi_wstrb[3:0]"}, + "WVALID": { "actual": "s_axi_wvalid"} + } + }, + "/ps7_0_axi_periph/xbar/M00_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "aclk"}, + "ARADDR": { "actual": "m_axi_araddr[31:0]"}, + "ARESETN": { "actual": "aresetn"}, + "ARPROT": { "actual": "m_axi_arprot[2:0]"}, + "ARREADY": { "actual": "m_axi_arready[0:0]"}, + "ARVALID": { "actual": "m_axi_arvalid[0:0]"}, + "AWADDR": { "actual": "m_axi_awaddr[31:0]"}, + "AWPROT": { "actual": "m_axi_awprot[2:0]"}, + "AWREADY": { "actual": "m_axi_awready[0:0]"}, + "AWVALID": { "actual": "m_axi_awvalid[0:0]"}, + "BREADY": { "actual": "m_axi_bready[0:0]"}, + "BRESP": { "actual": "m_axi_bresp[1:0]"}, + "BVALID": { "actual": "m_axi_bvalid[0:0]"}, + "RDATA": { "actual": "m_axi_rdata[31:0]"}, + "RREADY": { "actual": "m_axi_rready[0:0]"}, + "RRESP": { "actual": "m_axi_rresp[1:0]"}, + "RVALID": { "actual": "m_axi_rvalid[0:0]"}, + "WDATA": { "actual": "m_axi_wdata[31:0]"}, + "WREADY": { "actual": "m_axi_wready[0:0]"}, + "WSTRB": { "actual": "m_axi_wstrb[3:0]"}, + "WVALID": { "actual": "m_axi_wvalid[0:0]"} + } + }, + "/ps7_0_axi_periph/xbar/M01_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "aclk"}, + "ARADDR": { "actual": "m_axi_araddr[63:32]"}, + "ARESETN": { "actual": "aresetn"}, + "ARPROT": { "actual": "m_axi_arprot[5:3]"}, + "ARREADY": { "actual": "m_axi_arready[1:1]"}, + "ARVALID": { "actual": "m_axi_arvalid[1:1]"}, + "AWADDR": { "actual": "m_axi_awaddr[63:32]"}, + "AWPROT": { "actual": "m_axi_awprot[5:3]"}, + "AWREADY": { "actual": "m_axi_awready[1:1]"}, + "AWVALID": { "actual": "m_axi_awvalid[1:1]"}, + "BREADY": { "actual": "m_axi_bready[1:1]"}, + "BRESP": { "actual": "m_axi_bresp[3:2]"}, + "BVALID": { "actual": "m_axi_bvalid[1:1]"}, + "RDATA": { "actual": "m_axi_rdata[63:32]"}, + "RREADY": { "actual": "m_axi_rready[1:1]"}, + "RRESP": { "actual": "m_axi_rresp[3:2]"}, + "RVALID": { "actual": "m_axi_rvalid[1:1]"}, + "WDATA": { "actual": "m_axi_wdata[63:32]"}, + "WREADY": { "actual": "m_axi_wready[1:1]"}, + "WSTRB": { "actual": "m_axi_wstrb[7:4]"}, + "WVALID": { "actual": "m_axi_wvalid[1:1]"} + } + }, + "/ps7_0_axi_periph/xbar/M02_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "aclk"}, + "ARADDR": { "actual": "m_axi_araddr[95:64]"}, + "ARESETN": { "actual": "aresetn"}, + "ARPROT": { "actual": "m_axi_arprot[8:6]"}, + "ARREADY": { "actual": "m_axi_arready[2:2]"}, + "ARVALID": { "actual": "m_axi_arvalid[2:2]"}, + "AWADDR": { "actual": "m_axi_awaddr[95:64]"}, + "AWPROT": { "actual": "m_axi_awprot[8:6]"}, + "AWREADY": { "actual": "m_axi_awready[2:2]"}, + "AWVALID": { "actual": "m_axi_awvalid[2:2]"}, + "BREADY": { "actual": "m_axi_bready[2:2]"}, + "BRESP": { "actual": "m_axi_bresp[5:4]"}, + "BVALID": { "actual": "m_axi_bvalid[2:2]"}, + "RDATA": { "actual": "m_axi_rdata[95:64]"}, + "RREADY": { "actual": "m_axi_rready[2:2]"}, + "RRESP": { "actual": "m_axi_rresp[5:4]"}, + "RVALID": { "actual": "m_axi_rvalid[2:2]"}, + "WDATA": { "actual": "m_axi_wdata[95:64]"}, + "WREADY": { "actual": "m_axi_wready[2:2]"}, + "WSTRB": { "actual": "m_axi_wstrb[11:8]"}, + "WVALID": { "actual": "m_axi_wvalid[2:2]"} + } + }, + "/ps7_0_axi_periph/xbar/S00_AXI": { + "interface": "xilinx.com:interface:aximm:1.0", + "ports": { + "ACLK": { "actual": "aclk"}, + "ARADDR": { "actual": "s_axi_araddr[31:0]"}, + "ARESETN": { "actual": "aresetn"}, + "ARPROT": { "actual": "s_axi_arprot[2:0]"}, + "ARREADY": { "actual": "s_axi_arready[0:0]"}, + "ARVALID": { "actual": "s_axi_arvalid[0:0]"}, + "AWADDR": { "actual": "s_axi_awaddr[31:0]"}, + "AWPROT": { "actual": "s_axi_awprot[2:0]"}, + "AWREADY": { "actual": "s_axi_awready[0:0]"}, + "AWVALID": { "actual": "s_axi_awvalid[0:0]"}, + "BREADY": { "actual": "s_axi_bready[0:0]"}, + "BRESP": { "actual": "s_axi_bresp[1:0]"}, + "BVALID": { "actual": "s_axi_bvalid[0:0]"}, + "RDATA": { "actual": "s_axi_rdata[31:0]"}, + "RREADY": { "actual": "s_axi_rready[0:0]"}, + "RRESP": { "actual": "s_axi_rresp[1:0]"}, + "RVALID": { "actual": "s_axi_rvalid[0:0]"}, + "WDATA": { "actual": "s_axi_wdata[31:0]"}, + "WREADY": { "actual": "s_axi_wready[0:0]"}, + "WSTRB": { "actual": "s_axi_wstrb[3:0]"}, + "WVALID": { "actual": "s_axi_wvalid[0:0]"} + } + } + } + } + } +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/ps7_init.h b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/ps7_init.h new file mode 100755 index 0000000..224d7ea --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/ps7_init.h @@ -0,0 +1,117 @@ +/****************************************************************************** +* +* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + + + + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 142857132 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 25000000 +#define FPGA1_FREQ 50000000 +#define FPGA2_FREQ 100000000 +#define FPGA3_FREQ 200000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/ps7_init.html b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/ps7_init.html new file mode 100755 index 0000000..9ca53bd --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/ps7_init.html @@ -0,0 +1,125613 @@ + + + + +Zynq PS configuration detail + + + +

    +
    + +
  • +
    Zynq PS Register Summary Viewer +
    +
    • +     +
    +
    +
    + +
    Zynq PS7 Summary Report +
    +     +
    User Configurations +
    +
    + +
    MIO Configurations +
    +     +
    + +
    CLK Configurations +
    +     +
    + +
    DDR Configurations +
    +     +
    + +
    SMC Configurations +
    +     +
    +
    +
    Select Version: + +
    +
    +
    Zynq Register View +
    +
    + +
    MIO Registers +
    +     + +
    PLL Registers +
    +     + +
    Clock Registers +
    +     + +
    DDR Registers +
    +     + +
    Peripherals Registers +
    +     +
    +
    This design is targeted for xc7z035 board (part number: xc7z035ffg676-2) + +
    +

    Zynq Design Summary

    + + + + + + + + + + + + + + + + + + + + + +
    +Device + +xc7z035 +
    +SpeedGrade + +-2 +
    +Part + +xc7z035ffg676-2 +
    +Description + +Zynq PS Configuration Report with register details +
    +Vendor + +Xilinx +
    +

    MIO Table View

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +MIO Pin + +Peripheral + +Signal + +IO Type + +Speed + +Pullup + +Direction +
    +MIO 0 + +SD 1 + +wp + +LVCMOS 3.3V + +slow + +enabled + +in +
    +MIO 1 + +Quad SPI Flash + +qspi0_ss_b + +LVCMOS 3.3V + +slow + +enabled + +out +
    +MIO 2 + +Quad SPI Flash + +qspi0_io[0] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 3 + +Quad SPI Flash + +qspi0_io[1] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 4 + +Quad SPI Flash + +qspi0_io[2] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 5 + +Quad SPI Flash + +qspi0_io[3]/HOLD_B + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 6 + +Quad SPI Flash + +qspi0_sclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 7 + + + + + + + + + + + + +
    +MIO 8 + +Quad SPI Flash + +qspi_fbclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 9 + +SD 1 + +cd + +LVCMOS 3.3V + +slow + +enabled + +in +
    +MIO 10 + +SD 1 + +data[0] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 11 + +SD 1 + +cmd + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 12 + +SD 1 + +clk + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 13 + +SD 1 + +data[1] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 14 + +SD 1 + +data[2] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 15 + +SD 1 + +data[3] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 16 + +Enet 0 + +tx_clk + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 17 + +Enet 0 + +txd[0] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 18 + +Enet 0 + +txd[1] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 19 + +Enet 0 + +txd[2] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 20 + +Enet 0 + +txd[3] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 21 + +Enet 0 + +tx_ctl + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 22 + +Enet 0 + +rx_clk + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 23 + +Enet 0 + +rxd[0] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 24 + +Enet 0 + +rxd[1] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 25 + +Enet 0 + +rxd[2] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 26 + +Enet 0 + +rxd[3] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 27 + +Enet 0 + +rx_ctl + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 28 + + + + + + + + + + + + +
    +MIO 29 + + + + + + + + + + + + +
    +MIO 30 + + + + + + + + + + + + +
    +MIO 31 + + + + + + + + + + + + +
    +MIO 32 + + + + + + + + + + + + +
    +MIO 33 + + + + + + + + + + + + +
    +MIO 34 + + + + + + + + + + + + +
    +MIO 35 + + + + + + + + + + + + +
    +MIO 36 + + + + + + + + + + + + +
    +MIO 37 + + + + + + + + + + + + +
    +MIO 38 + + + + + + + + + + + + +
    +MIO 39 + + + + + + + + + + + + +
    +MIO 40 + +SD 0 + +clk + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 41 + +SD 0 + +cmd + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 42 + +SD 0 + +data[0] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 43 + +SD 0 + +data[1] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 44 + +SD 0 + +data[2] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 45 + +SD 0 + +data[3] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 46 + +SD 0 + +wp + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 47 + +SD 0 + +cd + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 48 + +UART 1 + +tx + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 49 + +UART 1 + +rx + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 50 + + + + + + + + + + + + +
    +MIO 51 + + + + + + + + + + + + +
    +MIO 52 + +Enet 0 + +mdc + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 53 + +Enet 0 + +mdio + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +

    DDR Memory information

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Parameter name + +Value + +Description +
    +Enable DDR + +1 + +Enable DDR Controller of Zynq PS +
    +Memory Part + +MT41J256M16 RE-125 + + +
    +DRAM bus width + +32 Bit + +Select the desired data width. Refer to the Thechnical Reference Manual(TRM) for a detailed list of supported DDR data widths +
    +ECC + +Disabled + +ECC is supported only for data width of 16-bit +
    +BURST Length (lppdr only) + +8 + +Select the burst Length. It refers to the amount of data read/written after a read/write command is presented to the controller +
    +Internal Vref + +0 + + +
    +Operating Frequency (MHz) + +533.333333 + +Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade +
    +HIGH temperature + +Normal (0-85) + +Select the operating temparature +
    +DRAM IC bus width + +16 Bits + +Provide the width of the DRAM chip +
    +DRAM Device Capacity + +4096 MBits + + +
    +Speed Bin + +DDR3_1066F + +Provide the Speed Bin +
    +BANK Address Count + +3 + +Defines the bank to which an active an ACTIVE, READ, WRITE, or Precharge Command is being applied +
    +ROW Address Count + +15 + +Provide the Row address for ACTIVE commands +
    +COLUMN Address Count + +10 + +Provide the Row address for READ/WRITE commands +
    +CAS Latency + +7 + +Select the Column Access Strobe (CAS) Latency. It refers to the amount of time it takes for data to appear on the pins of the memory module +
    +CAS Write Latency + +6 + +Select the CAS Write Latency +
    +RAS to CAS Delay + +7 + +Provide the row address to column address delay time. tRCD is t he time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS) +
    +RECHARGE Time + +7 + +Precharge Time (tRP) is the number of clock cycles needed o terminate acces s to an open row of memory, and open access to the next row +
    +tRC (ns ) + +48.91 + +Provide the Row cycle time tRC (ns) +
    +tRASmin ( ns ) + +35.0 + +tRASmin (ns) is the minimum number of clock cycles required between an Active command and issuing the Precharge command +
    +tFAW + +40.0 + +It restricts the number of activates that can be done within a certain window of time +
    +ADDITIVE Latency + +0 + +Provide the Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths +
    +Write levelling + +1 + + +
    +Read gate + +1 + + +
    +Read gate + +1 + + +
    +DQS to Clock delay [0] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [1] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [2] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [3] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +Board delay [0] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [1] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [2] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [3] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +

    PS Clocks information

    +

    PS Reference Clock : 33.333333

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Peripheral + +PLL source + +Frequency (MHz) +
    +CPU 6x Freq (MHz) + +ARM PLL + +666.666687 +
    +QSPI Flash Freq (MHz) + +IO PLL + +142.857132 +
    +ENET0 Freq (MHz) + +IO PLL + +125.000000 +
    +SDIO Freq (MHz) + +IO PLL + +100.000000 +
    +SDIO Freq (MHz) + +IO PLL + +100.000000 +
    +UART Freq (MHz) + +IO PLL + +100.000000 +
    +FPGA0 Freq (MHz) + +IO PLL + +25.000000 +
    +FPGA1 Freq (MHz) + +IO PLL + +50.000000 +
    +FPGA2 Freq (MHz) + +IO PLL + +100.000000 +
    +FPGA3 Freq (MHz) + +IO PLL + +200.000000 +
    +

    ps7_pll_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: ARM PLL 10: DDR PLL 11: IO PLL This field is reset by POR only. +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for programming the PLL. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock and Rx Signals Select +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +FPGA1_CLK_CTRL + + +0XF8000180 + +32 + +RW + +0x000000 + +PL Clock 1 Output control +
    + +FPGA2_CLK_CTRL + + +0XF8000190 + +32 + +RW + +0x000000 + +PL Clock 2 output control +
    + +FPGA3_CLK_CTRL + + +0XF80001A0 + +32 + +RW + +0x000000 + +PL Clock 3 output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source of the Rx clock, control and data signals: 0: MIO 1: EMIO +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock and Rx Signals Select +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +7 + +700 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +701 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a03 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +5 + +500000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +500800 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )FPGA1_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA1_CLK_CTRL + +0XF8000180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA1_CLK_CTRL@0XF8000180 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 1 Output control +
    +

    +

    Register ( slcr )FPGA2_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA2_CLK_CTRL + +0XF8000190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +2 + +200000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA2_CLK_CTRL@0XF8000190 + +31:0 + +3f03f30 + + + +200500 + +PL Clock 2 output control +
    +

    +

    Register ( slcr )FPGA3_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA3_CLK_CTRL + +0XF80001A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA3_CLK_CTRL@0XF80001A0 + +31:0 + +3f03f30 + + + +100500 + +PL Clock 3 output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ratio: (When this register changes, no access are allowed to OCM.) 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +1 + +800 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec0c4d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +82 + +82 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reserved_reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Reserved. Do not modify. +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +Two_rank_cfg@0XF8006004 + +31:0 + +7ffff + + + +1082 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a1 + +2840 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4285b + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +13 + +13 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d3 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. In non-LPDDR mode, the minimum DRAM Write Latency (DDR2) supported is 3. In LPDDR mode, the required DRAM Write Latency of 1 is supported. Since write latency (CWL) min is 3, and DDR2 CWL is CL-1, the min (DDR2) CL supported is 4 +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +f + +3c00 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +5 + +28000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +5 + +2800000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +7282bce5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_en_dfi_dram_clk_disable + +23:23 + +800000 + +0 + +0 + +Enables the assertion of ddrc_dfi_dram_clk_disable. In DDR2/DDR3, only asserted in Self Refresh. In mDDR/LPDDR2, can be asserted in following: - during normal operation (Clock Stop), - in Power Down - in Self Refresh - In Deep Power Down +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +7fdffffc + + + +270872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffc3 + + + +0 + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2: Value loaded into EMR2 register DDR3: Value loaded into MR2 register LPDDR2: Value loaded into MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2: Value loaded into EMR3 register DDR3: Value loaded into MR3 register. Set Bit[2:0] to 3'b000. These bits are set appropriately by the Controller during Read Data eye training and Read DQS gate leveling. LPDDR2: Unused +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +b30 + +b30 + +DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2: Value loaded into EMR1register. (Bits[9:7] are for OCD and the setting in this reg is ignored. Controller sets this bits appropriately during initialization DDR3: Value loaded into MR1 register. Set Bit[7] to 0. This bit is set appropriately by the Controller during Write Leveling LPDDR2: Value loaded into MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40b30 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 8, Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 7, Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 6, Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 5, Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reserved_reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +Reserved. Do not modify. +
    +reserved_reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Reserved. Do not modify. +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3f03f + + + +3c008 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +10000 + + + +0 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum d'128) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_2d@0XF80060B4 + +31:0 + +200 + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of uncorrectable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on board topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +0: Use reg_phy_ctrl_slave_ratio for address/command timing slave DLL 1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_64@0XF8006190 + +31:0 + +6ffffefe + + + +40080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. This feature should only be enabled after LPDDR2 initialization is completed +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff5 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Powerdown mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQ pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQS pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +Drive and Slew controls for Clock pins of the DDR Interface +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SD1_WP_CD_SEL + + +0XF8000834 + +32 + +RW + +0x000000 + +SDIO 1 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQ pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQS pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for Clock pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1x: Enable External VREF for upper 16 bits +
    +reserved_VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Reserved. Do not modify. +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +reserved_REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +1 + + + +1 + +DDR IOB DCI Config +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialize flops in DCI system +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDR IOB DCI Config +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +DCI System Enable. Set to 1 if any IOs in DDR IO Bank use DCI Termination. DDR2, DDR3 and LPDDR2 (Silicon Revision 2.0+) configurations require this bit set to 1 +
    +reserved_VRP_TRI + +2:2 + +4 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_TRI + +3:3 + +8 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRP_OUT + +4:4 + +10 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT1 + +15:14 + +c000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update Mode. Use the values in the Calibration Table. +
    +reserved_INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_CLK + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLN + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLP + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_RST + +25:25 + +2000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7feffff + + + +823 + +DDR IOB DCI Config +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. 0: disable 1: enable +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables Pullup on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3f01 + + + +1601 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3f01 + + + +1601 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1680 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1680 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait, Input 10: NAND Flash IO Bit 7, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 12 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1680 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5, Input/Output 10: NAND Flash IO Bit 3, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 13 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1680 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1680 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1680 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1, Output 10: NAND Flash IO Bit 8, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2, Output 10: NAND Flash IO Bit 9, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110 TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3, Output 10: NAND Flash IO Bit 10, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6, Output 10: NAND Flash IO Bit 13, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3f01 + + + +1201 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +2e + +2e + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f002e + +SDIO 0 WP CD select +
    +

    +

    Register ( slcr )SD1_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD1_WP_CD_SEL + +0XF8000834 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO1_WP_SEL + +5:0 + +3f + +0 + +0 + +SDIO 1 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO1_CD_SEL + +21:16 + +3f0000 + +9 + +90000 + +SDIO 1 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD1_WP_CD_SEL@0XF8000834 + +31:0 + +3f003f + + + +90000 + +SDIO 1 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +Baud Rate Divider Register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud Rate Generator Register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control Register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode Register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +Baud Rate Divider Register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud Rate Generator Register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter 1: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: enable 1: disable, regardless of the value of RXEN +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed. +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed. +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control Register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +3ff + + + +20 + +UART Mode Register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes . If not set, then external pull up is required on HOLDb and WPn pins . Note that this bit doesn't affect the quad(4-bit) mode as Controller always drives these pins in quad mode. It is highly recommended to set this bit always(irrespective of mode of operation) while using QSPI +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This register controls which POR timer the PL will use for power-up. 0 - Use 64k timer 1 - Use 4k timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    ENET RESET

    +

    I2C RESET

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_LVL_INP_EN_0 + +3:3 + +8 + +1 + +8 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_0 + +2:2 + +4 + +1 + +4 + +Level shifter enable to drive signals from PS to PL +
    +USER_LVL_INP_EN_1 + +1:1 + +2 + +1 + +2 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_1 + +0:0 + +1 + +1 + +1 + +Level shifter enable to drive signals from PS to PL +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +Reserved. Do not modify. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +PL Reset 3 (FCLKRESETN3 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN3 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +PL Reset 2 (FCLKRESETN2 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN2 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +PL Reset 1 (FCLKRESETN1 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN1 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +PL Reset 0 (FCLKRESETN0 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN0 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    AFI2 SECURE REGISTER

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_3_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: CPU PLL 10: divided DDR PLL 11: IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +FPGA1_CLK_CTRL + + +0XF8000180 + +32 + +RW + +0x000000 + +PL Clock 1 Output control +
    + +FPGA2_CLK_CTRL + + +0XF8000190 + +32 + +RW + +0x000000 + +PL Clock 2 output control +
    + +FPGA3_CLK_CTRL + + +0XF80001A0 + +32 + +RW + +0x000000 + +PL Clock 3 output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source to generate the Rx clock: 0: MIO Rx clock, 1: EMIO Rx clock +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +7 + +700 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +701 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a03 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +5 + +500000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +500800 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )FPGA1_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA1_CLK_CTRL + +0XF8000180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA1_CLK_CTRL@0XF8000180 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 1 Output control +
    +

    +

    Register ( slcr )FPGA2_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA2_CLK_CTRL + +0XF8000190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +2 + +200000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA2_CLK_CTRL@0XF8000190 + +31:0 + +3f03f30 + + + +200500 + +PL Clock 2 output control +
    +

    +

    Register ( slcr )FPGA3_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA3_CLK_CTRL + +0XF80001A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA3_CLK_CTRL@0XF80001A0 + +31:0 + +3f03f30 + + + +100500 + +PL Clock 3 output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ration: 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +1 + +800 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec0c4d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config0 + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config1 + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 1. +
    + +PHY_Config2 + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 2. +
    + +PHY_Config3 + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 3. +
    + +phy_init_ratio0 + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio1 + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 1. +
    + +phy_init_ratio2 + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 2. +
    + +phy_init_ratio3 + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 3. +
    + +phy_rd_dqs_cfg0 + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg1 + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 1. +
    + +phy_rd_dqs_cfg2 + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 2. +
    + +phy_rd_dqs_cfg3 + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 3. +
    + +phy_wr_dqs_cfg0 + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg1 + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 1. +
    + +phy_wr_dqs_cfg2 + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 2. +
    + +phy_wr_dqs_cfg3 + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 3. +
    + +phy_we_cfg0 + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg1 + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 1. +
    + +phy_we_cfg2 + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 2. +
    + +phy_we_cfg3 + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 3. +
    + +wr_data_slv0 + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv1 + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 1. +
    + +wr_data_slv2 + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 2. +
    + +wr_data_slv3 + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 3. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port0 + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port1 + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 1. +
    + +axi_priority_wr_port2 + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 2. +
    + +axi_priority_wr_port3 + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 3. +
    + +axi_priority_rd_port0 + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port1 + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 1. +
    + +axi_priority_rd_port2 + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 2. +
    + +axi_priority_rd_port3 + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 3. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +82 + +82 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Rank configuration: 01: One Rank of DDR 11: Two Ranks of DDR Others: reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +Block read/write scheduling cycle count when Write requires changing ODT settings 00: 1 cycle 01: 2 cycles 10: 3 cycles others: reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0: schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1: schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81082 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a1 + +2840 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4285b + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +13 + +13 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d3 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +f + +3c00 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +5 + +28000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +5 + +2800000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +7282bce5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1: sdram device 0: non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: stop_clk will never be asserted. 1: enable the assertion of stop_clk to the PHY whenever a clock is not required +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2 and DDR3: Value written into the DRAM EMR2 register. LPDDR2: Value written into the DRAM MR3 register. +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2 and DDR3: Value written into the DRAM EMR3 register. LPDDR2: not used. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +b30 + +b30 + +DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2 and DDR3: Value written into the DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. LPDDR2: Value written into the DRAM MR2 register. +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40b30 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODTs must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config0 + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config0@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config1 + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config1@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 1. +
    +

    +

    Register ( slcr )PHY_Config2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config2 + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config2@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 2. +
    +

    +

    Register ( slcr )PHY_Config3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config3 + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config3@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_init_ratio0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio0 + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio0@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio1 + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio1@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 1. +
    +

    +

    Register ( slcr )phy_init_ratio2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio2 + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio2@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 2. +
    +

    +

    Register ( slcr )phy_init_ratio3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio3 + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio3@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 3. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg0 + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg0@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg1 + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg1@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg2 + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg2@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg3 + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg3@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg0 + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg0@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg1 + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg1@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg2 + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg2@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg3 + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg3@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_we_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg0 + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg0@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg1 + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg1@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 1. +
    +

    +

    Register ( slcr )phy_we_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg2 + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg2@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 2. +
    +

    +

    Register ( slcr )phy_we_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg3 + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg3@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 3. +
    +

    +

    Register ( slcr )wr_data_slv0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv0 + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv0@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv1 + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv1@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 1. +
    +

    +

    Register ( slcr )wr_data_slv2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv2 + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv2@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 2. +
    +

    +

    Register ( slcr )wr_data_slv3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv3 + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv3@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 3. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +0: (default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) 1: assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 0: Each Rank uses its own delay 1: Rank 0 delays are used for all ranks +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1: enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port0 + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port0@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port1 + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port1@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 1. +
    +

    +

    Register ( slcr )axi_priority_wr_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port2 + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port2@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 2. +
    +

    +

    Register ( slcr )axi_priority_wr_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port3 + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port3@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 3. +
    +

    +

    Register ( slcr )axi_priority_rd_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port0 + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port0@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port1 + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port1@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 1. +
    +

    +

    Register ( slcr )axi_priority_rd_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port2 + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port2@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 2. +
    +

    +

    Register ( slcr )axi_priority_rd_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port3 + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port3@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 3. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +0:All bank refresh Per bank refresh allows traffic to flow to other banks. 1:Per bank refresh Per bank refresh is not supported on all LPDDR2 devices. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Power-down mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 0 +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 1 +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDR IOB Slew for Address +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDR IOB Slew for Data +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDR IOB Slew for Diff +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDR IOB Slew for Clock +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SD1_WP_CD_SEL + + +0XF8000834 + +32 + +RW + +0x000000 + +SDIO 1 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 0 +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 1 +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDR IOB Slew for Address +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Data +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Diff +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Clock +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1X: Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors x0: Disable VREF pull-up for lower 16 bits x1: Enable VREF pull-up for lower 16 bits 0x: Disable VREF pull-up for upper 16 bits 1x: Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Enable test mode for VRP and VRN: 00: VRP/VRN test mode not used 11: VRP/VRN test mode enabled using vref based receiver. VRP/VRN control is set using the VRN_OUT, VRP_OUT, VRN_TRI, VRP_TRI fields in the DDRIOB_DCI_CTRL register +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0: no pull-up 1: enable pull-up +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. 0: disable 1: enable +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables pull-up on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3f01 + + + +1601 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3f01 + + + +1601 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1680 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1680 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait 10: NAND Flash IO Bit 7 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 12 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1680 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5 10: NAND Flash IO Bit 3 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 13 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1680 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1680 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1680 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1 10: NAND Flash IO Bit 8 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Output 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2 10: NAND Flash IO Bit 9 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110 TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3 10: NAND Flash IO Bit 10 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6 10: NAND Flash IO Bit 13 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3f01 + + + +1201 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +2e + +2e + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f002e + +SDIO 0 WP CD select +
    +

    +

    Register ( slcr )SD1_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD1_WP_CD_SEL + +0XF8000834 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO1_WP_SEL + +5:0 + +3f + +0 + +0 + +SDIO 1 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO1_CD_SEL + +21:16 + +3f0000 + +9 + +90000 + +SDIO 1 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD1_WP_CD_SEL@0XF8000834 + +31:0 + +3f003f + + + +90000 + +SDIO 1 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass 2 - 65535: baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: start break transmission, 1: stop break transmission. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: 1: start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 0: receiver timeout counter disabled, 1: receiver timeout counter is restarted. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter, 0: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter, 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: disable, 1: enable +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable, 1: enable. When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: 1: transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: 1: receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode: 0: Default UART mode 1: Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select: 0: APB clock, pclk 1: a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: 00: normal 01: automatic cho 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: 0: clock source is uart_clk 1: clock source is uart_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    ENET RESET

    +

    I2C RESET

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset: 0: No reset 1: ACP AXI interface reset output asserted +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0: No reset 1: AXDS3AXI interface reset output asserted +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0: No reset 1: AXDS2 AXI interface reset output asserted +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0: No reset 1: AXDS1 AXI interface reset output asserted +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0: No reset 1: AXDS0 AXI interface reset output asserted +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0: No reset 1: FPGA slave interface 1 reset is asserted +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0: No reset 1: FPGA slave interface 0 reset is asserted +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface: 1: soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0: No reset 1: FPGA master interface 1 reset is asserted +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0: No reset 1: FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 3 peripheral request reset output asserted +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 2 peripheral request reset output asserted +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 1 peripheral request reset output asserted +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 0 peripheral request reset output asserted +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0: No reset 1: FPGA 3 top level reset output asserted +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0: No reset 1: FPGA 2 top level reset output asserted +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0: No reset 1: FPGA 1 top level reset output asserted +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0: No reset 1: FPGA 0 top level reset output asserted +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_2_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CORTEX A9 Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status. 0 - ARM PLL out of lock. 1 - ARM PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is CPU PLL. 10 - Source for generated clock is DDR divided clock. 11 - Source for generated clock is IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CORTEX A9 Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status. 0 - DDR PLL out of lock. 1 - DDR PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Divisor value for the ddr_3xclk +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk) +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status. 0 - IO PLL out of lock. 1 - IO PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 RX Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Linear Quad-SPI Reference Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Reference Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Reference Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP 2X Clock Contol +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +FPGA 0 Output Clock Control +
    + +FPGA1_CLK_CTRL + + +0XF8000180 + +32 + +RW + +0x000000 + +FPGA 1 Output Clock Control +
    + +FPGA2_CLK_CTRL + + +0XF8000190 + +32 + +RW + +0x000000 + +FPGA 2 Output Clock Control +
    + +FPGA3_CLK_CTRL + + +0XF80001A0 + +32 + +RW + +0x000000 + +FPGA 3 Output Clock Control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +6:2:1 ratio clock, if set +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Selects the source used to generate the clock. 0 - Source for generated clock is GEM 0 MIO RX clock. 1 - Source for generated clock is GEM 0 FMIO RX clock. +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +Gigabit Ethernet MAC 0 RX Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source used to generate the clock. 1xx - Source for generated clock is Ethernet 0 FMIO clock. 00x - Source for generated clock is IO PLL. 010 - Source for generated clock is ARM PLL. 011 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +7 + +700 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +701 + +Linear Quad-SPI Reference Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO 0 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +SDIO 1 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a03 + +SDIO Reference Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Reference Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active 0 - Clock is disabled 1 - Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP 2X Clock Contol +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +5 + +500000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +500800 + +FPGA 0 Output Clock Control +
    +

    +

    Register ( slcr )FPGA1_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA1_CLK_CTRL + +0XF8000180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA1_CLK_CTRL@0XF8000180 + +31:0 + +3f03f30 + + + +400500 + +FPGA 1 Output Clock Control +
    +

    +

    Register ( slcr )FPGA2_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA2_CLK_CTRL + +0XF8000190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +2 + +200000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA2_CLK_CTRL@0XF8000190 + +31:0 + +3f03f30 + + + +200500 + +FPGA 2 Output Clock Control +
    +

    +

    Register ( slcr )FPGA3_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA3_CLK_CTRL + +0XF80001A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA3_CLK_CTRL@0XF80001A0 + +31:0 + +3f03f30 + + + +100500 + +FPGA 3 Output Clock Control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Enable the 6:2:1 mode. 1 for 6:3:2:1. 0 for 4:2:2:1. +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +6:2:1 ratio clock, if set +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet MAC 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet MAC 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +1 + +800 + +SDIO 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +LQSPI AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec0c4d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two rank configuration register +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control register +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control register +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control register +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters register 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters register 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters register 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters register 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters register 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM initialization parameters register +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access register +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access register +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM burst 8 read/write register +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ register +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM bank address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT register +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO register +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration register +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold register +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller register 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller register 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller register 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller register 4 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters register +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters register +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown register +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control register +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug register +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing register +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear register +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction register +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status register +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count register +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub register +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control register (2) +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control register (3) +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask register +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 Register +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 Register +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 Register +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 Register +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control Register +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +82 + +82 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Only present for multi-rank configurations. Each bit represents one rank. 1=populated; 0=unpopulated 01 = One Rank 11 = Two Ranks Others = Reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +00 = block read/write scheduling for 1-cycle when Write requires changing ODT settings 01 = block read/write scheduling for 2 cycles when Write requires changing ODT settings 10 = block read/write scheduling for 3 cycles when Write requires changing ODT settings 11 = Reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0 = schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1 = schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81082 + +Two rank configuration register +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of clocks that the HPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control register +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control register +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control register +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a1 + +2840 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks DRAM RELATED +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4285b + +DRAM Parameters register 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +13 + +13 + +Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. LPDDR2 mode: Set this to the larger of tCKE or tCKESR. Non-LPDDR2 designs: Set this to tCKE value. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d3 + +DRAM Parameters register 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2/3 -> WL -1 LPDDR -> 1 LPDDR2 ->WL Where WL = Write Latency of DRAM DRAM RELATED. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. non-LPDDR2 -> RL + BL/2 + 2 - WL LPDDR2 -> RL + BL/2 + RU(tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +f + +3c00 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +5 + +28000 + +tXP: Minimum time after power down exit to any operation. DRAM RELATED. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +5 + +2800000 + +Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency DRAM RELATED +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +7282bce5 + +DRAM Parameters register 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1 DRAM RELATED +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1 = sdram device 0 = non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-mobile DRAM device in use. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +1=enable the assertion of stop_clk to the PHY whenever a clock is not required by LPDDR/ LPDDR2. 0=stop_clk will never be asserted. Note: This is only present for implementations supporting LPDDR/LPDDR2 devices. +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Set to RL. Time from Read command to Read data on DRAM interface. Unit: clocks This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. RL = Read Latency of DRAM Note: This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1 = disable the pad power down feature 0 = Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters register 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1 = DDRC will use 2T timing 0 = DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1 = Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and 'ddrc_reg_mr_wr_busy' is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +Mode register address - for non-LPDDR2 modes. This register is don't care in LPDDR2 mode 00 = MR0 01 = MR1 10 = MR2 11 = MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +Mode register write data - for non-LPDDR2 modes. For LPDDR2, these 16-bits are interpreted as Writes: \'7bMR Addr[7:0], MR Data[7:0]\'7d. Reads: \'7bMR Addr[7:0], Don't Care[7:0]\'7d +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 1 = Indicates that mode register write / read operation is in progress. 0 = Indicates that the core can initiate a mode register write / read operation. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 1 = read 0 = write +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 1'b0 by default. This bit will be cleared (1'b0), whenever a Mode Register Read command is issued. This bit will be set to 1'b1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters register 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands DRAM RELATED Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM initialization parameters register +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +Non LPDDR2- Value to be loaded into DRAM EMR2 registers. For LPDDR2 - Value to Write to the MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +Non LPDDR2- Value to be loaded into DRAM EMR3 registers. Used in non-LPDDR2 designs only. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access register +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +b30 + +b30 + +Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +Non LPDDR2-Value to be loaded into DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. For LPDDR2 - Value to Write to the MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40b30 + +DRAM EMR, MR access register +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +This controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. In LPDDR and LPDDR2, Burst length of 16 is supported only in Half Bus Width mode. Every input read/write command has 4 cycles of data associated with it and that is not enough data for doing Burst Length16 in Full Bus Width mode. 0010 - Burst length of 4 0100 - Burst length of 8 1000 - Burst length of 16 (only supported for LPDDR AND LPDDR2) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM burst 8 read/write register +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Active Low signal. When asserted (0), all incoming transactions will be forced to low priority. Forcing the incoming transactions to low priority implicitly turns OFF Bypass. Otherwise, HPR is allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. This bit is intended to be switched on-the-fly +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ register +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14 Internal Base: 5 The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Selects the address bits used as DRAM bank address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Selects the address bits used as DRAM column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Selects the address bits used as DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODT's must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT register +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1 = stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO register +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration register +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable for LPDDR and LPDDR2 modes. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold register +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +When 1, disable Write Combine +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to '0', auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller register 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +1 - Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on 'urgent' input coming from AXI master. 0 - Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 1'b0. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller register 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) Only present in designs that support DDR3 and LPDDR2 devices. +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Only present in designs that support DDR3 devices +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. Only present in designs that support DDR3 devices. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller register 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller register 4 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters register +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters register +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +1 - Controller puts the DRAM into Deep Powerdown mode when the transaction store is empty. 0 - Brings Controller out of Deep Powerdown mode Present only in designs configured to support LPDDR or LPDDR2 FOR PERFORMANCE ONLY. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown register +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +1 = Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0 = Write leveling disabled. +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +1 = Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0= Read DQS gate leveling is disabled. +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +1 = Read Data Eye training mode has been enabled as part of init sequence. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control register +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1 - Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0 - Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug register +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. Non-LPDDR -> RL-1 LPDDR -> RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing register +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear register +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when a correctable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction register +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when an uncorrectable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status register +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count register +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 3'b000 (No ECC) and 3'b100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 3'b100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 - No ECC, 001 - Reserved 010 - Parity 011 - Reserved 100 - SEC/DED over 1-beat 101 - SEC/DED over multiple beats 110 - Device Correction 111 - Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +This feature is NOT supported. Only default value works. 1 - Disable ECC scrubs 0 - Enable ECC scrubs Valid only when reg_ddrc_ecc_mode = 3'b100. +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub register +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +1 = run scan test at full clock speed but with less coverage 0 = run scan test at slow clock speed but with high coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 2'b00: constant pattern (0 repeated on each DQ bit) 2'b01: low freq pattern (00001111 repeated on each DQ bit) 2'b10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +1=assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) 0=(default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0 = Select algorithm # 1'b1 = Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 1- Rank 0 delays are used for all ranks 0- Each Rank uses its own delay +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-LPDDR DRAM device in use. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1=enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control register (2) +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control register (3) +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +This register must be set based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask register +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +1=LPDDR2 DRAM device in Use. 0=non-LPDDR2 device in use Present only in designs configured to support LPDDR2. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +1:Per bank refresh 0:All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported on all LPDDR2 devices. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 Register +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. Present only in designs configured to support LPDDR2. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 Register +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 Register +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 Register +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control Register +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0 = DDRC Init 1 = Normal operation 2 = Power-down mode 3 = Self-refresh mode 4 and above = deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDRIOB Address 0 Configuartion Register +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDRIOB Address 1 Configuration Register +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDRIOB Differential Clock Configuration Register +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Address Register +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Data Register +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Differential Strobe Register +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Clcok Register +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDRIOB DDR Control Register +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Control for Pin 0 +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Control for Pin 1 +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Control for Pin 2 +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Control for Pin 3 +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Control for Pin 4 +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Control for Pin 5 +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Control for Pin 6 +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Control for Pin 8 +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Control for Pin 9 +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Control for Pin 10 +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Control for Pin 11 +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Control for Pin 12 +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Control for Pin 13 +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Control for Pin 14 +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Control for Pin 15 +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Control for Pin 16 +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Control for Pin 17 +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Control for Pin 18 +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Control for Pin 19 +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Control for Pin 20 +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Control for Pin 21 +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Control for Pin 22 +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Control for Pin 23 +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Control for Pin 24 +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Control for Pin 25 +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Control for Pin 26 +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Control for Pin 27 +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Control for Pin 40 +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Control for Pin 41 +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Control for Pin 42 +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Control for Pin 43 +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Control for Pin 44 +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Control for Pin 45 +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Control for Pin 46 +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Control for Pin 47 +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Control for Pin 48 +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Control for Pin 49 +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Control for Pin 52 +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Control for Pin 53 +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select register +
    + +SD1_WP_CD_SEL + + +0XF8000834 + +32 + +RW + +0x000000 + +SDIO 1 WP CD select register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDRIOB Address 0 Configuartion Register +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDRIOB Address 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDRIOB Differential Clock Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDRIOB Drive Slew Address Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Data Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Differential Strobe Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Clcok Register +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output 0001 - VREF = 0.6V for LPDDR2 with 1.2V IO 0010 - VREF = 0.675V for LPDDR3 1.35 V IO 0100 - VREF = 0.75V for DDR3 with 1.5V IO 1000 - VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input X0 - Disable External VREF for lower 16 bits X1 - Enable External VREF for lower 16 bits 0X - Disable External VREF for upper 16 bits 1X - Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors X0 - Disable VREF pull-up for lower 16 bits X1 - Enable VREF pull-up for lower 16 bits 0X - Disable VREF pull-up for upper 16 bits 1X - Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0 - VRP/VRN not used 1 - VRP/VRN used as refio +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +73ff + + + +260 + +DDRIOB DDR Control Register +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3f01 + + + +1601 + +MIO Control for Pin 0 +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Control for Pin 1 +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 2 +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Control for Pin 3 +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 4 +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 5 +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 6 +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 8 +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3f01 + + + +1601 + +MIO Control for Pin 9 +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 10 +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 11 +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_wait- (SRAM Wait State indicator) 2= nand, Input, smc_nand_data_in[7]- (NAND Data Bus) = nand, Output, smc_nand_data_out[7]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 12 +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[5]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[5]- (SRAM Data) 2= nand, Input, smc_nand_data_in[3]- (NAND Data Bus) = nand, Output, smc_nand_data_out[3]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 13 +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 14 +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1680 + +MIO Control for Pin 15 +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[4]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[1]- (SRAM Address) 2= nand, Input, smc_nand_data_in[8]- (NAND Data Bus) = nand, Output, smc_nand_data_out[8]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 16 +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[5]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[2]- (SRAM Address) 2= nand, Input, smc_nand_data_in[9]- (NAND Data Bus) = nand, Output, smc_nand_data_out[9]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 17 +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[6]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[3]- (SRAM Address) 2= nand, Input, smc_nand_data_in[10]- (NAND Data Bus) = nand, Output, smc_nand_data_out[10]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 18 +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 19 +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 20 +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[6]- (SRAM Address) 2= nand, Input, smc_nand_data_in[13]- (NAND Data Bus) = nand, Output, smc_nand_data_out[13]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 21 +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 22 +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 23 +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 24 +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 25 +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 26 +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 27 +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 40 +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 41 +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 42 +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 43 +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 44 +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 45 +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3f01 + + + +1201 + +MIO Control for Pin 46 +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Control for Pin 47 +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Control for Pin 48 +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Control for Pin 49 +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 52 +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 53 +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +2e + +2e + +SDIO0 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO0 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f002e + +SDIO 0 WP CD select register +
    +

    +

    Register ( slcr )SD1_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD1_WP_CD_SEL + +0XF8000834 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO1_WP_SEL + +5:0 + +3f + +0 + +0 + +SDIO1 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SDIO1_CD_SEL + +21:16 + +3f0000 + +9 + +90000 + +SDIO1 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SD1_WP_CD_SEL@0XF8000834 + +31:0 + +3f003f + + + +90000 + +SDIO 1 WP CD select register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value 0 = Disables baud_sample 1 = Clock divisor bypass 2 - 65535 = baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break. 1 = stop transmission of the break. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break 1 = start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter 1 = receiver timeout counter is restarted +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable. 1, the transmitter is disabled +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable. 1, the transmitter is enabled, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable. 1= receiver is enabled +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable. 1=the receiver logic is enabled, provided RXDIS field is set to 0 +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for TX data path. 1=the transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for RX data path 1=receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode 0 : Default UART mode 1 : Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select 0 : APB clock, pclk 1 : a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode 00 = normal 01 = automatic cho 10 = local loopback 11 = remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits 00 = 1 stop bit 01 = 1.5 stop bits 10 = 2 stop bits 11 = reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select. 000 = even parity 001 = odd parity 010 = forced to 0 parity (space) 011 = forced to 1 parity (mark) 1xx = no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select 11 = 6 bits 10 = 7 bits 01 / 00 = 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +clock source select 1 = clock source is uart_clk/8 0 = clock source is uart_clk +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    ENET RESET

    +

    I2C RESET

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset. 0 - No reset. 1 - ACP AXI interface reset output asserted. +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS3AXI interface reset output asserted. +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS2 AXI interface reset output asserted. +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS1 AXI interface reset output asserted. +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS0 AXI interface reset output asserted. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 1 reset is asserted. +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 0 reset is asserted. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface 1 soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0 - No reset. 1 - FPGA master interface 1 reset is asserted. +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0 - No reset. 1 - FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 3 peripheral request reset output asserted. +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 2 peripheral request reset output asserted. +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 1 peripheral request reset output asserted. +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 0 peripheral request reset output asserted. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0 - No reset. 1 - FPGA 3 top level reset output asserted. +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0 - No reset. 1 - FPGA 2 top level reset output asserted. +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0 - No reset. 1 - FPGA 1 top level reset output asserted. +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0 - No reset. 1 - FPGA 0 top level reset output asserted. +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_1_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/ps7_init.tcl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/ps7_init.tcl new file mode 100755 index 0000000..85a6f34 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/ps7_init.tcl @@ -0,0 +1,781 @@ +proc ps7_pll_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000701 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00500800 + mask_write 0XF8000180 0x03F03F30 0x00400500 + mask_write 0XF8000190 0x03F03F30 0x00200500 + mask_write 0XF80001A0 0x03F03F30 0x00100500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_3_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x0007FFFF 0x00001082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006024 0x0FFFFFC3 0x00000000 + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00000003 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x0003F03F 0x0003C008 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x00010000 0x00000000 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x00000200 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFCF 0x40000001 + mask_write 0XF800611C 0x7FFFFFCF 0x40000001 + mask_write 0XF8006120 0x7FFFFFCF 0x40000001 + mask_write 0XF8006124 0x7FFFFFCF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0x6FFFFEFE 0x00040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000703FF 0x000003FF + mask_write 0XF800620C 0x000703FF 0x000003FF + mask_write 0XF8006210 0x000703FF 0x000003FF + mask_write 0XF8006214 0x000703FF 0x000003FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF5 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000001 0x00000001 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001601 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003F01 0x00001601 + mask_write 0XF8000728 0x00003FFF 0x00001680 + mask_write 0XF800072C 0x00003FFF 0x00001680 + mask_write 0XF8000730 0x00003FFF 0x00001680 + mask_write 0XF8000734 0x00003FFF 0x00001680 + mask_write 0XF8000738 0x00003FFF 0x00001680 + mask_write 0XF800073C 0x00003FFF 0x00001680 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003F01 0x00001201 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F002E + mask_write 0XF8000834 0x003F003F 0x00090000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x000003FF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 +} +proc ps7_post_config_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_3_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000701 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00500800 + mask_write 0XF8000180 0x03F03F30 0x00400500 + mask_write 0XF8000190 0x03F03F30 0x00200500 + mask_write 0XF80001A0 0x03F03F30 0x00100500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_2_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001601 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003F01 0x00001601 + mask_write 0XF8000728 0x00003FFF 0x00001680 + mask_write 0XF800072C 0x00003FFF 0x00001680 + mask_write 0XF8000730 0x00003FFF 0x00001680 + mask_write 0XF8000734 0x00003FFF 0x00001680 + mask_write 0XF8000738 0x00003FFF 0x00001680 + mask_write 0XF800073C 0x00003FFF 0x00001680 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003F01 0x00001201 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F002E + mask_write 0XF8000834 0x003F003F 0x00090000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 +} +proc ps7_post_config_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_2_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000701 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00500800 + mask_write 0XF8000180 0x03F03F30 0x00400500 + mask_write 0XF8000190 0x03F03F30 0x00200500 + mask_write 0XF80001A0 0x03F03F30 0x00100500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_1_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x000073FF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001601 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003F01 0x00001601 + mask_write 0XF8000728 0x00003FFF 0x00001680 + mask_write 0XF800072C 0x00003FFF 0x00001680 + mask_write 0XF8000730 0x00003FFF 0x00001680 + mask_write 0XF8000734 0x00003FFF 0x00001680 + mask_write 0XF8000738 0x00003FFF 0x00001680 + mask_write 0XF800073C 0x00003FFF 0x00001680 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003F01 0x00001201 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F002E + mask_write 0XF8000834 0x003F003F 0x00090000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 +} +proc ps7_post_config_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_1_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +set PCW_SILICON_VER_1_0 "0x0" +set PCW_SILICON_VER_2_0 "0x1" +set PCW_SILICON_VER_3_0 "0x2" +set APU_FREQ 666666666 + + + +proc mask_poll { addr mask } { + set count 1 + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + while { $maskedval == 0 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + set count [ expr { $count + 1 } ] + if { $count == 100000000 } { + puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask" + break + } + } +} + + + +proc mask_delay { addr val } { + set delay [ get_number_of_cycles_for_delay $val ] + perf_reset_and_start_timer + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + while { $maskedval == 1 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + } + perf_reset_clock +} + +proc ps_version { } { + set si_ver "0x[string range [mrd 0xF8007080] end-8 end]" + set mask_sil_ver "0x[expr {$si_ver >> 28}]" + return $mask_sil_ver; +} + +proc ps7_post_config {} { + set saved_mode [configparams force-mem-accesses] + configparams force-mem-accesses 1 + + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_post_config_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_post_config_2_0 + } else { + ps7_post_config_3_0 + } + configparams force-mem-accesses $saved_mode +} + +proc ps7_debug {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_debug_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_debug_2_0 + } else { + ps7_debug_3_0 + } +} +proc ps7_init {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_mio_init_data_1_0 + ps7_pll_init_data_1_0 + ps7_clock_init_data_1_0 + ps7_ddr_init_data_1_0 + ps7_peripherals_init_data_1_0 + #puts "PCW Silicon Version : 1.0" + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_mio_init_data_2_0 + ps7_pll_init_data_2_0 + ps7_clock_init_data_2_0 + ps7_ddr_init_data_2_0 + ps7_peripherals_init_data_2_0 + #puts "PCW Silicon Version : 2.0" + } else { + ps7_mio_init_data_3_0 + ps7_pll_init_data_3_0 + ps7_clock_init_data_3_0 + ps7_ddr_init_data_3_0 + ps7_peripherals_init_data_3_0 + #puts "PCW Silicon Version : 3.0" + } +} + + +# For delay calculation using global timer + +# start timer + proc perf_start_clock { } { + + #writing SCU_GLOBAL_TIMER_CONTROL register + + mask_write 0xF8F00208 0x00000109 0x00000009 +} + +# stop timer and reset timer count regs + proc perf_reset_clock { } { + perf_disable_clock + mask_write 0xF8F00200 0xFFFFFFFF 0x00000000 + mask_write 0xF8F00204 0xFFFFFFFF 0x00000000 +} + +# Compute mask for given delay in miliseconds +proc get_number_of_cycles_for_delay { delay } { + + # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + variable APU_FREQ + return [ expr ($delay * $APU_FREQ /(2 * 1000))] +} + + +# stop timer +proc perf_disable_clock {} { + mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 +} + +proc perf_reset_and_start_timer {} { + perf_reset_clock + perf_start_clock +} + + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/ps7_init_gpl.h b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/ps7_init_gpl.h new file mode 100755 index 0000000..45a7839 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/ps7_init_gpl.h @@ -0,0 +1,131 @@ +/****************************************************************************** +* +* Copyright (C) 2010-2020 +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, see +* +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init_gpl.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + + + + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 142857132 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 25000000 +#define FPGA1_FREQ 50000000 +#define FPGA2_FREQ 100000000 +#define FPGA3_FREQ 200000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/vhdl.prj b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/vhdl.prj new file mode 100644 index 0000000..dc3cca1 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/vhdl.prj @@ -0,0 +1,6 @@ +vhdl xil_defaultlib \ +"../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/sim/NewExtInst_TOP_proc_sys_reset_0_0.vhd" \ +"../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/sim/NewExtInst_TOP_rst_clk_wiz_0_100M_0.vhd" \ + +# Do not sort compile order +nosort diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/vlog.prj b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/vlog.prj new file mode 100644 index 0000000..e36eb08 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/vlog.prj @@ -0,0 +1,17 @@ +verilog xil_defaultlib --include "/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" --include "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" --include "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" --include "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" \ +"../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/sim/NewExtInst_TOP_processing_system7_0_0.v" \ +"../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_clk_wiz.v" \ +"../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.v" \ +"../../../bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v" \ +"../../../bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v" \ +"../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/sim/NewExtInst_TOP_SPI_Con_0_0.v" \ +"../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/sim/NewExtInst_TOP_SPI_Con_0_1.v" \ +"../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/sim/NewExtInst_TOP_SPI_Con_0_2.v" \ +"../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/sim/NewExtInst_TOP_xbar_0.v" \ +"../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_auto_pc_0/sim/NewExtInst_TOP_auto_pc_0.v" \ +"../../../bd/NewExtInst_TOP/sim/NewExtInst_TOP.v" \ + +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/xilinx-zynq.cc b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/xilinx-zynq.cc new file mode 100755 index 0000000..14e40f9 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/xsim/xilinx-zynq.cc @@ -0,0 +1,106 @@ +/* + * Xilinx SystemC/TLM-2.0 Zynq Wrapper. + * + * Written by Edgar E. Iglesias + * + * Copyright (c) 2016, Xilinx Inc. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#define SC_INCLUDE_DYNAMIC_PROCESSES + +#include + +#include "tlm_utils/simple_initiator_socket.h" +#include "tlm_utils/simple_target_socket.h" + +using namespace sc_core; +using namespace std; + +#include "xilinx-zynq.h" +#include + +//xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr, +// Iremoteport_tlm_sync *sync) +// : remoteport_tlm(name, -1, sk_descr, sync), +xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr) + : remoteport_tlm(name, -1, sk_descr), + rp_m_axi_gp0("rp_m_axi_gp0"), + rp_m_axi_gp1("rp_m_axi_gp1"), + rp_s_axi_gp0("rp_s_axi_gp0"), + rp_s_axi_gp1("rp_s_axi_gp1"), + rp_s_axi_hp0("rp_s_axi_hp0"), + rp_s_axi_hp1("rp_s_axi_hp1"), + rp_s_axi_hp2("rp_s_axi_hp2"), + rp_s_axi_hp3("rp_s_axi_hp3"), + rp_s_axi_acp("rp_s_axi_acp"), + rp_wires_in("wires_in", 20, 0), + rp_wires_out("wires_out", 0, 17), + rp_irq_out("irq_out", 0, 28), + pl2ps_irq("pl2ps_irq", 20), + ps2pl_irq("ps2pl_irq", 28), + ps2pl_rst("ps2pl_rst", 17) +{ + int i; + + m_axi_gp[0] = &rp_m_axi_gp0.sk; + m_axi_gp[1] = &rp_m_axi_gp1.sk; + + s_axi_gp[0] = &rp_s_axi_gp0.sk; + s_axi_gp[1] = &rp_s_axi_gp1.sk; + + s_axi_hp[0] = &rp_s_axi_hp0.sk; + s_axi_hp[1] = &rp_s_axi_hp1.sk; + s_axi_hp[2] = &rp_s_axi_hp2.sk; + s_axi_hp[3] = &rp_s_axi_hp3.sk; + s_axi_acp = &rp_s_axi_acp.sk; + + /* PL to PS Interrupt signals. */ + for (i = 0; i < 20; i++) { + rp_wires_in.wires_in[i](pl2ps_irq[i]); + } + + /* PS to PL Interrupt signals. */ + for (i = 0; i < 28; i++) { + rp_irq_out.wires_out[i](ps2pl_irq[i]); + } + + /* PS to PL resets. */ + for (i = 0; i < 17; i++) { + rp_wires_out.wires_out[i](ps2pl_rst[i]); + } + + register_dev(0, &rp_s_axi_gp0); + register_dev(1, &rp_s_axi_gp1); + + register_dev(2, &rp_s_axi_hp0); + register_dev(3, &rp_s_axi_hp1); + register_dev(4, &rp_s_axi_hp2); + register_dev(5, &rp_s_axi_hp3); + + register_dev(6, &rp_s_axi_acp); + + register_dev(7, &rp_m_axi_gp0); + register_dev(8, &rp_m_axi_gp1); + register_dev(9, &rp_wires_in); + register_dev(10, &rp_wires_out); + register_dev(11, &rp_irq_out); +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/.Vivado_Synthesis.queue.rst b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/.vivado.begin.rst b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/.vivado.begin.rst new file mode 100644 index 0000000..7b9b2a6 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/.vivado.error.rst b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/.vivado.error.rst new file mode 100644 index 0000000..e69de29 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/ISEWrap.js b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/ISEWrap.js new file mode 100755 index 0000000..61806d0 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/ISEWrap.sh b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/ISEWrap.sh new file mode 100755 index 0000000..05d5381 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/ISEWrap.sh @@ -0,0 +1,85 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +cmd_exists() +{ + command -v "$1" >/dev/null 2>&1 +} + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! + +HostNameFile=/proc/sys/kernel/hostname +if cmd_exists hostname +then +ISE_HOST=$(hostname) +elif cmd_exists uname +then +ISE_HOST=$(uname -n) +elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] +then +ISE_HOST=$(cat $HostNameFile) +elif [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi + +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/NewExtInst_TOP_SPI_Con_0_0.tcl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/NewExtInst_TOP_SPI_Con_0_0.tcl new file mode 100644 index 0000000..7c8d5bb --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/NewExtInst_TOP_SPI_Con_0_0.tcl @@ -0,0 +1,244 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +namespace eval ::optrace { + variable script "/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/NewExtInst_TOP_SPI_Con_0_0.tcl" + variable category "vivado_synth" +} + +# Try to connect to running dispatch if we haven't done so already. +# This code assumes that the Tcl interpreter is not using threads, +# since the ::dispatch::connected variable isn't mutex protected. +if {![info exists ::dispatch::connected]} { + namespace eval ::dispatch { + variable connected false + if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} { + set result "true" + if {[catch { + if {[lsearch -exact [package names] DispatchTcl] < 0} { + set result [load librdi_cd_clienttcl[info sharedlibextension]] + } + if {$result eq "false"} { + puts "WARNING: Could not load dispatch client library" + } + set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ] + if { $connect_id eq "" } { + puts "WARNING: Could not initialize dispatch client" + } else { + puts "INFO: Dispatch client connection id - $connect_id" + set connected true + } + } catch_res]} { + puts "WARNING: failed to connect to dispatch server - $catch_res" + } + } + } +} +if {$::dispatch::connected} { + # Remove the dummy proc if it exists. + if { [expr {[llength [info procs ::OPTRACE]] > 0}] } { + rename ::OPTRACE "" + } + proc ::OPTRACE { task action {tags {} } } { + ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category + } + # dispatch is generic. We specifically want to attach logging. + ::vitis_log::connect_client +} else { + # Add dummy proc if it doesn't exist. + if { [expr {[llength [info procs ::OPTRACE]] == 0}] } { + proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} { + # Do nothing + } + } +} + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +OPTRACE "NewExtInst_TOP_SPI_Con_0_0_synth_1" START { ROLLUP_AUTO } +set_param chipscope.maxJobs 8 +set_msg_config -id {HDL-1065} -limit 10000 +set_param project.vivado.isBlockSynthRun true +OPTRACE "Creating in-memory project" START { } +create_project -in_memory -part xc7z035ffg676-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/wt [current_project] +set_property parent.project_path /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_repo_paths /home/ly0kos/work/Zynq/ip_repo [current_project] +update_ip_catalog +set_property ip_output_repo /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +OPTRACE "Creating in-memory project" END { } +OPTRACE "Adding files" START { } +read_ip -quiet /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0.xci + +OPTRACE "Adding files" END { } +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +set_param ips.enableIPCacheLiteLoad 1 +OPTRACE "Configure IP Cache" START { } + +set cacheID [config_ip_cache -export -no_bom -dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1 -new_name NewExtInst_TOP_SPI_Con_0_0 -ip [get_ips NewExtInst_TOP_SPI_Con_0_0]] + +OPTRACE "Configure IP Cache" END { } +if { $cacheID == "" } { +close [open __synthesis_is_running__ w] + +OPTRACE "synth_design" START { } +synth_design -top NewExtInst_TOP_SPI_Con_0_0 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context +OPTRACE "synth_design" END { } +OPTRACE "Write IP Cache" START { } + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix NewExtInst_TOP_SPI_Con_0_0_ NewExtInst_TOP_SPI_Con_0_0.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_SPI_Con_0_0_stub.v + lappend ipCachedFiles NewExtInst_TOP_SPI_Con_0_0_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_SPI_Con_0_0_stub.vhdl + lappend ipCachedFiles NewExtInst_TOP_SPI_Con_0_0_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_SPI_Con_0_0_sim_netlist.v + lappend ipCachedFiles NewExtInst_TOP_SPI_Con_0_0_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_SPI_Con_0_0_sim_netlist.vhdl + lappend ipCachedFiles NewExtInst_TOP_SPI_Con_0_0_sim_netlist.vhdl + set TIME_taken [expr [clock seconds] - $TIME_start] + + if { [get_msg_config -count -severity {CRITICAL WARNING}] == 0 } { + config_ip_cache -add -dcp NewExtInst_TOP_SPI_Con_0_0.dcp -move_files $ipCachedFiles -synth_runtime $TIME_taken -ip [get_ips NewExtInst_TOP_SPI_Con_0_0] + } +OPTRACE "Write IP Cache" END { } +} +if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } { + send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING" +} + +rename_ref -prefix_all NewExtInst_TOP_SPI_Con_0_0_ + +OPTRACE "write_checkpoint" START { CHECKPOINT } +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef NewExtInst_TOP_SPI_Con_0_0.dcp +OPTRACE "write_checkpoint" END { } +OPTRACE "synth reports" START { REPORT } +create_report "NewExtInst_TOP_SPI_Con_0_0_synth_1_synth_report_utilization_0" "report_utilization -file NewExtInst_TOP_SPI_Con_0_0_utilization_synth.rpt -pb NewExtInst_TOP_SPI_Con_0_0_utilization_synth.pb" +OPTRACE "synth reports" END { } + +if { [catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/NewExtInst_TOP_SPI_Con_0_0.dcp /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0.dcp +} _RESULT ] } { + send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file." + error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." +} + +if { [catch { + write_verilog -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +if { [catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/NewExtInst_TOP_SPI_Con_0_0.dcp /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0.dcp +} _RESULT ] } { + send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file." + error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." +} + +if { [catch { + file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/NewExtInst_TOP_SPI_Con_0_0_stub.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/NewExtInst_TOP_SPI_Con_0_0_stub.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/NewExtInst_TOP_SPI_Con_0_0_sim_netlist.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/NewExtInst_TOP_SPI_Con_0_0_sim_netlist.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +close [open .end.used_ip_cache.rst w] +}; # end if cacheID + +if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_SPI_Con_0_0]} { + catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0_stub.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_SPI_Con_0_0 + } +} + +if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_SPI_Con_0_0]} { + catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0_stub.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_SPI_Con_0_0 + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] +OPTRACE "NewExtInst_TOP_SPI_Con_0_0_synth_1" END { } diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/NewExtInst_TOP_SPI_Con_0_0.vds b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/NewExtInst_TOP_SPI_Con_0_0.vds new file mode 100644 index 0000000..1ea5d48 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/NewExtInst_TOP_SPI_Con_0_0.vds @@ -0,0 +1,48 @@ +#----------------------------------------------------------- +# Vivado v2023.2 (64-bit) +# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 +# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 +# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 +# Start of session at: Fri May 15 15:32:50 2026 +# Process ID: 127523 +# Current directory: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1 +# Command line: vivado -log NewExtInst_TOP_SPI_Con_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_SPI_Con_0_0.tcl +# Log file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/NewExtInst_TOP_SPI_Con_0_0.vds +# Journal file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/vivado.jou +# Running On: mkb, OS: Linux, CPU Frequency: 5101.762 MHz, CPU Physical cores: 32, Host memory: 134145 MB +#----------------------------------------------------------- +source NewExtInst_TOP_SPI_Con_0_0.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/ly0kos/work/Zynq/ip_repo'. +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'. +INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: NewExtInst_TOP_SPI_Con_0_0 +Command: synth_design -top NewExtInst_TOP_SPI_Con_0_0 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z035' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z035' +INFO: [Device 21-403] Loading part xc7z035ffg676-2 +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 127567 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2113.016 ; gain = 402.746 ; free physical = 40854 ; free virtual = 102695 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'NewExtInst_TOP_SPI_Con_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/synth/NewExtInst_TOP_SPI_Con_0_0.v:53] +INFO: [Synth 8-6157] synthesizing module 'SPI_Con_v1_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v:4] +INFO: [Synth 8-6157] synthesizing module 'SPI_Con_v1_0_S00_AXI' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v:4] +INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v:291] +INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v:656] +INFO: [Synth 8-6155] done synthesizing module 'SPI_Con_v1_0_S00_AXI' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v:4] +WARNING: [Synth 8-689] width (24) of port connection 'i_spi_data' does not match port width (1) of module 'SPI_Con_v1_0_S00_AXI' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v:86] +ERROR: [Synth 8-685] variable 'w_req' should not be used in output port connection [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v:88] +ERROR: [Synth 8-6156] failed synthesizing module 'SPI_Con_v1_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v:4] +ERROR: [Synth 8-6156] failed synthesizing module 'NewExtInst_TOP_SPI_Con_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/synth/NewExtInst_TOP_SPI_Con_0_0.v:53] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2191.984 ; gain = 481.715 ; free physical = 40761 ; free virtual = 102602 +--------------------------------------------------------------------------------- +RTL Elaboration failed +INFO: [Common 17-83] Releasing license: Synthesis +16 Infos, 1 Warnings, 0 Critical Warnings and 4 Errors encountered. +synth_design failed +ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details +INFO: [Common 17-206] Exiting Vivado at Fri May 15 15:32:58 2026... diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/__synthesis_is_running__ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/__synthesis_is_running__ new file mode 100644 index 0000000..e69de29 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/htr.txt b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/htr.txt new file mode 100644 index 0000000..12b8df4 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/htr.txt @@ -0,0 +1,10 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +vivado -log NewExtInst_TOP_SPI_Con_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_SPI_Con_0_0.tcl diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/rundef.js b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/rundef.js new file mode 100644 index 0000000..d7e8fbe --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/rundef.js @@ -0,0 +1,41 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;"; +} else { + PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log NewExtInst_TOP_SPI_Con_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_SPI_Con_0_0.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/runme.bat b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/runme.bat new file mode 100644 index 0000000..3a5f853 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/runme.bat @@ -0,0 +1,12 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/runme.sh b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/runme.sh new file mode 100755 index 0000000..6b85419 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/runme.sh @@ -0,0 +1,40 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin +else + PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log NewExtInst_TOP_SPI_Con_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_SPI_Con_0_0.tcl diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/.Vivado_Synthesis.queue.rst b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/.vivado.begin.rst b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/.vivado.begin.rst new file mode 100644 index 0000000..b4ddd68 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/.vivado.error.rst b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/.vivado.error.rst new file mode 100644 index 0000000..e69de29 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/ISEWrap.js b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/ISEWrap.js new file mode 100755 index 0000000..61806d0 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/ISEWrap.sh b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/ISEWrap.sh new file mode 100755 index 0000000..05d5381 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/ISEWrap.sh @@ -0,0 +1,85 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +cmd_exists() +{ + command -v "$1" >/dev/null 2>&1 +} + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! + +HostNameFile=/proc/sys/kernel/hostname +if cmd_exists hostname +then +ISE_HOST=$(hostname) +elif cmd_exists uname +then +ISE_HOST=$(uname -n) +elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] +then +ISE_HOST=$(cat $HostNameFile) +elif [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi + +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/NewExtInst_TOP_SPI_Con_0_1.tcl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/NewExtInst_TOP_SPI_Con_0_1.tcl new file mode 100644 index 0000000..fb718c7 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/NewExtInst_TOP_SPI_Con_0_1.tcl @@ -0,0 +1,244 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +namespace eval ::optrace { + variable script "/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/NewExtInst_TOP_SPI_Con_0_1.tcl" + variable category "vivado_synth" +} + +# Try to connect to running dispatch if we haven't done so already. +# This code assumes that the Tcl interpreter is not using threads, +# since the ::dispatch::connected variable isn't mutex protected. +if {![info exists ::dispatch::connected]} { + namespace eval ::dispatch { + variable connected false + if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} { + set result "true" + if {[catch { + if {[lsearch -exact [package names] DispatchTcl] < 0} { + set result [load librdi_cd_clienttcl[info sharedlibextension]] + } + if {$result eq "false"} { + puts "WARNING: Could not load dispatch client library" + } + set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ] + if { $connect_id eq "" } { + puts "WARNING: Could not initialize dispatch client" + } else { + puts "INFO: Dispatch client connection id - $connect_id" + set connected true + } + } catch_res]} { + puts "WARNING: failed to connect to dispatch server - $catch_res" + } + } + } +} +if {$::dispatch::connected} { + # Remove the dummy proc if it exists. + if { [expr {[llength [info procs ::OPTRACE]] > 0}] } { + rename ::OPTRACE "" + } + proc ::OPTRACE { task action {tags {} } } { + ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category + } + # dispatch is generic. We specifically want to attach logging. + ::vitis_log::connect_client +} else { + # Add dummy proc if it doesn't exist. + if { [expr {[llength [info procs ::OPTRACE]] == 0}] } { + proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} { + # Do nothing + } + } +} + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +OPTRACE "NewExtInst_TOP_SPI_Con_0_1_synth_1" START { ROLLUP_AUTO } +set_param chipscope.maxJobs 8 +set_msg_config -id {HDL-1065} -limit 10000 +set_param project.vivado.isBlockSynthRun true +OPTRACE "Creating in-memory project" START { } +create_project -in_memory -part xc7z035ffg676-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/wt [current_project] +set_property parent.project_path /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_repo_paths /home/ly0kos/work/Zynq/ip_repo [current_project] +update_ip_catalog +set_property ip_output_repo /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +OPTRACE "Creating in-memory project" END { } +OPTRACE "Adding files" START { } +read_ip -quiet /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1.xci + +OPTRACE "Adding files" END { } +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +set_param ips.enableIPCacheLiteLoad 1 +OPTRACE "Configure IP Cache" START { } + +set cacheID [config_ip_cache -export -no_bom -dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1 -new_name NewExtInst_TOP_SPI_Con_0_1 -ip [get_ips NewExtInst_TOP_SPI_Con_0_1]] + +OPTRACE "Configure IP Cache" END { } +if { $cacheID == "" } { +close [open __synthesis_is_running__ w] + +OPTRACE "synth_design" START { } +synth_design -top NewExtInst_TOP_SPI_Con_0_1 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context +OPTRACE "synth_design" END { } +OPTRACE "Write IP Cache" START { } + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix NewExtInst_TOP_SPI_Con_0_1_ NewExtInst_TOP_SPI_Con_0_1.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_SPI_Con_0_1_stub.v + lappend ipCachedFiles NewExtInst_TOP_SPI_Con_0_1_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_SPI_Con_0_1_stub.vhdl + lappend ipCachedFiles NewExtInst_TOP_SPI_Con_0_1_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_SPI_Con_0_1_sim_netlist.v + lappend ipCachedFiles NewExtInst_TOP_SPI_Con_0_1_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_SPI_Con_0_1_sim_netlist.vhdl + lappend ipCachedFiles NewExtInst_TOP_SPI_Con_0_1_sim_netlist.vhdl + set TIME_taken [expr [clock seconds] - $TIME_start] + + if { [get_msg_config -count -severity {CRITICAL WARNING}] == 0 } { + config_ip_cache -add -dcp NewExtInst_TOP_SPI_Con_0_1.dcp -move_files $ipCachedFiles -synth_runtime $TIME_taken -ip [get_ips NewExtInst_TOP_SPI_Con_0_1] + } +OPTRACE "Write IP Cache" END { } +} +if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } { + send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING" +} + +rename_ref -prefix_all NewExtInst_TOP_SPI_Con_0_1_ + +OPTRACE "write_checkpoint" START { CHECKPOINT } +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef NewExtInst_TOP_SPI_Con_0_1.dcp +OPTRACE "write_checkpoint" END { } +OPTRACE "synth reports" START { REPORT } +create_report "NewExtInst_TOP_SPI_Con_0_1_synth_1_synth_report_utilization_0" "report_utilization -file NewExtInst_TOP_SPI_Con_0_1_utilization_synth.rpt -pb NewExtInst_TOP_SPI_Con_0_1_utilization_synth.pb" +OPTRACE "synth reports" END { } + +if { [catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/NewExtInst_TOP_SPI_Con_0_1.dcp /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1.dcp +} _RESULT ] } { + send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file." + error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." +} + +if { [catch { + write_verilog -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +if { [catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/NewExtInst_TOP_SPI_Con_0_1.dcp /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1.dcp +} _RESULT ] } { + send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file." + error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." +} + +if { [catch { + file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/NewExtInst_TOP_SPI_Con_0_1_stub.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/NewExtInst_TOP_SPI_Con_0_1_stub.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/NewExtInst_TOP_SPI_Con_0_1_sim_netlist.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/NewExtInst_TOP_SPI_Con_0_1_sim_netlist.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +close [open .end.used_ip_cache.rst w] +}; # end if cacheID + +if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_SPI_Con_0_1]} { + catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1_stub.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_SPI_Con_0_1 + } +} + +if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_SPI_Con_0_1]} { + catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1_stub.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_SPI_Con_0_1 + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] +OPTRACE "NewExtInst_TOP_SPI_Con_0_1_synth_1" END { } diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/NewExtInst_TOP_SPI_Con_0_1.vds b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/NewExtInst_TOP_SPI_Con_0_1.vds new file mode 100644 index 0000000..62255be --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/NewExtInst_TOP_SPI_Con_0_1.vds @@ -0,0 +1,48 @@ +#----------------------------------------------------------- +# Vivado v2023.2 (64-bit) +# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 +# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 +# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 +# Start of session at: Fri May 15 15:33:09 2026 +# Process ID: 127747 +# Current directory: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1 +# Command line: vivado -log NewExtInst_TOP_SPI_Con_0_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_SPI_Con_0_1.tcl +# Log file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/NewExtInst_TOP_SPI_Con_0_1.vds +# Journal file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/vivado.jou +# Running On: mkb, OS: Linux, CPU Frequency: 5097.889 MHz, CPU Physical cores: 32, Host memory: 134145 MB +#----------------------------------------------------------- +source NewExtInst_TOP_SPI_Con_0_1.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/ly0kos/work/Zynq/ip_repo'. +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'. +INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: NewExtInst_TOP_SPI_Con_0_1 +Command: synth_design -top NewExtInst_TOP_SPI_Con_0_1 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z035' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z035' +INFO: [Device 21-403] Loading part xc7z035ffg676-2 +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 127781 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2112.500 ; gain = 402.746 ; free physical = 39342 ; free virtual = 101182 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'NewExtInst_TOP_SPI_Con_0_1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/synth/NewExtInst_TOP_SPI_Con_0_1.v:53] +INFO: [Synth 8-6157] synthesizing module 'SPI_Con_v1_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v:4] +INFO: [Synth 8-6157] synthesizing module 'SPI_Con_v1_0_S00_AXI' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v:4] +INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v:291] +INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v:656] +INFO: [Synth 8-6155] done synthesizing module 'SPI_Con_v1_0_S00_AXI' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v:4] +WARNING: [Synth 8-689] width (24) of port connection 'i_spi_data' does not match port width (1) of module 'SPI_Con_v1_0_S00_AXI' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v:86] +ERROR: [Synth 8-685] variable 'w_req' should not be used in output port connection [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v:88] +ERROR: [Synth 8-6156] failed synthesizing module 'SPI_Con_v1_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v:4] +ERROR: [Synth 8-6156] failed synthesizing module 'NewExtInst_TOP_SPI_Con_0_1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/synth/NewExtInst_TOP_SPI_Con_0_1.v:53] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2191.438 ; gain = 481.684 ; free physical = 39155 ; free virtual = 100996 +--------------------------------------------------------------------------------- +RTL Elaboration failed +INFO: [Common 17-83] Releasing license: Synthesis +16 Infos, 1 Warnings, 0 Critical Warnings and 4 Errors encountered. +synth_design failed +ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details +INFO: [Common 17-206] Exiting Vivado at Fri May 15 15:33:17 2026... diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/__synthesis_is_running__ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/__synthesis_is_running__ new file mode 100644 index 0000000..e69de29 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/htr.txt b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/htr.txt new file mode 100644 index 0000000..433b0c6 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/htr.txt @@ -0,0 +1,10 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +vivado -log NewExtInst_TOP_SPI_Con_0_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_SPI_Con_0_1.tcl diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/rundef.js b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/rundef.js new file mode 100644 index 0000000..bdbd1cd --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/rundef.js @@ -0,0 +1,41 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;"; +} else { + PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log NewExtInst_TOP_SPI_Con_0_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_SPI_Con_0_1.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/runme.bat b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/runme.bat new file mode 100644 index 0000000..3a5f853 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/runme.bat @@ -0,0 +1,12 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/runme.sh b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/runme.sh new file mode 100755 index 0000000..e2a8d6e --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/runme.sh @@ -0,0 +1,40 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin +else + PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log NewExtInst_TOP_SPI_Con_0_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_SPI_Con_0_1.tcl diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/.Vivado_Synthesis.queue.rst b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/.vivado.begin.rst b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/.vivado.begin.rst new file mode 100644 index 0000000..ed96ed9 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/.vivado.error.rst b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/.vivado.error.rst new file mode 100644 index 0000000..e69de29 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/ISEWrap.js b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/ISEWrap.js new file mode 100755 index 0000000..61806d0 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/ISEWrap.sh b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/ISEWrap.sh new file mode 100755 index 0000000..05d5381 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/ISEWrap.sh @@ -0,0 +1,85 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +cmd_exists() +{ + command -v "$1" >/dev/null 2>&1 +} + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! + +HostNameFile=/proc/sys/kernel/hostname +if cmd_exists hostname +then +ISE_HOST=$(hostname) +elif cmd_exists uname +then +ISE_HOST=$(uname -n) +elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] +then +ISE_HOST=$(cat $HostNameFile) +elif [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi + +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/NewExtInst_TOP_SPI_Con_0_2.tcl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/NewExtInst_TOP_SPI_Con_0_2.tcl new file mode 100644 index 0000000..3cdee42 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/NewExtInst_TOP_SPI_Con_0_2.tcl @@ -0,0 +1,244 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +namespace eval ::optrace { + variable script "/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/NewExtInst_TOP_SPI_Con_0_2.tcl" + variable category "vivado_synth" +} + +# Try to connect to running dispatch if we haven't done so already. +# This code assumes that the Tcl interpreter is not using threads, +# since the ::dispatch::connected variable isn't mutex protected. +if {![info exists ::dispatch::connected]} { + namespace eval ::dispatch { + variable connected false + if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} { + set result "true" + if {[catch { + if {[lsearch -exact [package names] DispatchTcl] < 0} { + set result [load librdi_cd_clienttcl[info sharedlibextension]] + } + if {$result eq "false"} { + puts "WARNING: Could not load dispatch client library" + } + set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ] + if { $connect_id eq "" } { + puts "WARNING: Could not initialize dispatch client" + } else { + puts "INFO: Dispatch client connection id - $connect_id" + set connected true + } + } catch_res]} { + puts "WARNING: failed to connect to dispatch server - $catch_res" + } + } + } +} +if {$::dispatch::connected} { + # Remove the dummy proc if it exists. + if { [expr {[llength [info procs ::OPTRACE]] > 0}] } { + rename ::OPTRACE "" + } + proc ::OPTRACE { task action {tags {} } } { + ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category + } + # dispatch is generic. We specifically want to attach logging. + ::vitis_log::connect_client +} else { + # Add dummy proc if it doesn't exist. + if { [expr {[llength [info procs ::OPTRACE]] == 0}] } { + proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} { + # Do nothing + } + } +} + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +OPTRACE "NewExtInst_TOP_SPI_Con_0_2_synth_1" START { ROLLUP_AUTO } +set_param chipscope.maxJobs 8 +set_msg_config -id {HDL-1065} -limit 10000 +set_param project.vivado.isBlockSynthRun true +OPTRACE "Creating in-memory project" START { } +create_project -in_memory -part xc7z035ffg676-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/wt [current_project] +set_property parent.project_path /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_repo_paths /home/ly0kos/work/Zynq/ip_repo [current_project] +update_ip_catalog +set_property ip_output_repo /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +OPTRACE "Creating in-memory project" END { } +OPTRACE "Adding files" START { } +read_ip -quiet /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/NewExtInst_TOP_SPI_Con_0_2.xci + +OPTRACE "Adding files" END { } +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +set_param ips.enableIPCacheLiteLoad 1 +OPTRACE "Configure IP Cache" START { } + +set cacheID [config_ip_cache -export -no_bom -dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1 -new_name NewExtInst_TOP_SPI_Con_0_2 -ip [get_ips NewExtInst_TOP_SPI_Con_0_2]] + +OPTRACE "Configure IP Cache" END { } +if { $cacheID == "" } { +close [open __synthesis_is_running__ w] + +OPTRACE "synth_design" START { } +synth_design -top NewExtInst_TOP_SPI_Con_0_2 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context +OPTRACE "synth_design" END { } +OPTRACE "Write IP Cache" START { } + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix NewExtInst_TOP_SPI_Con_0_2_ NewExtInst_TOP_SPI_Con_0_2.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_SPI_Con_0_2_stub.v + lappend ipCachedFiles NewExtInst_TOP_SPI_Con_0_2_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_SPI_Con_0_2_stub.vhdl + lappend ipCachedFiles NewExtInst_TOP_SPI_Con_0_2_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_SPI_Con_0_2_sim_netlist.v + lappend ipCachedFiles NewExtInst_TOP_SPI_Con_0_2_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_SPI_Con_0_2_sim_netlist.vhdl + lappend ipCachedFiles NewExtInst_TOP_SPI_Con_0_2_sim_netlist.vhdl + set TIME_taken [expr [clock seconds] - $TIME_start] + + if { [get_msg_config -count -severity {CRITICAL WARNING}] == 0 } { + config_ip_cache -add -dcp NewExtInst_TOP_SPI_Con_0_2.dcp -move_files $ipCachedFiles -synth_runtime $TIME_taken -ip [get_ips NewExtInst_TOP_SPI_Con_0_2] + } +OPTRACE "Write IP Cache" END { } +} +if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } { + send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING" +} + +rename_ref -prefix_all NewExtInst_TOP_SPI_Con_0_2_ + +OPTRACE "write_checkpoint" START { CHECKPOINT } +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef NewExtInst_TOP_SPI_Con_0_2.dcp +OPTRACE "write_checkpoint" END { } +OPTRACE "synth reports" START { REPORT } +create_report "NewExtInst_TOP_SPI_Con_0_2_synth_1_synth_report_utilization_0" "report_utilization -file NewExtInst_TOP_SPI_Con_0_2_utilization_synth.rpt -pb NewExtInst_TOP_SPI_Con_0_2_utilization_synth.pb" +OPTRACE "synth reports" END { } + +if { [catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/NewExtInst_TOP_SPI_Con_0_2.dcp /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/NewExtInst_TOP_SPI_Con_0_2.dcp +} _RESULT ] } { + send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file." + error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." +} + +if { [catch { + write_verilog -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/NewExtInst_TOP_SPI_Con_0_2_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/NewExtInst_TOP_SPI_Con_0_2_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/NewExtInst_TOP_SPI_Con_0_2_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/NewExtInst_TOP_SPI_Con_0_2_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +if { [catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/NewExtInst_TOP_SPI_Con_0_2.dcp /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/NewExtInst_TOP_SPI_Con_0_2.dcp +} _RESULT ] } { + send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file." + error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." +} + +if { [catch { + file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/NewExtInst_TOP_SPI_Con_0_2_stub.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/NewExtInst_TOP_SPI_Con_0_2_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/NewExtInst_TOP_SPI_Con_0_2_stub.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/NewExtInst_TOP_SPI_Con_0_2_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/NewExtInst_TOP_SPI_Con_0_2_sim_netlist.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/NewExtInst_TOP_SPI_Con_0_2_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/NewExtInst_TOP_SPI_Con_0_2_sim_netlist.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/NewExtInst_TOP_SPI_Con_0_2_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +close [open .end.used_ip_cache.rst w] +}; # end if cacheID + +if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_SPI_Con_0_2]} { + catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/NewExtInst_TOP_SPI_Con_0_2_stub.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_SPI_Con_0_2 + } +} + +if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_SPI_Con_0_2]} { + catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/NewExtInst_TOP_SPI_Con_0_2_stub.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_SPI_Con_0_2 + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] +OPTRACE "NewExtInst_TOP_SPI_Con_0_2_synth_1" END { } diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/NewExtInst_TOP_SPI_Con_0_2.vds b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/NewExtInst_TOP_SPI_Con_0_2.vds new file mode 100644 index 0000000..dada45b --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/NewExtInst_TOP_SPI_Con_0_2.vds @@ -0,0 +1,48 @@ +#----------------------------------------------------------- +# Vivado v2023.2 (64-bit) +# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 +# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 +# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 +# Start of session at: Fri May 15 15:33:09 2026 +# Process ID: 127748 +# Current directory: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1 +# Command line: vivado -log NewExtInst_TOP_SPI_Con_0_2.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_SPI_Con_0_2.tcl +# Log file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/NewExtInst_TOP_SPI_Con_0_2.vds +# Journal file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/vivado.jou +# Running On: mkb, OS: Linux, CPU Frequency: 5087.536 MHz, CPU Physical cores: 32, Host memory: 134145 MB +#----------------------------------------------------------- +source NewExtInst_TOP_SPI_Con_0_2.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/ly0kos/work/Zynq/ip_repo'. +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'. +INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: NewExtInst_TOP_SPI_Con_0_2 +Command: synth_design -top NewExtInst_TOP_SPI_Con_0_2 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z035' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z035' +INFO: [Device 21-403] Loading part xc7z035ffg676-2 +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 127773 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2113.031 ; gain = 404.715 ; free physical = 39342 ; free virtual = 101182 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'NewExtInst_TOP_SPI_Con_0_2' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/synth/NewExtInst_TOP_SPI_Con_0_2.v:53] +INFO: [Synth 8-6157] synthesizing module 'SPI_Con_v1_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v:4] +INFO: [Synth 8-6157] synthesizing module 'SPI_Con_v1_0_S00_AXI' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v:4] +INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v:291] +INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v:656] +INFO: [Synth 8-6155] done synthesizing module 'SPI_Con_v1_0_S00_AXI' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v:4] +WARNING: [Synth 8-689] width (24) of port connection 'i_spi_data' does not match port width (1) of module 'SPI_Con_v1_0_S00_AXI' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v:86] +ERROR: [Synth 8-685] variable 'w_req' should not be used in output port connection [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v:88] +ERROR: [Synth 8-6156] failed synthesizing module 'SPI_Con_v1_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v:4] +ERROR: [Synth 8-6156] failed synthesizing module 'NewExtInst_TOP_SPI_Con_0_2' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/synth/NewExtInst_TOP_SPI_Con_0_2.v:53] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2192.000 ; gain = 483.684 ; free physical = 39155 ; free virtual = 100996 +--------------------------------------------------------------------------------- +RTL Elaboration failed +INFO: [Common 17-83] Releasing license: Synthesis +16 Infos, 1 Warnings, 0 Critical Warnings and 4 Errors encountered. +synth_design failed +ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details +INFO: [Common 17-206] Exiting Vivado at Fri May 15 15:33:17 2026... diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/__synthesis_is_running__ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/__synthesis_is_running__ new file mode 100644 index 0000000..e69de29 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/htr.txt b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/htr.txt new file mode 100644 index 0000000..a6c71a5 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/htr.txt @@ -0,0 +1,10 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +vivado -log NewExtInst_TOP_SPI_Con_0_2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_SPI_Con_0_2.tcl diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/rundef.js b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/rundef.js new file mode 100644 index 0000000..3bad87d --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/rundef.js @@ -0,0 +1,41 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;"; +} else { + PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log NewExtInst_TOP_SPI_Con_0_2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_SPI_Con_0_2.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/runme.bat b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/runme.bat new file mode 100644 index 0000000..3a5f853 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/runme.bat @@ -0,0 +1,12 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/runme.sh b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/runme.sh new file mode 100755 index 0000000..c1e3a54 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/runme.sh @@ -0,0 +1,40 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin +else + PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log NewExtInst_TOP_SPI_Con_0_2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_SPI_Con_0_2.tcl diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/.Vivado_Synthesis.queue.rst b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/.vivado.begin.rst b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/.vivado.begin.rst new file mode 100644 index 0000000..8f5bee6 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/.vivado.end.rst b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/ISEWrap.js b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/ISEWrap.js new file mode 100755 index 0000000..61806d0 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/ISEWrap.sh b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/ISEWrap.sh new file mode 100755 index 0000000..05d5381 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/ISEWrap.sh @@ -0,0 +1,85 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +cmd_exists() +{ + command -v "$1" >/dev/null 2>&1 +} + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! + +HostNameFile=/proc/sys/kernel/hostname +if cmd_exists hostname +then +ISE_HOST=$(hostname) +elif cmd_exists uname +then +ISE_HOST=$(uname -n) +elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] +then +ISE_HOST=$(cat $HostNameFile) +elif [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi + +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/NewExtInst_TOP_clk_wiz_0_0.dcp b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/NewExtInst_TOP_clk_wiz_0_0.dcp new file mode 100644 index 0000000..160da3e Binary files /dev/null and b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/NewExtInst_TOP_clk_wiz_0_0.dcp differ diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/NewExtInst_TOP_clk_wiz_0_0.tcl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/NewExtInst_TOP_clk_wiz_0_0.tcl new file mode 100644 index 0000000..e0de891 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/NewExtInst_TOP_clk_wiz_0_0.tcl @@ -0,0 +1,248 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +namespace eval ::optrace { + variable script "/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/NewExtInst_TOP_clk_wiz_0_0.tcl" + variable category "vivado_synth" +} + +# Try to connect to running dispatch if we haven't done so already. +# This code assumes that the Tcl interpreter is not using threads, +# since the ::dispatch::connected variable isn't mutex protected. +if {![info exists ::dispatch::connected]} { + namespace eval ::dispatch { + variable connected false + if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} { + set result "true" + if {[catch { + if {[lsearch -exact [package names] DispatchTcl] < 0} { + set result [load librdi_cd_clienttcl[info sharedlibextension]] + } + if {$result eq "false"} { + puts "WARNING: Could not load dispatch client library" + } + set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ] + if { $connect_id eq "" } { + puts "WARNING: Could not initialize dispatch client" + } else { + puts "INFO: Dispatch client connection id - $connect_id" + set connected true + } + } catch_res]} { + puts "WARNING: failed to connect to dispatch server - $catch_res" + } + } + } +} +if {$::dispatch::connected} { + # Remove the dummy proc if it exists. + if { [expr {[llength [info procs ::OPTRACE]] > 0}] } { + rename ::OPTRACE "" + } + proc ::OPTRACE { task action {tags {} } } { + ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category + } + # dispatch is generic. We specifically want to attach logging. + ::vitis_log::connect_client +} else { + # Add dummy proc if it doesn't exist. + if { [expr {[llength [info procs ::OPTRACE]] == 0}] } { + proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} { + # Do nothing + } + } +} + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +OPTRACE "NewExtInst_TOP_clk_wiz_0_0_synth_1" START { ROLLUP_AUTO } +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +OPTRACE "Creating in-memory project" START { } +create_project -in_memory -part xc7z035ffg676-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/wt [current_project] +set_property parent.project_path /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_repo_paths /home/ly0kos/work/Zynq/ip_repo [current_project] +update_ip_catalog +set_property ip_output_repo /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +OPTRACE "Creating in-memory project" END { } +OPTRACE "Adding files" START { } +read_ip -quiet /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.xci +set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_board.xdc] +set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.xdc] +set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_ooc.xdc] + +OPTRACE "Adding files" END { } +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc dont_touch.xdc +set_property used_in_implementation false [get_files dont_touch.xdc] +set_param ips.enableIPCacheLiteLoad 1 +OPTRACE "Configure IP Cache" START { } + +set cacheID [config_ip_cache -export -no_bom -dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1 -new_name NewExtInst_TOP_clk_wiz_0_0 -ip [get_ips NewExtInst_TOP_clk_wiz_0_0]] + +OPTRACE "Configure IP Cache" END { } +if { $cacheID == "" } { +close [open __synthesis_is_running__ w] + +OPTRACE "synth_design" START { } +synth_design -top NewExtInst_TOP_clk_wiz_0_0 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context +OPTRACE "synth_design" END { } +OPTRACE "Write IP Cache" START { } + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix NewExtInst_TOP_clk_wiz_0_0_ NewExtInst_TOP_clk_wiz_0_0.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_clk_wiz_0_0_stub.v + lappend ipCachedFiles NewExtInst_TOP_clk_wiz_0_0_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_clk_wiz_0_0_stub.vhdl + lappend ipCachedFiles NewExtInst_TOP_clk_wiz_0_0_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_clk_wiz_0_0_sim_netlist.v + lappend ipCachedFiles NewExtInst_TOP_clk_wiz_0_0_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_clk_wiz_0_0_sim_netlist.vhdl + lappend ipCachedFiles NewExtInst_TOP_clk_wiz_0_0_sim_netlist.vhdl + set TIME_taken [expr [clock seconds] - $TIME_start] + + if { [get_msg_config -count -severity {CRITICAL WARNING}] == 0 } { + config_ip_cache -add -dcp NewExtInst_TOP_clk_wiz_0_0.dcp -move_files $ipCachedFiles -synth_runtime $TIME_taken -ip [get_ips NewExtInst_TOP_clk_wiz_0_0] + } +OPTRACE "Write IP Cache" END { } +} +if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } { + send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING" +} + +rename_ref -prefix_all NewExtInst_TOP_clk_wiz_0_0_ + +OPTRACE "write_checkpoint" START { CHECKPOINT } +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef NewExtInst_TOP_clk_wiz_0_0.dcp +OPTRACE "write_checkpoint" END { } +OPTRACE "synth reports" START { REPORT } +create_report "NewExtInst_TOP_clk_wiz_0_0_synth_1_synth_report_utilization_0" "report_utilization -file NewExtInst_TOP_clk_wiz_0_0_utilization_synth.rpt -pb NewExtInst_TOP_clk_wiz_0_0_utilization_synth.pb" +OPTRACE "synth reports" END { } + +if { [catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/NewExtInst_TOP_clk_wiz_0_0.dcp /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.dcp +} _RESULT ] } { + send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file." + error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." +} + +if { [catch { + write_verilog -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +if { [catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/NewExtInst_TOP_clk_wiz_0_0.dcp /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.dcp +} _RESULT ] } { + send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file." + error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." +} + +if { [catch { + file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/NewExtInst_TOP_clk_wiz_0_0_stub.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/NewExtInst_TOP_clk_wiz_0_0_stub.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/NewExtInst_TOP_clk_wiz_0_0_sim_netlist.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/NewExtInst_TOP_clk_wiz_0_0_sim_netlist.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +close [open .end.used_ip_cache.rst w] +}; # end if cacheID + +if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_clk_wiz_0_0]} { + catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_stub.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_clk_wiz_0_0 + } +} + +if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_clk_wiz_0_0]} { + catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_stub.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_clk_wiz_0_0 + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] +OPTRACE "NewExtInst_TOP_clk_wiz_0_0_synth_1" END { } diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/NewExtInst_TOP_clk_wiz_0_0.vds b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/NewExtInst_TOP_clk_wiz_0_0.vds new file mode 100644 index 0000000..3010606 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/NewExtInst_TOP_clk_wiz_0_0.vds @@ -0,0 +1,247 @@ +#----------------------------------------------------------- +# Vivado v2023.2 (64-bit) +# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 +# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 +# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 +# Start of session at: Fri May 15 15:26:41 2026 +# Process ID: 123454 +# Current directory: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1 +# Command line: vivado -log NewExtInst_TOP_clk_wiz_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_clk_wiz_0_0.tcl +# Log file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/NewExtInst_TOP_clk_wiz_0_0.vds +# Journal file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/vivado.jou +# Running On: mkb, OS: Linux, CPU Frequency: 5012.890 MHz, CPU Physical cores: 32, Host memory: 134145 MB +#----------------------------------------------------------- +source NewExtInst_TOP_clk_wiz_0_0.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/ly0kos/work/Zynq/ip_repo'. +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'. +INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: NewExtInst_TOP_clk_wiz_0_0 +Command: synth_design -top NewExtInst_TOP_clk_wiz_0_0 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z035' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z035' +INFO: [Device 21-403] Loading part xc7z035ffg676-2 +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 123539 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2123.926 ; gain = 413.684 ; free physical = 32203 ; free virtual = 94029 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'NewExtInst_TOP_clk_wiz_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.v:65] +INFO: [Synth 8-6157] synthesizing module 'NewExtInst_TOP_clk_wiz_0_0_clk_wiz' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_clk_wiz.v:65] +INFO: [Synth 8-6157] synthesizing module 'IBUF' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:73631] +INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:73631] +INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:82174] + Parameter BANDWIDTH bound to: OPTIMIZED - type: string + Parameter CLKFBOUT_MULT_F bound to: 40.000000 - type: double + Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double + Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKIN1_PERIOD bound to: 40.000000 - type: double + Parameter CLKOUT0_DIVIDE_F bound to: 10.000000 - type: double + Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT4_CASCADE bound to: FALSE - type: string + Parameter COMPENSATION bound to: ZHOLD - type: string + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter STARTUP_WAIT bound to: FALSE - type: string +INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:82174] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6155] done synthesizing module 'NewExtInst_TOP_clk_wiz_0_0_clk_wiz' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_clk_wiz.v:65] +INFO: [Synth 8-6155] done synthesizing module 'NewExtInst_TOP_clk_wiz_0_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.v:65] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2199.895 ; gain = 489.652 ; free physical = 31617 ; free virtual = 93444 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2214.738 ; gain = 504.496 ; free physical = 31608 ; free virtual = 93436 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2214.738 ; gain = 504.496 ; free physical = 31608 ; free virtual = 93436 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2220.676 ; gain = 0.000 ; free physical = 31636 ; free virtual = 93464 +INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_ooc.xdc] for cell 'inst' +Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_board.xdc] for cell 'inst' +Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_board.xdc] for cell 'inst' +Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.xdc] for cell 'inst' +Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.xdc] for cell 'inst' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/NewExtInst_TOP_clk_wiz_0_0_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/NewExtInst_TOP_clk_wiz_0_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Timing 38-2] Deriving generated clocks +Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/dont_touch.xdc] +Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2287.676 ; gain = 0.000 ; free physical = 31381 ; free virtual = 93209 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2287.711 ; gain = 0.000 ; free physical = 31380 ; free virtual = 93208 +INFO: [Designutils 20-5008] Incremental synthesis strategy off +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31246 ; free virtual = 93076 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z035ffg676-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31246 ; free virtual = 93076 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/dont_touch.xdc, line 9). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31246 ; free virtual = 93077 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31243 ; free virtual = 93075 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 900 (col length:140) +BRAMs: 1000 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31257 ; free virtual = 93092 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31284 ; free virtual = 93120 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31284 ; free virtual = 93120 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31284 ; free virtual = 93120 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31144 ; free virtual = 92979 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31144 ; free virtual = 92979 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31144 ; free virtual = 92979 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31144 ; free virtual = 92979 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31144 ; free virtual = 92979 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31144 ; free virtual = 92979 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----------+------+ +| |Cell |Count | ++------+-----------+------+ +|1 |BUFG | 2| +|2 |MMCME2_ADV | 1| +|3 |IBUF | 1| ++------+-----------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31144 ; free virtual = 92979 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2287.711 ; gain = 504.496 ; free physical = 31145 ; free virtual = 92980 +Synthesis Optimization Complete : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31145 ; free virtual = 92980 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2287.711 ; gain = 0.000 ; free physical = 31145 ; free virtual = 92980 +INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2287.711 ; gain = 0.000 ; free physical = 31675 ; free virtual = 93510 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Synth Design complete | Checksum: 9139fe31 +INFO: [Common 17-83] Releasing license: Synthesis +33 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 2287.711 ; gain = 956.957 ; free physical = 31956 ; free virtual = 93791 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1660.118; main = 1359.195; forked = 307.572 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3258.320; main = 2255.664; forked = 1002.656 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2287.711 ; gain = 0.000 ; free physical = 31968 ; free virtual = 93803 +INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/NewExtInst_TOP_clk_wiz_0_0.dcp' has been generated. +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP NewExtInst_TOP_clk_wiz_0_0, cache-ID = fd36933d4d3c9079 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2311.688 ; gain = 0.000 ; free physical = 31968 ; free virtual = 93804 +INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/NewExtInst_TOP_clk_wiz_0_0.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file NewExtInst_TOP_clk_wiz_0_0_utilization_synth.rpt -pb NewExtInst_TOP_clk_wiz_0_0_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Fri May 15 15:26:59 2026... diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/__synthesis_is_complete__ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/__synthesis_is_complete__ new file mode 100644 index 0000000..e69de29 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/dont_touch.xdc b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/dont_touch.xdc new file mode 100644 index 0000000..632fc1e --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/dont_touch.xdc @@ -0,0 +1,32 @@ +# This file is automatically generated. +# It contains project source information necessary for synthesis and implementation. + +# IP: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.xci +# IP: The module: 'NewExtInst_TOP_clk_wiz_0_0' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_board.xdc +# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_clk_wiz_0_0'. Do not add the DONT_TOUCH constraint. +set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet + +# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.xdc +# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_clk_wiz_0_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet + +# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_clk_wiz_0_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet + +# IP: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.xci +# IP: The module: 'NewExtInst_TOP_clk_wiz_0_0' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_board.xdc +# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_clk_wiz_0_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet + +# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.xdc +# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_clk_wiz_0_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet + +# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_clk_wiz_0_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/htr.txt b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/htr.txt new file mode 100644 index 0000000..b32f956 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/htr.txt @@ -0,0 +1,10 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +vivado -log NewExtInst_TOP_clk_wiz_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_clk_wiz_0_0.tcl diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/rundef.js b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/rundef.js new file mode 100644 index 0000000..0fb06b6 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/rundef.js @@ -0,0 +1,41 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;"; +} else { + PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log NewExtInst_TOP_clk_wiz_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_clk_wiz_0_0.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/runme.bat b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/runme.bat new file mode 100644 index 0000000..3a5f853 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/runme.bat @@ -0,0 +1,12 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/runme.sh b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/runme.sh new file mode 100755 index 0000000..899ca4a --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/runme.sh @@ -0,0 +1,40 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin +else + PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log NewExtInst_TOP_clk_wiz_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_clk_wiz_0_0.tcl diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/.Vivado_Synthesis.queue.rst b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/.vivado.begin.rst b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/.vivado.begin.rst new file mode 100644 index 0000000..31a4cb9 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/.vivado.end.rst b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/ISEWrap.js b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/ISEWrap.js new file mode 100755 index 0000000..61806d0 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/ISEWrap.sh b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/ISEWrap.sh new file mode 100755 index 0000000..05d5381 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/ISEWrap.sh @@ -0,0 +1,85 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +cmd_exists() +{ + command -v "$1" >/dev/null 2>&1 +} + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! + +HostNameFile=/proc/sys/kernel/hostname +if cmd_exists hostname +then +ISE_HOST=$(hostname) +elif cmd_exists uname +then +ISE_HOST=$(uname -n) +elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] +then +ISE_HOST=$(cat $HostNameFile) +elif [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi + +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/NewExtInst_TOP_proc_sys_reset_0_0.dcp b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/NewExtInst_TOP_proc_sys_reset_0_0.dcp new file mode 100644 index 0000000..3416d89 Binary files /dev/null and b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/NewExtInst_TOP_proc_sys_reset_0_0.dcp differ diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/NewExtInst_TOP_proc_sys_reset_0_0.tcl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/NewExtInst_TOP_proc_sys_reset_0_0.tcl new file mode 100644 index 0000000..9d10b4f --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/NewExtInst_TOP_proc_sys_reset_0_0.tcl @@ -0,0 +1,248 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +namespace eval ::optrace { + variable script "/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/NewExtInst_TOP_proc_sys_reset_0_0.tcl" + variable category "vivado_synth" +} + +# Try to connect to running dispatch if we haven't done so already. +# This code assumes that the Tcl interpreter is not using threads, +# since the ::dispatch::connected variable isn't mutex protected. +if {![info exists ::dispatch::connected]} { + namespace eval ::dispatch { + variable connected false + if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} { + set result "true" + if {[catch { + if {[lsearch -exact [package names] DispatchTcl] < 0} { + set result [load librdi_cd_clienttcl[info sharedlibextension]] + } + if {$result eq "false"} { + puts "WARNING: Could not load dispatch client library" + } + set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ] + if { $connect_id eq "" } { + puts "WARNING: Could not initialize dispatch client" + } else { + puts "INFO: Dispatch client connection id - $connect_id" + set connected true + } + } catch_res]} { + puts "WARNING: failed to connect to dispatch server - $catch_res" + } + } + } +} +if {$::dispatch::connected} { + # Remove the dummy proc if it exists. + if { [expr {[llength [info procs ::OPTRACE]] > 0}] } { + rename ::OPTRACE "" + } + proc ::OPTRACE { task action {tags {} } } { + ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category + } + # dispatch is generic. We specifically want to attach logging. + ::vitis_log::connect_client +} else { + # Add dummy proc if it doesn't exist. + if { [expr {[llength [info procs ::OPTRACE]] == 0}] } { + proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} { + # Do nothing + } + } +} + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +OPTRACE "NewExtInst_TOP_proc_sys_reset_0_0_synth_1" START { ROLLUP_AUTO } +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +OPTRACE "Creating in-memory project" START { } +create_project -in_memory -part xc7z035ffg676-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/wt [current_project] +set_property parent.project_path /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_repo_paths /home/ly0kos/work/Zynq/ip_repo [current_project] +update_ip_catalog +set_property ip_output_repo /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +OPTRACE "Creating in-memory project" END { } +OPTRACE "Adding files" START { } +read_ip -quiet /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0.xci +set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_board.xdc] +set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0.xdc] +set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_ooc.xdc] + +OPTRACE "Adding files" END { } +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc dont_touch.xdc +set_property used_in_implementation false [get_files dont_touch.xdc] +set_param ips.enableIPCacheLiteLoad 1 +OPTRACE "Configure IP Cache" START { } + +set cacheID [config_ip_cache -export -no_bom -dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1 -new_name NewExtInst_TOP_proc_sys_reset_0_0 -ip [get_ips NewExtInst_TOP_proc_sys_reset_0_0]] + +OPTRACE "Configure IP Cache" END { } +if { $cacheID == "" } { +close [open __synthesis_is_running__ w] + +OPTRACE "synth_design" START { } +synth_design -top NewExtInst_TOP_proc_sys_reset_0_0 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context +OPTRACE "synth_design" END { } +OPTRACE "Write IP Cache" START { } + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix NewExtInst_TOP_proc_sys_reset_0_0_ NewExtInst_TOP_proc_sys_reset_0_0.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_proc_sys_reset_0_0_stub.v + lappend ipCachedFiles NewExtInst_TOP_proc_sys_reset_0_0_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_proc_sys_reset_0_0_stub.vhdl + lappend ipCachedFiles NewExtInst_TOP_proc_sys_reset_0_0_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_proc_sys_reset_0_0_sim_netlist.v + lappend ipCachedFiles NewExtInst_TOP_proc_sys_reset_0_0_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_proc_sys_reset_0_0_sim_netlist.vhdl + lappend ipCachedFiles NewExtInst_TOP_proc_sys_reset_0_0_sim_netlist.vhdl + set TIME_taken [expr [clock seconds] - $TIME_start] + + if { [get_msg_config -count -severity {CRITICAL WARNING}] == 0 } { + config_ip_cache -add -dcp NewExtInst_TOP_proc_sys_reset_0_0.dcp -move_files $ipCachedFiles -synth_runtime $TIME_taken -ip [get_ips NewExtInst_TOP_proc_sys_reset_0_0] + } +OPTRACE "Write IP Cache" END { } +} +if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } { + send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING" +} + +rename_ref -prefix_all NewExtInst_TOP_proc_sys_reset_0_0_ + +OPTRACE "write_checkpoint" START { CHECKPOINT } +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef NewExtInst_TOP_proc_sys_reset_0_0.dcp +OPTRACE "write_checkpoint" END { } +OPTRACE "synth reports" START { REPORT } +create_report "NewExtInst_TOP_proc_sys_reset_0_0_synth_1_synth_report_utilization_0" "report_utilization -file NewExtInst_TOP_proc_sys_reset_0_0_utilization_synth.rpt -pb NewExtInst_TOP_proc_sys_reset_0_0_utilization_synth.pb" +OPTRACE "synth reports" END { } + +if { [catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/NewExtInst_TOP_proc_sys_reset_0_0.dcp /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0.dcp +} _RESULT ] } { + send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file." + error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." +} + +if { [catch { + write_verilog -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +if { [catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/NewExtInst_TOP_proc_sys_reset_0_0.dcp /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0.dcp +} _RESULT ] } { + send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file." + error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." +} + +if { [catch { + file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/NewExtInst_TOP_proc_sys_reset_0_0_stub.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/NewExtInst_TOP_proc_sys_reset_0_0_stub.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/NewExtInst_TOP_proc_sys_reset_0_0_sim_netlist.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/NewExtInst_TOP_proc_sys_reset_0_0_sim_netlist.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +close [open .end.used_ip_cache.rst w] +}; # end if cacheID + +if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_proc_sys_reset_0_0]} { + catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_stub.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_proc_sys_reset_0_0 + } +} + +if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_proc_sys_reset_0_0]} { + catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_stub.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_proc_sys_reset_0_0 + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] +OPTRACE "NewExtInst_TOP_proc_sys_reset_0_0_synth_1" END { } diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/NewExtInst_TOP_proc_sys_reset_0_0.vds b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/NewExtInst_TOP_proc_sys_reset_0_0.vds new file mode 100644 index 0000000..40d6986 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/NewExtInst_TOP_proc_sys_reset_0_0.vds @@ -0,0 +1,300 @@ +#----------------------------------------------------------- +# Vivado v2023.2 (64-bit) +# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 +# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 +# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 +# Start of session at: Fri May 15 15:26:41 2026 +# Process ID: 123448 +# Current directory: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1 +# Command line: vivado -log NewExtInst_TOP_proc_sys_reset_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_proc_sys_reset_0_0.tcl +# Log file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/NewExtInst_TOP_proc_sys_reset_0_0.vds +# Journal file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/vivado.jou +# Running On: mkb, OS: Linux, CPU Frequency: 5005.748 MHz, CPU Physical cores: 32, Host memory: 134145 MB +#----------------------------------------------------------- +source NewExtInst_TOP_proc_sys_reset_0_0.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/ly0kos/work/Zynq/ip_repo'. +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'. +INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: NewExtInst_TOP_proc_sys_reset_0_0 +Command: synth_design -top NewExtInst_TOP_proc_sys_reset_0_0 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z035' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z035' +INFO: [Device 21-403] Loading part xc7z035ffg676-2 +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 123650 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2121.020 ; gain = 411.746 ; free physical = 32054 ; free virtual = 93879 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'NewExtInst_TOP_proc_sys_reset_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/synth/NewExtInst_TOP_proc_sys_reset_0_0.vhd:74] + Parameter C_FAMILY bound to: zynq - type: string + Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer + Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer + Parameter C_EXT_RESET_HIGH bound to: 1'b0 + Parameter C_AUX_RESET_HIGH bound to: 1'b0 + Parameter C_NUM_BUS_RST bound to: 1 - type: integer + Parameter C_NUM_PERP_RST bound to: 1 - type: integer + Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer + Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer +INFO: [Synth 8-3491] module 'proc_sys_reset' declared at '/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1271' bound to instance 'U0' of component 'proc_sys_reset' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/synth/NewExtInst_TOP_proc_sys_reset_0_0.vhd:129] +INFO: [Synth 8-638] synthesizing module 'proc_sys_reset' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1330] + Parameter INIT bound to: 1'b1 +INFO: [Synth 8-113] binding component instance 'FDRE_inst' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1399] + Parameter INIT bound to: 1'b1 +INFO: [Synth 8-113] binding component instance 'FDRE_BSR' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1415] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'FDRE_BSR_N' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1441] + Parameter INIT bound to: 1'b1 +INFO: [Synth 8-113] binding component instance 'FDRE_PER' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1464] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'FDRE_PER_N' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1488] +INFO: [Synth 8-638] synthesizing module 'lpf' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:821] +INFO: [Synth 8-3491] module 'SRL16' declared at '/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721' bound to instance 'POR_SRL_I' of component 'SRL16' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:873] +INFO: [Synth 8-6157] synthesizing module 'SRL16' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721] +INFO: [Synth 8-6155] done synthesizing module 'SRL16' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721] +INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:514] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:545] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:554] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:564] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:574] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:584] +INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] +INFO: [Synth 8-256] done synthesizing module 'lpf' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:821] +INFO: [Synth 8-638] synthesizing module 'sequence_psr' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:304] +INFO: [Synth 8-638] synthesizing module 'upcnt_n' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:126] +INFO: [Synth 8-256] done synthesizing module 'upcnt_n' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:126] +INFO: [Synth 8-256] done synthesizing module 'sequence_psr' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:304] +INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1330] +INFO: [Synth 8-256] done synthesizing module 'NewExtInst_TOP_proc_sys_reset_0_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/synth/NewExtInst_TOP_proc_sys_reset_0_0.vhd:74] +WARNING: [Synth 8-7129] Port prmry_aclk in module cdc_sync is either unconnected or has no load +WARNING: [Synth 8-7129] Port prmry_resetn in module cdc_sync is either unconnected or has no load +WARNING: [Synth 8-7129] Port prmry_vect_in[1] in module cdc_sync is either unconnected or has no load +WARNING: [Synth 8-7129] Port prmry_vect_in[0] in module cdc_sync is either unconnected or has no load +WARNING: [Synth 8-7129] Port scndry_resetn in module cdc_sync is either unconnected or has no load +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2199.988 ; gain = 490.715 ; free physical = 31580 ; free virtual = 93409 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2214.832 ; gain = 505.559 ; free physical = 31565 ; free virtual = 93393 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2214.832 ; gain = 505.559 ; free physical = 31565 ; free virtual = 93393 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2220.770 ; gain = 0.000 ; free physical = 31562 ; free virtual = 93390 +INFO: [Netlist 29-17] Analyzing 13 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_ooc.xdc] for cell 'U0' +Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_ooc.xdc] for cell 'U0' +Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_board.xdc] for cell 'U0' +Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_board.xdc] for cell 'U0' +Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0.xdc] for cell 'U0' +Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0.xdc] for cell 'U0' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/NewExtInst_TOP_proc_sys_reset_0_0_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/NewExtInst_TOP_proc_sys_reset_0_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/dont_touch.xdc] +Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2368.582 ; gain = 0.000 ; free physical = 31353 ; free virtual = 93181 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 13 instances were transformed. + FDR => FDRE: 12 instances + SRL16 => SRL16E: 1 instance + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2368.617 ; gain = 0.000 ; free physical = 31345 ; free virtual = 93174 +INFO: [Designutils 20-5008] Incremental synthesis strategy off +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31241 ; free virtual = 93074 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z035ffg676-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31241 ; free virtual = 93074 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property KEEP_HIERARCHY = SOFT for U0. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/dont_touch.xdc, line 9). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31241 ; free virtual = 93074 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31238 ; free virtual = 93073 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 6 Bit Adders := 1 ++---Registers : + 6 Bit Registers := 1 + 3 Bit Registers := 3 + 1 Bit Registers := 8 ++---Muxes : + 2 Input 6 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 900 (col length:140) +BRAMs: 1000 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module proc_sys_reset. +WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module proc_sys_reset. +WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module proc_sys_reset. +WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module proc_sys_reset. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31257 ; free virtual = 93091 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31261 ; free virtual = 93096 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31261 ; free virtual = 93096 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31245 ; free virtual = 93081 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31675 ; free virtual = 93510 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31675 ; free virtual = 93510 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31675 ; free virtual = 93510 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31675 ; free virtual = 93510 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31675 ; free virtual = 93510 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31675 ; free virtual = 93510 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+------+------+ +| |Cell |Count | ++------+------+------+ +|1 |LUT1 | 5| +|2 |LUT2 | 9| +|3 |LUT3 | 1| +|4 |LUT4 | 6| +|5 |LUT5 | 3| +|6 |LUT6 | 1| +|7 |SRL16 | 1| +|8 |FDR | 8| +|9 |FDRE | 28| +|10 |FDSE | 4| ++------+------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31675 ; free virtual = 93510 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 5 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2368.617 ; gain = 505.559 ; free physical = 31675 ; free virtual = 93510 +Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31675 ; free virtual = 93510 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2368.617 ; gain = 0.000 ; free physical = 31675 ; free virtual = 93510 +INFO: [Netlist 29-17] Analyzing 9 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2368.617 ; gain = 0.000 ; free physical = 31970 ; free virtual = 93803 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 9 instances were transformed. + FDR => FDRE: 8 instances + SRL16 => SRL16E: 1 instance + +Synth Design complete | Checksum: afc55a15 +INFO: [Common 17-83] Releasing license: Synthesis +49 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:14 . Memory (MB): peak = 2368.617 ; gain = 1038.895 ; free physical = 31970 ; free virtual = 93803 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1683.673; main = 1382.355; forked = 308.374 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3339.230; main = 2368.586; forked = 1002.660 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2392.594 ; gain = 0.000 ; free physical = 31970 ; free virtual = 93803 +INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/NewExtInst_TOP_proc_sys_reset_0_0.dcp' has been generated. +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP NewExtInst_TOP_proc_sys_reset_0_0, cache-ID = 38386ef74787698d +INFO: [Coretcl 2-1174] Renamed 6 cell refs. +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2392.594 ; gain = 0.000 ; free physical = 31970 ; free virtual = 93803 +INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/NewExtInst_TOP_proc_sys_reset_0_0.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file NewExtInst_TOP_proc_sys_reset_0_0_utilization_synth.rpt -pb NewExtInst_TOP_proc_sys_reset_0_0_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Fri May 15 15:26:59 2026... diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/__synthesis_is_complete__ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/__synthesis_is_complete__ new file mode 100644 index 0000000..e69de29 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/dont_touch.xdc b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/dont_touch.xdc new file mode 100644 index 0000000..2bc8041 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/dont_touch.xdc @@ -0,0 +1,32 @@ +# This file is automatically generated. +# It contains project source information necessary for synthesis and implementation. + +# IP: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0.xci +# IP: The module: 'NewExtInst_TOP_proc_sys_reset_0_0' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_board.xdc +# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_proc_sys_reset_0_0'. Do not add the DONT_TOUCH constraint. +set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet + +# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0.xdc +# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_proc_sys_reset_0_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet + +# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_proc_sys_reset_0_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet + +# IP: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0.xci +# IP: The module: 'NewExtInst_TOP_proc_sys_reset_0_0' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_board.xdc +# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_proc_sys_reset_0_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet + +# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0.xdc +# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_proc_sys_reset_0_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet + +# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_proc_sys_reset_0_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/htr.txt b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/htr.txt new file mode 100644 index 0000000..ad38fa3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/htr.txt @@ -0,0 +1,10 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +vivado -log NewExtInst_TOP_proc_sys_reset_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_proc_sys_reset_0_0.tcl diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/rundef.js b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/rundef.js new file mode 100644 index 0000000..c90e46b --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/rundef.js @@ -0,0 +1,41 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;"; +} else { + PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log NewExtInst_TOP_proc_sys_reset_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_proc_sys_reset_0_0.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/runme.bat b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/runme.bat new file mode 100644 index 0000000..3a5f853 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/runme.bat @@ -0,0 +1,12 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/runme.sh b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/runme.sh new file mode 100755 index 0000000..b6c2e3a --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/runme.sh @@ -0,0 +1,40 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin +else + PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log NewExtInst_TOP_proc_sys_reset_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_proc_sys_reset_0_0.tcl diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/.Vivado_Synthesis.queue.rst b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/.vivado.begin.rst b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/.vivado.begin.rst new file mode 100644 index 0000000..21b8cc5 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/.vivado.end.rst b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/ISEWrap.js b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/ISEWrap.js new file mode 100755 index 0000000..61806d0 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/ISEWrap.sh b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/ISEWrap.sh new file mode 100755 index 0000000..05d5381 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/ISEWrap.sh @@ -0,0 +1,85 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +cmd_exists() +{ + command -v "$1" >/dev/null 2>&1 +} + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! + +HostNameFile=/proc/sys/kernel/hostname +if cmd_exists hostname +then +ISE_HOST=$(hostname) +elif cmd_exists uname +then +ISE_HOST=$(uname -n) +elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] +then +ISE_HOST=$(cat $HostNameFile) +elif [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi + +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/NewExtInst_TOP_processing_system7_0_0.dcp b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/NewExtInst_TOP_processing_system7_0_0.dcp new file mode 100644 index 0000000..1c577be Binary files /dev/null and b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/NewExtInst_TOP_processing_system7_0_0.dcp differ diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/NewExtInst_TOP_processing_system7_0_0.tcl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/NewExtInst_TOP_processing_system7_0_0.tcl new file mode 100644 index 0000000..16c641a --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/NewExtInst_TOP_processing_system7_0_0.tcl @@ -0,0 +1,172 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +namespace eval ::optrace { + variable script "/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/NewExtInst_TOP_processing_system7_0_0.tcl" + variable category "vivado_synth" +} + +# Try to connect to running dispatch if we haven't done so already. +# This code assumes that the Tcl interpreter is not using threads, +# since the ::dispatch::connected variable isn't mutex protected. +if {![info exists ::dispatch::connected]} { + namespace eval ::dispatch { + variable connected false + if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} { + set result "true" + if {[catch { + if {[lsearch -exact [package names] DispatchTcl] < 0} { + set result [load librdi_cd_clienttcl[info sharedlibextension]] + } + if {$result eq "false"} { + puts "WARNING: Could not load dispatch client library" + } + set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ] + if { $connect_id eq "" } { + puts "WARNING: Could not initialize dispatch client" + } else { + puts "INFO: Dispatch client connection id - $connect_id" + set connected true + } + } catch_res]} { + puts "WARNING: failed to connect to dispatch server - $catch_res" + } + } + } +} +if {$::dispatch::connected} { + # Remove the dummy proc if it exists. + if { [expr {[llength [info procs ::OPTRACE]] > 0}] } { + rename ::OPTRACE "" + } + proc ::OPTRACE { task action {tags {} } } { + ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category + } + # dispatch is generic. We specifically want to attach logging. + ::vitis_log::connect_client +} else { + # Add dummy proc if it doesn't exist. + if { [expr {[llength [info procs ::OPTRACE]] == 0}] } { + proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} { + # Do nothing + } + } +} + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +OPTRACE "NewExtInst_TOP_processing_system7_0_0_synth_1" START { ROLLUP_AUTO } +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +OPTRACE "Creating in-memory project" START { } +create_project -in_memory -part xc7z035ffg676-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/wt [current_project] +set_property parent.project_path /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_repo_paths /home/ly0kos/work/Zynq/ip_repo [current_project] +update_ip_catalog +set_property ip_output_repo /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +OPTRACE "Creating in-memory project" END { } +OPTRACE "Adding files" START { } +read_ip -quiet /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0.xci +set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0.xdc] + +OPTRACE "Adding files" END { } +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc dont_touch.xdc +set_property used_in_implementation false [get_files dont_touch.xdc] +set_param ips.enableIPCacheLiteLoad 1 +close [open __synthesis_is_running__ w] + +OPTRACE "synth_design" START { } +synth_design -top NewExtInst_TOP_processing_system7_0_0 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context +OPTRACE "synth_design" END { } +if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } { + send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING" +} + +rename_ref -prefix_all NewExtInst_TOP_processing_system7_0_0_ + +OPTRACE "write_checkpoint" START { CHECKPOINT } +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef NewExtInst_TOP_processing_system7_0_0.dcp +OPTRACE "write_checkpoint" END { } +OPTRACE "synth reports" START { REPORT } +create_report "NewExtInst_TOP_processing_system7_0_0_synth_1_synth_report_utilization_0" "report_utilization -file NewExtInst_TOP_processing_system7_0_0_utilization_synth.rpt -pb NewExtInst_TOP_processing_system7_0_0_utilization_synth.pb" +OPTRACE "synth reports" END { } + +if { [catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/NewExtInst_TOP_processing_system7_0_0.dcp /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0.dcp +} _RESULT ] } { + send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file." + error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." +} + +if { [catch { + write_verilog -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_processing_system7_0_0]} { + catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0_stub.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_processing_system7_0_0 + } +} + +if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_processing_system7_0_0]} { + catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0_stub.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_processing_system7_0_0 + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] +OPTRACE "NewExtInst_TOP_processing_system7_0_0_synth_1" END { } diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/NewExtInst_TOP_processing_system7_0_0.vds b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/NewExtInst_TOP_processing_system7_0_0.vds new file mode 100644 index 0000000..50c3fe9 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/NewExtInst_TOP_processing_system7_0_0.vds @@ -0,0 +1,337 @@ +#----------------------------------------------------------- +# Vivado v2023.2 (64-bit) +# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 +# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 +# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 +# Start of session at: Fri May 15 15:26:41 2026 +# Process ID: 123452 +# Current directory: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1 +# Command line: vivado -log NewExtInst_TOP_processing_system7_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_processing_system7_0_0.tcl +# Log file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/NewExtInst_TOP_processing_system7_0_0.vds +# Journal file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/vivado.jou +# Running On: mkb, OS: Linux, CPU Frequency: 4987.800 MHz, CPU Physical cores: 32, Host memory: 134145 MB +#----------------------------------------------------------- +source NewExtInst_TOP_processing_system7_0_0.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/ly0kos/work/Zynq/ip_repo'. +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'. +Command: synth_design -top NewExtInst_TOP_processing_system7_0_0 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z035' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z035' +INFO: [Device 21-403] Loading part xc7z035ffg676-2 +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 123729 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2118.531 ; gain = 402.715 ; free physical = 32101 ; free virtual = 93926 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'NewExtInst_TOP_processing_system7_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:53] +INFO: [Synth 8-6157] synthesizing module 'processing_system7_v5_5_processing_system7' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:152] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6157] synthesizing module 'BIBUF' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1598] +INFO: [Synth 8-6155] done synthesizing module 'BIBUF' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1598] +INFO: [Synth 8-6157] synthesizing module 'PS7' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111859] +INFO: [Synth 8-6155] done synthesizing module 'PS7' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111859] +INFO: [Synth 8-6155] done synthesizing module 'processing_system7_v5_5_processing_system7' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:152] +WARNING: [Synth 8-7071] port 'M_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:326] +WARNING: [Synth 8-7071] port 'M_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:326] +WARNING: [Synth 8-7071] port 'S_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:326] +WARNING: [Synth 8-7071] port 'S_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:326] +WARNING: [Synth 8-7071] port 'S_AXI_ACP_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:326] +WARNING: [Synth 8-7071] port 'S_AXI_HP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:326] +WARNING: [Synth 8-7071] port 'S_AXI_HP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:326] +WARNING: [Synth 8-7071] port 'S_AXI_HP2_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:326] +WARNING: [Synth 8-7071] port 'S_AXI_HP3_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:326] +WARNING: [Synth 8-7071] port 'DMA0_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:326] +WARNING: [Synth 8-7071] port 'DMA1_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:326] +WARNING: [Synth 8-7071] port 'DMA2_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:326] +WARNING: [Synth 8-7071] port 'DMA3_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:326] +WARNING: [Synth 8-7023] instance 'inst' of module 'processing_system7_v5_5_processing_system7' has 685 connections declared, but only 672 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:326] +INFO: [Synth 8-6155] done synthesizing module 'NewExtInst_TOP_processing_system7_0_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:53] +WARNING: [Synth 8-7129] Port ENET0_GMII_COL in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET0_GMII_CRS in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET0_GMII_RX_DV in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET0_GMII_RX_ER in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[7] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[6] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[5] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[4] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[3] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[1] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[0] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET1_GMII_COL in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET1_GMII_CRS in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET1_GMII_RX_DV in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET1_GMII_RX_ER in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET1_GMII_RXD[7] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET1_GMII_RXD[6] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET1_GMII_RXD[5] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET1_GMII_RXD[4] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET1_GMII_RXD[3] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET1_GMII_RXD[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET1_GMII_RXD[1] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET1_GMII_RXD[0] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_GP0_ARSIZE[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_GP0_AWSIZE[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_GP1_ARSIZE[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_GP1_AWSIZE[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_ACP_ARSIZE[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_ACP_AWSIZE[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_HP0_ARSIZE[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_HP0_AWSIZE[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_HP1_ARSIZE[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_HP1_AWSIZE[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_HP2_ARSIZE[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_HP2_AWSIZE[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_HP3_ARSIZE[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_HP3_AWSIZE[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FCLK_CLKTRIG3_N in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FCLK_CLKTRIG2_N in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FCLK_CLKTRIG1_N in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FCLK_CLKTRIG0_N in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[31] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[30] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[29] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[28] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[27] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[26] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[25] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[24] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[23] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[22] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[21] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[20] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[19] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[18] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[17] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[16] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[15] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[14] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[13] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[12] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[11] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[10] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[9] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[8] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[7] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[6] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[5] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[4] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[3] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[1] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[0] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_VALID in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_ATID[3] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_ATID[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_ATID[1] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FTMD_TRACEIN_ATID[0] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2211.500 ; gain = 495.684 ; free physical = 31589 ; free virtual = 93418 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2223.375 ; gain = 507.559 ; free physical = 31580 ; free virtual = 93409 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2223.375 ; gain = 507.559 ; free physical = 31580 ; free virtual = 93409 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2229.312 ; gain = 0.000 ; free physical = 31562 ; free virtual = 93390 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0.xdc] for cell 'inst' +Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0.xdc] for cell 'inst' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/NewExtInst_TOP_processing_system7_0_0_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/NewExtInst_TOP_processing_system7_0_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/dont_touch.xdc] +Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2293.344 ; gain = 0.000 ; free physical = 31329 ; free virtual = 93158 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2293.379 ; gain = 0.000 ; free physical = 31329 ; free virtual = 93158 +INFO: [Designutils 20-5008] Incremental synthesis strategy off +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2293.379 ; gain = 577.562 ; free physical = 31238 ; free virtual = 93071 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z035ffg676-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2293.379 ; gain = 577.562 ; free physical = 31238 ; free virtual = 93071 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/dont_touch.xdc, line 9). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2293.379 ; gain = 577.562 ; free physical = 31257 ; free virtual = 93089 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2293.379 ; gain = 577.562 ; free physical = 31257 ; free virtual = 93090 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 900 (col length:140) +BRAMs: 1000 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +WARNING: [Synth 8-7129] Port ENET0_GMII_COL in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET0_GMII_CRS in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET0_GMII_RX_DV in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET0_GMII_RX_ER in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[7] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[6] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[5] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[4] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[3] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[1] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[0] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET1_GMII_COL in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET1_GMII_CRS in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET1_GMII_RX_DV in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET1_GMII_RX_ER in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET1_GMII_RXD[7] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET1_GMII_RXD[6] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET1_GMII_RXD[5] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET1_GMII_RXD[4] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ENET1_GMII_RXD[3] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 2293.379 ; gain = 577.562 ; free physical = 31257 ; free virtual = 93091 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2342.328 ; gain = 626.512 ; free physical = 31151 ; free virtual = 92987 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2361.336 ; gain = 645.520 ; free physical = 31136 ; free virtual = 92971 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2369.344 ; gain = 653.527 ; free physical = 31142 ; free virtual = 92977 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2378.250 ; gain = 662.434 ; free physical = 31970 ; free virtual = 93803 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2378.250 ; gain = 662.434 ; free physical = 31970 ; free virtual = 93803 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2378.250 ; gain = 662.434 ; free physical = 31970 ; free virtual = 93803 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2378.250 ; gain = 662.434 ; free physical = 31970 ; free virtual = 93803 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2378.250 ; gain = 662.434 ; free physical = 31970 ; free virtual = 93803 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2378.250 ; gain = 662.434 ; free physical = 31970 ; free virtual = 93803 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+------+------+ +| |Cell |Count | ++------+------+------+ +|1 |BIBUF | 130| +|2 |BUFG | 4| +|3 |LUT1 | 24| +|4 |PS7 | 1| ++------+------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2378.250 ; gain = 662.434 ; free physical = 31970 ; free virtual = 93803 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 80 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2378.250 ; gain = 592.430 ; free physical = 31970 ; free virtual = 93802 +Synthesis Optimization Complete : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2378.258 ; gain = 662.434 ; free physical = 31970 ; free virtual = 93802 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2378.258 ; gain = 0.000 ; free physical = 32196 ; free virtual = 94028 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2403.031 ; gain = 0.000 ; free physical = 32195 ; free virtual = 94027 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Synth Design complete | Checksum: 31c0eba1 +INFO: [Common 17-83] Releasing license: Synthesis +28 Infos, 115 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:14 . Memory (MB): peak = 2403.066 ; gain = 1106.738 ; free physical = 32194 ; free virtual = 94026 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1768.330; main = 1489.861; forked = 307.605 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3388.105; main = 2403.035; forked = 1026.766 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2403.066 ; gain = 0.000 ; free physical = 32194 ; free virtual = 94026 +INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/NewExtInst_TOP_processing_system7_0_0.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file NewExtInst_TOP_processing_system7_0_0_utilization_synth.rpt -pb NewExtInst_TOP_processing_system7_0_0_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Fri May 15 15:27:00 2026... diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/__synthesis_is_complete__ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/__synthesis_is_complete__ new file mode 100644 index 0000000..e69de29 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/dont_touch.xdc b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/dont_touch.xdc new file mode 100644 index 0000000..b2d4c9a --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/dont_touch.xdc @@ -0,0 +1,16 @@ +# This file is automatically generated. +# It contains project source information necessary for synthesis and implementation. + +# IP: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0.xci +# IP: The module: 'NewExtInst_TOP_processing_system7_0_0' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0.xdc +# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_processing_system7_0_0'. Do not add the DONT_TOUCH constraint. +set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet + +# IP: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0.xci +# IP: The module: 'NewExtInst_TOP_processing_system7_0_0' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0.xdc +# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_processing_system7_0_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/htr.txt b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/htr.txt new file mode 100644 index 0000000..4af34c4 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/htr.txt @@ -0,0 +1,10 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +vivado -log NewExtInst_TOP_processing_system7_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_processing_system7_0_0.tcl diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/rundef.js b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/rundef.js new file mode 100644 index 0000000..c2cbeac --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/rundef.js @@ -0,0 +1,41 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;"; +} else { + PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log NewExtInst_TOP_processing_system7_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_processing_system7_0_0.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/runme.bat b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/runme.bat new file mode 100644 index 0000000..3a5f853 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/runme.bat @@ -0,0 +1,12 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/runme.sh b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/runme.sh new file mode 100755 index 0000000..0ac6b67 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/runme.sh @@ -0,0 +1,40 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin +else + PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log NewExtInst_TOP_processing_system7_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_processing_system7_0_0.tcl diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/.Vivado_Synthesis.queue.rst b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/.vivado.begin.rst b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/.vivado.begin.rst new file mode 100644 index 0000000..7e9babc --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/.vivado.end.rst b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/ISEWrap.js b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/ISEWrap.js new file mode 100755 index 0000000..61806d0 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/ISEWrap.sh b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/ISEWrap.sh new file mode 100755 index 0000000..05d5381 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/ISEWrap.sh @@ -0,0 +1,85 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +cmd_exists() +{ + command -v "$1" >/dev/null 2>&1 +} + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! + +HostNameFile=/proc/sys/kernel/hostname +if cmd_exists hostname +then +ISE_HOST=$(hostname) +elif cmd_exists uname +then +ISE_HOST=$(uname -n) +elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] +then +ISE_HOST=$(cat $HostNameFile) +elif [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi + +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0.dcp b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0.dcp new file mode 100644 index 0000000..ec7c49f Binary files /dev/null and b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0.dcp differ diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0.tcl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0.tcl new file mode 100644 index 0000000..1a82b83 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0.tcl @@ -0,0 +1,248 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +namespace eval ::optrace { + variable script "/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0.tcl" + variable category "vivado_synth" +} + +# Try to connect to running dispatch if we haven't done so already. +# This code assumes that the Tcl interpreter is not using threads, +# since the ::dispatch::connected variable isn't mutex protected. +if {![info exists ::dispatch::connected]} { + namespace eval ::dispatch { + variable connected false + if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} { + set result "true" + if {[catch { + if {[lsearch -exact [package names] DispatchTcl] < 0} { + set result [load librdi_cd_clienttcl[info sharedlibextension]] + } + if {$result eq "false"} { + puts "WARNING: Could not load dispatch client library" + } + set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ] + if { $connect_id eq "" } { + puts "WARNING: Could not initialize dispatch client" + } else { + puts "INFO: Dispatch client connection id - $connect_id" + set connected true + } + } catch_res]} { + puts "WARNING: failed to connect to dispatch server - $catch_res" + } + } + } +} +if {$::dispatch::connected} { + # Remove the dummy proc if it exists. + if { [expr {[llength [info procs ::OPTRACE]] > 0}] } { + rename ::OPTRACE "" + } + proc ::OPTRACE { task action {tags {} } } { + ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category + } + # dispatch is generic. We specifically want to attach logging. + ::vitis_log::connect_client +} else { + # Add dummy proc if it doesn't exist. + if { [expr {[llength [info procs ::OPTRACE]] == 0}] } { + proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} { + # Do nothing + } + } +} + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +OPTRACE "NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1" START { ROLLUP_AUTO } +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +OPTRACE "Creating in-memory project" START { } +create_project -in_memory -part xc7z035ffg676-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/wt [current_project] +set_property parent.project_path /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_repo_paths /home/ly0kos/work/Zynq/ip_repo [current_project] +update_ip_catalog +set_property ip_output_repo /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +OPTRACE "Creating in-memory project" END { } +OPTRACE "Adding files" START { } +read_ip -quiet /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0.xci +set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_board.xdc] +set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0.xdc] +set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_ooc.xdc] + +OPTRACE "Adding files" END { } +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc dont_touch.xdc +set_property used_in_implementation false [get_files dont_touch.xdc] +set_param ips.enableIPCacheLiteLoad 1 +OPTRACE "Configure IP Cache" START { } + +set cacheID [config_ip_cache -export -no_bom -dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1 -new_name NewExtInst_TOP_rst_clk_wiz_0_100M_0 -ip [get_ips NewExtInst_TOP_rst_clk_wiz_0_100M_0]] + +OPTRACE "Configure IP Cache" END { } +if { $cacheID == "" } { +close [open __synthesis_is_running__ w] + +OPTRACE "synth_design" START { } +synth_design -top NewExtInst_TOP_rst_clk_wiz_0_100M_0 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context +OPTRACE "synth_design" END { } +OPTRACE "Write IP Cache" START { } + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix NewExtInst_TOP_rst_clk_wiz_0_100M_0_ NewExtInst_TOP_rst_clk_wiz_0_100M_0.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_rst_clk_wiz_0_100M_0_stub.v + lappend ipCachedFiles NewExtInst_TOP_rst_clk_wiz_0_100M_0_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_rst_clk_wiz_0_100M_0_stub.vhdl + lappend ipCachedFiles NewExtInst_TOP_rst_clk_wiz_0_100M_0_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_rst_clk_wiz_0_100M_0_sim_netlist.v + lappend ipCachedFiles NewExtInst_TOP_rst_clk_wiz_0_100M_0_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_rst_clk_wiz_0_100M_0_sim_netlist.vhdl + lappend ipCachedFiles NewExtInst_TOP_rst_clk_wiz_0_100M_0_sim_netlist.vhdl + set TIME_taken [expr [clock seconds] - $TIME_start] + + if { [get_msg_config -count -severity {CRITICAL WARNING}] == 0 } { + config_ip_cache -add -dcp NewExtInst_TOP_rst_clk_wiz_0_100M_0.dcp -move_files $ipCachedFiles -synth_runtime $TIME_taken -ip [get_ips NewExtInst_TOP_rst_clk_wiz_0_100M_0] + } +OPTRACE "Write IP Cache" END { } +} +if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } { + send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING" +} + +rename_ref -prefix_all NewExtInst_TOP_rst_clk_wiz_0_100M_0_ + +OPTRACE "write_checkpoint" START { CHECKPOINT } +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef NewExtInst_TOP_rst_clk_wiz_0_100M_0.dcp +OPTRACE "write_checkpoint" END { } +OPTRACE "synth reports" START { REPORT } +create_report "NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1_synth_report_utilization_0" "report_utilization -file NewExtInst_TOP_rst_clk_wiz_0_100M_0_utilization_synth.rpt -pb NewExtInst_TOP_rst_clk_wiz_0_100M_0_utilization_synth.pb" +OPTRACE "synth reports" END { } + +if { [catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0.dcp /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0.dcp +} _RESULT ] } { + send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file." + error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." +} + +if { [catch { + write_verilog -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +if { [catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0.dcp /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0.dcp +} _RESULT ] } { + send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file." + error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." +} + +if { [catch { + file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0_stub.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0_stub.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0_sim_netlist.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0_sim_netlist.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +close [open .end.used_ip_cache.rst w] +}; # end if cacheID + +if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0]} { + catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_stub.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0 + } +} + +if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0]} { + catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_stub.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0 + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] +OPTRACE "NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1" END { } diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0.vds b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0.vds new file mode 100644 index 0000000..16736bd --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0.vds @@ -0,0 +1,300 @@ +#----------------------------------------------------------- +# Vivado v2023.2 (64-bit) +# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 +# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 +# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 +# Start of session at: Fri May 15 15:26:41 2026 +# Process ID: 123451 +# Current directory: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1 +# Command line: vivado -log NewExtInst_TOP_rst_clk_wiz_0_100M_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_rst_clk_wiz_0_100M_0.tcl +# Log file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0.vds +# Journal file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/vivado.jou +# Running On: mkb, OS: Linux, CPU Frequency: 4998.693 MHz, CPU Physical cores: 32, Host memory: 134145 MB +#----------------------------------------------------------- +source NewExtInst_TOP_rst_clk_wiz_0_100M_0.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/ly0kos/work/Zynq/ip_repo'. +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'. +INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: NewExtInst_TOP_rst_clk_wiz_0_100M_0 +Command: synth_design -top NewExtInst_TOP_rst_clk_wiz_0_100M_0 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z035' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z035' +INFO: [Device 21-403] Loading part xc7z035ffg676-2 +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 123548 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2112.535 ; gain = 402.715 ; free physical = 32328 ; free virtual = 94154 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'NewExtInst_TOP_rst_clk_wiz_0_100M_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/synth/NewExtInst_TOP_rst_clk_wiz_0_100M_0.vhd:74] + Parameter C_FAMILY bound to: zynq - type: string + Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer + Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer + Parameter C_EXT_RESET_HIGH bound to: 1'b1 + Parameter C_AUX_RESET_HIGH bound to: 1'b0 + Parameter C_NUM_BUS_RST bound to: 1 - type: integer + Parameter C_NUM_PERP_RST bound to: 1 - type: integer + Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer + Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer +INFO: [Synth 8-3491] module 'proc_sys_reset' declared at '/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1271' bound to instance 'U0' of component 'proc_sys_reset' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/synth/NewExtInst_TOP_rst_clk_wiz_0_100M_0.vhd:129] +INFO: [Synth 8-638] synthesizing module 'proc_sys_reset' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1330] + Parameter INIT bound to: 1'b1 +INFO: [Synth 8-113] binding component instance 'FDRE_inst' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1399] + Parameter INIT bound to: 1'b1 +INFO: [Synth 8-113] binding component instance 'FDRE_BSR' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1415] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'FDRE_BSR_N' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1441] + Parameter INIT bound to: 1'b1 +INFO: [Synth 8-113] binding component instance 'FDRE_PER' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1464] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'FDRE_PER_N' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1488] +INFO: [Synth 8-638] synthesizing module 'lpf' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:821] +INFO: [Synth 8-3491] module 'SRL16' declared at '/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721' bound to instance 'POR_SRL_I' of component 'SRL16' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:873] +INFO: [Synth 8-6157] synthesizing module 'SRL16' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721] +INFO: [Synth 8-6155] done synthesizing module 'SRL16' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721] +INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:514] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:545] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:554] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:564] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:574] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:584] +INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] +INFO: [Synth 8-256] done synthesizing module 'lpf' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:821] +INFO: [Synth 8-638] synthesizing module 'sequence_psr' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:304] +INFO: [Synth 8-638] synthesizing module 'upcnt_n' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:126] +INFO: [Synth 8-256] done synthesizing module 'upcnt_n' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:126] +INFO: [Synth 8-256] done synthesizing module 'sequence_psr' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:304] +INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1330] +INFO: [Synth 8-256] done synthesizing module 'NewExtInst_TOP_rst_clk_wiz_0_100M_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/synth/NewExtInst_TOP_rst_clk_wiz_0_100M_0.vhd:74] +WARNING: [Synth 8-7129] Port prmry_aclk in module cdc_sync is either unconnected or has no load +WARNING: [Synth 8-7129] Port prmry_resetn in module cdc_sync is either unconnected or has no load +WARNING: [Synth 8-7129] Port prmry_vect_in[1] in module cdc_sync is either unconnected or has no load +WARNING: [Synth 8-7129] Port prmry_vect_in[0] in module cdc_sync is either unconnected or has no load +WARNING: [Synth 8-7129] Port scndry_resetn in module cdc_sync is either unconnected or has no load +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2191.504 ; gain = 481.684 ; free physical = 31641 ; free virtual = 93467 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2206.348 ; gain = 496.527 ; free physical = 31623 ; free virtual = 93451 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2206.348 ; gain = 496.527 ; free physical = 31623 ; free virtual = 93451 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2212.285 ; gain = 0.000 ; free physical = 31616 ; free virtual = 93444 +INFO: [Netlist 29-17] Analyzing 13 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_ooc.xdc] for cell 'U0' +Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_ooc.xdc] for cell 'U0' +Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_board.xdc] for cell 'U0' +Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_board.xdc] for cell 'U0' +Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0.xdc] for cell 'U0' +Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0.xdc] for cell 'U0' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/NewExtInst_TOP_rst_clk_wiz_0_100M_0_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/NewExtInst_TOP_rst_clk_wiz_0_100M_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/dont_touch.xdc] +Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2351.098 ; gain = 0.000 ; free physical = 31382 ; free virtual = 93210 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 13 instances were transformed. + FDR => FDRE: 12 instances + SRL16 => SRL16E: 1 instance + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2351.133 ; gain = 0.000 ; free physical = 31381 ; free virtual = 93209 +INFO: [Designutils 20-5008] Incremental synthesis strategy off +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31246 ; free virtual = 93077 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z035ffg676-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31246 ; free virtual = 93077 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property KEEP_HIERARCHY = SOFT for U0. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/dont_touch.xdc, line 9). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31246 ; free virtual = 93077 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31243 ; free virtual = 93075 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 6 Bit Adders := 1 ++---Registers : + 6 Bit Registers := 1 + 3 Bit Registers := 3 + 1 Bit Registers := 8 ++---Muxes : + 2 Input 6 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 900 (col length:140) +BRAMs: 1000 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module proc_sys_reset. +WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module proc_sys_reset. +WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module proc_sys_reset. +WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module proc_sys_reset. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31257 ; free virtual = 93092 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31284 ; free virtual = 93120 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31284 ; free virtual = 93120 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31262 ; free virtual = 93097 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31144 ; free virtual = 92979 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31144 ; free virtual = 92979 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31144 ; free virtual = 92979 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31144 ; free virtual = 92979 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31144 ; free virtual = 92979 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31144 ; free virtual = 92979 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+------+------+ +| |Cell |Count | ++------+------+------+ +|1 |LUT1 | 5| +|2 |LUT2 | 9| +|3 |LUT3 | 1| +|4 |LUT4 | 6| +|5 |LUT5 | 3| +|6 |LUT6 | 1| +|7 |SRL16 | 1| +|8 |FDR | 8| +|9 |FDRE | 28| +|10 |FDSE | 4| ++------+------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31144 ; free virtual = 92979 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 5 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2351.133 ; gain = 496.527 ; free physical = 31392 ; free virtual = 93228 +Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31392 ; free virtual = 93228 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2351.133 ; gain = 0.000 ; free physical = 31392 ; free virtual = 93228 +INFO: [Netlist 29-17] Analyzing 9 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2351.133 ; gain = 0.000 ; free physical = 31675 ; free virtual = 93510 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 9 instances were transformed. + FDR => FDRE: 8 instances + SRL16 => SRL16E: 1 instance + +Synth Design complete | Checksum: 2497e3b9 +INFO: [Common 17-83] Releasing license: Synthesis +49 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 2351.133 ; gain = 1058.770 ; free physical = 31968 ; free virtual = 93804 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1679.910; main = 1379.216; forked = 307.635 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3321.746; main = 2351.102; forked = 1002.660 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2375.109 ; gain = 0.000 ; free physical = 31968 ; free virtual = 93804 +INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0.dcp' has been generated. +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP NewExtInst_TOP_rst_clk_wiz_0_100M_0, cache-ID = 2e8c33c5e53a7d6d +INFO: [Coretcl 2-1174] Renamed 6 cell refs. +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2375.109 ; gain = 0.000 ; free physical = 31970 ; free virtual = 93804 +INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file NewExtInst_TOP_rst_clk_wiz_0_100M_0_utilization_synth.rpt -pb NewExtInst_TOP_rst_clk_wiz_0_100M_0_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Fri May 15 15:26:59 2026... diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/__synthesis_is_complete__ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/__synthesis_is_complete__ new file mode 100644 index 0000000..e69de29 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/dont_touch.xdc b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/dont_touch.xdc new file mode 100644 index 0000000..8cba285 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/dont_touch.xdc @@ -0,0 +1,32 @@ +# This file is automatically generated. +# It contains project source information necessary for synthesis and implementation. + +# IP: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0.xci +# IP: The module: 'NewExtInst_TOP_rst_clk_wiz_0_100M_0' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_board.xdc +# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_rst_clk_wiz_0_100M_0'. Do not add the DONT_TOUCH constraint. +set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet + +# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0.xdc +# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_rst_clk_wiz_0_100M_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet + +# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_rst_clk_wiz_0_100M_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet + +# IP: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0.xci +# IP: The module: 'NewExtInst_TOP_rst_clk_wiz_0_100M_0' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_board.xdc +# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_rst_clk_wiz_0_100M_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet + +# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0.xdc +# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_rst_clk_wiz_0_100M_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet + +# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_rst_clk_wiz_0_100M_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/htr.txt b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/htr.txt new file mode 100644 index 0000000..8eaeda6 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/htr.txt @@ -0,0 +1,10 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +vivado -log NewExtInst_TOP_rst_clk_wiz_0_100M_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_rst_clk_wiz_0_100M_0.tcl diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/rundef.js b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/rundef.js new file mode 100644 index 0000000..2e005a2 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/rundef.js @@ -0,0 +1,41 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;"; +} else { + PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log NewExtInst_TOP_rst_clk_wiz_0_100M_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_rst_clk_wiz_0_100M_0.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/runme.bat b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/runme.bat new file mode 100644 index 0000000..3a5f853 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/runme.bat @@ -0,0 +1,12 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/runme.sh b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/runme.sh new file mode 100755 index 0000000..2cba200 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/runme.sh @@ -0,0 +1,40 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin +else + PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log NewExtInst_TOP_rst_clk_wiz_0_100M_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_rst_clk_wiz_0_100M_0.tcl diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/.Vivado_Synthesis.queue.rst b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/.vivado.begin.rst b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/.vivado.begin.rst new file mode 100644 index 0000000..d4e8a70 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/.vivado.end.rst b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/ISEWrap.js b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/ISEWrap.js new file mode 100755 index 0000000..61806d0 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/ISEWrap.sh b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/ISEWrap.sh new file mode 100755 index 0000000..05d5381 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/ISEWrap.sh @@ -0,0 +1,85 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +cmd_exists() +{ + command -v "$1" >/dev/null 2>&1 +} + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! + +HostNameFile=/proc/sys/kernel/hostname +if cmd_exists hostname +then +ISE_HOST=$(hostname) +elif cmd_exists uname +then +ISE_HOST=$(uname -n) +elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] +then +ISE_HOST=$(cat $HostNameFile) +elif [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi + +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/NewExtInst_TOP_xbar_0.dcp b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/NewExtInst_TOP_xbar_0.dcp new file mode 100644 index 0000000..78ebec7 Binary files /dev/null and b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/NewExtInst_TOP_xbar_0.dcp differ diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/NewExtInst_TOP_xbar_0.tcl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/NewExtInst_TOP_xbar_0.tcl new file mode 100644 index 0000000..3a9e215 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/NewExtInst_TOP_xbar_0.tcl @@ -0,0 +1,246 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +namespace eval ::optrace { + variable script "/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/NewExtInst_TOP_xbar_0.tcl" + variable category "vivado_synth" +} + +# Try to connect to running dispatch if we haven't done so already. +# This code assumes that the Tcl interpreter is not using threads, +# since the ::dispatch::connected variable isn't mutex protected. +if {![info exists ::dispatch::connected]} { + namespace eval ::dispatch { + variable connected false + if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} { + set result "true" + if {[catch { + if {[lsearch -exact [package names] DispatchTcl] < 0} { + set result [load librdi_cd_clienttcl[info sharedlibextension]] + } + if {$result eq "false"} { + puts "WARNING: Could not load dispatch client library" + } + set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ] + if { $connect_id eq "" } { + puts "WARNING: Could not initialize dispatch client" + } else { + puts "INFO: Dispatch client connection id - $connect_id" + set connected true + } + } catch_res]} { + puts "WARNING: failed to connect to dispatch server - $catch_res" + } + } + } +} +if {$::dispatch::connected} { + # Remove the dummy proc if it exists. + if { [expr {[llength [info procs ::OPTRACE]] > 0}] } { + rename ::OPTRACE "" + } + proc ::OPTRACE { task action {tags {} } } { + ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category + } + # dispatch is generic. We specifically want to attach logging. + ::vitis_log::connect_client +} else { + # Add dummy proc if it doesn't exist. + if { [expr {[llength [info procs ::OPTRACE]] == 0}] } { + proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} { + # Do nothing + } + } +} + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +OPTRACE "NewExtInst_TOP_xbar_0_synth_1" START { ROLLUP_AUTO } +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +OPTRACE "Creating in-memory project" START { } +create_project -in_memory -part xc7z035ffg676-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/wt [current_project] +set_property parent.project_path /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_repo_paths /home/ly0kos/work/Zynq/ip_repo [current_project] +update_ip_catalog +set_property ip_output_repo /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +OPTRACE "Creating in-memory project" END { } +OPTRACE "Adding files" START { } +read_ip -quiet /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0.xci +set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_ooc.xdc] + +OPTRACE "Adding files" END { } +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc dont_touch.xdc +set_property used_in_implementation false [get_files dont_touch.xdc] +set_param ips.enableIPCacheLiteLoad 1 +OPTRACE "Configure IP Cache" START { } + +set cacheID [config_ip_cache -export -no_bom -dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1 -new_name NewExtInst_TOP_xbar_0 -ip [get_ips NewExtInst_TOP_xbar_0]] + +OPTRACE "Configure IP Cache" END { } +if { $cacheID == "" } { +close [open __synthesis_is_running__ w] + +OPTRACE "synth_design" START { } +synth_design -top NewExtInst_TOP_xbar_0 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context +OPTRACE "synth_design" END { } +OPTRACE "Write IP Cache" START { } + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix NewExtInst_TOP_xbar_0_ NewExtInst_TOP_xbar_0.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_xbar_0_stub.v + lappend ipCachedFiles NewExtInst_TOP_xbar_0_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_xbar_0_stub.vhdl + lappend ipCachedFiles NewExtInst_TOP_xbar_0_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_xbar_0_sim_netlist.v + lappend ipCachedFiles NewExtInst_TOP_xbar_0_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_xbar_0_sim_netlist.vhdl + lappend ipCachedFiles NewExtInst_TOP_xbar_0_sim_netlist.vhdl + set TIME_taken [expr [clock seconds] - $TIME_start] + + if { [get_msg_config -count -severity {CRITICAL WARNING}] == 0 } { + config_ip_cache -add -dcp NewExtInst_TOP_xbar_0.dcp -move_files $ipCachedFiles -synth_runtime $TIME_taken -ip [get_ips NewExtInst_TOP_xbar_0] + } +OPTRACE "Write IP Cache" END { } +} +if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } { + send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING" +} + +rename_ref -prefix_all NewExtInst_TOP_xbar_0_ + +OPTRACE "write_checkpoint" START { CHECKPOINT } +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef NewExtInst_TOP_xbar_0.dcp +OPTRACE "write_checkpoint" END { } +OPTRACE "synth reports" START { REPORT } +create_report "NewExtInst_TOP_xbar_0_synth_1_synth_report_utilization_0" "report_utilization -file NewExtInst_TOP_xbar_0_utilization_synth.rpt -pb NewExtInst_TOP_xbar_0_utilization_synth.pb" +OPTRACE "synth reports" END { } + +if { [catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/NewExtInst_TOP_xbar_0.dcp /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0.dcp +} _RESULT ] } { + send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file." + error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." +} + +if { [catch { + write_verilog -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +if { [catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/NewExtInst_TOP_xbar_0.dcp /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0.dcp +} _RESULT ] } { + send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file." + error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." +} + +if { [catch { + file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/NewExtInst_TOP_xbar_0_stub.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/NewExtInst_TOP_xbar_0_stub.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/NewExtInst_TOP_xbar_0_sim_netlist.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/NewExtInst_TOP_xbar_0_sim_netlist.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +close [open .end.used_ip_cache.rst w] +}; # end if cacheID + +if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_xbar_0]} { + catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_stub.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_xbar_0 + } +} + +if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_xbar_0]} { + catch { + file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_stub.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_xbar_0 + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] +OPTRACE "NewExtInst_TOP_xbar_0_synth_1" END { } diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/NewExtInst_TOP_xbar_0.vds b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/NewExtInst_TOP_xbar_0.vds new file mode 100644 index 0000000..6a791a3 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/NewExtInst_TOP_xbar_0.vds @@ -0,0 +1,371 @@ +#----------------------------------------------------------- +# Vivado v2023.2 (64-bit) +# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 +# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 +# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 +# Start of session at: Fri May 15 15:26:41 2026 +# Process ID: 123449 +# Current directory: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1 +# Command line: vivado -log NewExtInst_TOP_xbar_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_xbar_0.tcl +# Log file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/NewExtInst_TOP_xbar_0.vds +# Journal file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/vivado.jou +# Running On: mkb, OS: Linux, CPU Frequency: 4976.515 MHz, CPU Physical cores: 32, Host memory: 134145 MB +#----------------------------------------------------------- +source NewExtInst_TOP_xbar_0.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/ly0kos/work/Zynq/ip_repo'. +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'. +INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: NewExtInst_TOP_xbar_0 +Command: synth_design -top NewExtInst_TOP_xbar_0 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z035' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z035' +INFO: [Device 21-403] Loading part xc7z035ffg676-2 +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 123767 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2121.438 ; gain = 399.746 ; free physical = 31605 ; free virtual = 93432 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'NewExtInst_TOP_xbar_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/synth/NewExtInst_TOP_xbar_0.v:53] +INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_30_axi_crossbar' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:4871] +INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_30_crossbar_sasd' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:1234] +INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_30_addr_decoder' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:790] +INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_1_comparator_static' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2119] +INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_1_carry_and' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:60] +INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_1_carry_and' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:60] +INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_1_comparator_static' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2119] +INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_1_comparator_static__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2119] +INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_1_comparator_static__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2119] +INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_1_comparator_static__parameterized1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2119] +INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_1_comparator_static__parameterized1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2119] +INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_30_addr_decoder' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:790] +INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_30_decerr_slave' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:3493] +INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_30_decerr_slave' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:3493] +INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_30_addr_arbiter_sasd' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:63] +INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_30_addr_arbiter_sasd' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:63] +INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_30_splitter' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:4451] +INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_30_splitter' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:4451] +INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_30_splitter__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:4451] +INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_30_splitter__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:4451] +INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_1_mux_enc' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2436] +INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_1_mux_enc' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2436] +INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_1_mux_enc__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2436] +INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_1_mux_enc__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2436] +INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_1_mux_enc__parameterized1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2436] +INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_1_mux_enc__parameterized1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2436] +INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] +INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] +INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_1_mux_enc__parameterized2' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2436] +INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_1_mux_enc__parameterized2' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2436] +INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_30_crossbar_sasd' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:1234] +INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_30_axi_crossbar' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:4871] +INFO: [Synth 8-6155] done synthesizing module 'NewExtInst_TOP_xbar_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/synth/NewExtInst_TOP_xbar_0.v:53] +WARNING: [Synth 8-6014] Unused sequential element gen_debug_trans_seq.debug_aw_trans_seq_i_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:2051] +WARNING: [Synth 8-6014] Unused sequential element gen_debug_trans_seq.debug_ar_trans_seq_i_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:2062] +WARNING: [Synth 8-6014] Unused sequential element gen_debug_trans_seq.debug_w_beat_cnt_i_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:2073] +WARNING: [Synth 8-6014] Unused sequential element gen_debug_trans_seq.debug_r_beat_cnt_i_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:2086] +WARNING: [Synth 8-7129] Port S[0] in module generic_baseblocks_v2_1_1_mux_enc__parameterized0 is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_AWID[0] in module axi_crossbar_v2_1_30_decerr_slave is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_WLAST in module axi_crossbar_v2_1_30_decerr_slave is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_ARID[0] in module axi_crossbar_v2_1_30_decerr_slave is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_ARLEN[7] in module axi_crossbar_v2_1_30_decerr_slave is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_ARLEN[6] in module axi_crossbar_v2_1_30_decerr_slave is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_ARLEN[5] in module axi_crossbar_v2_1_30_decerr_slave is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_ARLEN[4] in module axi_crossbar_v2_1_30_decerr_slave is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_ARLEN[3] in module axi_crossbar_v2_1_30_decerr_slave is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_ARLEN[2] in module axi_crossbar_v2_1_30_decerr_slave is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_ARLEN[1] in module axi_crossbar_v2_1_30_decerr_slave is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_ARLEN[0] in module axi_crossbar_v2_1_30_decerr_slave is either unconnected or has no load +WARNING: [Synth 8-7129] Port ADDR[1] in module axi_crossbar_v2_1_30_addr_decoder is either unconnected or has no load +WARNING: [Synth 8-7129] Port ADDR[0] in module axi_crossbar_v2_1_30_addr_decoder is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_AWID[0] in module axi_crossbar_v2_1_30_crossbar_sasd is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_ARID[0] in module axi_crossbar_v2_1_30_crossbar_sasd is either unconnected or has no load +WARNING: [Synth 8-7129] Port M_AXI_BID[2] in module axi_crossbar_v2_1_30_crossbar_sasd is either unconnected or has no load +WARNING: [Synth 8-7129] Port M_AXI_BID[1] in module axi_crossbar_v2_1_30_crossbar_sasd is either unconnected or has no load +WARNING: [Synth 8-7129] Port M_AXI_BID[0] in module axi_crossbar_v2_1_30_crossbar_sasd is either unconnected or has no load +WARNING: [Synth 8-7129] Port M_AXI_RID[2] in module axi_crossbar_v2_1_30_crossbar_sasd is either unconnected or has no load +WARNING: [Synth 8-7129] Port M_AXI_RID[1] in module axi_crossbar_v2_1_30_crossbar_sasd is either unconnected or has no load +WARNING: [Synth 8-7129] Port M_AXI_RID[0] in module axi_crossbar_v2_1_30_crossbar_sasd is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awid[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awlen[7] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awlen[6] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awlen[5] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awlen[4] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awlen[3] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awlen[2] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awlen[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awlen[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awsize[2] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awsize[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awsize[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awburst[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awburst[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awlock[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awcache[3] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awcache[2] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awcache[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awcache[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awqos[3] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awqos[2] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awqos[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awqos[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awuser[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_wid[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_wlast[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_wuser[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_arid[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_arlen[7] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_arlen[6] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_arlen[5] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_arlen[4] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_arlen[3] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_arlen[2] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_arlen[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_arlen[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_arsize[2] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_arsize[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_arsize[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_arburst[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_arburst[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_arlock[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_arcache[3] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_arcache[2] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_arcache[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_arcache[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_arqos[3] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_arqos[2] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_arqos[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_arqos[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_aruser[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port m_axi_bid[2] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port m_axi_bid[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port m_axi_bid[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port m_axi_buser[2] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port m_axi_buser[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port m_axi_buser[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port m_axi_rid[2] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port m_axi_rid[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port m_axi_rid[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port m_axi_rlast[2] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port m_axi_rlast[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port m_axi_rlast[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port m_axi_ruser[2] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port m_axi_ruser[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port m_axi_ruser[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2315.375 ; gain = 593.684 ; free physical = 31245 ; free virtual = 93076 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2315.375 ; gain = 593.684 ; free physical = 31245 ; free virtual = 93075 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2315.375 ; gain = 593.684 ; free physical = 31245 ; free virtual = 93075 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2315.375 ; gain = 0.000 ; free physical = 31245 ; free virtual = 93075 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_ooc.xdc] for cell 'inst' +Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/dont_touch.xdc] +Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2412.219 ; gain = 0.000 ; free physical = 31249 ; free virtual = 93079 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2412.254 ; gain = 0.000 ; free physical = 31248 ; free virtual = 93078 +INFO: [Designutils 20-5008] Incremental synthesis strategy off +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 31275 ; free virtual = 93110 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z035ffg676-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 31275 ; free virtual = 93110 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/dont_touch.xdc, line 9). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 31275 ; free virtual = 93111 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 31261 ; free virtual = 93097 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Registers : + 64 Bit Registers := 1 + 36 Bit Registers := 2 + 4 Bit Registers := 1 + 3 Bit Registers := 1 + 2 Bit Registers := 3 + 1 Bit Registers := 14 ++---Muxes : + 2 Input 64 Bit Muxes := 1 + 2 Input 36 Bit Muxes := 2 + 2 Input 4 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 36 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 900 (col length:140) +BRAMs: 1000 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +INFO: [Synth 8-3936] Found unconnected internal register 'gen_sasd.crossbar_sasd_0/reg_slice_r/m_payload_i_reg' and it is trimmed from '36' to '35' bits. [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1726] +WARNING: [Synth 8-7129] Port s_axi_awid[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awlen[7] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awlen[6] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awlen[5] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awlen[4] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awlen[3] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awlen[2] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awlen[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awlen[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awsize[2] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awsize[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +WARNING: [Synth 8-7129] Port s_axi_awsize[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 31159 ; free virtual = 92994 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 31970 ; free virtual = 93803 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 32217 ; free virtual = 94049 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 32212 ; free virtual = 94044 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 33246 ; free virtual = 95077 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 33246 ; free virtual = 95077 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 33246 ; free virtual = 95077 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 33246 ; free virtual = 95077 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 33246 ; free virtual = 95077 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 33246 ; free virtual = 95077 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |LUT1 | 1| +|2 |LUT2 | 8| +|3 |LUT3 | 39| +|4 |LUT4 | 49| +|5 |LUT5 | 33| +|6 |LUT6 | 42| +|7 |FDRE | 131| ++------+-----+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 33246 ; free virtual = 95077 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 67 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2412.254 ; gain = 593.684 ; free physical = 33259 ; free virtual = 95091 +Synthesis Optimization Complete : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 33259 ; free virtual = 95091 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2412.254 ; gain = 0.000 ; free physical = 33519 ; free virtual = 95350 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2412.254 ; gain = 0.000 ; free physical = 33517 ; free virtual = 95348 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Synth Design complete | Checksum: f26108b +INFO: [Common 17-83] Releasing license: Synthesis +53 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 2412.254 ; gain = 1114.926 ; free physical = 33515 ; free virtual = 95346 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1765.393; main = 1479.902; forked = 307.549 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3382.863; main = 2412.223; forked = 1002.656 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2436.230 ; gain = 0.000 ; free physical = 33515 ; free virtual = 95346 +INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/NewExtInst_TOP_xbar_0.dcp' has been generated. +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP NewExtInst_TOP_xbar_0, cache-ID = 244f670d2d87c357 +INFO: [Coretcl 2-1174] Renamed 7 cell refs. +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2436.230 ; gain = 0.000 ; free physical = 33505 ; free virtual = 95337 +INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/NewExtInst_TOP_xbar_0.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file NewExtInst_TOP_xbar_0_utilization_synth.rpt -pb NewExtInst_TOP_xbar_0_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Fri May 15 15:27:02 2026... diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/__synthesis_is_complete__ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/__synthesis_is_complete__ new file mode 100644 index 0000000..e69de29 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/dont_touch.xdc b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/dont_touch.xdc new file mode 100644 index 0000000..eb96386 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/dont_touch.xdc @@ -0,0 +1,16 @@ +# This file is automatically generated. +# It contains project source information necessary for synthesis and implementation. + +# IP: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0.xci +# IP: The module: 'NewExtInst_TOP_xbar_0' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_xbar_0'. Do not add the DONT_TOUCH constraint. +set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet + +# IP: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0.xci +# IP: The module: 'NewExtInst_TOP_xbar_0' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_xbar_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/htr.txt b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/htr.txt new file mode 100644 index 0000000..0de4862 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/htr.txt @@ -0,0 +1,10 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +vivado -log NewExtInst_TOP_xbar_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_xbar_0.tcl diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/rundef.js b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/rundef.js new file mode 100644 index 0000000..e4e79c6 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/rundef.js @@ -0,0 +1,41 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;"; +} else { + PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log NewExtInst_TOP_xbar_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_xbar_0.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/runme.bat b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/runme.bat new file mode 100644 index 0000000..3a5f853 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/runme.bat @@ -0,0 +1,12 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/runme.sh b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/runme.sh new file mode 100755 index 0000000..1ab99b7 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/runme.sh @@ -0,0 +1,40 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin +else + PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log NewExtInst_TOP_xbar_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_xbar_0.tcl diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/impl_1/ISEWrap.js b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/impl_1/ISEWrap.js new file mode 100755 index 0000000..61806d0 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/impl_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/impl_1/ISEWrap.sh b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/impl_1/ISEWrap.sh new file mode 100755 index 0000000..05d5381 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/impl_1/ISEWrap.sh @@ -0,0 +1,85 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +cmd_exists() +{ + command -v "$1" >/dev/null 2>&1 +} + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! + +HostNameFile=/proc/sys/kernel/hostname +if cmd_exists hostname +then +ISE_HOST=$(hostname) +elif cmd_exists uname +then +ISE_HOST=$(uname -n) +elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] +then +ISE_HOST=$(cat $HostNameFile) +elif [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi + +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/impl_1/NewExtInst_TOP_wrapper.tcl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/impl_1/NewExtInst_TOP_wrapper.tcl new file mode 100644 index 0000000..7f3face --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/impl_1/NewExtInst_TOP_wrapper.tcl @@ -0,0 +1,312 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +namespace eval ::optrace { + variable script "/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/impl_1/NewExtInst_TOP_wrapper.tcl" + variable category "vivado_impl" +} + +# Try to connect to running dispatch if we haven't done so already. +# This code assumes that the Tcl interpreter is not using threads, +# since the ::dispatch::connected variable isn't mutex protected. +if {![info exists ::dispatch::connected]} { + namespace eval ::dispatch { + variable connected false + if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} { + set result "true" + if {[catch { + if {[lsearch -exact [package names] DispatchTcl] < 0} { + set result [load librdi_cd_clienttcl[info sharedlibextension]] + } + if {$result eq "false"} { + puts "WARNING: Could not load dispatch client library" + } + set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ] + if { $connect_id eq "" } { + puts "WARNING: Could not initialize dispatch client" + } else { + puts "INFO: Dispatch client connection id - $connect_id" + set connected true + } + } catch_res]} { + puts "WARNING: failed to connect to dispatch server - $catch_res" + } + } + } +} +if {$::dispatch::connected} { + # Remove the dummy proc if it exists. + if { [expr {[llength [info procs ::OPTRACE]] > 0}] } { + rename ::OPTRACE "" + } + proc ::OPTRACE { task action {tags {} } } { + ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category + } + # dispatch is generic. We specifically want to attach logging. + ::vitis_log::connect_client +} else { + # Add dummy proc if it doesn't exist. + if { [expr {[llength [info procs ::OPTRACE]] == 0}] } { + proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} { + # Do nothing + } + } +} + +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } elseif { [info exist ::env(HOST)] } { + set host $::env(HOST) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +OPTRACE "impl_1" END { } +} + +set_msg_config -id {HDL-1065} -limit 10000 + +OPTRACE "impl_1" START { ROLLUP_1 } +OPTRACE "Phase: Init Design" START { ROLLUP_AUTO } +start_step init_design +set ACTIVE_STEP init_design +set rc [catch { + create_msg_db init_design.pb + set_param chipscope.maxJobs 8 + set_param runs.launchOptions { -jobs 32 } +OPTRACE "create in-memory project" START { } + create_project -in_memory -part xc7z035ffg676-2 + set_property design_mode GateLvl [current_fileset] + set_param project.singleFileAddWarning.threshold 0 +OPTRACE "create in-memory project" END { } +OPTRACE "set parameters" START { } + set_property webtalk.parent_dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/wt [current_project] + set_property parent.project_path /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.xpr [current_project] + set_property ip_repo_paths /home/ly0kos/work/Zynq/ip_repo [current_project] + update_ip_catalog + set_property ip_output_repo /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/ip [current_project] + set_property ip_cache_permissions {read write} [current_project] + set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +OPTRACE "set parameters" END { } +OPTRACE "add files" START { } + add_files -quiet /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/synth_1/NewExtInst_TOP_wrapper.dcp + set_msg_config -source 4 -id {BD 41-1661} -limit 0 + set_param project.isImplRun true + add_files /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/NewExtInst_TOP.bd + set_param project.isImplRun false +OPTRACE "read constraints: implementation" START { } +OPTRACE "read constraints: implementation" END { } +OPTRACE "read constraints: implementation_pre" START { } +OPTRACE "read constraints: implementation_pre" END { } +OPTRACE "add files" END { } +OPTRACE "link_design" START { } + set_param project.isImplRun true + link_design -top NewExtInst_TOP_wrapper -part xc7z035ffg676-2 +OPTRACE "link_design" END { } + set_param project.isImplRun false +OPTRACE "gray box cells" START { } +OPTRACE "gray box cells" END { } +OPTRACE "init_design_reports" START { REPORT } +OPTRACE "init_design_reports" END { } +OPTRACE "init_design_write_hwdef" START { } +OPTRACE "init_design_write_hwdef" END { } + close_msg_db -file init_design.pb +} RESULT] +if {$rc} { + step_failed init_design + return -code error $RESULT +} else { + end_step init_design + unset ACTIVE_STEP +} + +OPTRACE "Phase: Init Design" END { } +OPTRACE "Phase: Opt Design" START { ROLLUP_AUTO } +start_step opt_design +set ACTIVE_STEP opt_design +set rc [catch { + create_msg_db opt_design.pb +OPTRACE "read constraints: opt_design" START { } +OPTRACE "read constraints: opt_design" END { } +OPTRACE "opt_design" START { } + opt_design +OPTRACE "opt_design" END { } +OPTRACE "read constraints: opt_design_post" START { } +OPTRACE "read constraints: opt_design_post" END { } +OPTRACE "opt_design reports" START { REPORT } + create_report "impl_1_opt_report_drc_0" "report_drc -file NewExtInst_TOP_wrapper_drc_opted.rpt -pb NewExtInst_TOP_wrapper_drc_opted.pb -rpx NewExtInst_TOP_wrapper_drc_opted.rpx" +OPTRACE "opt_design reports" END { } +OPTRACE "Opt Design: write_checkpoint" START { CHECKPOINT } + write_checkpoint -force NewExtInst_TOP_wrapper_opt.dcp +OPTRACE "Opt Design: write_checkpoint" END { } + close_msg_db -file opt_design.pb +} RESULT] +if {$rc} { + step_failed opt_design + return -code error $RESULT +} else { + end_step opt_design + unset ACTIVE_STEP +} + +OPTRACE "Phase: Opt Design" END { } +OPTRACE "Phase: Place Design" START { ROLLUP_AUTO } +start_step place_design +set ACTIVE_STEP place_design +set rc [catch { + create_msg_db place_design.pb +OPTRACE "read constraints: place_design" START { } +OPTRACE "read constraints: place_design" END { } + if { [llength [get_debug_cores -quiet] ] > 0 } { +OPTRACE "implement_debug_core" START { } + implement_debug_core +OPTRACE "implement_debug_core" END { } + } +OPTRACE "place_design" START { } + place_design +OPTRACE "place_design" END { } +OPTRACE "read constraints: place_design_post" START { } +OPTRACE "read constraints: place_design_post" END { } +OPTRACE "place_design reports" START { REPORT } + create_report "impl_1_place_report_io_0" "report_io -file NewExtInst_TOP_wrapper_io_placed.rpt" + create_report "impl_1_place_report_utilization_0" "report_utilization -file NewExtInst_TOP_wrapper_utilization_placed.rpt -pb NewExtInst_TOP_wrapper_utilization_placed.pb" + create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file NewExtInst_TOP_wrapper_control_sets_placed.rpt" +OPTRACE "place_design reports" END { } +OPTRACE "Place Design: write_checkpoint" START { CHECKPOINT } + write_checkpoint -force NewExtInst_TOP_wrapper_placed.dcp +OPTRACE "Place Design: write_checkpoint" END { } + close_msg_db -file place_design.pb +} RESULT] +if {$rc} { + step_failed place_design + return -code error $RESULT +} else { + end_step place_design + unset ACTIVE_STEP +} + +OPTRACE "Phase: Place Design" END { } +OPTRACE "Phase: Route Design" START { ROLLUP_AUTO } +start_step route_design +set ACTIVE_STEP route_design +set rc [catch { + create_msg_db route_design.pb +OPTRACE "read constraints: route_design" START { } +OPTRACE "read constraints: route_design" END { } +OPTRACE "route_design" START { } + route_design +OPTRACE "route_design" END { } +OPTRACE "read constraints: route_design_post" START { } +OPTRACE "read constraints: route_design_post" END { } +OPTRACE "route_design reports" START { REPORT } + create_report "impl_1_route_report_drc_0" "report_drc -file NewExtInst_TOP_wrapper_drc_routed.rpt -pb NewExtInst_TOP_wrapper_drc_routed.pb -rpx NewExtInst_TOP_wrapper_drc_routed.rpx" + create_report "impl_1_route_report_methodology_0" "report_methodology -file NewExtInst_TOP_wrapper_methodology_drc_routed.rpt -pb NewExtInst_TOP_wrapper_methodology_drc_routed.pb -rpx NewExtInst_TOP_wrapper_methodology_drc_routed.rpx" + create_report "impl_1_route_report_power_0" "report_power -file NewExtInst_TOP_wrapper_power_routed.rpt -pb NewExtInst_TOP_wrapper_power_summary_routed.pb -rpx NewExtInst_TOP_wrapper_power_routed.rpx" + create_report "impl_1_route_report_route_status_0" "report_route_status -file NewExtInst_TOP_wrapper_route_status.rpt -pb NewExtInst_TOP_wrapper_route_status.pb" + create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file NewExtInst_TOP_wrapper_timing_summary_routed.rpt -pb NewExtInst_TOP_wrapper_timing_summary_routed.pb -rpx NewExtInst_TOP_wrapper_timing_summary_routed.rpx -warn_on_violation " + create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file NewExtInst_TOP_wrapper_incremental_reuse_routed.rpt" + create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file NewExtInst_TOP_wrapper_clock_utilization_routed.rpt" + create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file NewExtInst_TOP_wrapper_bus_skew_routed.rpt -pb NewExtInst_TOP_wrapper_bus_skew_routed.pb -rpx NewExtInst_TOP_wrapper_bus_skew_routed.rpx" +OPTRACE "route_design reports" END { } +OPTRACE "Route Design: write_checkpoint" START { CHECKPOINT } + write_checkpoint -force NewExtInst_TOP_wrapper_routed.dcp +OPTRACE "Route Design: write_checkpoint" END { } +OPTRACE "route_design misc" START { } + close_msg_db -file route_design.pb +} RESULT] +if {$rc} { +OPTRACE "route_design write_checkpoint" START { CHECKPOINT } +OPTRACE "route_design write_checkpoint" END { } + write_checkpoint -force NewExtInst_TOP_wrapper_routed_error.dcp + step_failed route_design + return -code error $RESULT +} else { + end_step route_design + unset ACTIVE_STEP +} + +OPTRACE "route_design misc" END { } +OPTRACE "Phase: Route Design" END { } +OPTRACE "Phase: Write Bitstream" START { ROLLUP_AUTO } +OPTRACE "write_bitstream setup" START { } +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb +OPTRACE "read constraints: write_bitstream" START { } +OPTRACE "read constraints: write_bitstream" END { } + set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] + catch { write_mem_info -force -no_partial_mmi NewExtInst_TOP_wrapper.mmi } +OPTRACE "write_bitstream setup" END { } +OPTRACE "write_bitstream" START { } + write_bitstream -force NewExtInst_TOP_wrapper.bit +OPTRACE "write_bitstream" END { } +OPTRACE "write_bitstream misc" START { } +OPTRACE "read constraints: write_bitstream_post" START { } +OPTRACE "read constraints: write_bitstream_post" END { } + catch {write_debug_probes -quiet -force NewExtInst_TOP_wrapper} + catch {file copy -force NewExtInst_TOP_wrapper.ltx debug_nets.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + +OPTRACE "write_bitstream misc" END { } +OPTRACE "Phase: Write Bitstream" END { } +OPTRACE "impl_1" END { } diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/impl_1/htr.txt b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/impl_1/htr.txt new file mode 100644 index 0000000..63b11e6 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/impl_1/htr.txt @@ -0,0 +1,10 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +vivado -log NewExtInst_TOP_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source NewExtInst_TOP_wrapper.tcl -notrace diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/impl_1/project.wdf b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/impl_1/project.wdf new file mode 100644 index 0000000..b080f67 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/impl_1/project.wdf @@ -0,0 +1,41 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:32:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:32:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:32:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3138316565326132363931643437396538363537393434303732666266633531:506172656e742050412070726f6a656374204944:00 +eof:2450799289 diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/impl_1/rundef.js b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/impl_1/rundef.js new file mode 100644 index 0000000..7710abf --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/impl_1/rundef.js @@ -0,0 +1,45 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;"; +} else { + PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +// pre-commands: +ISETouchFile( "init_design", "begin" ); +ISEStep( "vivado", + "-log NewExtInst_TOP_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source NewExtInst_TOP_wrapper.tcl -notrace" ); + + + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/impl_1/runme.bat b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/impl_1/runme.bat new file mode 100644 index 0000000..3a5f853 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/impl_1/runme.bat @@ -0,0 +1,12 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/impl_1/runme.sh b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/impl_1/runme.sh new file mode 100755 index 0000000..9a49b70 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/impl_1/runme.sh @@ -0,0 +1,44 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin +else + PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/impl_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +# pre-commands: +/bin/touch .init_design.begin.rst +EAStep vivado -log NewExtInst_TOP_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source NewExtInst_TOP_wrapper.tcl -notrace + + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/synth_1/ISEWrap.js b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/synth_1/ISEWrap.js new file mode 100755 index 0000000..61806d0 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/synth_1/ISEWrap.sh b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/synth_1/ISEWrap.sh new file mode 100755 index 0000000..05d5381 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/synth_1/ISEWrap.sh @@ -0,0 +1,85 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +cmd_exists() +{ + command -v "$1" >/dev/null 2>&1 +} + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! + +HostNameFile=/proc/sys/kernel/hostname +if cmd_exists hostname +then +ISE_HOST=$(hostname) +elif cmd_exists uname +then +ISE_HOST=$(uname -n) +elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] +then +ISE_HOST=$(cat $HostNameFile) +elif [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi + +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/synth_1/NewExtInst_TOP_wrapper.tcl b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/synth_1/NewExtInst_TOP_wrapper.tcl new file mode 100644 index 0000000..250b68a --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/synth_1/NewExtInst_TOP_wrapper.tcl @@ -0,0 +1,141 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +namespace eval ::optrace { + variable script "/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/synth_1/NewExtInst_TOP_wrapper.tcl" + variable category "vivado_synth" +} + +# Try to connect to running dispatch if we haven't done so already. +# This code assumes that the Tcl interpreter is not using threads, +# since the ::dispatch::connected variable isn't mutex protected. +if {![info exists ::dispatch::connected]} { + namespace eval ::dispatch { + variable connected false + if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} { + set result "true" + if {[catch { + if {[lsearch -exact [package names] DispatchTcl] < 0} { + set result [load librdi_cd_clienttcl[info sharedlibextension]] + } + if {$result eq "false"} { + puts "WARNING: Could not load dispatch client library" + } + set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ] + if { $connect_id eq "" } { + puts "WARNING: Could not initialize dispatch client" + } else { + puts "INFO: Dispatch client connection id - $connect_id" + set connected true + } + } catch_res]} { + puts "WARNING: failed to connect to dispatch server - $catch_res" + } + } + } +} +if {$::dispatch::connected} { + # Remove the dummy proc if it exists. + if { [expr {[llength [info procs ::OPTRACE]] > 0}] } { + rename ::OPTRACE "" + } + proc ::OPTRACE { task action {tags {} } } { + ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category + } + # dispatch is generic. We specifically want to attach logging. + ::vitis_log::connect_client +} else { + # Add dummy proc if it doesn't exist. + if { [expr {[llength [info procs ::OPTRACE]] == 0}] } { + proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} { + # Do nothing + } + } +} + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +OPTRACE "synth_1" START { ROLLUP_AUTO } +set_param chipscope.maxJobs 8 +set_msg_config -id {HDL-1065} -limit 10000 +OPTRACE "Creating in-memory project" START { } +create_project -in_memory -part xc7z035ffg676-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/wt [current_project] +set_property parent.project_path /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_repo_paths /home/ly0kos/work/Zynq/ip_repo [current_project] +update_ip_catalog +set_property ip_output_repo /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +OPTRACE "Creating in-memory project" END { } +OPTRACE "Adding files" START { } +read_verilog -library xil_defaultlib /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/hdl/NewExtInst_TOP_wrapper.v +add_files /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/NewExtInst_TOP.bd +set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0.xdc] +set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_board.xdc] +set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.xdc] +set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_ooc.xdc] +set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_board.xdc] +set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0.xdc] +set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_ooc.xdc] +set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_ooc.xdc] +set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_board.xdc] +set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0.xdc] +set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_ooc.xdc] +set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_auto_pc_0/NewExtInst_TOP_auto_pc_0_ooc.xdc] +set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/NewExtInst_TOP_ooc.xdc] + +OPTRACE "Adding files" END { } +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc dont_touch.xdc +set_property used_in_implementation false [get_files dont_touch.xdc] +set_param ips.enableIPCacheLiteLoad 1 +close [open __synthesis_is_running__ w] + +OPTRACE "synth_design" START { } +synth_design -top NewExtInst_TOP_wrapper -part xc7z035ffg676-2 +OPTRACE "synth_design" END { } +if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } { + send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING" +} + + +OPTRACE "write_checkpoint" START { CHECKPOINT } +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef NewExtInst_TOP_wrapper.dcp +OPTRACE "write_checkpoint" END { } +OPTRACE "synth reports" START { REPORT } +create_report "synth_1_synth_report_utilization_0" "report_utilization -file NewExtInst_TOP_wrapper_utilization_synth.rpt -pb NewExtInst_TOP_wrapper_utilization_synth.pb" +OPTRACE "synth reports" END { } +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] +OPTRACE "synth_1" END { } diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/synth_1/dont_touch.xdc b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/synth_1/dont_touch.xdc new file mode 100644 index 0000000..0ded830 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/synth_1/dont_touch.xdc @@ -0,0 +1,37 @@ +# This file is automatically generated. +# It contains project source information necessary for synthesis and implementation. + +# Block Designs: bd/NewExtInst_TOP/NewExtInst_TOP.bd +set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==NewExtInst_TOP || ORIG_REF_NAME==NewExtInst_TOP} -quiet] -quiet + +# IP: bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0.xci +set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==NewExtInst_TOP_processing_system7_0_0 || ORIG_REF_NAME==NewExtInst_TOP_processing_system7_0_0} -quiet] -quiet + +# IP: bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.xci +set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==NewExtInst_TOP_clk_wiz_0_0 || ORIG_REF_NAME==NewExtInst_TOP_clk_wiz_0_0} -quiet] -quiet + +# IP: bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0.xci +set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==NewExtInst_TOP_proc_sys_reset_0_0 || ORIG_REF_NAME==NewExtInst_TOP_proc_sys_reset_0_0} -quiet] -quiet + +# IP: bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0.xci +set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==NewExtInst_TOP_SPI_Con_0_0 || ORIG_REF_NAME==NewExtInst_TOP_SPI_Con_0_0} -quiet] -quiet + +# IP: bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1.xci +set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==NewExtInst_TOP_SPI_Con_0_1 || ORIG_REF_NAME==NewExtInst_TOP_SPI_Con_0_1} -quiet] -quiet + +# IP: bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/NewExtInst_TOP_SPI_Con_0_2.xci +set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==NewExtInst_TOP_SPI_Con_0_2 || ORIG_REF_NAME==NewExtInst_TOP_SPI_Con_0_2} -quiet] -quiet + +# IP: bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0.xci +set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==NewExtInst_TOP_xbar_0 || ORIG_REF_NAME==NewExtInst_TOP_xbar_0} -quiet] -quiet + +# IP: bd/NewExtInst_TOP/ip/NewExtInst_TOP_ps7_0_axi_periph_0/NewExtInst_TOP_ps7_0_axi_periph_0.xci +set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==NewExtInst_TOP_ps7_0_axi_periph_0 || ORIG_REF_NAME==NewExtInst_TOP_ps7_0_axi_periph_0} -quiet] -quiet + +# IP: bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0.xci +set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==NewExtInst_TOP_rst_clk_wiz_0_100M_0 || ORIG_REF_NAME==NewExtInst_TOP_rst_clk_wiz_0_100M_0} -quiet] -quiet + +# IP: bd/NewExtInst_TOP/ip/NewExtInst_TOP_auto_pc_0/NewExtInst_TOP_auto_pc_0.xci +set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==NewExtInst_TOP_auto_pc_0 || ORIG_REF_NAME==NewExtInst_TOP_auto_pc_0} -quiet] -quiet + +# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/NewExtInst_TOP_ooc.xdc diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/synth_1/htr.txt b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/synth_1/htr.txt new file mode 100644 index 0000000..99ca1e5 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/synth_1/htr.txt @@ -0,0 +1,10 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +vivado -log NewExtInst_TOP_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_wrapper.tcl diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/synth_1/rundef.js b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/synth_1/rundef.js new file mode 100644 index 0000000..1808eda --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/synth_1/rundef.js @@ -0,0 +1,41 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;"; +} else { + PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log NewExtInst_TOP_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_wrapper.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/synth_1/runme.bat b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/synth_1/runme.bat new file mode 100644 index 0000000..3a5f853 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/synth_1/runme.bat @@ -0,0 +1,12 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/synth_1/runme.sh b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/synth_1/runme.sh new file mode 100755 index 0000000..9d274ab --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/synth_1/runme.sh @@ -0,0 +1,40 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin +else + PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log NewExtInst_TOP_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_wrapper.tcl diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/NewExtInst_TOP.bd b/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/NewExtInst_TOP.bd new file mode 100644 index 0000000..60a59d7 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/NewExtInst_TOP.bd @@ -0,0 +1,2625 @@ +{ + "design": { + "design_info": { + "boundary_crc": "0xF3EAB84C2DCB4A87", + "device": "xc7z035ffg676-2", + "gen_directory": "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP", + "name": "NewExtInst_TOP", + "rev_ctrl_bd_flag": "RevCtrlBdOff", + "synth_flow_mode": "Hierarchical", + "tool_version": "2023.2", + "validated": "true" + }, + "design_tree": { + "processing_system7_0": "", + "clk_wiz_0": "", + "proc_sys_reset_0": "", + "SPI_Con_0": "", + "SPI_Con_1": "", + "SPI_Con_2": "", + "ps7_0_axi_periph": { + "xbar": "", + "s00_couplers": { + "auto_pc": "" + }, + "m00_couplers": {}, + "m01_couplers": {}, + "m02_couplers": {} + }, + "rst_clk_wiz_0_100M": "" + }, + "interface_ports": { + "DDR": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:ddrx:1.0", + "vlnv": "xilinx.com:interface:ddrx_rtl:1.0", + "parameters": { + "AXI_ARBITRATION_SCHEME": { + "value": "TDM", + "value_src": "default" + }, + "BURST_LENGTH": { + "value": "8", + "value_src": "default" + }, + "CAN_DEBUG": { + "value": "false", + "value_src": "default" + }, + "CAS_LATENCY": { + "value": "11", + "value_src": "default" + }, + "CAS_WRITE_LATENCY": { + "value": "11", + "value_src": "default" + }, + "CS_ENABLED": { + "value": "true", + "value_src": "default" + }, + "DATA_MASK_ENABLED": { + "value": "true", + "value_src": "default" + }, + "DATA_WIDTH": { + "value": "8", + "value_src": "default" + }, + "MEMORY_TYPE": { + "value": "COMPONENTS", + "value_src": "default" + }, + "MEM_ADDR_MAP": { + "value": "ROW_COLUMN_BANK", + "value_src": "default" + }, + "SLOT": { + "value": "Single", + "value_src": "default" + }, + "TIMEPERIOD_PS": { + "value": "1250", + "value_src": "default" + } + }, + "port_maps": { + "CAS_N": { + "physical_name": "DDR_cas_n", + "direction": "IO" + }, + "CKE": { + "physical_name": "DDR_cke", + "direction": "IO" + }, + "CK_N": { + "physical_name": "DDR_ck_n", + "direction": "IO" + }, + "CK_P": { + "physical_name": "DDR_ck_p", + "direction": "IO" + }, + "CS_N": { + "physical_name": "DDR_cs_n", + "direction": "IO" + }, + "RESET_N": { + "physical_name": "DDR_reset_n", + "direction": "IO" + }, + "ODT": { + "physical_name": "DDR_odt", + "direction": "IO" + }, + "RAS_N": { + "physical_name": "DDR_ras_n", + "direction": "IO" + }, + "WE_N": { + "physical_name": "DDR_we_n", + "direction": "IO" + }, + "BA": { + "physical_name": "DDR_ba", + "direction": "IO", + "left": "2", + "right": "0" + }, + "ADDR": { + "physical_name": "DDR_addr", + "direction": "IO", + "left": "14", + "right": "0" + }, + "DM": { + "physical_name": "DDR_dm", + "direction": "IO", + "left": "3", + "right": "0" + }, + "DQ": { + "physical_name": "DDR_dq", + "direction": "IO", + "left": "31", + "right": "0" + }, + "DQS_N": { + "physical_name": "DDR_dqs_n", + "direction": "IO", + "left": "3", + "right": "0" + }, + "DQS_P": { + "physical_name": "DDR_dqs_p", + "direction": "IO", + "left": "3", + "right": "0" + } + } + }, + "FIXED_IO": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:display_processing_system7:fixedio:1.0", + "vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0", + "parameters": { + "CAN_DEBUG": { + "value": "false", + "value_src": "default" + } + }, + "port_maps": { + "MIO": { + "physical_name": "FIXED_IO_mio", + "direction": "IO", + "left": "53", + "right": "0" + }, + "DDR_VRN": { + "physical_name": "FIXED_IO_ddr_vrn", + "direction": "IO" + }, + "DDR_VRP": { + "physical_name": "FIXED_IO_ddr_vrp", + "direction": "IO" + }, + "PS_SRSTB": { + "physical_name": "FIXED_IO_ps_srstb", + "direction": "IO" + }, + "PS_CLK": { + "physical_name": "FIXED_IO_ps_clk", + "direction": "IO" + }, + "PS_PORB": { + "physical_name": "FIXED_IO_ps_porb", + "direction": "IO" + } + } + } + }, + "ports": { + "o_cs_0": { + "direction": "O" + }, + "i_miso_0": { + "direction": "I" + }, + "o_sclk_0": { + "direction": "O" + }, + "o_mosi_0": { + "direction": "O" + }, + "o_cs_1": { + "direction": "O" + }, + "o_mosi_1": { + "direction": "O" + }, + "o_sclk_1": { + "direction": "O" + }, + "i_miso_1": { + "direction": "I" + }, + "o_mosi_2": { + "direction": "O" + }, + "o_sclk_2": { + "direction": "O" + }, + "o_cs_2": { + "direction": "O" + }, + "i_miso_2": { + "direction": "I" + } + }, + "components": { + "processing_system7_0": { + "vlnv": "xilinx.com:ip:processing_system7:5.5", + "ip_revision": "6", + "xci_name": "NewExtInst_TOP_processing_system7_0_0", + "xci_path": "ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0.xci", + "inst_hier_path": "processing_system7_0", + "parameters": { + "PCW_ACT_APU_PERIPHERAL_FREQMHZ": { + "value": "666.666687" + }, + "PCW_ACT_CAN0_PERIPHERAL_FREQMHZ": { + "value": "23.8095" + }, + "PCW_ACT_CAN1_PERIPHERAL_FREQMHZ": { + "value": "23.8095" + }, + "PCW_ACT_CAN_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_DCI_PERIPHERAL_FREQMHZ": { + "value": "10.158730" + }, + "PCW_ACT_ENET0_PERIPHERAL_FREQMHZ": { + "value": "125.000000" + }, + "PCW_ACT_ENET1_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": { + "value": "25.000000" + }, + "PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": { + "value": "50.000000" + }, + "PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ": { + "value": "100.000000" + }, + "PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ": { + "value": "200.000000" + }, + "PCW_ACT_I2C_PERIPHERAL_FREQMHZ": { + "value": "50" + }, + "PCW_ACT_PCAP_PERIPHERAL_FREQMHZ": { + "value": "200.000000" + }, + "PCW_ACT_QSPI_PERIPHERAL_FREQMHZ": { + "value": "142.857132" + }, + "PCW_ACT_SDIO_PERIPHERAL_FREQMHZ": { + "value": "100.000000" + }, + "PCW_ACT_SMC_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_SPI_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_TPIU_PERIPHERAL_FREQMHZ": { + "value": "200.000000" + }, + "PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC_PERIPHERAL_FREQMHZ": { + "value": "50" + }, + "PCW_ACT_UART_PERIPHERAL_FREQMHZ": { + "value": "100.000000" + }, + "PCW_ACT_USB0_PERIPHERAL_FREQMHZ": { + "value": "60" + }, + "PCW_ACT_USB1_PERIPHERAL_FREQMHZ": { + "value": "60" + }, + "PCW_ACT_WDT_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_APU_CLK_RATIO_ENABLE": { + "value": "6:2:1" + }, + "PCW_APU_PERIPHERAL_FREQMHZ": { + "value": "666.666666" + }, + "PCW_CAN0_PERIPHERAL_CLKSRC": { + "value": "External" + }, + "PCW_CAN0_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_CAN1_PERIPHERAL_CLKSRC": { + "value": "External" + }, + "PCW_CAN1_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_CAN_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_CAN_PERIPHERAL_VALID": { + "value": "0" + }, + "PCW_CLK0_FREQ": { + "value": "25000000" + }, + "PCW_CLK1_FREQ": { + "value": "50000000" + }, + "PCW_CLK2_FREQ": { + "value": "100000000" + }, + "PCW_CLK3_FREQ": { + "value": "200000000" + }, + "PCW_CPU_CPU_6X4X_MAX_RANGE": { + "value": "800" + }, + "PCW_CPU_PERIPHERAL_CLKSRC": { + "value": "ARM PLL" + }, + "PCW_CRYSTAL_PERIPHERAL_FREQMHZ": { + "value": "33.333333" + }, + "PCW_DCI_PERIPHERAL_CLKSRC": { + "value": "DDR PLL" + }, + "PCW_DCI_PERIPHERAL_FREQMHZ": { + "value": "10.159" + }, + "PCW_DDR_PERIPHERAL_CLKSRC": { + "value": "DDR PLL" + }, + "PCW_DDR_RAM_BASEADDR": { + "value": "0x00100000" + }, + "PCW_DDR_RAM_HIGHADDR": { + "value": "0x3FFFFFFF" + }, + "PCW_DM_WIDTH": { + "value": "4" + }, + "PCW_DQS_WIDTH": { + "value": "4" + }, + "PCW_DQ_WIDTH": { + "value": "32" + }, + "PCW_ENET0_BASEADDR": { + "value": "0xE000B000" + }, + "PCW_ENET0_ENET0_IO": { + "value": "MIO 16 .. 27" + }, + "PCW_ENET0_GRP_MDIO_ENABLE": { + "value": "1" + }, + "PCW_ENET0_GRP_MDIO_IO": { + "value": "MIO 52 .. 53" + }, + "PCW_ENET0_HIGHADDR": { + "value": "0xE000BFFF" + }, + "PCW_ENET0_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_ENET0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_ENET0_PERIPHERAL_FREQMHZ": { + "value": "1000 Mbps" + }, + "PCW_ENET1_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_ENET1_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_ENET_RESET_POLARITY": { + "value": "Active Low" + }, + "PCW_EN_4K_TIMER": { + "value": "0" + }, + "PCW_EN_CAN0": { + "value": "0" + }, + "PCW_EN_CAN1": { + "value": "0" + }, + "PCW_EN_CLK0_PORT": { + "value": "1" + }, + "PCW_EN_CLK1_PORT": { + "value": "1" + }, + "PCW_EN_CLK2_PORT": { + "value": "1" + }, + "PCW_EN_CLK3_PORT": { + "value": "1" + }, + "PCW_EN_CLKTRIG0_PORT": { + "value": "0" + }, + "PCW_EN_CLKTRIG1_PORT": { + "value": "0" + }, + "PCW_EN_CLKTRIG2_PORT": { + "value": "0" + }, + "PCW_EN_CLKTRIG3_PORT": { + "value": "0" + }, + "PCW_EN_DDR": { + "value": "1" + }, + "PCW_EN_EMIO_CAN0": { + "value": "0" + }, + "PCW_EN_EMIO_CAN1": { + "value": "0" + }, + "PCW_EN_EMIO_CD_SDIO0": { + "value": "0" + }, + "PCW_EN_EMIO_CD_SDIO1": { + "value": "0" + }, + "PCW_EN_EMIO_ENET0": { + "value": "0" + }, + "PCW_EN_EMIO_ENET1": { + "value": "0" + }, + "PCW_EN_EMIO_GPIO": { + "value": "0" + }, + "PCW_EN_EMIO_I2C0": { + "value": "0" + }, + "PCW_EN_EMIO_I2C1": { + "value": "0" + }, + "PCW_EN_EMIO_MODEM_UART0": { + "value": "0" + }, + "PCW_EN_EMIO_MODEM_UART1": { + "value": "0" + }, + "PCW_EN_EMIO_PJTAG": { + "value": "0" + }, + "PCW_EN_EMIO_SDIO0": { + "value": "0" + }, + "PCW_EN_EMIO_SDIO1": { + "value": "0" + }, + "PCW_EN_EMIO_SPI0": { + "value": "0" + }, + "PCW_EN_EMIO_SPI1": { + "value": "0" + }, + "PCW_EN_EMIO_SRAM_INT": { + "value": "0" + }, + "PCW_EN_EMIO_TRACE": { + "value": "0" + }, + "PCW_EN_EMIO_TTC0": { + "value": "0" + }, + "PCW_EN_EMIO_TTC1": { + "value": "0" + }, + "PCW_EN_EMIO_UART0": { + "value": "0" + }, + "PCW_EN_EMIO_UART1": { + "value": "0" + }, + "PCW_EN_EMIO_WDT": { + "value": "0" + }, + "PCW_EN_EMIO_WP_SDIO0": { + "value": "0" + }, + "PCW_EN_EMIO_WP_SDIO1": { + "value": "0" + }, + "PCW_EN_ENET0": { + "value": "1" + }, + "PCW_EN_ENET1": { + "value": "0" + }, + "PCW_EN_GPIO": { + "value": "0" + }, + "PCW_EN_I2C0": { + "value": "0" + }, + "PCW_EN_I2C1": { + "value": "0" + }, + "PCW_EN_MODEM_UART0": { + "value": "0" + }, + "PCW_EN_MODEM_UART1": { + "value": "0" + }, + "PCW_EN_PJTAG": { + "value": "0" + }, + "PCW_EN_PTP_ENET0": { + "value": "0" + }, + "PCW_EN_PTP_ENET1": { + "value": "0" + }, + "PCW_EN_QSPI": { + "value": "1" + }, + "PCW_EN_RST0_PORT": { + "value": "1" + }, + "PCW_EN_RST1_PORT": { + "value": "0" + }, + "PCW_EN_RST2_PORT": { + "value": "0" + }, + "PCW_EN_RST3_PORT": { + "value": "0" + }, + "PCW_EN_SDIO0": { + "value": "1" + }, + "PCW_EN_SDIO1": { + "value": "1" + }, + "PCW_EN_SMC": { + "value": "0" + }, + "PCW_EN_SPI0": { + "value": "0" + }, + "PCW_EN_SPI1": { + "value": "0" + }, + "PCW_EN_TRACE": { + "value": "0" + }, + "PCW_EN_TTC0": { + "value": "0" + }, + "PCW_EN_TTC1": { + "value": "0" + }, + "PCW_EN_UART0": { + "value": "0" + }, + "PCW_EN_UART1": { + "value": "1" + }, + "PCW_EN_USB0": { + "value": "0" + }, + "PCW_EN_USB1": { + "value": "0" + }, + "PCW_EN_WDT": { + "value": "0" + }, + "PCW_FCLK0_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_FCLK1_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_FCLK2_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_FCLK3_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_FCLK_CLK0_BUF": { + "value": "TRUE" + }, + "PCW_FCLK_CLK1_BUF": { + "value": "TRUE" + }, + "PCW_FCLK_CLK2_BUF": { + "value": "TRUE" + }, + "PCW_FCLK_CLK3_BUF": { + "value": "TRUE" + }, + "PCW_FPGA0_PERIPHERAL_FREQMHZ": { + "value": "25" + }, + "PCW_FPGA1_PERIPHERAL_FREQMHZ": { + "value": "50" + }, + "PCW_FPGA2_PERIPHERAL_FREQMHZ": { + "value": "100" + }, + "PCW_FPGA3_PERIPHERAL_FREQMHZ": { + "value": "200" + }, + "PCW_FPGA_FCLK0_ENABLE": { + "value": "1" + }, + "PCW_FPGA_FCLK1_ENABLE": { + "value": "1" + }, + "PCW_FPGA_FCLK2_ENABLE": { + "value": "1" + }, + "PCW_FPGA_FCLK3_ENABLE": { + "value": "1" + }, + "PCW_GP0_EN_MODIFIABLE_TXN": { + "value": "1" + }, + "PCW_GP0_NUM_READ_THREADS": { + "value": "4" + }, + "PCW_GP0_NUM_WRITE_THREADS": { + "value": "4" + }, + "PCW_GP1_EN_MODIFIABLE_TXN": { + "value": "1" + }, + "PCW_GP1_NUM_READ_THREADS": { + "value": "4" + }, + "PCW_GP1_NUM_WRITE_THREADS": { + "value": "4" + }, + "PCW_GPIO_EMIO_GPIO_ENABLE": { + "value": "0" + }, + "PCW_GPIO_MIO_GPIO_ENABLE": { + "value": "0" + }, + "PCW_GPIO_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_I2C0_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_I2C1_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_I2C_RESET_POLARITY": { + "value": "Active Low" + }, + "PCW_IMPORT_BOARD_PRESET": { + "value": "None" + }, + "PCW_INCLUDE_ACP_TRANS_CHECK": { + "value": "0" + }, + "PCW_IRQ_F2P_MODE": { + "value": "DIRECT" + }, + "PCW_MIO_0_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_0_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_0_SLEW": { + "value": "slow" + }, + "PCW_MIO_10_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_10_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_10_SLEW": { + "value": "slow" + }, + "PCW_MIO_11_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_11_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_11_SLEW": { + "value": "slow" + }, + "PCW_MIO_12_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_12_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_12_SLEW": { + "value": "slow" + }, + "PCW_MIO_13_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_13_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_13_SLEW": { + "value": "slow" + }, + "PCW_MIO_14_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_14_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_14_SLEW": { + "value": "slow" + }, + "PCW_MIO_15_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_15_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_15_SLEW": { + "value": "slow" + }, + "PCW_MIO_16_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_16_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_16_SLEW": { + "value": "slow" + }, + "PCW_MIO_17_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_17_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_17_SLEW": { + "value": "slow" + }, + "PCW_MIO_18_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_18_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_18_SLEW": { + "value": "slow" + }, + "PCW_MIO_19_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_19_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_19_SLEW": { + "value": "slow" + }, + "PCW_MIO_1_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_1_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_1_SLEW": { + "value": "slow" + }, + "PCW_MIO_20_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_20_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_20_SLEW": { + "value": "slow" + }, + "PCW_MIO_21_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_21_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_21_SLEW": { + "value": "slow" + }, + "PCW_MIO_22_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_22_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_22_SLEW": { + "value": "slow" + }, + "PCW_MIO_23_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_23_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_23_SLEW": { + "value": "slow" + }, + "PCW_MIO_24_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_24_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_24_SLEW": { + "value": "slow" + }, + "PCW_MIO_25_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_25_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_25_SLEW": { + "value": "slow" + }, + "PCW_MIO_26_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_26_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_26_SLEW": { + "value": "slow" + }, + "PCW_MIO_27_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_27_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_27_SLEW": { + "value": "slow" + }, + "PCW_MIO_2_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_2_SLEW": { + "value": "slow" + }, + "PCW_MIO_3_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_3_SLEW": { + "value": "slow" + }, + "PCW_MIO_40_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_40_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_40_SLEW": { + "value": "slow" + }, + "PCW_MIO_41_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_41_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_41_SLEW": { + "value": "slow" + }, + "PCW_MIO_42_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_42_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_42_SLEW": { + "value": "slow" + }, + "PCW_MIO_43_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_43_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_43_SLEW": { + "value": "slow" + }, + "PCW_MIO_44_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_44_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_44_SLEW": { + "value": "slow" + }, + "PCW_MIO_45_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_45_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_45_SLEW": { + "value": "slow" + }, + "PCW_MIO_46_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_46_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_46_SLEW": { + "value": "slow" + }, + "PCW_MIO_47_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_47_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_47_SLEW": { + "value": "slow" + }, + "PCW_MIO_48_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_48_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_48_SLEW": { + "value": "slow" + }, + "PCW_MIO_49_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_49_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_49_SLEW": { + "value": "slow" + }, + "PCW_MIO_4_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_4_SLEW": { + "value": "slow" + }, + "PCW_MIO_52_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_52_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_52_SLEW": { + "value": "slow" + }, + "PCW_MIO_53_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_53_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_53_SLEW": { + "value": "slow" + }, + "PCW_MIO_5_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_5_SLEW": { + "value": "slow" + }, + "PCW_MIO_6_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_6_SLEW": { + "value": "slow" + }, + "PCW_MIO_8_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_8_SLEW": { + "value": "slow" + }, + "PCW_MIO_9_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_9_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_9_SLEW": { + "value": "slow" + }, + "PCW_MIO_PRIMITIVE": { + "value": "54" + }, + "PCW_MIO_TREE_PERIPHERALS": { + "value": [ + "SD 1#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#unassigned#Quad SPI Flash#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet", + "0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#SD 0#SD 0#SD 0#SD 0#SD", + "0#SD 0#SD 0#SD 0#UART 1#UART 1#unassigned#unassigned#Enet 0#Enet 0" + ] + }, + "PCW_MIO_TREE_SIGNALS": { + "value": "wp#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#unassigned#qspi_fbclk#cd#data[0]#cmd#clk#data[1]#data[2]#data[3]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#clk#cmd#data[0]#data[1]#data[2]#data[3]#wp#cd#tx#rx#unassigned#unassigned#mdc#mdio" + }, + "PCW_M_AXI_GP0_ENABLE_STATIC_REMAP": { + "value": "0" + }, + "PCW_M_AXI_GP0_ID_WIDTH": { + "value": "12" + }, + "PCW_M_AXI_GP0_SUPPORT_NARROW_BURST": { + "value": "0" + }, + "PCW_M_AXI_GP0_THREAD_ID_WIDTH": { + "value": "12" + }, + "PCW_NAND_CYCLES_T_AR": { + "value": "1" + }, + "PCW_NAND_CYCLES_T_CLR": { + "value": "1" + }, + "PCW_NAND_CYCLES_T_RC": { + "value": "11" + }, + "PCW_NAND_CYCLES_T_REA": { + "value": "1" + }, + "PCW_NAND_CYCLES_T_RR": { + "value": "1" + }, + "PCW_NAND_CYCLES_T_WC": { + "value": "11" + }, + "PCW_NAND_CYCLES_T_WP": { + "value": "1" + }, + "PCW_NOR_CS0_T_CEOE": { + "value": "1" + }, + "PCW_NOR_CS0_T_PC": { + "value": "1" + }, + "PCW_NOR_CS0_T_RC": { + "value": "11" + }, + "PCW_NOR_CS0_T_TR": { + "value": "1" + }, + "PCW_NOR_CS0_T_WC": { + "value": "11" + }, + "PCW_NOR_CS0_T_WP": { + "value": "1" + }, + "PCW_NOR_CS0_WE_TIME": { + "value": "0" + }, + "PCW_NOR_CS1_T_CEOE": { + "value": "1" + }, + "PCW_NOR_CS1_T_PC": { + "value": "1" + }, + "PCW_NOR_CS1_T_RC": { + "value": "11" + }, + "PCW_NOR_CS1_T_TR": { + "value": "1" + }, + "PCW_NOR_CS1_T_WC": { + "value": "11" + }, + "PCW_NOR_CS1_T_WP": { + "value": "1" + }, + "PCW_NOR_CS1_WE_TIME": { + "value": "0" + }, + "PCW_NOR_SRAM_CS0_T_CEOE": { + "value": "1" + }, + "PCW_NOR_SRAM_CS0_T_PC": { + "value": "1" + }, + "PCW_NOR_SRAM_CS0_T_RC": { + "value": "11" + }, + "PCW_NOR_SRAM_CS0_T_TR": { + "value": "1" + }, + "PCW_NOR_SRAM_CS0_T_WC": { + "value": "11" + }, + "PCW_NOR_SRAM_CS0_T_WP": { + "value": "1" + }, + "PCW_NOR_SRAM_CS0_WE_TIME": { + "value": "0" + }, + "PCW_NOR_SRAM_CS1_T_CEOE": { + "value": "1" + }, + "PCW_NOR_SRAM_CS1_T_PC": { + "value": "1" + }, + "PCW_NOR_SRAM_CS1_T_RC": { + "value": "11" + }, + "PCW_NOR_SRAM_CS1_T_TR": { + "value": "1" + }, + "PCW_NOR_SRAM_CS1_T_WC": { + "value": "11" + }, + "PCW_NOR_SRAM_CS1_T_WP": { + "value": "1" + }, + "PCW_NOR_SRAM_CS1_WE_TIME": { + "value": "0" + }, + "PCW_OVERRIDE_BASIC_CLOCK": { + "value": "0" + }, + "PCW_PACKAGE_DDR_BOARD_DELAY0": { + "value": "0.075" + }, + "PCW_PACKAGE_DDR_BOARD_DELAY1": { + "value": "0.070" + }, + "PCW_PACKAGE_DDR_BOARD_DELAY2": { + "value": "0.077" + }, + "PCW_PACKAGE_DDR_BOARD_DELAY3": { + "value": "0.094" + }, + "PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0": { + "value": "-0.000" + }, + "PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1": { + "value": "-0.001" + }, + "PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2": { + "value": "0.004" + }, + "PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3": { + "value": "-0.035" + }, + "PCW_PACKAGE_NAME": { + "value": "ffg676" + }, + "PCW_PCAP_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_PCAP_PERIPHERAL_FREQMHZ": { + "value": "200" + }, + "PCW_PERIPHERAL_BOARD_PRESET": { + "value": "None" + }, + "PCW_PJTAG_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_PLL_BYPASSMODE_ENABLE": { + "value": "0" + }, + "PCW_PRESET_BANK0_VOLTAGE": { + "value": "LVCMOS 3.3V" + }, + "PCW_PRESET_BANK1_VOLTAGE": { + "value": "LVCMOS 1.8V" + }, + "PCW_PS7_SI_REV": { + "value": "PRODUCTION" + }, + "PCW_QSPI_GRP_FBCLK_ENABLE": { + "value": "1" + }, + "PCW_QSPI_GRP_FBCLK_IO": { + "value": "MIO 8" + }, + "PCW_QSPI_GRP_IO1_ENABLE": { + "value": "0" + }, + "PCW_QSPI_GRP_SINGLE_SS_ENABLE": { + "value": "1" + }, + "PCW_QSPI_GRP_SINGLE_SS_IO": { + "value": "MIO 1 .. 6" + }, + "PCW_QSPI_GRP_SS1_ENABLE": { + "value": "0" + }, + "PCW_QSPI_INTERNAL_HIGHADDRESS": { + "value": "0xFCFFFFFF" + }, + "PCW_QSPI_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_QSPI_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_QSPI_PERIPHERAL_FREQMHZ": { + "value": "150" + }, + "PCW_QSPI_QSPI_IO": { + "value": "MIO 1 .. 6" + }, + "PCW_SD0_GRP_CD_ENABLE": { + "value": "1" + }, + "PCW_SD0_GRP_CD_IO": { + "value": "MIO 47" + }, + "PCW_SD0_GRP_POW_ENABLE": { + "value": "0" + }, + "PCW_SD0_GRP_WP_ENABLE": { + "value": "1" + }, + "PCW_SD0_GRP_WP_IO": { + "value": "MIO 46" + }, + "PCW_SD0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_SD0_SD0_IO": { + "value": "MIO 40 .. 45" + }, + "PCW_SD1_GRP_CD_ENABLE": { + "value": "1" + }, + "PCW_SD1_GRP_CD_IO": { + "value": "MIO 9" + }, + "PCW_SD1_GRP_POW_ENABLE": { + "value": "0" + }, + "PCW_SD1_GRP_WP_ENABLE": { + "value": "1" + }, + "PCW_SD1_GRP_WP_IO": { + "value": "MIO 0" + }, + "PCW_SD1_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_SD1_SD1_IO": { + "value": "MIO 10 .. 15" + }, + "PCW_SDIO0_BASEADDR": { + "value": "0xE0100000" + }, + "PCW_SDIO0_HIGHADDR": { + "value": "0xE0100FFF" + }, + "PCW_SDIO1_BASEADDR": { + "value": "0xE0101000" + }, + "PCW_SDIO1_HIGHADDR": { + "value": "0xE0101FFF" + }, + "PCW_SDIO_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_SDIO_PERIPHERAL_FREQMHZ": { + "value": "100" + }, + "PCW_SDIO_PERIPHERAL_VALID": { + "value": "1" + }, + "PCW_SINGLE_QSPI_DATA_MODE": { + "value": "x4" + }, + "PCW_SMC_CYCLE_T0": { + "value": "NA" + }, + "PCW_SMC_CYCLE_T1": { + "value": "NA" + }, + "PCW_SMC_CYCLE_T2": { + "value": "NA" + }, + "PCW_SMC_CYCLE_T3": { + "value": "NA" + }, + "PCW_SMC_CYCLE_T4": { + "value": "NA" + }, + "PCW_SMC_CYCLE_T5": { + "value": "NA" + }, + "PCW_SMC_CYCLE_T6": { + "value": "NA" + }, + "PCW_SMC_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_SMC_PERIPHERAL_VALID": { + "value": "0" + }, + "PCW_SPI0_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_SPI1_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_SPI_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_SPI_PERIPHERAL_VALID": { + "value": "0" + }, + "PCW_TPIU_PERIPHERAL_CLKSRC": { + "value": "External" + }, + "PCW_TRACE_INTERNAL_WIDTH": { + "value": "2" + }, + "PCW_TRACE_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_TTC0_CLK0_PERIPHERAL_CLKSRC": { + "value": "CPU_1X" + }, + "PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0": { + "value": "1" + }, + "PCW_TTC0_CLK1_PERIPHERAL_CLKSRC": { + "value": "CPU_1X" + }, + "PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0": { + "value": "1" + }, + "PCW_TTC0_CLK2_PERIPHERAL_CLKSRC": { + "value": "CPU_1X" + }, + "PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0": { + "value": "1" + }, + "PCW_TTC0_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_TTC1_CLK0_PERIPHERAL_CLKSRC": { + "value": "CPU_1X" + }, + "PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0": { + "value": "1" + }, + "PCW_TTC1_CLK1_PERIPHERAL_CLKSRC": { + "value": "CPU_1X" + }, + "PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0": { + "value": "1" + }, + "PCW_TTC1_CLK2_PERIPHERAL_CLKSRC": { + "value": "CPU_1X" + }, + "PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0": { + "value": "1" + }, + "PCW_TTC1_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_UART0_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_UART1_BASEADDR": { + "value": "0xE0001000" + }, + "PCW_UART1_BAUD_RATE": { + "value": "115200" + }, + "PCW_UART1_GRP_FULL_ENABLE": { + "value": "0" + }, + "PCW_UART1_HIGHADDR": { + "value": "0xE0001FFF" + }, + "PCW_UART1_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_UART1_UART1_IO": { + "value": "MIO 48 .. 49" + }, + "PCW_UART_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_UART_PERIPHERAL_FREQMHZ": { + "value": "100" + }, + "PCW_UART_PERIPHERAL_VALID": { + "value": "1" + }, + "PCW_UIPARAM_ACT_DDR_FREQ_MHZ": { + "value": "533.333374" + }, + "PCW_UIPARAM_DDR_ADV_ENABLE": { + "value": "0" + }, + "PCW_UIPARAM_DDR_AL": { + "value": "0" + }, + "PCW_UIPARAM_DDR_BL": { + "value": "8" + }, + "PCW_UIPARAM_DDR_BOARD_DELAY0": { + "value": "0.25" + }, + "PCW_UIPARAM_DDR_BOARD_DELAY1": { + "value": "0.25" + }, + "PCW_UIPARAM_DDR_BOARD_DELAY2": { + "value": "0.25" + }, + "PCW_UIPARAM_DDR_BOARD_DELAY3": { + "value": "0.25" + }, + "PCW_UIPARAM_DDR_BUS_WIDTH": { + "value": "32 Bit" + }, + "PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM": { + "value": "0" + }, + "PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH": { + "value": "76.428" + }, + "PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM": { + "value": "0" + }, + "PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH": { + "value": "76.428" + }, + "PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM": { + "value": "0" + }, + "PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH": { + "value": "76.428" + }, + "PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM": { + "value": "0" + }, + "PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH": { + "value": "76.428" + }, + "PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_CLOCK_STOP_EN": { + "value": "0" + }, + "PCW_UIPARAM_DDR_DQS_0_LENGTH_MM": { + "value": "0" + }, + "PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH": { + "value": "76.687" + }, + "PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQS_1_LENGTH_MM": { + "value": "0" + }, + "PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH": { + "value": "77.8025" + }, + "PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQS_2_LENGTH_MM": { + "value": "0" + }, + "PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH": { + "value": "72.8405" + }, + "PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQS_3_LENGTH_MM": { + "value": "0" + }, + "PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH": { + "value": "111.904" + }, + "PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0": { + "value": "0.0" + }, + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1": { + "value": "0.0" + }, + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2": { + "value": "0.0" + }, + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3": { + "value": "0.0" + }, + "PCW_UIPARAM_DDR_DQ_0_LENGTH_MM": { + "value": "0" + }, + "PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH": { + "value": "73.119" + }, + "PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQ_1_LENGTH_MM": { + "value": "0" + }, + "PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH": { + "value": "63.8935" + }, + "PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQ_2_LENGTH_MM": { + "value": "0" + }, + "PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH": { + "value": "77.045" + }, + "PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQ_3_LENGTH_MM": { + "value": "0" + }, + "PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH": { + "value": "111.903" + }, + "PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_ENABLE": { + "value": "1" + }, + "PCW_UIPARAM_DDR_FREQ_MHZ": { + "value": "533.333333" + }, + "PCW_UIPARAM_DDR_HIGH_TEMP": { + "value": "Normal (0-85)" + }, + "PCW_UIPARAM_DDR_MEMORY_TYPE": { + "value": "DDR 3" + }, + "PCW_UIPARAM_DDR_PARTNO": { + "value": "MT41J256M16 RE-125" + }, + "PCW_UIPARAM_DDR_TRAIN_DATA_EYE": { + "value": "1" + }, + "PCW_UIPARAM_DDR_TRAIN_READ_GATE": { + "value": "1" + }, + "PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL": { + "value": "1" + }, + "PCW_UIPARAM_DDR_USE_INTERNAL_VREF": { + "value": "0" + }, + "PCW_UIPARAM_GENERATE_SUMMARY": { + "value": "NA" + }, + "PCW_USB0_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_USB1_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_USB_RESET_POLARITY": { + "value": "Active Low" + }, + "PCW_USE_AXI_FABRIC_IDLE": { + "value": "0" + }, + "PCW_USE_AXI_NONSECURE": { + "value": "0" + }, + "PCW_USE_CORESIGHT": { + "value": "0" + }, + "PCW_USE_CROSS_TRIGGER": { + "value": "0" + }, + "PCW_USE_CR_FABRIC": { + "value": "1" + }, + "PCW_USE_DDR_BYPASS": { + "value": "0" + }, + "PCW_USE_DEBUG": { + "value": "0" + }, + "PCW_USE_DMA0": { + "value": "0" + }, + "PCW_USE_DMA1": { + "value": "0" + }, + "PCW_USE_DMA2": { + "value": "0" + }, + "PCW_USE_DMA3": { + "value": "0" + }, + "PCW_USE_EXPANDED_IOP": { + "value": "0" + }, + "PCW_USE_FABRIC_INTERRUPT": { + "value": "0" + }, + "PCW_USE_HIGH_OCM": { + "value": "0" + }, + "PCW_USE_M_AXI_GP0": { + "value": "1" + }, + "PCW_USE_M_AXI_GP1": { + "value": "0" + }, + "PCW_USE_PROC_EVENT_BUS": { + "value": "0" + }, + "PCW_USE_PS_SLCR_REGISTERS": { + "value": "0" + }, + "PCW_USE_S_AXI_ACP": { + "value": "0" + }, + "PCW_USE_S_AXI_GP0": { + "value": "0" + }, + "PCW_USE_S_AXI_GP1": { + "value": "0" + }, + "PCW_USE_S_AXI_HP0": { + "value": "0" + }, + "PCW_USE_S_AXI_HP1": { + "value": "0" + }, + "PCW_USE_S_AXI_HP2": { + "value": "0" + }, + "PCW_USE_S_AXI_HP3": { + "value": "0" + }, + "PCW_USE_TRACE": { + "value": "0" + }, + "PCW_VALUE_SILVERSION": { + "value": "3" + }, + "PCW_WDT_PERIPHERAL_CLKSRC": { + "value": "CPU_1X" + }, + "PCW_WDT_PERIPHERAL_DIVISOR0": { + "value": "1" + }, + "PCW_WDT_PERIPHERAL_ENABLE": { + "value": "0" + } + }, + "interface_ports": { + "M_AXI_GP0": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Master", + "address_space_ref": "Data", + "base_address": { + "minimum": "0x40000000", + "maximum": "0x7FFFFFFF", + "width": "32" + } + } + }, + "addressing": { + "address_spaces": { + "Data": { + "range": "4G", + "width": "32", + "local_memory_map": { + "name": "Data", + "description": "Address Space Segments", + "address_blocks": { + "segment1": { + "name": "segment1", + "display_name": "segment1", + "base_address": "0x00000000", + "range": "256K", + "width": "18", + "usage": "register" + }, + "segment2": { + "name": "segment2", + "display_name": "segment2", + "base_address": "0x00040000", + "range": "256K", + "width": "19", + "usage": "register" + }, + "segment3": { + "name": "segment3", + "display_name": "segment3", + "base_address": "0x00080000", + "range": "512K", + "width": "20", + "usage": "register" + }, + "segment4": { + "name": "segment4", + "display_name": "segment4", + "base_address": "0x00100000", + "range": "1023M", + "width": "30", + "usage": "register" + }, + "M_AXI_GP0": { + "name": "M_AXI_GP0", + "display_name": "M_AXI_GP0", + "base_address": "0x40000000", + "range": "1G", + "width": "31", + "usage": "register" + }, + "M_AXI_GP1": { + "name": "M_AXI_GP1", + "display_name": "M_AXI_GP1", + "base_address": "0x80000000", + "range": "1G", + "width": "32", + "usage": "register" + }, + "IO_Peripheral_Registers": { + "name": "IO_Peripheral_Registers", + "display_name": "IO Peripheral Registers", + "base_address": "0xE0000000", + "range": "3M", + "width": "32", + "usage": "register" + }, + "SMC_Memories": { + "name": "SMC_Memories", + "display_name": "SMC Memories", + "base_address": "0xE1000000", + "range": "80M", + "width": "32", + "usage": "register" + }, + "SLCR_Registers": { + "name": "SLCR_Registers", + "display_name": "SLCR Registers", + "base_address": "0xF8000000", + "range": "3K", + "width": "32", + "usage": "register" + }, + "PS_System_Registers": { + "name": "PS_System_Registers", + "display_name": "PS System Registers", + "base_address": "0xF8001000", + "range": "8252K", + "width": "32", + "usage": "register" + }, + "CPU_Private_Registers": { + "name": "CPU_Private_Registers", + "display_name": "CPU Private Registers", + "base_address": "0xF8900000", + "range": "6156K", + "width": "32", + "usage": "register" + }, + "segment5": { + "name": "segment5", + "display_name": "segment5", + "base_address": "0xFC000000", + "range": "32M", + "width": "32", + "usage": "register" + }, + "segment6": { + "name": "segment6", + "display_name": "segment6", + "base_address": "0xFFFC0000", + "range": "256K", + "width": "32", + "usage": "register" + } + } + } + } + } + } + }, + "clk_wiz_0": { + "vlnv": "xilinx.com:ip:clk_wiz:6.0", + "ip_revision": "13", + "xci_name": "NewExtInst_TOP_clk_wiz_0_0", + "xci_path": "ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.xci", + "inst_hier_path": "clk_wiz_0", + "parameters": { + "CLKIN1_JITTER_PS": { + "value": "400.0" + }, + "CLKOUT1_JITTER": { + "value": "226.965" + }, + "CLKOUT1_PHASE_ERROR": { + "value": "237.727" + }, + "MMCM_CLKFBOUT_MULT_F": { + "value": "40.000" + }, + "MMCM_CLKIN1_PERIOD": { + "value": "40.000" + }, + "MMCM_CLKIN2_PERIOD": { + "value": "10.0" + } + } + }, + "proc_sys_reset_0": { + "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", + "ip_revision": "14", + "xci_name": "NewExtInst_TOP_proc_sys_reset_0_0", + "xci_path": "ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0.xci", + "inst_hier_path": "proc_sys_reset_0" + }, + "SPI_Con_0": { + "vlnv": "xilinx.com:user:SPI_Con:1.0", + "ip_revision": "3", + "xci_name": "NewExtInst_TOP_SPI_Con_0_0", + "xci_path": "ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0.xci", + "inst_hier_path": "SPI_Con_0" + }, + "SPI_Con_1": { + "vlnv": "xilinx.com:user:SPI_Con:1.0", + "ip_revision": "3", + "xci_name": "NewExtInst_TOP_SPI_Con_0_1", + "xci_path": "ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1.xci", + "inst_hier_path": "SPI_Con_1" + }, + "SPI_Con_2": { + "vlnv": "xilinx.com:user:SPI_Con:1.0", + "ip_revision": "3", + "xci_name": "NewExtInst_TOP_SPI_Con_0_2", + "xci_path": "ip/NewExtInst_TOP_SPI_Con_0_2/NewExtInst_TOP_SPI_Con_0_2.xci", + "inst_hier_path": "SPI_Con_2" + }, + "ps7_0_axi_periph": { + "vlnv": "xilinx.com:ip:axi_interconnect:2.1", + "xci_path": "ip/NewExtInst_TOP_ps7_0_axi_periph_0/NewExtInst_TOP_ps7_0_axi_periph_0.xci", + "inst_hier_path": "ps7_0_axi_periph", + "xci_name": "NewExtInst_TOP_ps7_0_axi_periph_0", + "parameters": { + "NUM_MI": { + "value": "3" + } + }, + "interface_ports": { + "S00_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M00_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M01_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M02_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_RESET": { + "value": "ARESETN" + } + } + }, + "ARESETN": { + "type": "rst", + "direction": "I" + }, + "S00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S00_ARESETN" + } + } + }, + "S00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M00_ARESETN" + } + } + }, + "M00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M01_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M01_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M01_ARESETN" + } + } + }, + "M01_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M02_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M02_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M02_ARESETN" + } + } + }, + "M02_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "xbar": { + "vlnv": "xilinx.com:ip:axi_crossbar:2.1", + "ip_revision": "30", + "xci_name": "NewExtInst_TOP_xbar_0", + "xci_path": "ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0.xci", + "inst_hier_path": "ps7_0_axi_periph/xbar", + "parameters": { + "NUM_MI": { + "value": "3" + }, + "NUM_SI": { + "value": "1" + }, + "STRATEGY": { + "value": "0" + } + }, + "interface_ports": { + "S00_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M00_AXI", + "M01_AXI", + "M02_AXI" + ] + } + } + }, + "s00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "auto_pc": { + "vlnv": "xilinx.com:ip:axi_protocol_converter:2.1", + "ip_revision": "29", + "xci_name": "NewExtInst_TOP_auto_pc_0", + "xci_path": "ip/NewExtInst_TOP_auto_pc_0/NewExtInst_TOP_auto_pc_0.xci", + "inst_hier_path": "ps7_0_axi_periph/s00_couplers/auto_pc", + "parameters": { + "MI_PROTOCOL": { + "value": "AXI4LITE" + }, + "SI_PROTOCOL": { + "value": "AXI3" + } + }, + "interface_ports": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "auto_pc_to_s00_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] + }, + "s00_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] + } + }, + "nets": { + "S_ACLK_1": { + "ports": [ + "S_ACLK", + "auto_pc/aclk" + ] + }, + "S_ARESETN_1": { + "ports": [ + "S_ARESETN", + "auto_pc/aresetn" + ] + } + } + }, + "m00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m00_couplers_to_m00_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m01_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m01_couplers_to_m01_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m02_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m02_couplers_to_m02_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "m00_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "m00_couplers/M_AXI", + "M00_AXI" + ] + }, + "m01_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "m01_couplers/M_AXI", + "M01_AXI" + ] + }, + "m02_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "m02_couplers/M_AXI", + "M02_AXI" + ] + }, + "ps7_0_axi_periph_to_s00_couplers": { + "interface_ports": [ + "S00_AXI", + "s00_couplers/S_AXI" + ] + }, + "s00_couplers_to_xbar": { + "interface_ports": [ + "s00_couplers/M_AXI", + "xbar/S00_AXI" + ] + }, + "xbar_to_m00_couplers": { + "interface_ports": [ + "xbar/M00_AXI", + "m00_couplers/S_AXI" + ] + }, + "xbar_to_m01_couplers": { + "interface_ports": [ + "xbar/M01_AXI", + "m01_couplers/S_AXI" + ] + }, + "xbar_to_m02_couplers": { + "interface_ports": [ + "xbar/M02_AXI", + "m02_couplers/S_AXI" + ] + } + }, + "nets": { + "ps7_0_axi_periph_ACLK_net": { + "ports": [ + "ACLK", + "xbar/aclk", + "s00_couplers/S_ACLK", + "s00_couplers/M_ACLK", + "m00_couplers/M_ACLK", + "m01_couplers/M_ACLK", + "m02_couplers/M_ACLK", + "m00_couplers/S_ACLK", + "m01_couplers/S_ACLK", + "m02_couplers/S_ACLK" + ] + }, + "ps7_0_axi_periph_ARESETN_net": { + "ports": [ + "ARESETN", + "xbar/aresetn", + "s00_couplers/S_ARESETN", + "s00_couplers/M_ARESETN", + "m00_couplers/M_ARESETN", + "m01_couplers/M_ARESETN", + "m02_couplers/M_ARESETN", + "m00_couplers/S_ARESETN", + "m01_couplers/S_ARESETN", + "m02_couplers/S_ARESETN" + ] + } + } + }, + "rst_clk_wiz_0_100M": { + "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", + "ip_revision": "14", + "xci_name": "NewExtInst_TOP_rst_clk_wiz_0_100M_0", + "xci_path": "ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0.xci", + "inst_hier_path": "rst_clk_wiz_0_100M" + } + }, + "interface_nets": { + "processing_system7_0_DDR": { + "interface_ports": [ + "DDR", + "processing_system7_0/DDR" + ] + }, + "processing_system7_0_FIXED_IO": { + "interface_ports": [ + "FIXED_IO", + "processing_system7_0/FIXED_IO" + ] + }, + "processing_system7_0_M_AXI_GP0": { + "interface_ports": [ + "processing_system7_0/M_AXI_GP0", + "ps7_0_axi_periph/S00_AXI" + ] + }, + "ps7_0_axi_periph_M00_AXI": { + "interface_ports": [ + "ps7_0_axi_periph/M00_AXI", + "SPI_Con_0/S00_AXI" + ] + }, + "ps7_0_axi_periph_M01_AXI": { + "interface_ports": [ + "ps7_0_axi_periph/M01_AXI", + "SPI_Con_1/S00_AXI" + ] + }, + "ps7_0_axi_periph_M02_AXI": { + "interface_ports": [ + "ps7_0_axi_periph/M02_AXI", + "SPI_Con_2/S00_AXI" + ] + } + }, + "nets": { + "SPI_Con_0_o_cs": { + "ports": [ + "SPI_Con_0/o_cs", + "o_cs_0" + ] + }, + "SPI_Con_0_o_mosi": { + "ports": [ + "SPI_Con_0/o_mosi", + "o_mosi_0" + ] + }, + "SPI_Con_0_o_sclk": { + "ports": [ + "SPI_Con_0/o_sclk", + "o_sclk_0" + ] + }, + "SPI_Con_1_o_cs": { + "ports": [ + "SPI_Con_1/o_cs", + "o_cs_1" + ] + }, + "SPI_Con_1_o_mosi": { + "ports": [ + "SPI_Con_1/o_mosi", + "o_mosi_1" + ] + }, + "SPI_Con_1_o_sclk": { + "ports": [ + "SPI_Con_1/o_sclk", + "o_sclk_1" + ] + }, + "SPI_Con_2_o_cs": { + "ports": [ + "SPI_Con_2/o_cs", + "o_cs_2" + ] + }, + "SPI_Con_2_o_mosi": { + "ports": [ + "SPI_Con_2/o_mosi", + "o_mosi_2" + ] + }, + "SPI_Con_2_o_sclk": { + "ports": [ + "SPI_Con_2/o_sclk", + "o_sclk_2" + ] + }, + "clk_wiz_0_clk_out1": { + "ports": [ + "clk_wiz_0/clk_out1", + "processing_system7_0/M_AXI_GP0_ACLK", + "ps7_0_axi_periph/ACLK", + "ps7_0_axi_periph/S00_ACLK", + "ps7_0_axi_periph/M00_ACLK", + "ps7_0_axi_periph/M01_ACLK", + "ps7_0_axi_periph/M02_ACLK", + "rst_clk_wiz_0_100M/slowest_sync_clk", + "SPI_Con_0/s00_axi_aclk", + "SPI_Con_1/s00_axi_aclk", + "SPI_Con_2/s00_axi_aclk" + ] + }, + "clk_wiz_0_locked": { + "ports": [ + "clk_wiz_0/locked", + "rst_clk_wiz_0_100M/dcm_locked" + ] + }, + "i_miso_0_1": { + "ports": [ + "i_miso_0", + "SPI_Con_0/i_miso" + ] + }, + "i_miso_1_1": { + "ports": [ + "i_miso_1", + "SPI_Con_1/i_miso" + ] + }, + "i_miso_2_1": { + "ports": [ + "i_miso_2", + "SPI_Con_2/i_miso" + ] + }, + "proc_sys_reset_0_peripheral_reset": { + "ports": [ + "proc_sys_reset_0/peripheral_reset", + "clk_wiz_0/reset", + "rst_clk_wiz_0_100M/ext_reset_in" + ] + }, + "processing_system7_0_FCLK_CLK0": { + "ports": [ + "processing_system7_0/FCLK_CLK0", + "clk_wiz_0/clk_in1", + "proc_sys_reset_0/slowest_sync_clk" + ] + }, + "processing_system7_0_FCLK_RESET0_N": { + "ports": [ + "processing_system7_0/FCLK_RESET0_N", + "proc_sys_reset_0/ext_reset_in" + ] + }, + "rst_clk_wiz_0_100M_peripheral_aresetn": { + "ports": [ + "rst_clk_wiz_0_100M/peripheral_aresetn", + "ps7_0_axi_periph/ARESETN", + "ps7_0_axi_periph/S00_ARESETN", + "ps7_0_axi_periph/M00_ARESETN", + "ps7_0_axi_periph/M01_ARESETN", + "ps7_0_axi_periph/M02_ARESETN", + "SPI_Con_0/s00_axi_aresetn", + "SPI_Con_1/s00_axi_aresetn", + "SPI_Con_2/s00_axi_aresetn" + ] + } + }, + "addressing": { + "/processing_system7_0": { + "address_spaces": { + "Data": { + "segments": { + "SEG_SPI_Con_0_S00_AXI_reg": { + "address_block": "/SPI_Con_0/S00_AXI/S00_AXI_reg", + "offset": "0x43C00000", + "range": "64K", + "offset_base_param": "C_S00_AXI_BASEADDR", + "offset_high_param": "C_S00_AXI_HIGHADDR" + }, + "SEG_SPI_Con_1_S00_AXI_reg": { + "address_block": "/SPI_Con_1/S00_AXI/S00_AXI_reg", + "offset": "0x43C10000", + "range": "64K", + "offset_base_param": "C_S00_AXI_BASEADDR", + "offset_high_param": "C_S00_AXI_HIGHADDR" + }, + "SEG_SPI_Con_2_S00_AXI_reg": { + "address_block": "/SPI_Con_2/S00_AXI/S00_AXI_reg", + "offset": "0x43C20000", + "range": "64K", + "offset_base_param": "C_S00_AXI_BASEADDR", + "offset_high_param": "C_S00_AXI_HIGHADDR" + } + } + } + } + } + } + } +} \ No newline at end of file diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/NewExtInst_TOP.bda b/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/NewExtInst_TOP.bda new file mode 100644 index 0000000..ab7b1f9 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/NewExtInst_TOP.bda @@ -0,0 +1,272 @@ +{ + "graphjs": { + "version": "1.0", + "keys": [ + { + "abrv": "VH", + "name": "vert_hid", + "type": "int", + "for": "node" + }, + { + "abrv": "VM", + "name": "vert_name", + "type": "string", + "for": "node" + }, + { + "abrv": "VT", + "name": "vert_type", + "type": "string", + "for": "node" + }, + { + "abrv": "BA", + "name": "base_addr", + "type": "string", + "for": "node" + }, + { + "abrv": "HA", + "name": "high_addr", + "type": "string", + "for": "node" + }, + { + "abrv": "BP", + "name": "base_param", + "type": "string", + "for": "node" + }, + { + "abrv": "HP", + "name": "high_param", + "type": "string", + "for": "node" + }, + { + "abrv": "MA", + "name": "master_addrspace", + "type": "string", + "for": "node" + }, + { + "abrv": "MX", + "name": "master_instance", + "type": "string", + "for": "node" + }, + { + "abrv": "MI", + "name": "master_interface", + "type": "string", + "for": "node" + }, + { + "abrv": "MS", + "name": "master_segment", + "type": "string", + "for": "node" + }, + { + "abrv": "MV", + "name": "master_vlnv", + "type": "string", + "for": "node" + }, + { + "abrv": "SX", + "name": "slave_instance", + "type": "string", + "for": "node" + }, + { + "abrv": "SI", + "name": "slave_interface", + "type": "string", + "for": "node" + }, + { + "abrv": "MM", + "name": "slave_memmap", + "type": "string", + "for": "node" + }, + { + "abrv": "SS", + "name": "slave_segment", + "type": "string", + "for": "node" + }, + { + "abrv": "SV", + "name": "slave_vlnv", + "type": "string", + "for": "node" + }, + { + "abrv": "TM", + "name": "memory_type", + "type": "string", + "for": "node" + }, + { + "abrv": "TU", + "name": "usage_type", + "type": "string", + "for": "node" + }, + { + "abrv": "LT", + "name": "lock_type", + "type": "string", + "for": "node" + }, + { + "abrv": "BT", + "name": "boot_type", + "type": "string", + "for": "node" + }, + { + "abrv": "EH", + "name": "edge_hid", + "type": "int", + "for": "edge" + } + ], + "vertice_type_order": [ + { + "abrv": "BC", + "desc": "Block Container" + }, + { + "abrv": "PR", + "desc": "Parital Reference" + }, + { + "abrv": "VR", + "desc": "Variant" + }, + { + "abrv": "PM", + "desc": "Variant Permutations" + }, + { + "abrv": "CX", + "desc": "Boundary Connection" + }, + { + "abrv": "AC", + "desc": "Assignment Coordinate" + }, + { + "abrv": "ACE", + "desc": "Excluded Assign Coordinate" + }, + { + "abrv": "APX", + "desc": "Boundary Aperture" + }, + { + "abrv": "CIP", + "desc": "High level Processing System" + } + ], + "vertices": { + "V0": { + "VM": "NewExtInst_TOP", + "VT": "BC" + }, + "V1": { + "VH": "2", + "VM": "NewExtInst_TOP", + "VT": "VR" + }, + "V2": { + "VH": "2", + "VT": "PM", + "TU": "active" + }, + "V3": { + "VT": "AC", + "BA": "0x43C00000", + "HA": "0x43C0FFFF", + "BP": "C_S00_AXI_BASEADDR", + "HP": "C_S00_AXI_HIGHADDR", + "MA": "Data", + "MX": "/processing_system7_0", + "MI": "M_AXI_GP0", + "MS": "SEG_SPI_Con_0_S00_AXI_reg", + "MV": "xilinx.com:ip:processing_system7:5.5", + "SX": "/SPI_Con_0", + "SI": "S00_AXI", + "SS": "S00_AXI_reg", + "SV": "xilinx.com:user:SPI_Con:1.0", + "TM": "both", + "TU": "register" + }, + "V4": { + "VT": "AC", + "BA": "0x43C10000", + "HA": "0x43C1FFFF", + "BP": "C_S00_AXI_BASEADDR", + "HP": "C_S00_AXI_HIGHADDR", + "MA": "Data", + "MX": "/processing_system7_0", + "MI": "M_AXI_GP0", + "MS": "SEG_SPI_Con_1_S00_AXI_reg", + "MV": "xilinx.com:ip:processing_system7:5.5", + "SX": "/SPI_Con_1", + "SI": "S00_AXI", + "SS": "S00_AXI_reg", + "SV": "xilinx.com:user:SPI_Con:1.0", + "TM": "both", + "TU": "register" + }, + "V5": { + "VT": "AC", + "BA": "0x43C20000", + "HA": "0x43C2FFFF", + "BP": "C_S00_AXI_BASEADDR", + "HP": "C_S00_AXI_HIGHADDR", + "MA": "Data", + "MX": "/processing_system7_0", + "MI": "M_AXI_GP0", + "MS": "SEG_SPI_Con_2_S00_AXI_reg", + "MV": "xilinx.com:ip:processing_system7:5.5", + "SX": "/SPI_Con_2", + "SI": "S00_AXI", + "SS": "S00_AXI_reg", + "SV": "xilinx.com:user:SPI_Con:1.0", + "TM": "both", + "TU": "register" + } + }, + "edges": [ + { + "src": "V0", + "trg": "V1" + }, + { + "src": "V1", + "trg": "V2" + }, + { + "src": "V3", + "trg": "V2", + "EH": "2" + }, + { + "src": "V4", + "trg": "V2", + "EH": "2" + }, + { + "src": "V5", + "trg": "V2", + "EH": "2" + } + ] + } +} diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/NewExtInst_TOP_ooc.xdc b/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/NewExtInst_TOP_ooc.xdc new file mode 100644 index 0000000..6c60e55 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/NewExtInst_TOP_ooc.xdc @@ -0,0 +1,14 @@ +################################################################################ + +# This XDC is used only for OOC mode of synthesis, implementation +# This constraints file contains default clock frequencies to be used during +# out-of-context flows such as OOC Synthesis and Hierarchical Designs. +# This constraints file is not used in normal top-down synthesis (default flow +# of Vivado) +################################################################################ +create_clock -name processing_system7_0_FCLK_CLK0 -period 40 [get_pins processing_system7_0/FCLK_CLK0] +create_clock -name processing_system7_0_FCLK_CLK1 -period 20 [get_pins processing_system7_0/FCLK_CLK1] +create_clock -name processing_system7_0_FCLK_CLK2 -period 10 [get_pins processing_system7_0/FCLK_CLK2] +create_clock -name processing_system7_0_FCLK_CLK3 -period 5 [get_pins processing_system7_0/FCLK_CLK3] + +################################################################################ \ No newline at end of file diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0.xci b/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0.xci new file mode 100644 index 0000000..a48bd54 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0.xci @@ -0,0 +1,186 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "NewExtInst_TOP_SPI_Con_0_0", + "cell_name": "SPI_Con_0", + "component_reference": "xilinx.com:user:SPI_Con:1.0", + "ip_revision": "3", + "gen_directory": "../../../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0", + "parameters": { + "component_parameters": { + "C_S00_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "C_S00_AXI_ADDR_WIDTH": [ { "value": "7", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "C_S00_AXI_BASEADDR": [ { "value": "0xFFFFFFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "C_S00_AXI_HIGHADDR": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "Component_Name": [ { "value": "NewExtInst_TOP_SPI_Con_0_0", "resolve_type": "user", "usage": "all" } ] + }, + "model_parameters": { + "C_S00_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_S00_AXI_ADDR_WIDTH": [ { "value": "7", "resolve_type": "generated", "format": "long", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynq" } ], + "BASE_BOARD_PART": [ { "value": "" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7z035" } ], + "PACKAGE": [ { "value": "ffg676" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-2" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ], + "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], + "USE_RDI_GENERATION": [ { "value": "TRUE" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Integrator" } ], + "IPREVISION": [ { "value": "3" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SWVERSION": [ { "value": "2023.2" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "i_miso": [ { "direction": "in" } ], + "o_sclk": [ { "direction": "out" } ], + "o_cs": [ { "direction": "out" } ], + "o_mosi": [ { "direction": "out" } ], + "s00_axi_aclk": [ { "direction": "in" } ], + "s00_axi_aresetn": [ { "direction": "in" } ], + "s00_axi_awaddr": [ { "direction": "in", "size_left": "6", "size_right": "0" } ], + "s00_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0" } ], + "s00_axi_awvalid": [ { "direction": "in" } ], + "s00_axi_awready": [ { "direction": "out" } ], + "s00_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0" } ], + "s00_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0" } ], + "s00_axi_wvalid": [ { "direction": "in" } ], + "s00_axi_wready": [ { "direction": "out" } ], + "s00_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ], + "s00_axi_bvalid": [ { "direction": "out" } ], + "s00_axi_bready": [ { "direction": "in" } ], + "s00_axi_araddr": [ { "direction": "in", "size_left": "6", "size_right": "0" } ], + "s00_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0" } ], + "s00_axi_arvalid": [ { "direction": "in" } ], + "s00_axi_arready": [ { "direction": "out" } ], + "s00_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], + "s00_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ], + "s00_axi_rvalid": [ { "direction": "out" } ], + "s00_axi_rready": [ { "direction": "in" } ] + }, + "interfaces": { + "S00_AXI": { + "vlnv": "xilinx.com:interface:aximm:1.0", + "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "slave", + "memory_map_ref": "S00_AXI", + "parameters": { + "WIZ_DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ], + "WIZ_NUM_REG": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ], + "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ], + "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ADDR_WIDTH": [ { "value": "7", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "/clk_wiz_0_clk_out1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "AWADDR": [ { "physical_name": "s00_axi_awaddr" } ], + "AWPROT": [ { "physical_name": "s00_axi_awprot" } ], + "AWVALID": [ { "physical_name": "s00_axi_awvalid" } ], + "AWREADY": [ { "physical_name": "s00_axi_awready" } ], + "WDATA": [ { "physical_name": "s00_axi_wdata" } ], + "WSTRB": [ { "physical_name": "s00_axi_wstrb" } ], + "WVALID": [ { "physical_name": "s00_axi_wvalid" } ], + "WREADY": [ { "physical_name": "s00_axi_wready" } ], + "BRESP": [ { "physical_name": "s00_axi_bresp" } ], + "BVALID": [ { "physical_name": "s00_axi_bvalid" } ], + "BREADY": [ { "physical_name": "s00_axi_bready" } ], + "ARADDR": [ { "physical_name": "s00_axi_araddr" } ], + "ARPROT": [ { "physical_name": "s00_axi_arprot" } ], + "ARVALID": [ { "physical_name": "s00_axi_arvalid" } ], + "ARREADY": [ { "physical_name": "s00_axi_arready" } ], + "RDATA": [ { "physical_name": "s00_axi_rdata" } ], + "RRESP": [ { "physical_name": "s00_axi_rresp" } ], + "RVALID": [ { "physical_name": "s00_axi_rvalid" } ], + "RREADY": [ { "physical_name": "s00_axi_rready" } ] + } + }, + "S00_AXI_RST": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "s00_axi_aresetn" } ] + } + }, + "S00_AXI_CLK": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "S00_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "s00_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "/clk_wiz_0_clk_out1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "s00_axi_aclk" } ] + } + } + }, + "memory_maps": { + "S00_AXI": { + "address_blocks": { + "S00_AXI_reg": { + "base_address": "0", + "range": "4096", + "usage": "register", + "parameters": { + "OFFSET_BASE_PARAM": [ { "value": "C_S00_AXI_BASEADDR" } ], + "OFFSET_HIGH_PARAM": [ { "value": "C_S00_AXI_HIGHADDR" } ] + } + } + } + } + } + } + } +} \ No newline at end of file diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1.xci b/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1.xci new file mode 100644 index 0000000..2456628 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1.xci @@ -0,0 +1,186 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "NewExtInst_TOP_SPI_Con_0_1", + "cell_name": "SPI_Con_1", + "component_reference": "xilinx.com:user:SPI_Con:1.0", + "ip_revision": "3", + "gen_directory": "../../../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1", + "parameters": { + "component_parameters": { + "C_S00_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "C_S00_AXI_ADDR_WIDTH": [ { "value": "7", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "C_S00_AXI_BASEADDR": [ { "value": "0xFFFFFFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "C_S00_AXI_HIGHADDR": [ { "value": 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"is_static_object": false } ], + "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "/clk_wiz_0_clk_out1", "value_src": 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"generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_RESET": [ { "value": "ARESETN", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "aclk" } ] + } + }, + "RST": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ], + "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "aresetn" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.xci b/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.xci new file mode 100644 index 0000000..395a692 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.xci @@ -0,0 +1,673 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "NewExtInst_TOP_clk_wiz_0_0", + "cell_name": "clk_wiz_0", + "component_reference": "xilinx.com:ip:clk_wiz:6.0", + "ip_revision": "13", + "gen_directory": "../../../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "NewExtInst_TOP_clk_wiz_0_0", "resolve_type": "user", "usage": "all" } ], + "USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ], + "PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ], + "CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ], + "USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ], + "PRIM_IN_FREQ": [ { "value": "25.000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ], + "PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ], + "IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ], + "RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ], + "USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "SECONDARY_IN_FREQ": [ { "value": "100.000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ], + "SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ], + "JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ], + "CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN1_JITTER_PS": [ { "value": "400.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT2_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ], + "DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ], + "DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ], + "DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ], + "DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ], + "DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ], + "DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ], + "DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ], + "PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ], + "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ], + "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ], + "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ], + "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ], + "CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ], + "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ], + "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_RESET": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ], + "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ], + "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ], + "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ], + "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ], + "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ], + "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ], + "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ], + "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ], + "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": 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"MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ], + "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + 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"MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + 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{ "value": "None", "resolve_type": "user", "usage": "all" } ], + "PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ], + "PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ], + "PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ], + "PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + 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"physical_name": "aux_reset_in" } ] + } + }, + "dbg_reset": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "mb_debug_sys_rst" } ] + } + }, + "mb_rst": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "master", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "TYPE": [ { "value": "PROCESSOR", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "mb_reset" } ] + } + }, + "bus_struct_reset": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "master", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "bus_struct_reset" } ] + } + }, + "interconnect_low_rst": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "master", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "interconnect_aresetn" } ] + } + }, + "peripheral_high_rst": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "master", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "peripheral_reset" } ] + } + }, + "peripheral_low_rst": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "master", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "peripheral_aresetn" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0.xci b/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0.xci new file mode 100644 index 0000000..fdfb569 --- /dev/null +++ b/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0.xci @@ -0,0 +1,1311 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "NewExtInst_TOP_processing_system7_0_0", + "cell_name": "processing_system7_0", + "component_reference": "xilinx.com:ip:processing_system7:5.5", + "ip_revision": "6", + "gen_directory": "../../../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0", + "parameters": { + "component_parameters": { + "PCW_DDR_RAM_BASEADDR": [ { "value": "0x00100000", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_DDR_RAM_HIGHADDR": [ { "value": "0x3FFFFFFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_UART0_BASEADDR": [ { "value": "0xE0000000", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_UART0_HIGHADDR": [ { "value": "0xE0000FFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_UART1_BASEADDR": [ { "value": "0xE0001000", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_UART1_HIGHADDR": [ { "value": "0xE0001FFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_I2C0_BASEADDR": [ { "value": "0xE0004000", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_I2C0_HIGHADDR": [ { "value": "0xE0004FFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_I2C1_BASEADDR": [ { "value": "0xE0005000", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_I2C1_HIGHADDR": [ { "value": "0xE0005FFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_SPI0_BASEADDR": [ { "value": "0xE0006000", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_SPI0_HIGHADDR": [ { "value": "0xE0006FFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_SPI1_BASEADDR": [ { "value": "0xE0007000", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_SPI1_HIGHADDR": [ { "value": "0xE0007FFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_CAN0_BASEADDR": [ { "value": "0xE0008000", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_CAN0_HIGHADDR": [ { "value": "0xE0008FFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_CAN1_BASEADDR": [ { "value": "0xE0009000", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_CAN1_HIGHADDR": [ { "value": "0xE0009FFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_GPIO_BASEADDR": [ { "value": "0xE000A000", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_GPIO_HIGHADDR": [ { "value": "0xE000AFFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_ENET0_BASEADDR": [ { "value": "0xE000B000", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_ENET0_HIGHADDR": [ { "value": "0xE000BFFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_ENET1_BASEADDR": [ { "value": "0xE000C000", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_ENET1_HIGHADDR": [ { "value": "0xE000CFFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_SDIO0_BASEADDR": [ { "value": "0xE0100000", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_SDIO0_HIGHADDR": [ { "value": "0xE0100FFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_SDIO1_BASEADDR": [ { "value": "0xE0101000", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_SDIO1_HIGHADDR": [ { "value": "0xE0101FFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_USB0_BASEADDR": [ { "value": "0xE0102000", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_USB0_HIGHADDR": [ { "value": "0xE0102fff", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_USB1_BASEADDR": [ { "value": "0xE0103000", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_USB1_HIGHADDR": [ { "value": "0xE0103fff", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_TTC0_BASEADDR": [ { "value": "0xE0104000", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_TTC0_HIGHADDR": [ { "value": "0xE0104fff", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_TTC1_BASEADDR": [ { "value": "0xE0105000", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_TTC1_HIGHADDR": [ { "value": "0xE0105fff", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_FCLK_CLK0_BUF": [ { "value": "TRUE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_FCLK_CLK1_BUF": [ { "value": "TRUE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_FCLK_CLK2_BUF": [ { "value": "TRUE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_FCLK_CLK3_BUF": [ { "value": "TRUE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_FREQ_MHZ": [ { "value": "533.333333", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_BANK_ADDR_COUNT": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_ROW_ADDR_COUNT": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_COL_ADDR_COUNT": [ { "value": "10", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_CL": [ { "value": "7", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_CWL": [ { "value": "6", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_T_RCD": [ { "value": "7", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_T_RP": [ { "value": "7", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_T_RC": [ { "value": "48.91", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_T_RAS_MIN": [ { "value": "35.0", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_T_FAW": [ { "value": "40.0", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_AL": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0": [ { "value": "0.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1": [ { "value": "0.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2": [ { "value": "0.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3": [ { "value": "0.0", "value_src": "user", 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"1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_CLK3_PORT": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_RST0_PORT": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_RST1_PORT": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_RST2_PORT": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_RST3_PORT": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_CLKTRIG0_PORT": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_CLKTRIG1_PORT": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_CLKTRIG2_PORT": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_CLKTRIG3_PORT": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_P2F_DMAC_ABORT_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_DMAC0_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_DMAC1_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_DMAC2_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_DMAC3_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_DMAC4_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_DMAC5_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_DMAC6_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_DMAC7_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_SMC_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_QSPI_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_CTI_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_GPIO_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_USB0_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_ENET0_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_SDIO0_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_I2C0_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_SPI0_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_UART0_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_CAN0_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_USB1_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_ENET1_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_SDIO1_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_I2C1_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_SPI1_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_UART1_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_CAN1_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_IRQ_F2P_INTR": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_IRQ_F2P_MODE": [ { "value": "DIRECT", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_CORE0_FIQ_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_CORE0_IRQ_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_CORE1_FIQ_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_CORE1_IRQ_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_VALUE_SILVERSION": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_GP0_EN_MODIFIABLE_TXN": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_GP1_EN_MODIFIABLE_TXN": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_IMPORT_BOARD_PRESET": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_PERIPHERAL_BOARD_PRESET": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_PRESET_BANK0_VOLTAGE": [ { "value": "LVCMOS 3.3V", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_PRESET_BANK1_VOLTAGE": [ { "value": "LVCMOS 1.8V", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_ADV_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_MEMORY_TYPE": [ { "value": "DDR 3", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_ECC": [ { "value": "Disabled", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_BUS_WIDTH": [ { "value": "32 Bit", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_BL": [ { "value": "8", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_HIGH_TEMP": [ { "value": "Normal (0-85)", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_PARTNO": [ { "value": "MT41J256M16 RE-125", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_DRAM_WIDTH": [ { "value": "16 Bits", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_DEVICE_CAPACITY": [ { "value": "4096 MBits", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_SPEED_BIN": [ { "value": "DDR3_1066F", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_TRAIN_READ_GATE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_TRAIN_DATA_EYE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_CLOCK_STOP_EN": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_USE_INTERNAL_VREF": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_DDR_PRIORITY_WRITEPORT_0": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_PRIORITY_WRITEPORT_2": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_PRIORITY_READPORT_0": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_PRIORITY_READPORT_2": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_PORT0_HPR_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_PORT1_HPR_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_PORT2_HPR_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_PORT3_HPR_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_HPRLPR_QUEUE_PARTITION": [ { "value": "HPR(0)/LPR(32)", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_NAND_PERIPHERAL_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_NAND_NAND_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_NOR_PERIPHERAL_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_NOR_NOR_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_NOR_GRP_CS0_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_NOR_GRP_CS0_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_NOR_GRP_CS1_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_NOR_GRP_CS1_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_NOR_GRP_SRAM_INT_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_NOR_GRP_SRAM_INT_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SINGLE_QSPI_DATA_MODE": [ { "value": "x4", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_DUAL_STACK_QSPI_DATA_MODE": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_QSPI_GRP_IO1_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_QSPI_GRP_IO1_IO": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_ENET0_RESET_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_ENET0_RESET_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_ENET1_GRP_MDIO_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_ENET1_GRP_MDIO_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SD0_PERIPHERAL_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_SD0_SD0_IO": [ { "value": "MIO 40 .. 45", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_SD0_GRP_CD_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_SD0_GRP_CD_IO": [ { "value": "MIO 47", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_SD0_GRP_WP_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_SD0_GRP_WP_IO": [ { "value": "MIO 46", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_SD0_GRP_POW_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_SD0_GRP_POW_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_UART0_PERIPHERAL_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UART0_UART0_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_UART1_PERIPHERAL_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UART1_UART1_IO": [ { "value": "MIO 48 .. 49", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UART1_GRP_FULL_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UART1_GRP_FULL_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SPI0_GRP_SS0_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SPI0_GRP_SS0_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SPI0_GRP_SS2_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SPI0_GRP_SS2_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SPI1_GRP_SS0_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SPI1_GRP_SS0_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SPI1_GRP_SS2_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SPI1_GRP_SS2_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_CAN0_GRP_CLK_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_CAN0_GRP_CLK_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_CAN1_GRP_CLK_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_CAN1_GRP_CLK_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_TRACE_GRP_2BIT_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_TRACE_GRP_2BIT_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_TRACE_GRP_8BIT_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_TRACE_GRP_8BIT_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_TRACE_GRP_32BIT_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_TRACE_GRP_32BIT_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_TTC0_PERIPHERAL_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_TTC0_TTC0_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_PJTAG_PERIPHERAL_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_PJTAG_PJTAG_IO": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_USB_RESET_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_USB_RESET_SELECT": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_USB1_PERIPHERAL_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_USB1_USB1_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_I2C0_PERIPHERAL_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_I2C0_I2C0_IO": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_I2C0_RESET_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_I2C0_RESET_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_I2C1_GRP_INT_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_I2C1_GRP_INT_IO": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_I2C1_RESET_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_I2C1_RESET_IO": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_GPIO_EMIO_GPIO_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_GPIO_EMIO_GPIO_IO": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_7_IOTYPE": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_7_SLEW": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_28_IOTYPE": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_28_SLEW": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_29_IOTYPE": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_29_SLEW": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_30_IOTYPE": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_30_SLEW": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_31_IOTYPE": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_31_SLEW": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_32_IOTYPE": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_32_SLEW": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_33_IOTYPE": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_33_SLEW": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_34_IOTYPE": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_34_SLEW": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_35_IOTYPE": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_35_SLEW": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_36_IOTYPE": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_36_SLEW": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_37_IOTYPE": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_37_SLEW": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_38_IOTYPE": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_38_SLEW": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_39_IOTYPE": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_39_SLEW": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_50_IOTYPE": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_50_SLEW": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_51_IOTYPE": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_51_SLEW": [ { "value": "